diff options
Diffstat (limited to 'ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf')
12 files changed, 436 insertions, 0 deletions
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.h b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.h new file mode 100644 index 0000000..daf0474 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.h @@ -0,0 +1,32 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram_l (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_l_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_l_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_sram (0x20000000) +#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_FBR_CACHED_BASE) +#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ramcod (CYGHWR_HAL_KINETIS_FBR_CODE_BASE) +#define CYGMEM_REGION_ramcod_SIZE (CYGHWR_HAL_KINETIS_FBR_CODE_SIZE) +#define CYGMEM_REGION_ramcod_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ramnc (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE) +#define CYGMEM_REGION_ramnc_SIZE (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE) +#define CYGMEM_REGION_ramnc_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi new file mode 100644 index 0000000..6095daa --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi @@ -0,0 +1,41 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + sram_l : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE + sram : ORIGIN = 0x20000000, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE + ramcod : ORIGIN = CYGHWR_HAL_KINETIS_FBR_CODE_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_CODE_SIZE + ram : ORIGIN = CYGHWR_HAL_KINETIS_FBR_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + ramnc : ORIGIN = CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE +} + +SECTIONS +{ + SECTIONS_BEGIN + USER_SECTION (code_sram, sram_l, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400 + 0x100, LMA_EQ_VMA) + SECTION_sram (sram, 0x20000000, LMA_EQ_VMA) + SECTION_rom_vectors (ramcod, CYGHWR_HAL_KINETIS_FBR_CODE_BASE, LMA_EQ_VMA) + SECTION_RELOCS (ramcod, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (ramcod, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (ramcod, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (ram, CYGHWR_HAL_KINETIS_FBR_CACHED_BASE+CYGHWR_MEMORY_RAM_RESERVED, LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + USER_SECTION (noncache, ramnc, CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE (NOLOAD), LMA_EQ_VMA) + SECTIONS_END +} + +hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE; + diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h new file mode 100644 index 0000000..a00ce95 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h @@ -0,0 +1,40 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram_l (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_l_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_l_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_sram (0x20000000) +#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_flash (0x00000000) +#define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE) +#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R) + +#define CYGMEM_REGION_ramcod (CYGHWR_HAL_KINETIS_FBR_CODE_BASE) +#define CYGMEM_REGION_ramcod_SIZE (CYGHWR_HAL_KINETIS_FBR_CODE_SIZE) +#define CYGMEM_REGION_ramcod_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_FBR_CACHED_BASE) +#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +//#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_FBR_BASE) +//#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE) +//#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ramnc (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE) +#define CYGMEM_REGION_ramnc_SIZE (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE) +#define CYGMEM_REGION_ramnc_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi new file mode 100644 index 0000000..3888a13 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi @@ -0,0 +1,49 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + sram_l : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + sram : ORIGIN = 0x20000000, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE + ramcod : ORIGIN = CYGHWR_HAL_KINETIS_FBR_CODE_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_CODE_SIZE + ram : ORIGIN = CYGHWR_HAL_KINETIS_FBR_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE + ramnc : ORIGIN = CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (flash, 0x00000000, LMA_EQ_VMA) + USER_SECTION(kinetis_misc, flash, ALIGN (0x8), LMA_EQ_VMA) + + // Kinetis FLASH configuration field. Must be present at 0x00000400 + // Warning: Omitting FLASH configuration field or moving it to + // other location may lock Kinetis controller. + // See src/kinetis_mis.c for definition + + .flash_conf 0x00000400 : { KEEP (*(.flash_conf)) } > flash + + SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA) + USER_SECTION (code_sram, sram_l, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400 (NOLOAD), LMA_EQ_VMA) + SECTION_sram (sram, 0x20000000, FOLLOWING (.got)) + SECTION_data (ram, CYGHWR_HAL_KINETIS_FBR_CACHED_BASE, FOLLOWING (.sram)) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + USER_SECTION (noncache, ramnc, CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE (NOLOAD), LMA_EQ_VMA) + SECTIONS_END +} + +hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = (0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram.h b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram.h new file mode 100644 index 0000000..53dceb8 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram.h @@ -0,0 +1,26 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_FB_EXTRAM_BASE) +#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_FB_EXTRAM_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_sram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_flash (0x00000000) +#define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE) +#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) + + diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram.ldi b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram.ldi new file mode 100644 index 0000000..f8330ee --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram.ldi @@ -0,0 +1,35 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = CYGHWR_HAL_KINETIS_FB_EXTRAM_BASE, LENGTH = CYGHWR_HAL_KINETIS_FB_EXTRAM_SIZE + sram : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (ram, 0x20000400 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LMA_EQ_VMA) + SECTION_RELOCS (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_sram (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} + +hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE; diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.h b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.h new file mode 100644 index 0000000..b466a08 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.h @@ -0,0 +1,28 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_FBR_CACHED_BASE) +#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ramcod (CYGHWR_HAL_KINETIS_FBR_CODE_BASE) +#define CYGMEM_REGION_ramcod_SIZE (CYGHWR_HAL_KINETIS_FBR_CODE_SIZE) +#define CYGMEM_REGION_ramcod_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ramnc (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE) +#define CYGMEM_REGION_ramnc_SIZE (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE) +#define CYGMEM_REGION_ramnc_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi new file mode 100644 index 0000000..bab581b --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi @@ -0,0 +1,39 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + + +MEMORY +{ + sram : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE + ramcod : ORIGIN = CYGHWR_HAL_KINETIS_FBR_CODE_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_CODE_SIZE + ram : ORIGIN = CYGHWR_HAL_KINETIS_FBR_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + ramnc : ORIGIN = CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_sram (sram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400 + 0x100, LMA_EQ_VMA) + SECTION_rom_vectors (ramcod, CYGHWR_HAL_KINETIS_FBR_CODE_BASE, LMA_EQ_VMA) + SECTION_RELOCS (ramcod, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (ramcod, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (ramcod, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (ram, CYGHWR_HAL_KINETIS_FBR_CACHED_BASE + CYGHWR_MEMORY_RAM_RESERVED, LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (ramcod, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + USER_SECTION (noncache, ramnc, CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE (NOLOAD), LMA_EQ_VMA) + SECTIONS_END +} + +hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE; diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.h b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.h new file mode 100644 index 0000000..5c6db56 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.h @@ -0,0 +1,32 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_flash (0x00000000) +#define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE) +#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R) + +#define CYGMEM_REGION_ramcod (CYGHWR_HAL_KINETIS_FBR_CODE_BASE) +#define CYGMEM_REGION_ramcod_SIZE (CYGHWR_HAL_KINETIS_FBR_CODE_SIZE) +#define CYGMEM_REGION_ramcod_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_FBR_CACHED_BASE) +#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ramnc (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE) +#define CYGMEM_REGION_ramnc_SIZE (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE) +#define CYGMEM_REGION_ramnc_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi new file mode 100644 index 0000000..b43ce41 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi @@ -0,0 +1,47 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + sram : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE + ramcod : ORIGIN = CYGHWR_HAL_KINETIS_FBR_CODE_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_CODE_SIZE + ram : ORIGIN = CYGHWR_HAL_KINETIS_FBR_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE + ramnc : ORIGIN = CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (flash, 0x00000000, LMA_EQ_VMA) + USER_SECTION(kinetis_misc, flash, ALIGN (0x8), LMA_EQ_VMA) + + // Kinetis FLASH configuration field. Must be present at 0x00000400 + // Warning: Omitting FLASH configuration field or moving it to + // other location may lock Kinetis controller. + // See src/kinetis_mis.c for definition + + .flash_conf 0x00000400 : { KEEP (*(.flash_conf)) } > flash + + SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_sram (sram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400, FOLLOWING (.got)) + SECTION_data (ram, CYGHWR_HAL_KINETIS_FBR_CACHED_BASE, FOLLOWING (.sram)) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + USER_SECTION (noncache, ramnc, CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE (NOLOAD), LMA_EQ_VMA) + SECTIONS_END +} + +hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE; diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_ram.h b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_ram.h new file mode 100644 index 0000000..5370f8f --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_ram.h @@ -0,0 +1,24 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_flash (0x00000000) +#define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE) +#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_ram.ldi b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_ram.ldi new file mode 100644 index 0000000..e74d8a9 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_ram.ldi @@ -0,0 +1,43 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (flash, 0x00000000, LMA_EQ_VMA) + USER_SECTION(kinetis_misc, flash, ALIGN (0x8), LMA_EQ_VMA) + + // Kinetis FLASH security configuration. Must be present at 0x00000400 + // Warning: Omitting FLASH security configuration or moving it to + // other location may lock Kinetis controller. + // See src/kinetis_mis.c for definition + + .flash_security 0x00000400 : { KEEP (*(.flash_security)) } > flash + + SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data (ram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400, FOLLOWING (.got)) + SECTION_sram (ram, ALIGN (0x8), FOLLOWING (.data)) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} + +hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE; |