summaryrefslogtreecommitdiff
path: root/board/clock_config.c
diff options
context:
space:
mode:
Diffstat (limited to 'board/clock_config.c')
-rw-r--r--board/clock_config.c229
1 files changed, 0 insertions, 229 deletions
diff --git a/board/clock_config.c b/board/clock_config.c
deleted file mode 100644
index 4da9ef5..0000000
--- a/board/clock_config.c
+++ /dev/null
@@ -1,229 +0,0 @@
-/*
- * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- * of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- * list of conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.
- *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
- * contributors may be used to endorse or promote products derived from this
- * software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/* This is a template for clock configuration created by New Kinetis SDK 2.x Project Wizard. Enjoy! */
-
-#include "fsl_device_registers.h"
-#include "fsl_common.h"
-#include "fsl_clock.h"
-#include "fsl_port.h"
-#include "clock_config.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-
-#define MCG_IRCLK_DISABLE 0U /*!< MCGIRCLK disabled */
-#define MCG_PLL_DISABLE 0U /*!< MCGPLLCLK disabled */
-#define OSC_CAP0P 0U /*!< Oscillator 0pF capacitor load */
-#define OSC_ER_CLK_DISABLE 0U /*!< Disable external reference clock */
-#define SIM_OSC32KSEL_OSC32KCLK_CLK 0U /*!< OSC32KSEL select: OSC32KCLK clock */
-#define SIM_PLLFLLSEL_MCGFLLCLK_CLK 0U /*!< PLLFLL select: MCGFLLCLK clock */
-#define SIM_PLLFLLSEL_MCGPLLCLK_CLK 1U /*!< PLLFLL select: MCGPLLCLK clock */
-#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 100000000U /*!< Core clock frequency: 100000000Hz */
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-/* System clock frequency. */
-extern uint32_t SystemCoreClock;
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-/*FUNCTION**********************************************************************
- *
- * Function Name : CLOCK_CONFIG_SetFllExtRefDiv
- * Description : Configure FLL external reference divider (FRDIV).
- * Param frdiv : The value to set FRDIV.
- *
- *END**************************************************************************/
-static void CLOCK_CONFIG_SetFllExtRefDiv(uint8_t frdiv)
-{
- MCG->C1 = ((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv));
-}
-
-/*******************************************************************************
- ************************ BOARD_InitBootClocks function ************************
- ******************************************************************************/
-void BOARD_InitBootClocks(void)
-{
- BOARD_BootClockRUN();
-}
-
-/*******************************************************************************
- ********************** Configuration BOARD_BootClockRUN ***********************
- ******************************************************************************/
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockRUN
-called_from_default_init: true
-outputs:
-- {id: Bus_clock.outFreq, value: 50 MHz}
-- {id: Core_clock.outFreq, value: 100 MHz, locked: true, accuracy: '0.001'}
-- {id: Flash_clock.outFreq, value: 25 MHz}
-- {id: FlexBus_clock.outFreq, value: 50 MHz}
-- {id: LPO_clock.outFreq, value: 1 kHz}
-- {id: MCGFFCLK.outFreq, value: 250 kHz}
-- {id: System_clock.outFreq, value: 100 MHz}
-settings:
-- {id: MCGMode, value: PEE}
-- {id: MCG.FRDIV.scale, value: '32'}
-- {id: MCG.IREFS.sel, value: MCG.FRDIV}
-- {id: MCG.PLLS.sel, value: MCG.PLL}
-- {id: MCG.PRDIV.scale, value: '2'}
-- {id: MCG.VDIV.scale, value: '25'}
-- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
-- {id: MCG_C2_RANGE0_CFG, value: Very_high}
-- {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
-- {id: SIM.OUTDIV2.scale, value: '2'}
-- {id: SIM.OUTDIV3.scale, value: '2'}
-- {id: SIM.OUTDIV4.scale, value: '4'}
-sources:
-- {id: OSC.OSC.outFreq, value: 8 MHz, enabled: true}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-
-/*******************************************************************************
- * Variables for BOARD_BootClockRUN configuration
- ******************************************************************************/
-const mcg_config_t mcgConfig_BOARD_BootClockRUN =
- {
- .mcgMode = kMCG_ModePEE, /* PEE - PLL Engaged External */
- .irclkEnableMode = MCG_IRCLK_DISABLE, /* MCGIRCLK disabled */
- .ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */
- .fcrdiv = 0x1U, /* Fast IRC divider: divided by 2 */
- .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
- .drs = kMCG_DrsLow, /* Low frequency range */
- .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
- .oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
- .pll0Config =
- {
- .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
- .prdiv = 0x1U, /* PLL Reference divider: divided by 2 */
- .vdiv = 0x1U, /* VCO divider: multiplied by 25 */
- },
- };
-const sim_clock_config_t simConfig_BOARD_BootClockRUN =
- {
- .pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */
- .er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
- .clkdiv1 = 0x01130000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /2, OUTDIV4: /4 */
- };
-const osc_config_t oscConfig_BOARD_BootClockRUN =
- {
- .freq = 8000000U, /* Oscillator frequency: 8000000Hz */
- .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
- .workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
- .oscerConfig =
- {
- .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
- }
- };
-
-
-/*******************************************************************************
- * Code for BOARD_BootClockRUN configuration
- ******************************************************************************/
-void BOARD_BootClockRUN(void)
-{
- /* Set the system clock dividers in SIM to safe value. */
- CLOCK_SetSimSafeDivs();
- /* Initializes OSC0 according to board configuration. */
- CLOCK_InitOsc0(&oscConfig_BOARD_BootClockRUN);
- CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq);
- /* Configure FLL external reference divider (FRDIV). */
- CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockRUN.frdiv);
- /* Set MCG to PEE mode. */
- CLOCK_BootToPeeMode(mcgConfig_BOARD_BootClockRUN.oscsel,
- kMCG_PllClkSelPll0,
- &mcgConfig_BOARD_BootClockRUN.pll0Config);
- /* Set the clock configuration in SIM module. */
- CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
- /* Set SystemCoreClock variable. */
- SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
-}
-
-#if 0
-void BOARD_InitOsc0(void)
-{
- const osc_config_t oscConfig = {.freq = BOARD_XTAL0_CLK_HZ,
- .capLoad = 0,
- .workMode = kOSC_ModeOscLowPower,
- .oscerConfig = {
- .enableMode = kOSC_ErClkEnable,
-#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
- .erclkDiv = 0U,
-#endif
- }};
-
- CLOCK_InitOsc0(&oscConfig);
-
- /* Passing the XTAL0 frequency to clock driver. */
- CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ);
- /* Use RTC_CLKIN input clock directly. */
- //CLOCK_SetXtal32Freq(BOARD_XTAL32K_CLK_HZ);
-}
-
-void BOARD_BootClockRUN(void)
-{
- /*
- * Core clock: 100MHz
- * Bus clock: 50MHz
- */
- mcg_pll_config_t pll0Config = {
- .enableMode = 0U, .prdiv = 0x3U, .vdiv = 0x18U,
- };
- const sim_clock_config_t simConfig = {
- .pllFllSel = 1U, /* PLLFLLSEL select PLL. */
- .er32kSrc = 2U, /* ERCLK32K selection, use RTC. */
- .clkdiv1 = 0x01130000U, /* SIM_CLKDIV1. */
- };
-
- CLOCK_SetSimSafeDivs();
- BOARD_InitOsc0();
-
- CLOCK_CalcPllDiv(BOARD_XTAL0_CLK_HZ, 100000000U, &pll0Config.prdiv, &pll0Config.vdiv);
- CLOCK_BootToPeeMode(kMCG_OscselOsc, kMCG_PllClkSelPll0, &pll0Config);
-
- CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow, 0);
- CLOCK_SetSimConfig(&simConfig);
-
- SystemCoreClock = 100000000U;
-}
-#endif
-
generated by cgit v1.2.3 (git 2.0.4) at 2024-05-23 11:54:34 +0000