diff options
| author | davidcunado-arm <david.cunado@arm.com> | 2017-09-13 14:52:24 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2017-09-13 14:52:24 +0100 |
| commit | f18f5f9867551d0d21da79e25371a298933aaff1 (patch) | |
| tree | 3f4c8c34f2cabb6defdab8389a592c9efe885a0c /docs/cpu-specific-build-macros.rst | |
| parent | a747b08e3a60800178a17cd6621dd5a6f27ae98c (diff) | |
| parent | 96ff26012fceab3e5e3b226cefdbedd0b294f312 (diff) | |
Merge pull request #1092 from jeenu-arm/errata-workarounds
Errata workarounds
Diffstat (limited to 'docs/cpu-specific-build-macros.rst')
| -rw-r--r-- | docs/cpu-specific-build-macros.rst | 16 |
1 files changed, 14 insertions, 2 deletions
diff --git a/docs/cpu-specific-build-macros.rst b/docs/cpu-specific-build-macros.rst index 5738927c..f74b4593 100644 --- a/docs/cpu-specific-build-macros.rst +++ b/docs/cpu-specific-build-macros.rst @@ -21,6 +21,7 @@ by ARM: - `Cortex-A53 MPCore Software Developers Errata Notice`_ - `Cortex-A57 MPCore Software Developers Errata Notice`_ +- `Cortex-A72 MPCore Software Developers Errata Notice`_ The errata workarounds are implemented for a particular revision or a set of processor revisions. This is checked by the reset handler at runtime. Each @@ -30,7 +31,8 @@ errata workaround is ``ERRATA_<Processor name>_<ID>``, where the ``Processor nam is for example ``A57`` for the ``Cortex_A57`` CPU. Refer to the section *CPU errata status reporting* in -`Firmware Design guide`_ for information on to write errata workaround functions. +`Firmware Design guide`_ for information on how to write errata workaround +functions. All workarounds are disabled by default. The platform is responsible for enabling these workarounds according to its requirement by defining the @@ -98,6 +100,15 @@ For Cortex-A57, following errata build flags are defined : - ``ERRATA_A57_833471``: This applies errata 833471 workaround to Cortex-A57 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. +- ``ERRATA_A57_859972``: This applies errata 859972 workaround to Cortex-A57 + CPU. This needs to be enabled only for revision <= r1p3 of the CPU. + + +For Cortex-A72, following errata build flags are defined : + +- ``ERRATA_A72_859971``: This applies errata 859971 workaround to Cortex-A72 + CPU. This needs to be enabled only for revision <= r0p3 of the CPU. + CPU Specific optimizations -------------------------- @@ -131,7 +142,8 @@ architecture that can be enabled by the platform as desired. *Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.* -.. _Cortex-A53 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm048406/index.html +.. _Cortex-A53 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm048406/Cortex_A53_MPCore_Software_Developers_Errata_Notice.pdf .. _Cortex-A57 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm049219/cortex_a57_mpcore_software_developers_errata_notice.pdf +.. _Cortex-A72 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm012079/index.html .. _Firmware Design guide: firmware-design.rst .. _Cortex-A57 Software Optimization Guide: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf |