boards: add toradex verdin imx95 boardmain

Add support for the Toradex Verdin iMX95 board, based on the Toradex
SMARC iMX95 board.
The only modification is the board name, updated to
"tdx-verdin-imx95".

When the UART monitor is enabled, it uses SoC UART2, which is connected
to Verdin UART_4. This UART, on Verdin family, can be used as the
realtime OS debug. Anyway, when the debug monitor is not activated, the
UART is free.

Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>

29 files changed, 8007 insertions, 0 deletions

diff --git a/boards/tdx-verdin-imx95/board.c b/boards/tdx-verdin-imx95/board.c
new file mode 100755
index 0000000..55bd498
--- /dev/null
+++ b/boards/tdx-verdin-imx95/board.c
@@ -0,0 +1,576 @@
+/*
+ * Copyright 2023-2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "sm.h"
+#include "board.h"
+#include "brd_sm_voltage.h"
+#include "fsl_lpuart.h"
+#include "fsl_lpi2c.h"
+#include "fsl_ccm.h"
+#include "fsl_clock.h"
+#include "fsl_bbnsm.h"
+#include "fsl_reset.h"
+#include "fsl_sysctr.h"
+#include "fsl_systick.h"
+#include "fsl_wdog32.h"
+#include "fsl_cache.h"
+#include "fsl_iomuxc.h"
+#include "fsl_fro.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* External board-level clock rates */
+#define BOARD_EXT_CLK_RATE          25000000UL  /* 25MHz */
+
+/* ADC clck rate */
+#define BOARD_ADC_CLK_RATE          80000000UL  /* 80MHz */
+
+/* SM SysTick parameters */
+#define BOARD_SYSTICK_CLKSRC    0U                      /* 0 = external ref  */
+#define BOARD_SYSTICK_CLK_ROOT  CLOCK_ROOT_M33SYSTICK   /* Dedicated CCM root */
+
+/* SM WDOG */
+#define BOARD_WDOG_BASE_PTR         WDOG2
+#define BOARD_WDOG_IRQn             WDOG2_IRQn
+#define BOARD_WDOG_CLK_SRC          kWDOG32_ClockSource1  /* lpo_clk @ 32K */
+#define BOARD_WDOG_TIMEOUT          0xFFFFU  /* 65535 ticks @ 32K = 2 sec */
+#define BOARD_WDOG_SRMASK           (1UL << RST_REASON_WDOG2)
+#define BOARD_WDOG_ANY_INIT         ~(BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG2_MASK)
+#define BOARD_WDOG_ANY_MASK         BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG2_MASK
+#define BOARD_WDOG_IPG_DEBUG        BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_WDOG2_MASK
+
+/* Board UART */
+#ifdef INC_LIBC
+#define BOARD_UART                  BOARD_DEBUG_UART_INSTANCE
+#else
+#define BOARD_UART                  0U
+#endif
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+static wdog32_config_t s_wdogConfig;
+
+/* Debug UART base pointer list */
+static LPUART_Type *const s_uartBases[] = LPUART_BASE_PTRS;
+
+/* Debug UART base pointer list */
+static IRQn_Type const s_uartIrqs[] = LPUART_RX_TX_IRQS;
+
+/* Debug UART clock list */
+static uint32_t const s_uartClks[] =
+{
+    0U,
+    CLOCK_ROOT_LPUART1,
+    CLOCK_ROOT_LPUART2,
+    CLOCK_ROOT_LPUART3,
+    CLOCK_ROOT_LPUART4,
+    CLOCK_ROOT_LPUART5,
+    CLOCK_ROOT_LPUART6,
+    CLOCK_ROOT_LPUART7,
+    CLOCK_ROOT_LPUART8
+};
+
+/* Debug UART peripheral LPI list */
+static uint32_t const s_uartPerLpi[] =
+{
+    0U,
+    CPU_PER_LPI_IDX_LPUART1,
+    CPU_PER_LPI_IDX_LPUART2,
+    CPU_PER_LPI_IDX_LPUART3,
+    CPU_PER_LPI_IDX_LPUART4,
+    CPU_PER_LPI_IDX_LPUART5,
+    CPU_PER_LPI_IDX_LPUART6,
+    CPU_PER_LPI_IDX_LPUART7,
+    CPU_PER_LPI_IDX_LPUART8
+};
+
+/* Debug UART configuration info */
+static board_uart_config_t const s_uartConfig =
+{
+    .base = s_uartBases[BOARD_UART],
+    .irq = s_uartIrqs[BOARD_UART],
+    .clockId = s_uartClks[BOARD_UART],
+    .perLpiId = s_uartPerLpi[BOARD_UART],
+    .baud = BOARD_DEBUG_UART_BAUDRATE,
+    .inst = BOARD_UART
+};
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*--------------------------------------------------------------------------*/
+/* Configure CM33 MPU and XCACHE controller                                 */
+/*--------------------------------------------------------------------------*/
+void BOARD_ConfigMPU(void)
+{
+    uint8_t attr;
+
+    /* Disable code cache(ICache) and system cache(DCache) */
+    XCACHE_DisableCache(LPCAC_PC);
+    XCACHE_DisableCache(LPCAC_PS);
+
+    /* NOTE: All TCRAM is non-cacheable regardless of MPU setting. */
+
+    /*
+     * default cache policy(default memory access behavior) after enable
+     * mpu on cortex-m33(according to RM of cortex-m33):
+     * 0x00000000-0x1FFFFFFF Normal memory, Non-shareable, Write-Through,
+     *                       not Write Allocate
+     * 0x20000000-0x3FFFFFFF Normal memory, Non-shareable, Write-Back,
+     *                       Write Allocate
+     * 0x40000000-0x5FFFFFFF Device, Shareable
+     * 0x60000000-0x7FFFFFFF Normal memory, Non-shareable, Write-Back,
+     *                       Write Allocate
+     * 0x80000000-0x9FFFFFFF Normal memory, Non-shareable, Write-Through,
+     *                       not Write Allocate
+     * 0xA0000000-0xDFFFFFFF Device, Shareable
+     * 0xE0000000-0xE003FFFF Device, Shareable
+     * 0xE0040000-0xE0043FFF Device, Shareable
+     * 0xE0044000-0xE00EFFFF Device, Shareable
+     * 0xF0000000-0xFFFFFFFF Device, Shareable
+     */
+    /* Disable MPU */
+    ARM_MPU_Disable();
+
+    /* Attr0: Device-nGnRnE */
+    // coverity[misra_c_2012_rule_14_3_violation:FALSE]
+    ARM_MPU_SetMemAttr(0U, ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE,
+        ARM_MPU_ATTR_DEVICE));
+
+    /* Attr1: Normal memory, Outer non-cacheable, Inner non-cacheable */
+    // coverity[misra_c_2012_rule_14_3_violation:FALSE]
+    ARM_MPU_SetMemAttr(1U, ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE,
+        ARM_MPU_ATTR_NON_CACHEABLE));
+
+    /* Attr2: Normal memory, Inner write-through transient, read allocate.
+     * Inner write-through transient, read allocate
+     */
+    attr = ARM_MPU_ATTR_MEMORY_(0U, 0U, 1U, 0U);
+    ARM_MPU_SetMemAttr(2U, ARM_MPU_ATTR(attr, attr));
+
+    /* Attr3: Normal memory, Outer write-back transient, read/write allocate.
+     * Inner write-back transient, read/write
+     * allocate */
+    attr = ARM_MPU_ATTR_MEMORY_(0U, 1U, 1U, 1U);
+    ARM_MPU_SetMemAttr(3U, ARM_MPU_ATTR(attr, attr));
+
+    /*
+     * Change macro definitions as follows when choose cache policy
+     * as non-cacheable:
+     * #define DDR_NONCACHEABLE (1U)
+     * #define DDR_WRITE_THROUGH (0U)
+     * #define DDR_WRITE_BACK (0U)
+     *
+     *
+     * Change macro definitions as follows when choose cache policy
+     * as Write-Through:
+     * #define DDR_NONCACHEABLE (0U)
+     * #define DDR_WRITE_THROUGH (1U)
+     * #define DDR_WRITE_BACK (0U)
+     *
+     *
+     * Change macro definitions as follows when choose cache policy
+     * as Write-Back:
+     * #define DDR_NONCACHEABLE (0U)
+     * #define DDR_WRITE_THROUGH (0U)
+     * #define DDR_WRITE_BACK (1U)
+     */
+#define DDR_NONCACHEABLE  (1U)
+#define DDR_WRITE_THROUGH (0U)
+#define DDR_WRITE_BACK    (0U)
+#if DDR_NONCACHEABLE
+    /* NOTE: DDR is used as shared memory for A/M core communication,
+     * set it to non-cacheable. */
+    /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable,
+     * read/write, any privileged, executable. Attr 1 (non-cacheable). */
+    ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000U, ARM_MPU_SH_OUTER, 0U,
+        1U, 0U), ARM_MPU_RLAR(0xDFFFFFFFU, 1U));
+#elif DDR_WRITE_THROUGH
+    /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write,
+     * any privileged, executable. Attr 2
+     * (Normal memory, Inner write-through transient, read allocate. Inner
+     * write-through transient, read allocate). */
+    ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000U, ARM_MPU_SH_OUTER, 0U,
+        1U, 0U), ARM_MPU_RLAR(0xDFFFFFFFU, 2U));
+#elif DDR_WRITE_BACK
+    /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write,
+     * any privileged, executable. Attr 3
+     * (Normal memory, Outer write-back transient, read/write allocate. Inner
+     * write-back transient, read/write allocate). */
+    ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000U, ARM_MPU_SH_OUTER, 0U,
+        1U, 0U), ARM_MPU_RLAR(0xDFFFFFFFU, 3U));
+#endif
+
+#define OCRAM_NONCACHEABLE  (1U)
+#define OCRAM_WRITE_THROUGH (0U)
+#define OCRAM_WRITE_BACK    (0U)
+#if OCRAM_NONCACHEABLE
+    /* Region 1: [0x20480000, 0x2051FFFF](OCRAM), outer shareable, read/write,
+     * any privileged, executable. Attr 1 (non-cacheable). */
+    ARM_MPU_SetRegion(1U, ARM_MPU_RBAR(0x20480000U, ARM_MPU_SH_OUTER, 0U,
+        1U, 0U), ARM_MPU_RLAR(0x2051FFFFU, 1U));
+#elif OCRAM_WRITE_THROUGH
+    /* Region 1: [0x20480000, 0x2051FFFF](OCRAM), outer shareable,
+     * read/write, any privileged, executable. Attr 2 (Normal memory, Inner
+     * write-through transient, read allocate. Inner write-through transient,
+     * read allocate). */
+    ARM_MPU_SetRegion(1U, ARM_MPU_RBAR(0x20480000U, ARM_MPU_SH_OUTER, 0U,
+        1U, 0U), ARM_MPU_RLAR(0x2051FFFFU, 2U));
+#elif OCRAM_WRITE_BACK
+    /* Region 1: [0x20480000, 0x2051FFFF](OCRAM), outer shareable,
+     * read/write, any privileged, executable. Attr 3 (Normal memory,
+     * Outer write-back transient, read/write allocate. Inner write-back
+     * transient, read/write allocate). */
+    ARM_MPU_SetRegion(1U, ARM_MPU_RBAR(0x20480000U, ARM_MPU_SH_OUTER, 0U,
+        1U, 0U), ARM_MPU_RLAR(0x2051FFFFU, 3U));
+#endif
+
+    /* Enable MPU(use default memory map when access the memory within
+     * region) */
+    ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
+
+    /* Enable ICache and DCache */
+    XCACHE_EnableCache(LPCAC_PC);
+    XCACHE_EnableCache(LPCAC_PS);
+}
+
+/*--------------------------------------------------------------------------*/
+/* Initialize clocking                                                      */
+/*--------------------------------------------------------------------------*/
+void BOARD_InitClocks(void)
+{
+    uint32_t fuseTrim = FSB->FUSE[FSB_FUSE_ANA_CFG4];
+
+    if (fuseTrim == 0U)
+    {
+        /* Enable the FRO clock with default value */
+        (void)FRO_SetEnable(true);
+    }
+    else
+    {
+        /* Set the Trim value read from the fuses */
+        bool status = FRO_SetTrim(fuseTrim);
+
+        if (status)
+        {
+            /* Enable the FRO clock with default value */
+            (void) FRO_SetEnable(true);
+        }
+    }
+
+    /* Configure default EXT_CLK1 rate tied to XTAL_OUT/EXT_CLK pin */
+    (void) CLOCK_SourceSetRate(CLOCK_SRC_EXT1, BOARD_EXT_CLK_RATE, 0U);
+
+    /* Configure ADC clock */
+    (void) CCM_RootSetParent(CLOCK_ROOT_ADC, CLOCK_SRC_SYSPLL1_PFD1_DIV2);
+    (void) CCM_RootSetRate(CLOCK_ROOT_ADC, BOARD_ADC_CLK_RATE,
+        CLOCK_ROUND_RULE_CEILING);
+}
+
+/*--------------------------------------------------------------------------*/
+/* Return the debug UART info                                               */
+/*--------------------------------------------------------------------------*/
+const board_uart_config_t *BOARD_GetDebugUart(void)
+{
+    return &s_uartConfig;
+}
+
+/*--------------------------------------------------------------------------*/
+/* Initialize debug console                                                 */
+/*--------------------------------------------------------------------------*/
+void BOARD_InitDebugConsole(void)
+{
+    if (s_uartConfig.base != NULL)
+    {
+        uint64_t rate = CCM_RootGetRate(s_uartConfig.clockId);
+
+        /* Configure debug UART */
+        lpuart_config_t lpuart_config;
+        LPUART_GetDefaultConfig(&lpuart_config);
+        lpuart_config.baudRate_Bps = s_uartConfig.baud;
+        lpuart_config.rxFifoWatermark = ((uint8_t)
+            FSL_FEATURE_LPUART_FIFO_SIZEn(s_uartConfig.base)) - 1U;
+        lpuart_config.txFifoWatermark = ((uint8_t)
+            FSL_FEATURE_LPUART_FIFO_SIZEn(s_uartConfig.base)) - 1U;
+        lpuart_config.enableTx = true;
+        lpuart_config.enableRx = true;
+        (void) LPUART_Init(s_uartConfig.base, &lpuart_config,
+            (uint32_t) rate & 0xFFFFFFFFU);
+    }
+}
+
+/*--------------------------------------------------------------------------*/
+/* Initialize IRQ handlers                                                  */
+/*--------------------------------------------------------------------------*/
+void BOARD_InitHandlers(void)
+{
+    /* Configure default priority of exceptions and IRQs */
+    for (int32_t irq = ((int32_t) SVCall_IRQn); irq < ((int32_t)
+        NUMBER_OF_INT_VECTORS); irq++)
+    {
+        // coverity[misra_c_2012_rule_10_5_violation:FALSE]
+        NVIC_SetPriority((IRQn_Type) irq, IRQ_PRIO_NOPREEMPT_NORMAL);
+    }
+
+    /* Configure SWI handler */
+    NVIC_EnableIRQ(BOARD_SWI_IRQn);
+
+    /* Enable BBNSM handler */
+    NVIC_EnableIRQ(BBNSM_IRQn);
+
+    /* Enable GPC SM handler */
+    NVIC_SetPriority(GPC_SM_REQ_IRQn, IRQ_PRIO_NOPREEMPT_VERY_HIGH);
+    NVIC_EnableIRQ(GPC_SM_REQ_IRQn);
+
+    /* Enable ELE Group IRQ handlers */
+    NVIC_EnableIRQ(ELE_Group1_IRQn);
+    NVIC_EnableIRQ(ELE_Group2_IRQn);
+    NVIC_EnableIRQ(ELE_Group3_IRQn);
+
+    /* Enable FCCU handler */
+    NVIC_SetPriority(FCCU_INT0_IRQn, IRQ_PRIO_NOPREEMPT_CRITICAL);
+    NVIC_EnableIRQ(FCCU_INT0_IRQn);
+}
+
+/*--------------------------------------------------------------------------*/
+/* Initialize timers                                                        */
+/*--------------------------------------------------------------------------*/
+void BOARD_InitTimers(void)
+{
+    /* Configure and enable the BBNSM RTC */
+    bbnsm_rtc_config_t rtcConfig;
+    BBNSM_RTC_GetDefaultConfig(&rtcConfig);
+    BBNSM_RTC_Init(BBNSM, &rtcConfig);
+
+    /* Configure and enable system counter */
+    SYSCTR_Init();
+
+    /* Configure and enable M33 SysTick */
+    uint64_t rate = CCM_RootGetRate(BOARD_SYSTICK_CLK_ROOT);
+    uint32_t reloadVal = (uint32_t) (rate & 0xFFFFFFFFU);
+    reloadVal = ((reloadVal * BOARD_TICK_PERIOD_MSEC) + 999U) / 1000U;
+    SYSTICK_Init(1U, BOARD_SYSTICK_CLKSRC, (uint32_t) (rate & 0xFFFFFFFFU),
+        reloadVal);
+    NVIC_EnableIRQ(SysTick_IRQn);
+
+    /* Configure and enable the WDOG */
+    WDOG32_GetDefaultConfig(&s_wdogConfig);
+    s_wdogConfig.clockSource = BOARD_WDOG_CLK_SRC;
+    s_wdogConfig.timeoutValue = BOARD_WDOG_TIMEOUT;
+    s_wdogConfig.enableInterrupt = true;
+    WDOG32_Init(BOARD_WDOG_BASE_PTR, &s_wdogConfig);
+    NVIC_SetPriority(BOARD_WDOG_IRQn, IRQ_PRIO_PREEMPT_CRITICAL);
+
+    /* Configure to just non-FCCU SM watchdogs */
+    BLK_CTRL_S_AONMIX->WDOG_ANY_MASK = BOARD_WDOG_ANY_INIT;
+
+    /* Switch WDOG to COLD mode */
+    BOARD_WdogModeSet(BOARD_WDOG_MODE_COLD);
+
+    /* Halt SM WDOG on M33 debug entry */
+    BLK_CTRL_NS_AONMIX->IPG_DEBUG_CM33 = (BOARD_WDOG_IPG_DEBUG);
+
+    /* Halt CM7 WDOG on CM7 debug entry */
+    BLK_CTRL_WAKEUPMIX->IPG_DEBUG_CM7 =
+        BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_WDOG5_MASK;
+}
+
+/*--------------------------------------------------------------------------*/
+/* Set watchdog mode                                                        */
+/*--------------------------------------------------------------------------*/
+void BOARD_WdogModeSet(uint32_t mode)
+{
+    switch (mode)
+    {
+        case BOARD_WDOG_MODE_WARM: /* warm */
+            /* Allow WDOG to generate internal warm reset */
+            SRC_GEN->SRMASK &= (~BOARD_WDOG_SRMASK);
+
+            /* Enable WDOG interrupt */
+            NVIC_EnableIRQ(BOARD_WDOG_IRQn);
+
+            /* Disable WDOG_ANY */
+            BLK_CTRL_S_AONMIX->WDOG_ANY_MASK |= BOARD_WDOG_ANY_MASK;
+
+            /* Drive WDOG_ANY from WDOG */
+            IOMUXC_SetPinMux(IOMUXC_PAD_WDOG_ANY__WDOG_ANY, 0U);
+            break;
+        case BOARD_WDOG_MODE_COLD: /* cold */
+            /* Allow WDOG to generate internal warm reset */
+            SRC_GEN->SRMASK &= (~BOARD_WDOG_SRMASK);
+
+            /* Enable WDOG interrupt */
+            NVIC_EnableIRQ(BOARD_WDOG_IRQn);
+
+            /* Enable WDOG_ANY */
+            BLK_CTRL_S_AONMIX->WDOG_ANY_MASK &= ~BOARD_WDOG_ANY_MASK;
+
+            /* Drive WDOG_ANY from WDOG */
+            IOMUXC_SetPinMux(IOMUXC_PAD_WDOG_ANY__WDOG_ANY, 0U);
+            break;
+        case BOARD_WDOG_MODE_IRQ: /* irq */
+            /* Enable WDOG interrupt */
+            NVIC_EnableIRQ(BOARD_WDOG_IRQn);
+
+            /* Disallow WDOG to generate internal warm reset */
+            SRC_GEN->SRMASK |= BOARD_WDOG_SRMASK;
+
+            /* Disable WDOG_ANY */
+            BLK_CTRL_S_AONMIX->WDOG_ANY_MASK |= BOARD_WDOG_ANY_MASK;
+
+            /* Drive WDOG_ANY from WDOG */
+            IOMUXC_SetPinMux(IOMUXC_PAD_WDOG_ANY__WDOG_ANY, 0U);
+            break;
+        case BOARD_WDOG_MODE_OFF:  /* off */
+            s_wdogConfig.enableWdog32 = false;
+            WDOG32_Deinit(BOARD_WDOG_BASE_PTR);
+            break;
+        case BOARD_WDOG_MODE_TRIGGER: /* trigger */
+            BOARD_WDOG_BASE_PTR->CNT = 0U;
+            break;
+        case BOARD_WDOG_MODE_FCCU: /* fccu */
+            /* Drive WDOG_ANY from FCCU */
+            IOMUXC_SetPinMux(IOMUXC_PAD_WDOG_ANY__FCCU_EOUT1, 0U);
+
+            /* Disallow WDOG to generate internal warm reset */
+            SRC_GEN->SRMASK |= BOARD_WDOG_SRMASK;
+
+            /* Disable WDOG interrupt */
+            NVIC_DisableIRQ(BOARD_WDOG_IRQn);
+            break;
+        default:
+            ; /* Intentional empty default */
+            break;
+    }
+}
+
+/*--------------------------------------------------------------------------*/
+/* Kick the watchdog timer                                                  */
+/*--------------------------------------------------------------------------*/
+void BOARD_WdogRefresh(void)
+{
+    WDOG32_Refresh(BOARD_WDOG_BASE_PTR);
+}
+
+/*--------------------------------------------------------------------------*/
+/* Initialize serial bus for external devices                               */
+/*--------------------------------------------------------------------------*/
+void BOARD_InitSerialBus(void)
+{
+    static LPI2C_Type *const s_i2cBases[] = LPI2C_BASE_PTRS;
+    LPI2C_Type *base = s_i2cBases[BOARD_I2C_INSTANCE];
+    lpi2c_master_config_t lpi2cConfig = {0};
+    static uint32_t const s_i2cClks[] =
+    {
+        0U,
+        CLOCK_ROOT_LPI2C1,
+        CLOCK_ROOT_LPI2C2
+    };
+    uint32_t clockId = s_i2cClks[BOARD_I2C_INSTANCE];
+
+    uint32_t rate = (uint32_t) CCM_RootGetRate(clockId);
+
+    LPI2C_MasterGetDefaultConfig(&lpi2cConfig);
+
+    lpi2cConfig.baudRate_Hz = BOARD_I2C_BAUDRATE;
+    lpi2cConfig.enableDoze = false;
+
+    LPI2C_MasterInit(base, &lpi2cConfig, rate);
+}
+
+/*--------------------------------------------------------------------------*/
+/* System sleep prepare                                                     */
+/*--------------------------------------------------------------------------*/
+void BOARD_SystemSleepPrepare(uint32_t sleepMode, uint32_t sleepFlags)
+{
+    BRD_SM_VoltageSuspend(true);
+
+    /* Configure SM LPUART for wakeup */
+    if (s_uartConfig.base != NULL)
+    {
+        /* Enable edge-detect IRQ */
+        (void) LPUART_ClearStatusFlags(s_uartConfig.base,
+            (uint32_t)kLPUART_RxActiveEdgeFlag);
+        LPUART_EnableInterrupts(s_uartConfig.base,
+            (uint32_t)kLPUART_RxActiveEdgeInterruptEnable);
+        NVIC_EnableIRQ(s_uartConfig.irq);
+
+        /* Configure LPI of SM LPUART */
+        (void) CPU_PerLpiConfigSet(CPU_IDX_M33P, s_uartConfig.perLpiId,
+            CPU_PER_LPI_ON_RUN_WAIT_STOP);
+    }
+
+    /* Configure LPI for GPIO1 */
+    (void) CPU_PerLpiConfigSet(CPU_IDX_M33P, CPU_PER_LPI_IDX_GPIO1,
+        CPU_PER_LPI_ON_RUN_WAIT_STOP);
+}
+
+/*--------------------------------------------------------------------------*/
+/* System sleep entry                                                       */
+/*--------------------------------------------------------------------------*/
+void BOARD_SystemSleepEnter(uint32_t sleepMode, uint32_t sleepFlags)
+{
+    /* Disable SysTick */
+    uint32_t sysTickMask = SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk;
+    SysTick->CTRL &= (~sysTickMask);
+
+    /* Clear pending SysTick exception */
+    SCB->ICSR = SCB_ICSR_PENDSTCLR_Msk;
+
+    if (s_wdogConfig.enableWdog32)
+    {
+        /* Disable WDOG */
+        WDOG32_Deinit(BOARD_WDOG_BASE_PTR);
+
+        /* Waits for new configuration to take effect. */
+        while (0U == ((BOARD_WDOG_BASE_PTR->CS) & WDOG_CS_RCS_MASK))
+        {
+            ; /* Intentional empty while */
+        }
+    }
+}
+
+/*--------------------------------------------------------------------------*/
+/* System sleep exit                                                        */
+/*--------------------------------------------------------------------------*/
+void BOARD_SystemSleepExit(uint32_t sleepMode, uint32_t sleepFlags)
+{
+    if (s_wdogConfig.enableWdog32)
+    {
+        /* Enable WDOG */
+        WDOG32_Init(BOARD_WDOG_BASE_PTR, &s_wdogConfig);
+    }
+
+    /* Enable SysTick */
+    uint32_t sysTickMask = SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk;
+    SysTick->VAL   = 0U;
+    SysTick->CTRL |= (sysTickMask);
+}
+
+/*--------------------------------------------------------------------------*/
+/* System sleep unprepare                                                   */
+/*--------------------------------------------------------------------------*/
+void BOARD_SystemSleepUnprepare(uint32_t sleepMode, uint32_t sleepFlags)
+{
+    BRD_SM_VoltageRestore();
+
+    /* Service SM LPUART wakeup events */
+    if (s_uartConfig.base != NULL)
+    {
+        (void) LPUART_ClearStatusFlags(s_uartConfig.base,
+            (uint32_t)kLPUART_RxActiveEdgeFlag);
+        LPUART_DisableInterrupts(s_uartConfig.base,
+            (uint32_t)kLPUART_RxActiveEdgeInterruptEnable);
+
+        NVIC_DisableIRQ(s_uartConfig.irq);
+        NVIC_ClearPendingIRQ(s_uartConfig.irq);
+    }
+}
+
diff --git a/boards/tdx-verdin-imx95/board.h b/boards/tdx-verdin-imx95/board.h
new file mode 100755
index 0000000..3cddd2f
--- /dev/null
+++ b/boards/tdx-verdin-imx95/board.h
@@ -0,0 +1,164 @@
+/*
+ * Copyright 2023-2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef BOARD_H
+#define BOARD_H
+
+#include "fsl_common.h"
+#include "config_board.h"
+#include "dev_sm.h"
+
+/*!
+ * @addtogroup BRD_SM_TDXVERDINIMX95
+ * @{
+ *
+ * @file
+ * @brief
+ *
+ * Header file containing the board API.
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @name Board general parameters
+ */
+/** @{ */
+#define BOARD_TICK_PERIOD_MSEC  10U                       /*!< Tick period */
+#define BOARD_SWI_IRQn          Reserved110_IRQn          /*!< SWI IRQ */
+#define BOARD_HAS_WDOG                                    /*!< Has a watchdog */
+#define BOARD_HAS_PMIC                                    /*!< Has a PMIC */
+#define BOARD_PMIC_RESUME_TICKS ((20U * 32768U) / 10000U) /*!< 2ms in 32K ticks */
+/** @} */
+
+/*!
+ * @name Board PF09 OTP voltages (uV)
+ */
+/** @{ */
+#define BOARD_VOLT_SOC  920000  /*!< SOC OTP */
+#define BOARD_VOLT_ARM  920000  /*!< ARM OTP */
+/** @} */
+
+/*!
+ * @name Watchdog modes
+ */
+/** @{ */
+#define BOARD_WDOG_MODE_WARM     0U  /*!< Wdog generate warm reset */
+#define BOARD_WDOG_MODE_COLD     1U  /*!< Wdog generate cold reset */
+#define BOARD_WDOG_MODE_IRQ      2U  /*!< Wdog generate IRQ only */
+#define BOARD_WDOG_MODE_OFF      3U  /*!< Wdog disabled */
+#define BOARD_WDOG_MODE_TRIGGER  4U  /*!< Trigger wdog */
+#define BOARD_WDOG_MODE_FCCU     5U  /*!< Wdog generate FCCU fault */
+/** @} */
+
+/*******************************************************************************
+ * Types
+ ******************************************************************************/
+
+/*!
+ * Debug UART configuration info
+ */
+typedef struct
+{
+    LPUART_Type *const base;  /*!< LPUART base pointer */
+    IRQn_Type irq;            /*!< Interrupt number */
+    uint32_t clockId;         /*!< Clock ID */
+    uint32_t perLpiId;        /*!< Peripheral LPI ID */
+    uint32_t baud;            /*!< Baud rate */
+    uint8_t inst;             /*!< Instance number */
+} board_uart_config_t;
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+/*! Configure the M33 MPU */
+void BOARD_ConfigMPU(void);
+
+/*! Init hardware */
+void BOARD_InitHardware(void);
+
+/*! Init clocks */
+void BOARD_InitClocks(void);
+
+/*!
+ * Get a device clock debug UART info.
+ *
+ * This function returns the UART info for the UART used for SM
+ * debug.
+ *
+ * @return Returns the debug UART config info.
+ */
+const board_uart_config_t *BOARD_GetDebugUart(void);
+
+/*! Init the debug UART */
+void BOARD_InitDebugConsole(void);
+
+/*! Init interrupt handlers */
+void BOARD_InitHandlers(void);
+
+/*! Init timers */
+void BOARD_InitTimers(void);
+
+/*! Init serial buses */
+void BOARD_InitSerialBus(void);
+
+/*!
+ * Board-level prepare for system sleep entry
+ *
+ * @param sleepMode  Sleep mode being entered.
+ * @param sleepFlags Sleep flag options.
+ */
+void BOARD_SystemSleepPrepare(uint32_t sleepMode, uint32_t sleepFlags);
+
+/*!
+ * Board-level system sleep entry
+ *
+ * @param sleepMode  Sleep mode being entered.
+ * @param sleepFlags Sleep flag options.
+ */
+void BOARD_SystemSleepEnter(uint32_t sleepMode, uint32_t sleepFlags);
+
+/*!
+ * Board-level system sleep exit
+ *
+ * @param sleepMode  Sleep mode being exited.
+ * @param sleepFlags Sleep flag options.
+ */
+void BOARD_SystemSleepExit(uint32_t sleepMode, uint32_t sleepFlags);
+
+/*!
+ * Board-level unprepare for system sleep entry
+ *
+ * @param sleepMode  Sleep mode being entered.
+ * @param sleepFlags Sleep flag options.
+ */
+void BOARD_SystemSleepUnprepare(uint32_t sleepMode, uint32_t sleepFlags);
+
+/*!
+ * Set the watchdog mode
+ *
+ * @param mode Mode to set.
+ */
+void BOARD_WdogModeSet(uint32_t mode);
+
+/*! Service the watchdog */
+void BOARD_WdogRefresh(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/** @} */
+
+#endif /* BOARD_H */
+
diff --git a/boards/tdx-verdin-imx95/pin_mux.c b/boards/tdx-verdin-imx95/pin_mux.c
new file mode 100755
index 0000000..797150c
--- /dev/null
+++ b/boards/tdx-verdin-imx95/pin_mux.c
@@ -0,0 +1,54 @@
+/*
+ * Copyright 2023 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pin_mux.h"
+#include "board.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void)
+{
+#if (BOARD_DEBUG_UART_INSTANCE == 1U)
+    /* Configure LPUART 1 */
+    IOMUXC_SetPinMux(IOMUXC_PAD_UART1_RXD__LPUART1_RX, 0U);
+    IOMUXC_SetPinConfig(IOMUXC_PAD_UART1_RXD__LPUART1_RX, IOMUXC_PAD_PD(1U));
+
+    IOMUXC_SetPinMux(IOMUXC_PAD_UART1_TXD__LPUART1_TX, 0);
+    IOMUXC_SetPinConfig(IOMUXC_PAD_UART1_TXD__LPUART1_TX, IOMUXC_PAD_DSE(0xFU));
+#elif (BOARD_DEBUG_UART_INSTANCE == 2U)
+    /* Configure LPUART 2 */
+    IOMUXC_SetPinMux(IOMUXC_PAD_UART2_RXD__LPUART2_RX, 0);
+    IOMUXC_SetPinConfig(IOMUXC_PAD_UART2_RXD__LPUART2_RX, IOMUXC_PAD_PD(1U));
+
+    IOMUXC_SetPinMux(IOMUXC_PAD_UART2_TXD__LPUART2_TX, 0);
+    IOMUXC_SetPinConfig(IOMUXC_PAD_UART2_TXD__LPUART2_TX, IOMUXC_PAD_DSE(0xFU));
+#endif
+
+#if (BOARD_I2C_INSTANCE == 1U)
+    /* Configure LPI2C 1 */
+    IOMUXC_SetPinMux(IOMUXC_PAD_I2C1_SCL__LPI2C1_SCL, 1U);
+    IOMUXC_SetPinConfig(IOMUXC_PAD_I2C1_SCL__LPI2C1_SCL, IOMUXC_PAD_DSE(0xFU)
+        | IOMUXC_PAD_FSEL1(0x3U) | IOMUXC_PAD_PU(0x1U) | IOMUXC_PAD_OD(0x1U));
+
+    IOMUXC_SetPinMux(IOMUXC_PAD_I2C1_SDA__LPI2C1_SDA, 1U);
+    IOMUXC_SetPinConfig(IOMUXC_PAD_I2C1_SDA__LPI2C1_SDA, IOMUXC_PAD_DSE(0xFU)
+        | IOMUXC_PAD_FSEL1(0x3U) | IOMUXC_PAD_PU(0x1U) | IOMUXC_PAD_OD(0x1U));
+#elif (BOARD_I2C_INSTANCE == 2U)
+    /* Configure LPI2C 2 */
+    IOMUXC_SetPinMux(IOMUXC_PAD_I2C2_SCL__LPI2C2_SCL, 1U);
+    IOMUXC_SetPinConfig(IOMUXC_PAD_I2C2_SCL__LPI2C2_SCL, IOMUXC_PAD_DSE(0xFU)
+        | IOMUXC_PAD_FSEL1(0x3U) | IOMUXC_PAD_PU(0x1U) | IOMUXC_PAD_OD(0x1U));
+
+    IOMUXC_SetPinMux(IOMUXC_PAD_I2C2_SDA__LPI2C2_SDA, 1U);
+    IOMUXC_SetPinConfig(IOMUXC_PAD_I2C2_SDA__LPI2C2_SDA, IOMUXC_PAD_DSE(0xFU)
+        | IOMUXC_PAD_FSEL1(0x3U) | IOMUXC_PAD_PU(0x1U) | IOMUXC_PAD_OD(0x1U));
+#endif
+}
+
diff --git a/boards/tdx-verdin-imx95/pin_mux.h b/boards/tdx-verdin-imx95/pin_mux.h
new file mode 100755
index 0000000..4b5940b
--- /dev/null
+++ b/boards/tdx-verdin-imx95/pin_mux.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright 2023 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PIN_MUX_H
+#define PIN_MUX_H
+
+#include "fsl_iomuxc.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*!
+ * @addtogroup BRD_SM_TDXVERDINIMX95
+ * @file
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M33[cm33] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* PIN_MUX_H */
+
diff --git a/boards/tdx-verdin-imx95/sm/Makefile b/boards/tdx-verdin-imx95/sm/Makefile
new file mode 100755
index 0000000..9d7c28f
--- /dev/null
+++ b/boards/tdx-verdin-imx95/sm/Makefile
@@ -0,0 +1,63 @@
+## ###################################################################
+##
+## Copyright 2023 NXP
+##
+## Redistribution and use in source and binary forms, with or without modification,
+## are permitted provided that the following conditions are met:
+##
+## o Redistributions of source code must retain the above copyright notice, this list
+##   of conditions and the following disclaimer.
+##
+## o Redistributions in binary form must reproduce the above copyright notice, this
+##   list of conditions and the following disclaimer in the documentation and/or
+##   other materials provided with the distribution.
+##
+## o Neither the name of the copyright holder nor the names of its
+##   contributors may be used to endorse or promote products derived from this
+##   software without specific prior written permission.
+##
+## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+## WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+## ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+## (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+## ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+## (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+## SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+##
+##
+## ###################################################################
+
+BOARD ?= tdx-verdin-imx95
+BRD_SM_API_DIR = $(ROOT_DIR)/sm/brd
+BOARDS_DIR = $(ROOT_DIR)/boards
+BOARD_DIR = $(BOARDS_DIR)/$(BOARD)
+
+INCLUDE +=  \
+	-I$(BRD_SM_API_DIR)  \
+	-I$(BOARDS_DIR)  \
+	-I$(BOARD_DIR)  \
+	-I$(BOARD_DIR)/sm \
+	-I$(COMPONENTS_DIR)/pf09  \
+	-I$(COMPONENTS_DIR)/pf53
+
+VPATH +=  \
+	$(BRD_SM_API_DIR)  \
+	$(BOARDS_DIR)  \
+	$(BOARD_DIR)  \
+	$(BOARD_DIR)/sm  \
+	$(COMPONENTS_DIR)/pf09  \
+	$(COMPONENTS_DIR)/pf53
+
+OBJS += \
+	$(OUT)/board.o  \
+	$(OUT)/brd_sm.o  \
+	$(OUT)/brd_sm_handlers.o  \
+	$(OUT)/brd_sm_control.o  \
+	$(OUT)/brd_sm_sensor.o  \
+	$(OUT)/brd_sm_voltage.o  \
+	$(OUT)/fsl_pf09.o  \
+	$(OUT)/fsl_pf53.o
+
diff --git a/boards/tdx-verdin-imx95/sm/brd_sm.c b/boards/tdx-verdin-imx95/sm/brd_sm.c
new file mode 100755
index 0000000..5d60d1e
--- /dev/null
+++ b/boards/tdx-verdin-imx95/sm/brd_sm.c
@@ -0,0 +1,686 @@
+/*
+** ###################################################################
+**
+** Copyright 2023-2024 NXP
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** o Redistributions of source code must retain the above copyright notice, this list
+**   of conditions and the following disclaimer.
+**
+** o Redistributions in binary form must reproduce the above copyright notice, this
+**   list of conditions and the following disclaimer in the documentation and/or
+**   other materials provided with the distribution.
+**
+** o Neither the name of the copyright holder nor the names of its
+**   contributors may be used to endorse or promote products derived from this
+**   software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+** ###################################################################
+*/
+
+/*==========================================================================*/
+/* File containing the implementation of the SM abstraction for the board.  */
+/*==========================================================================*/
+
+/* Includes */
+
+#include "sm.h"
+#include "brd_sm.h"
+#include "dev_sm.h"
+#include "lmm.h"
+#include "fsl_lpi2c.h"
+#include "fsl_bbnsm.h"
+#include "fsl_rgpio.h"
+#include "fsl_iomuxc.h"
+
+/* Local defines */
+
+#define BRD_SM_RST_REC_FIRST  4U     /* First GPR for shutdown record */
+#define BRD_SM_RST_REC_NUM    4U     /* Number of GPR for shutdown record */
+
+/* Defines to encode the reason */
+#define BRD_SM_REC_REASON_MASK  (0x000000FFU)
+#define BRD_SM_REC_REASON_SHIFT (0U)
+#define BRD_SM_REC_REASON(x) \
+    (((uint32_t)(((uint32_t)(x)) << BRD_SM_REC_REASON_SHIFT)) & \
+    BRD_SM_REC_REASON_MASK)
+
+/* Defines to encode the error ID */
+#define BRD_SM_REC_EID_MASK  (0x007FFF00U)
+#define BRD_SM_REC_EID_SHIFT (8U)
+#define BRD_SM_REC_EID(x) \
+    (((uint32_t)(((uint32_t)(x)) << BRD_SM_REC_EID_SHIFT)) & \
+    BRD_SM_REC_EID_MASK)
+#define BRD_SM_REC_EID_SIGN  (0x00004000U)
+#define BRD_SM_REC_EID_EXT   (0xFFFF8000U)
+
+/* Defines to encode the valid flag for the errId */
+#define BRD_SM_REC_VERR_MASK  (0x00800000U)
+#define BRD_SM_REC_VERR_SHIFT (23U)
+#define BRD_SM_REC_VERR(x) \
+    (((uint32_t)(((uint32_t)(x)) << BRD_SM_REC_VERR_SHIFT)) & \
+    BRD_SM_REC_VERR_MASK)
+
+/* Defines to encode the source/origin */
+#define BRD_SM_REC_SRC_MASK  (0x0F000000U)
+#define BRD_SM_REC_SRC_SHIFT (24U)
+#define BRD_SM_REC_SRC(x) \
+    (((uint32_t)(((uint32_t)(x)) << BRD_SM_REC_SRC_SHIFT)) & \
+    BRD_SM_REC_SRC_MASK)
+
+/* Defines to encode the valid flag for the source */
+#define BRD_SM_REC_VSRC_MASK  (0x10000000U)
+#define BRD_SM_REC_VSRC_SHIFT (28U)
+#define BRD_SM_REC_VSRC(x) \
+    (((uint32_t)(((uint32_t)(x)) << BRD_SM_REC_VSRC_SHIFT)) & \
+    BRD_SM_REC_VSRC_MASK)
+
+/* Defines to encode the extended info length */
+#define BRD_SM_REC_LEN_MASK  (0x60000000U)
+#define BRD_SM_REC_LEN_SHIFT (29U)
+#define BRD_SM_REC_LEN(x) \
+    (((uint32_t)(((uint32_t)(x)) << BRD_SM_REC_LEN_SHIFT)) & \
+    BRD_SM_REC_LEN_MASK)
+
+/* Defines to encode the valid */
+#define BRD_SM_REC_VLD_MASK  (0x80000000U)
+#define BRD_SM_REC_VLD_SHIFT (31U)
+#define BRD_SM_REC_VLD(x) \
+    (((uint32_t)(((uint32_t)(x)) << BRD_SM_REC_VLD_SHIFT)) & \
+    BRD_SM_REC_VLD_MASK)
+
+/* Performance parameters */
+#define BOARD_PERF_LEVEL  DEV_SM_PERF_LVL_ODV  /* Target perf level */
+#define BOARD_PERF_VDROP  20000                /* Perf voltage drop */
+#if BOARD_VOLT_SOC >= ES_ODV_UV_VDD_SOC
+#define BOARD_BOOT_LEVEL  DEV_SM_PERF_LVL_ODV  /* Boot perf overdrive */
+#elif BOARD_VOLT_SOC >= ES_NOM_UV_VDD_SOC
+#define BOARD_BOOT_LEVEL  DEV_SM_PERF_LVL_NOM  /* Boot perf nominal */
+#else
+#define BOARD_BOOT_LEVEL  DEV_SM_PERF_LVL_LOW  /* Boot perf low */
+#endif
+
+/* Defines to encode the GPIO1 access protection */
+#define GPIO_PCNS_I2C_GP_CK             RGPIO_PCNS_NSE2_MASK
+#define GPIO_PCNS_I2C_GP_DAT            RGPIO_PCNS_NSE3_MASK
+#define GPIO_PCNS_PMIC_RTC_IRQ_N        RGPIO_PCNS_NSE10_MASK
+#define GPIO_PCNS_EC_MCU_INT            RGPIO_PCNS_NSE11_MASK
+#define GPIO_PCNS_CTRL_IO_EXP_INT_B     RGPIO_PCNS_NSE14_MASK
+
+#define GPIO_PCNP_I2C_GP_CK             RGPIO_PCNP_NSE2_MASK
+#define GPIO_PCNP_I2C_GP_DAT            RGPIO_PCNP_NSE3_MASK
+#define GPIO_PCNP_PMIC_RTC_IRQ_N        RGPIO_PCNP_NPE10_MASK
+#define GPIO_PCNP_EC_MCU_INT            RGPIO_PCNP_NPE11_MASK
+#define GPIO_PCNP_CTRL_IO_EXP_INT_B     RGPIO_PCNP_NPE14_MASK
+
+/* Local types */
+
+/* Local variables */
+
+/* Local functions */
+
+static int32_t BRD_SM_InitComplete(uint32_t mSel);
+
+/*--------------------------------------------------------------------------*/
+/* Init board                                                               */
+/*--------------------------------------------------------------------------*/
+// coverity[misra_c_2012_directive_4_6_violation:FALSE]
+int32_t BRD_SM_Init(int argc, const char * const argv[], uint32_t *mSel)
+{
+    int32_t status;
+    uint64_t addr;
+    uint32_t ms;
+    uint32_t flags;
+
+    /* Init board hardware */
+    BOARD_InitHardware();
+
+    /* Get the boot mode select */
+    if (DEV_SM_RomBootCpuGet(DEV_SM_CPU_M33P, &addr, &ms, &flags)
+        == SM_ERR_SUCCESS)
+    {
+        *mSel = ms;
+    }
+
+    /* Initialize devices connected to serial buses (PMIC, IOExp, etc) */
+    status = BRD_SM_SerialDevicesInit();
+
+    if (status == SM_ERR_SUCCESS)
+    {
+        /* Init the device */
+        status = DEV_SM_Init(BOARD_BOOT_LEVEL, BOARD_PERF_LEVEL);
+    }
+
+    if (status == SM_ERR_SUCCESS)
+    {
+        /* Complete board init after device init */
+        status = BRD_SM_InitComplete(*mSel);
+    }
+
+    if (status == SM_ERR_SUCCESS)
+    {
+        /* Disallow ANA TMPSNS to generate internal warm reset */
+        SRC_GEN->SRMASK |= BIT32(RST_REASON_TEMPSENSE);
+
+        /* Switch WDOG to FCCU mode */
+        BOARD_WdogModeSet(BOARD_WDOG_MODE_FCCU);
+    }
+
+    /* Configure non secure non privileged access to
+     * GPIO1 registers and interrupts
+     */
+    GPIO1->PCNS = ( GPIO_PCNS_I2C_GP_CK |
+                    GPIO_PCNS_I2C_GP_DAT |
+                    GPIO_PCNS_PMIC_RTC_IRQ_N |
+                    GPIO_PCNS_EC_MCU_INT |
+                    GPIO_PCNS_CTRL_IO_EXP_INT_B);
+    GPIO1->ICNS = 1;
+    GPIO1->PCNP = ( GPIO_PCNS_I2C_GP_CK |
+                    GPIO_PCNS_I2C_GP_DAT |
+                    GPIO_PCNP_PMIC_RTC_IRQ_N |
+                    GPIO_PCNP_EC_MCU_INT |
+                    GPIO_PCNP_CTRL_IO_EXP_INT_B);
+    GPIO1->ICNP = 1;
+
+    /* TODO: Remove when A0 support dropped */
+    /* Configure ISO controls based on feature fuses */
+    uint32_t ipIsoMask = 0U;
+
+    /* Deassert PCIe ISO if corresponding module is enabled */
+    uint32_t fuseHwCfg2 = FSB->FUSE[FSB_FUSE_HW_CFG2];
+
+    /* PCIe1 is tied to HSIO ISO[0] */
+    if ((fuseHwCfg2 & FSB_FUSE_HW_CFG2_PCIE1_DISABLE_MASK) == 0U)
+    {
+        ipIsoMask |= SRC_XSPR_SLICE_SW_CTRL_ISO_CTRL_0_MASK;
+    }
+
+    /* PCIe2 is tied to HSIO ISO[1] */
+    if ((fuseHwCfg2 & FSB_FUSE_HW_CFG2_PCIE2_DISABLE_MASK) == 0U)
+    {
+        ipIsoMask |= SRC_XSPR_SLICE_SW_CTRL_ISO_CTRL_1_MASK;
+    }
+
+    /* Apply ISO mask */
+    if (ipIsoMask != 0U)
+    {
+        SRC_XSPR_HSIOMIX_TOP->SLICE_SW_CTRL &= (~ipIsoMask);
+    }
+
+    /* Return status */
+    return status;
+}
+
+/*--------------------------------------------------------------------------*/
+/* Exit function                                                            */
+/*--------------------------------------------------------------------------*/
+void BRD_SM_Exit(int32_t status, uint32_t pc)
+{
+#if defined(MONITOR) || defined(RUN_TEST)
+    printf("exit %d, 0x%08X\n", status, pc);
+
+    /* Disable watchdog */
+    BOARD_WdogModeSet(BOARD_WDOG_MODE_OFF);
+#else
+    SM_SYSTEMERROR(status, pc);
+    // coverity[misra_c_2012_rule_2_2_violation:FALSE]
+    SystemExit();
+#endif
+
+    /* Hang */
+    // coverity[infinite_loop:FALSE]
+    while (true)
+    {
+        ; /* Intentional empty while */
+    }
+}
+
+/*--------------------------------------------------------------------------*/
+/* Board timer tick                                                         */
+/*--------------------------------------------------------------------------*/
+void BRD_SM_TimerTick(uint32_t msec)
+{
+    /* Kick the dog */
+    BOARD_WdogRefresh();
+}
+
+/*--------------------------------------------------------------------------*/
+/* Custom monitor function                                                  */
+/*--------------------------------------------------------------------------*/
+int32_t BRD_SM_Custom(int32_t argc, const char * const argv[])
+{
+    return SM_ERR_SUCCESS;
+}
+
+/*--------------------------------------------------------------------------*/
+/* Get fault reaction                                                       */
+/*--------------------------------------------------------------------------*/
+int32_t BRD_SM_FaultReactionGet(dev_sm_rst_rec_t resetRec,
+    // coverity[misra_c_2012_rule_8_13_violation:FALSE]
+    uint32_t *reaction, uint32_t *lm)
+{
+    int32_t status = SM_ERR_SUCCESS;
+
+    /* Print reaction */
+    switch (*reaction)
+    {
+        case LMM_REACT_SYS_RESET:
+        case LMM_REACT_SYS_SHUTDOWN:
+            ; /* Intentional empty as will print elsewhere */
+            break;
+        case LMM_REACT_GRP_RESET:
+            printf("\nReset group %u", *lm);
+            BRD_SM_ResetRecordPrint(",", resetRec);
+            break;
+        case LMM_REACT_GRP_SHUTDOWN:
+            printf("\nShutdown group %u", *lm);
+            BRD_SM_ResetRecordPrint(",", resetRec);
+            break;
+        case LMM_REACT_LM_RESET:
+            printf("\nReset LM %u", *lm);
+            BRD_SM_ResetRecordPrint(",", resetRec);
+            break;
+        case LMM_REACT_LM_SHUTDOWN:
+            printf("\nShutdown LM %u", *lm);
+            BRD_SM_ResetRecordPrint(",", resetRec);
+            break;
+        case LMM_REACT_BOARD:
+            printf("\nBoard %u", *lm);
+            BRD_SM_ResetRecordPrint(",", resetRec);
+            break;
+        case LMM_REACT_FUSA:
+            printf("\nFuSa %u", *lm);
+            BRD_SM_ResetRecordPrint(",", resetRec);
+            break;
+        case LMM_REACT_NONE:
+            ; /* Intentional empty case */
+            break;
+        default:
+            status = SM_ERR_INVALID_PARAMETERS;
+            break;
+    }
+
+    /* Return status */
+    return status;
+}
+
+/*--------------------------------------------------------------------------*/
+/* Custom fault handler                                                     */
+/*--------------------------------------------------------------------------*/
+int32_t BRD_SM_CustomFault(dev_sm_rst_rec_t resetRec, uint32_t lm)
+{
+    /* Return status */
+    return SM_ERR_SUCCESS;
+}
+
+/*--------------------------------------------------------------------------*/
+/* Print reset record                                                       */
+/*--------------------------------------------------------------------------*/
+void BRD_SM_ResetRecordPrint(string name, dev_sm_rst_rec_t resetRec)
+{
+    if (resetRec.valid)
+    {
+        int32_t status;
+        string reasonNameAddr;
+
+        /* Get name */
+        status = LMM_SystemReasonNameGet(0U, resetRec.reason,
+            &reasonNameAddr, NULL);
+
+        /* Print reason */
+        printf("%s reason=", name);
+        if (status == SM_ERR_SUCCESS)
+        {
+            printf("%s", reasonNameAddr);
+        }
+        else
+        {
+            printf("%u", resetRec.reason);
+        }
+        if (resetRec.validErr)
+        {
+            printf(", errId=%d", (int32_t) resetRec.errId);
+        }
+        if (resetRec.validOrigin)
+        {
+            printf(", srcLm=%u", resetRec.origin);
+        }
+        printf("\n");
+
+        /* Print extended info */
+        for (uint32_t ex = 0U; ex < resetRec.extLen; ex++)
+        {
+            printf("  0x%08X\n", resetRec.extInfo[ex]);
+        }
+    }
+}
+
+/*--------------------------------------------------------------------------*/
+/* Load and clear persistent shutdown record of previous boot               */
+/*--------------------------------------------------------------------------*/
+void BRD_SM_ShutdownRecordLoad(dev_sm_rst_rec_t *shutdownRec)
+{
+#if BRD_SM_RST_REC_NUM > 0
+    uint32_t hdr = 0U;
+    uint32_t *ePtr = &(shutdownRec->extInfo[0]);
+
+    /* Read and clear header */
+    (void) BBNSM_GprGetValue(BBNSM, BRD_SM_RST_REC_FIRST, &hdr);
+    (void) BBNSM_GprSetValue(BBNSM, BRD_SM_RST_REC_FIRST, 0U);
+
+    /* Valid? */
+    if (((hdr & BRD_SM_REC_VLD_MASK ) >> BRD_SM_REC_VLD_SHIFT) != 0U)
+    {
+        shutdownRec->valid = true;
+
+        /* Parse header */
+        shutdownRec->reason = (hdr & BRD_SM_REC_REASON_MASK ) >>
+            BRD_SM_REC_REASON_SHIFT;
+        shutdownRec->errId = (hdr & BRD_SM_REC_EID_MASK ) >>
+            BRD_SM_REC_EID_SHIFT;
+        shutdownRec->validErr = ((hdr & BRD_SM_REC_VERR_MASK ) != 0U);
+        shutdownRec->origin = (hdr & BRD_SM_REC_SRC_MASK ) >>
+            BRD_SM_REC_SRC_SHIFT;
+        shutdownRec->validOrigin = ((hdr & BRD_SM_REC_VSRC_MASK ) != 0U);
+        shutdownRec->extLen = (hdr & BRD_SM_REC_LEN_MASK ) >>
+            BRD_SM_REC_LEN_SHIFT;
+
+        /* Sign extend */
+        if ((shutdownRec->errId & BRD_SM_REC_EID_SIGN) != 0U)
+        {
+            shutdownRec->errId |= BRD_SM_REC_EID_EXT;
+        }
+
+        shutdownRec->extLen = MIN(shutdownRec->extLen, DEV_SM_NUM_EXT_INFO);
+    }
+
+    /* Copy out extended info */
+    for (uint8_t idx = 1U; idx < BRD_SM_RST_REC_NUM; idx++)
+    {
+        if (idx <= shutdownRec->extLen)
+        {
+            (void) BBNSM_GprGetValue(BBNSM, idx + BRD_SM_RST_REC_FIRST,
+                ePtr);
+            ePtr++;
+        }
+        else
+        {
+            break;
+        }
+    }
+#endif
+
+    /* PMIC reset? */
+    if ((g_pmicFaultFlags & ~PF09_XRESET_FLG) != 0U)
+    {
+        shutdownRec->valid = true;
+        shutdownRec->reset = true;
+        shutdownRec->reason = DEV_SM_REASON_PMIC;
+        shutdownRec->extLen = 1U;
+        shutdownRec->extInfo[0] = g_pmicFaultFlags;
+    }
+}
+
+/*--------------------------------------------------------------------------*/
+/* Save shutdown record to persistent storage                               */
+/*--------------------------------------------------------------------------*/
+void BRD_SM_ShutdownRecordSave(dev_sm_rst_rec_t shutdownRec)
+{
+#if BRD_SM_RST_REC_NUM > 0
+    uint32_t hdr;
+    const uint32_t *ePtr = &(shutdownRec.extInfo[0]);
+
+    /* Store extended info */
+    for (uint8_t idx = 1U; idx < BRD_SM_RST_REC_NUM; idx++)
+    {
+        if (idx <= shutdownRec.extLen)
+        {
+            (void) BBNSM_GprSetValue(BBNSM, idx + BRD_SM_RST_REC_FIRST,
+                *ePtr);
+            ePtr++;
+        }
+        else
+        {
+            break;
+        }
+    }
+
+    /* Create header */
+    hdr = BRD_SM_REC_REASON(shutdownRec.reason)
+        | BRD_SM_REC_EID(shutdownRec.errId)
+        | BRD_SM_REC_VERR(shutdownRec.validErr ? 1U : 0U)
+        | BRD_SM_REC_SRC(shutdownRec.origin)
+        | BRD_SM_REC_VSRC(shutdownRec.validOrigin ? 1U : 0U)
+        | BRD_SM_REC_LEN(shutdownRec.extLen)
+        | BRD_SM_REC_VLD(shutdownRec.valid ? 1U : 0U);
+
+    /* Save header */
+    (void) BBNSM_GprSetValue(BBNSM, BRD_SM_RST_REC_FIRST, hdr);
+#endif
+
+    /* Print shutdown record */
+    if (shutdownRec.reset)
+    {
+        BRD_SM_ResetRecordPrint("\nReset request:", shutdownRec);
+    }
+    else
+    {
+        BRD_SM_ResetRecordPrint("\nShutdown request:", shutdownRec);
+    }
+}
+
+/*--------------------------------------------------------------------------*/
+/* Reset board                                                              */
+/*--------------------------------------------------------------------------*/
+int32_t BRD_SM_SystemReset(void)
+{
+    int32_t status = SM_ERR_SUCCESS;
+    rgpio_pin_config_t gpioConfig =
+    {
+        kRGPIO_DigitalOutput,
+        0U
+    };
+
+    /* Drive WDOG_ANY to reset PMIC */
+    RGPIO_PinInit(GPIO1, 15U, &gpioConfig);
+    IOMUXC_SetPinMux(IOMUXC_PAD_WDOG_ANY__GPIO1_IO_BIT15, 0U);
+
+    /* Wait for PMIC to react */
+    SystemTimeDelay(1000U);
+
+    /* Fall back to warm reset of the device */
+    status = DEV_SM_SystemReset();
+
+    /* Return status */
+    return status;
+}
+
+/*--------------------------------------------------------------------------*/
+/* Get PMIC info                                                            */
+/*--------------------------------------------------------------------------*/
+int32_t BRD_SM_PmicInfoGet(uint32_t idx, uint8_t *devAddr, uint8_t **info,
+    uint8_t *len)
+{
+    int32_t status = SM_ERR_SUCCESS;
+
+    /* Call PMIC driver to get info */
+    switch (idx)
+    {
+        case 0U:
+            *devAddr = g_pf09Dev.devAddr;
+            if (!PF09_PmicInfoGet(&g_pf09Dev, info, len))
+            {
+                status = SM_ERR_HARDWARE_ERROR;
+            }
+            break;
+        case 1U:
+            *devAddr = g_pf5301Dev.devAddr;
+            if (!PF53_PmicInfoGet(&g_pf5301Dev, info, len))
+            {
+                status = SM_ERR_HARDWARE_ERROR;
+            }
+            break;
+        case 2U:
+            *devAddr = g_pf5302Dev.devAddr;
+            if (!PF53_PmicInfoGet(&g_pf5302Dev, info, len))
+            {
+                status = SM_ERR_HARDWARE_ERROR;
+            }
+            break;
+        default:
+            status = SM_ERR_NOT_FOUND;
+            break;
+    }
+
+    /* Return status */
+    return status;
+}
+
+/*--------------------------------------------------------------------------*/
+/* PMIC register write                                                      */
+/*--------------------------------------------------------------------------*/
+int32_t BRD_SM_PmicWrite(uint8_t devAddr, uint8_t regAddr, uint8_t val,
+    uint8_t mask)
+{
+    int32_t status = SM_ERR_SUCCESS;
+
+    /* Call PF09 driver write data */
+    if (devAddr == g_pf09Dev.devAddr)
+    {
+        if (!PF09_PmicWrite(&g_pf09Dev, regAddr, val, mask))
+        {
+            status = SM_ERR_HARDWARE_ERROR;
+        }
+    }
+    /* Call PF5301 driver write data */
+    else if (devAddr == g_pf5301Dev.devAddr)
+    {
+        if (!PF53_PmicWrite(&g_pf5301Dev, regAddr, val, mask))
+        {
+            status = SM_ERR_HARDWARE_ERROR;
+        }
+    }
+    /* Call PF5302 driver write data */
+    else if (devAddr == g_pf5302Dev.devAddr)
+    {
+        if (!PF53_PmicWrite(&g_pf5302Dev, regAddr, val, mask))
+        {
+            status = SM_ERR_HARDWARE_ERROR;
+        }
+    }
+    /* Invalid device address */
+    else
+    {
+        status = SM_ERR_NOT_FOUND;
+    }
+
+    /* Return status */
+    return status;
+}
+
+/*--------------------------------------------------------------------------*/
+/* PMIC register read                                                       */
+/*--------------------------------------------------------------------------*/
+int32_t BRD_SM_PmicRead(uint8_t devAddr, uint8_t regAddr, uint8_t *val)
+{
+    int32_t status = SM_ERR_SUCCESS;
+
+    /* Call PF09 driver read data */
+    if (devAddr == g_pf09Dev.devAddr)
+    {
+        if (!PF09_PmicRead(&g_pf09Dev, regAddr, val))
+        {
+            status = SM_ERR_HARDWARE_ERROR;
+        }
+    }
+    /* Call PF5301 driver read data */
+    else if (devAddr == g_pf5301Dev.devAddr)
+    {
+        if (!PF53_PmicRead(&g_pf5301Dev, regAddr, val))
+        {
+            status = SM_ERR_HARDWARE_ERROR;
+        }
+    }
+    /* Call PF5302 driver read data */
+    else if (devAddr == g_pf5302Dev.devAddr)
+    {
+        if (!PF53_PmicRead(&g_pf5302Dev, regAddr, val))
+        {
+            status = SM_ERR_HARDWARE_ERROR;
+        }
+    }
+    /* Invalid device address */
+    else
+    {
+        status = SM_ERR_NOT_FOUND;
+    }
+
+    /* Return status */
+    return status;
+}
+
+/*--------------------------------------------------------------------------*/
+/* Set mode of specified SoC supply                                         */
+/*--------------------------------------------------------------------------*/
+int32_t BRD_SM_SupplyModeSet(uint32_t domain, uint8_t voltMode)
+{
+    /* Set voltage mode */
+    return BRD_SM_VoltageModeSet(domain, voltMode);
+}
+
+/*--------------------------------------------------------------------------*/
+/* Get mode of specified SoC supply                                         */
+/*--------------------------------------------------------------------------*/
+int32_t BRD_SM_SupplyModeGet(uint32_t domain, uint8_t *voltMode)
+{
+    /* Get voltage mode */
+    return BRD_SM_VoltageModeGet(domain, voltMode);
+}
+
+/*--------------------------------------------------------------------------*/
+/* Set voltage of specified SoC supply                                      */
+/*--------------------------------------------------------------------------*/
+int32_t BRD_SM_SupplyLevelSet(uint32_t domain, uint32_t microVolt)
+{
+    /* Set voltage level */
+    return BRD_SM_VoltageLevelSet(domain, ((int32_t) microVolt)
+        + BOARD_PERF_VDROP);
+}
+
+/*--------------------------------------------------------------------------*/
+/* Get voltage of specified SoC supply                                      */
+/*--------------------------------------------------------------------------*/
+int32_t BRD_SM_SupplyLevelGet(uint32_t domain, uint32_t *microVolt)
+{
+    /* Get voltage level */
+    return BRD_SM_VoltageLevelGet(domain, (int32_t*) microVolt);
+}
+
+/*==========================================================================*/
+
+/*--------------------------------------------------------------------------*/
+/* Complete init after DEV_SM init                                          */
+/*--------------------------------------------------------------------------*/
+static int32_t BRD_SM_InitComplete(uint32_t mSel)
+{
+    /* Safe to call DEV_SM functions to init hardware. For example, to
+       enabled a power domain, configure a clock SSC, clock rate, or pin.
+       Not safe to call LMM functions! */
+
+    return SM_ERR_SUCCESS;
+}
+
diff --git a/boards/tdx-verdin-imx95/sm/brd_sm.dox b/boards/tdx-verdin-imx95/sm/brd_sm.dox
new file mode 100755
index 0000000..2101f47
--- /dev/null
+++ b/boards/tdx-verdin-imx95/sm/brd_sm.dox
@@ -0,0 +1,55 @@
+/*
+** ###################################################################
+**
+** Copyright 2023 NXP
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** o Redistributions of source code must retain the above copyright notice, this list
+**   of conditions and the following disclaimer.
+**
+** o Redistributions in binary form must reproduce the above copyright notice, this
+**   list of conditions and the following disclaimer in the documentation and/or
+**   other materials provided with the distribution.
+**
+** o Neither the name of the copyright holder nor the names of its
+**   contributors may be used to endorse or promote products derived from this
+**   software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+** ###################################################################
+*/
+
+/*!
+ * @addtogroup BRD_SM
+ * @{
+ */
+
+/*!
+
+@defgroup BRD_SM_TDXVERDINIMX95 BOARD_TDXVERDINIMX95: Toradex Verdin iMX95 SM Implementation
+
+@brief Module for the Toradex Verdin iMX95 for the SM.
+
+Board Module
+============
+
+This port supports i.MX95 on Toradex Verdin iMX95. See
+the @ref PORT_MX95_EVK section for more information.
+
+*/
+
+/** @} */
+
diff --git a/boards/tdx-verdin-imx95/sm/brd_sm.h b/boards/tdx-verdin-imx95/sm/brd_sm.h
new file mode 100755
index 0000000..5a22d61
--- /dev/null
+++ b/boards/tdx-verdin-imx95/sm/brd_sm.h
@@ -0,0 +1,96 @@
+/*
+** ###################################################################
+**
+** Copyright 2023-2024 NXP
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** o Redistributions of source code must retain the above copyright notice, this list
+**   of conditions and the following disclaimer.
+**
+** o Redistributions in binary form must reproduce the above copyright notice, this
+**   list of conditions and the following disclaimer in the documentation and/or
+**   other materials provided with the distribution.
+**
+** o Neither the name of the copyright holder nor the names of its
+**   contributors may be used to endorse or promote products derived from this
+**   software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+** ###################################################################
+*/
+
+#ifndef BRD_SM_H
+#define BRD_SM_H
+
+/*==========================================================================*/
+/*!
+ * @addtogroup BRD_SM_TDXVERDINIMX95
+ * @{
+ *
+ * @file
+ * @brief
+ *
+ * Header file containing the API for the SM abstraction of the board.
+ */
+/*==========================================================================*/
+
+/* Includes */
+
+#include "sm.h"
+#include "brd_sm_handlers.h"
+#include "brd_sm_control.h"
+#include "brd_sm_sensor.h"
+#include "brd_sm_voltage.h"
+#include "board.h"
+#include "brd_sm_api.h"
+
+/* Defines */
+
+/*! Board name string */
+#define BRD_SM_NAME  "Toradex Verdin iMX95"
+
+/*! Board attributes */
+#define BRD_SM_ATTR  0x0
+
+/*!
+ * @name Board redirection defines
+ * @{
+ */
+#define SM_SYSTEMRESET  BRD_SM_SystemReset       /*!< Reset */
+/** @} */
+
+/* Types */
+
+/* External variables */
+
+/* Functions */
+
+/*!
+ * Reset the system.
+ *
+ * Redirect to just spin.
+ *
+ * @return Returns the status (::SM_ERR_SUCCESS = success).
+ *
+ * Return errors (see @ref STATUS "SM error codes"):
+ * - ::SM_ERR_SUCCESS
+ */
+int32_t BRD_SM_SystemReset(void);
+
+/** @} */
+
+#endif /* BRD_SM_H */
+
diff --git a/boards/tdx-verdin-imx95/sm/brd_sm_control.c b/boards/tdx-verdin-imx95/sm/brd_sm_control.c
new file mode 100755
index 0000000..dabb349
--- /dev/null
+++ b/boards/tdx-verdin-imx95/sm/brd_sm_control.c
@@ -0,0 +1,155 @@
+/*
+** ###################################################################
+**
+**     Copyright 2023-2024 NXP
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of the copyright holder nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+** ###################################################################
+*/
+
+/*==========================================================================*/
+/* File containing the implementation of the board controls.                */
+/*==========================================================================*/
+
+/* Includes */
+
+#include "sm.h"
+#include "brd_sm.h"
+#include "lmm.h"
+
+/* Local defines */
+
+/* Local types */
+
+/* Local variables */
+
+/*--------------------------------------------------------------------------*/
+/* Set a control value                                                      */
+/*--------------------------------------------------------------------------*/
+int32_t BRD_SM_ControlSet(uint32_t ctrlId, uint32_t numVal,
+    const uint32_t *val)
+{
+    int32_t status = SM_ERR_SUCCESS;
+
+    /* Check to see if ctrlId is within bounds*/
+    if (ctrlId < SM_NUM_CTRL)
+    {
+        /* Check if device or board */
+        if (ctrlId < DEV_SM_NUM_CTRL)
+        {
+            status = DEV_SM_ControlSet(ctrlId, numVal, val);
+        }
+        else if (ctrlId == BRD_SM_CTRL_TEST)
+        {
+            /* Test response to an reported SM error */
+            SM_Error(SM_ERR_GENERIC_ERROR);
+        }
+        else
+        {
+            status = SM_ERR_NOT_SUPPORTED;
+        }
+    }
+    else
+    {
+        status = SM_ERR_NOT_FOUND;
+    }
+
+    /* Return status */
+    return status;
+}
+
+/*--------------------------------------------------------------------------*/
+/* Get a control value                                                      */
+/*--------------------------------------------------------------------------*/
+int32_t BRD_SM_ControlGet(uint32_t ctrlId, uint32_t *numRtn, uint32_t *rtn)
+{
+    if (ctrlId < DEV_SM_NUM_CTRL)
+        return DEV_SM_ControlGet(ctrlId, numRtn, rtn);
+
+    return SM_ERR_NOT_FOUND;
+}
+
+/*--------------------------------------------------------------------------*/
+/* Set an extended control value                                            */
+/*--------------------------------------------------------------------------*/
+int32_t BRD_SM_ControlExtSet(uint32_t ctrlId, uint32_t addr,
+    uint32_t numVal, const uint32_t *val)
+{
+    int32_t status = SM_ERR_SUCCESS;
+
+    /* Check to see if ctrlId is within bounds*/
+    if (ctrlId < SM_NUM_CTRL)
+    {
+        /* Check if device or board */
+        if (ctrlId < DEV_SM_NUM_CTRL)
+        {
+            status = DEV_SM_ControlExtSet(ctrlId, addr, numVal, val);
+        }
+        else
+        {
+            status = SM_ERR_NOT_SUPPORTED;
+        }
+    }
+    else
+    {
+        status = SM_ERR_NOT_FOUND;
+    }
+
+    /* Return status */
+    return status;
+}
+
+/*--------------------------------------------------------------------------*/
+/* Get an extended control value                                            */
+/*--------------------------------------------------------------------------*/
+int32_t BRD_SM_ControlExtGet(uint32_t ctrlId, uint32_t addr,
+    uint32_t numRtn, uint32_t *rtn)
+{
+    int32_t status = SM_ERR_SUCCESS;
+
+    /* Check to see if ctrlId is within bounds*/
+    if (ctrlId < SM_NUM_CTRL)
+    {
+        /* Check if device or board */
+        if (ctrlId < DEV_SM_NUM_CTRL)
+        {
+            status = DEV_SM_ControlExtGet(ctrlId, addr, numRtn, rtn);
+        }
+        else
+        {
+            status = SM_ERR_NOT_SUPPORTED;
+        }
+    }
+    else
+    {
+        status = SM_ERR_NOT_FOUND;
+    }
+
+    /* Return status */
+    return status;
+}
diff --git a/boards/tdx-verdin-imx95/sm/brd_sm_control.h b/boards/tdx-verdin-imx95/sm/brd_sm_control.h
new file mode 100755
index 0000000..fcb3390
--- /dev/null
+++ b/boards/tdx-verdin-imx95/sm/brd_sm_control.h
@@ -0,0 +1,172 @@
+/*
+** ###################################################################
+**
+**     Copyright 2023-2024 NXP
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of the copyright holder nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+** ###################################################################
+*/
+
+/*==========================================================================*/
+/*!
+ * @addtogroup BRD_SM_TDXVERDINIMX95
+ * @{
+ *
+ * @file
+ * @brief
+ *
+ * Header file containing the SM API for the board controls.
+ */
+/*==========================================================================*/
+
+#ifndef BRD_SM_CONTROL_H
+#define BRD_SM_CONTROL_H
+
+/* Includes */
+
+#include "sm.h"
+#include "dev_sm.h"
+
+/* Defines */
+
+/*!
+ * @name Board redirection defines
+ * @{
+ */
+#define SM_CONTROLSET          BRD_SM_ControlSet          /*!< Control set */
+#define SM_CONTROLGET          BRD_SM_ControlGet          /*!< Control get */
+#define SM_CONTROLEXTSET       BRD_SM_ControlExtSet       /*!< Extended control set */
+#define SM_CONTROLEXTGET       BRD_SM_ControlExtGet       /*!< Extended control get */
+#define SM_CONTROLFLAGSSET     DEV_SM_ControlFlagsSet     /*!< Control flags */
+/** @} */
+
+/*! Number of board controls */
+#define BRD_SM_NUM_CTRL  1UL
+
+/*! Total number of controls */
+#define SM_NUM_CTRL  (DEV_SM_NUM_CTRL + BRD_SM_NUM_CTRL)
+
+/*!
+ * @name BRD_SM control domain indexes
+ */
+/** @{ */
+#define BRD_SM_CTRL_TEST        (DEV_SM_NUM_CTRL + 0U)  /*!< Test */
+/** @} */
+
+/* Types */
+
+/* Functions */
+
+/*!
+ * @name Board control functions
+ * @{
+ */
+
+/*!
+ * Set a board control value.
+ *
+ * @param[in]     ctrlId   Index of control to write
+ * @param[in]     numVal   Number of array elements
+ * @param[in]     val      Pointer to array of values to set
+ *
+ * This function allows a caller to write an array of values for
+ * a control.
+ *
+ * @return Returns the status (::SM_ERR_SUCCESS = success).
+ *
+ * Return errors (see @ref STATUS "SM error codes"):
+ * - ::SM_ERR_NOT_FOUND: if ctrlId is not valid.
+ */
+int32_t BRD_SM_ControlSet(uint32_t ctrlId, uint32_t numVal,
+    const uint32_t *val);
+
+/*!
+ * Get a board control value.
+ *
+ * @param[in]     ctrlId   Index of control to read
+ * @param[out]    numRtn   Return pointer to number of array elements
+ * @param[out]    rtn      Pointer to array to store return
+ *
+ * This function allows a caller to read an array of values for
+ * a control.
+ *
+ * @return Returns the status (::SM_ERR_SUCCESS = success).
+ *
+ * Return errors (see @ref STATUS "SM error codes"):
+ * - ::SM_ERR_NOT_FOUND: if ctrlId is not valid.
+ */
+int32_t BRD_SM_ControlGet(uint32_t ctrlId, uint32_t *numRtn, uint32_t *rtn);
+
+/*!
+ * Set an extended board control value.
+ *
+ * @param[in]     ctrlId   Index of control to write
+ * @param[in]     addr     Address of write
+ * @param[in]     numVal   Number of array elements
+ * @param[in]     val      Pointer to array of values to set
+ *
+ * This function allows a caller to write an array of values for
+ * a control. Extra parameters allow this write to be more complex
+ * such as to an I2C.
+ *
+ * @return Returns the status (::SM_ERR_SUCCESS = success).
+ *
+ * Return errors (see @ref STATUS "SM error codes"):
+ * - ::SM_ERR_NOT_FOUND: if ctrlId is not valid.
+ * - ::SM_ERR_INVALID_PARAMETERS: if addr or numVal are not valid.
+ */
+int32_t BRD_SM_ControlExtSet(uint32_t ctrlId, uint32_t addr,
+    uint32_t numVal, const uint32_t *val);
+
+/*!
+ * Get an extended board control value.
+ *
+ * @param[in]     ctrlId   Index of control to read
+ * @param[in]     addr     Address of read
+ * @param[in]     numRtn   Number of array elements
+ * @param[out]    rtn      Pointer to array to store return
+ *
+ * This function allows a caller to read an array of values for
+ * a control. Extra parameters allow this read to be more complex
+ * such as from an I2C.
+ *
+ * @return Returns the status (::SM_ERR_SUCCESS = success).
+ *
+ * Return errors (see @ref STATUS "SM error codes"):
+ * - ::SM_ERR_NOT_FOUND: if ctrlId is not valid.
+ * - ::SM_ERR_INVALID_PARAMETERS: if addr or numRtn are not valid.
+ */
+int32_t BRD_SM_ControlExtGet(uint32_t ctrlId, uint32_t addr,
+    uint32_t numRtn, uint32_t *rtn);
+
+/** @} */
+
+#endif /* BRD_SM_CONTROL_H */
+
+/** @} */
+
diff --git a/boards/tdx-verdin-imx95/sm/brd_sm_handlers.c b/boards/tdx-verdin-imx95/sm/brd_sm_handlers.c
new file mode 100755
index 0000000..0840103
--- /dev/null
+++ b/boards/tdx-verdin-imx95/sm/brd_sm_handlers.c
@@ -0,0 +1,215 @@
+/*
+** ###################################################################
+**
+** Copyright 2023-2024 NXP
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** o Redistributions of source code must retain the above copyright notice, this list
+**   of conditions and the following disclaimer.
+**
+** o Redistributions in binary form must reproduce the above copyright notice, this
+**   list of conditions and the following disclaimer in the documentation and/or
+**   other materials provided with the distribution.
+**
+** o Neither the name of the copyright holder nor the names of its
+**   contributors may be used to endorse or promote products derived from this
+**   software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+** ###################################################################
+*/
+
+/*==========================================================================*/
+/* File containing the implementation of the handlers for the board.        */
+/*==========================================================================*/
+
+/* Includes */
+
+#include "sm.h"
+#include "brd_sm.h"
+#include "dev_sm.h"
+#include "fsl_lpi2c.h"
+#include "fsl_rgpio.h"
+
+/* Local defines */
+
+/* I2C device addresses */
+#define BOARD_PF09_DEV_ADDR         0x08U
+#define BOARD_PF5301_DEV_ADDR       0x2AU
+#define BOARD_PF5302_DEV_ADDR       0x29U
+
+/* Local types */
+
+/* Local variables */
+
+/* Global variables */
+
+PF09_Type g_pf09Dev;
+PF53_Type g_pf5301Dev;
+PF53_Type g_pf5302Dev;
+
+uint32_t g_pmicFaultFlags = 0U;
+
+/* Local functions */
+
+static void BRD_SM_Pf09Handler(void);
+
+/*--------------------------------------------------------------------------*/
+/* Init serial devices                                                      */
+/*--------------------------------------------------------------------------*/
+int32_t BRD_SM_SerialDevicesInit(void)
+{
+    int32_t status = SM_ERR_SUCCESS;
+    LPI2C_Type *const s_i2cBases[] = LPI2C_BASE_PTRS;
+
+    /* Fill in PF09 PMIC handle */
+    g_pf09Dev.i2cBase = s_i2cBases[BOARD_I2C_INSTANCE];
+    g_pf09Dev.devAddr = BOARD_PF09_DEV_ADDR;
+    g_pf09Dev.crcEn = true;
+
+    /* Inialize PF09 PMIC */
+    if (!PF09_Init(&g_pf09Dev))
+    {
+        status = SM_ERR_HARDWARE_ERROR;
+    }
+
+    /* Disable voltage monitor 1 */
+    if (status == SM_ERR_SUCCESS)
+    {
+        if (!PF09_MonitorEnable(&g_pf09Dev, PF09_VMON1, false))
+        {
+            status = SM_ERR_HARDWARE_ERROR;
+        }
+    }
+
+    /* Disable voltage monitor 2 */
+    if (status == SM_ERR_SUCCESS)
+    {
+        if (!PF09_MonitorEnable(&g_pf09Dev, PF09_VMON2, false))
+        {
+            status = SM_ERR_HARDWARE_ERROR;
+        }
+    }
+
+    /* Disable the PWRUP interrupt */
+    if (status == SM_ERR_SUCCESS)
+    {
+        const uint8_t mask[PF09_MASK_LEN] =
+        {
+            [PF09_MASK_IDX_STATUS1] = 0x08U
+        };
+
+        if (!PF09_IntEnable(&g_pf09Dev, mask, PF09_MASK_LEN, false))
+        {
+            status = SM_ERR_HARDWARE_ERROR;
+        }
+    }
+
+    /* Change the LDO3 sequence */
+    if (status == SM_ERR_SUCCESS)
+    {
+        if (!PF09_PmicWrite(&g_pf09Dev, 0x4AU, 0x1EU, 0xFFU))
+        {
+            status = SM_ERR_HARDWARE_ERROR;
+        }
+    }
+
+    /* Set the LDO3 OV bypass */
+    if (status == SM_ERR_SUCCESS)
+    {
+        if (!PF09_PmicWrite(&g_pf09Dev, 0x7FU, 0xFCU, 0xFFU))
+        {
+            status = SM_ERR_HARDWARE_ERROR;
+        }
+    }
+
+    /* Set the OV debounce to 50us due to errata ER011/12 */
+    if (status == SM_ERR_SUCCESS)
+    {
+        if (!PF09_PmicWrite(&g_pf09Dev, 0x37U, 0x94U, 0xFFU))
+        {
+            status = SM_ERR_HARDWARE_ERROR;
+        }
+    }
+
+    /* Save and clear any fault flags */
+    if (status == SM_ERR_SUCCESS)
+    {
+        if (!PF09_FaultFlags(&g_pf09Dev, &g_pmicFaultFlags, true))
+        {
+            status = SM_ERR_HARDWARE_ERROR;
+        }
+    }
+
+    /* Handle any already pending PF09 interrupts */
+    if (status == SM_ERR_SUCCESS)
+    {
+        BRD_SM_Pf09Handler();
+    }
+
+    if (status == SM_ERR_SUCCESS)
+    {
+        /* Fill in PF5301 PMIC handle */
+        g_pf5301Dev.i2cBase = s_i2cBases[BOARD_I2C_INSTANCE];
+        g_pf5301Dev.devAddr = BOARD_PF5301_DEV_ADDR;
+
+        /* Inialize PF0901 PMIC */
+        if (!PF53_Init(&g_pf5301Dev))
+        {
+            status = SM_ERR_HARDWARE_ERROR;
+        }
+
+    }
+
+    if (status == SM_ERR_SUCCESS)
+    {
+        /* Fill in PF5302 PMIC handle */
+        g_pf5302Dev.i2cBase = s_i2cBases[BOARD_I2C_INSTANCE];
+        g_pf5302Dev.devAddr = BOARD_PF5302_DEV_ADDR;
+
+        /* Inialize PF0901 PMIC */
+        if (!PF53_Init(&g_pf5302Dev))
+        {
+            status = SM_ERR_HARDWARE_ERROR;
+        }
+    }
+
+    /* Return status */
+    return status;
+}
+
+/*==========================================================================*/
+
+/*--------------------------------------------------------------------------*/
+/* PF09 handler                                                             */
+/*--------------------------------------------------------------------------*/
+static void BRD_SM_Pf09Handler(void)
+{
+    uint8_t stat[PF09_MASK_LEN] = { 0 };
+
+    /* Read status of interrupts */
+    (void) PF09_IntStatus(&g_pf09Dev, stat, PF09_MASK_LEN);
+
+    /* Clear pending */
+    (void) PF09_IntClear(&g_pf09Dev, stat, PF09_MASK_LEN);
+
+    /* Handle pending temp interrupts */
+    if ((stat[PF09_MASK_IDX_STATUS2] & 0x0FU) != 0U)
+    {
+        BRD_SM_SensorHandler();
+    }
+}
+
diff --git a/boards/tdx-verdin-imx95/sm/brd_sm_handlers.h b/boards/tdx-verdin-imx95/sm/brd_sm_handlers.h
new file mode 100755
index 0000000..937525c
--- /dev/null
+++ b/boards/tdx-verdin-imx95/sm/brd_sm_handlers.h
@@ -0,0 +1,88 @@
+/*
+** ###################################################################
+**
+** Copyright 2023-2024 NXP
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** o Redistributions of source code must retain the above copyright notice, this list
+**   of conditions and the following disclaimer.
+**
+** o Redistributions in binary form must reproduce the above copyright notice, this
+**   list of conditions and the following disclaimer in the documentation and/or
+**   other materials provided with the distribution.
+**
+** o Neither the name of the copyright holder nor the names of its
+**   contributors may be used to endorse or promote products derived from this
+**   software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+** ###################################################################
+*/
+
+#ifndef BRD_SM_HANDLERS_H
+#define BRD_SM_HANDLERS_H
+
+/*==========================================================================*/
+/*!
+ * @addtogroup BRD_SM_TDXVERDINIMX95
+ * @{
+ *
+ * @file
+ * @brief
+ *
+ * Header file containing the implementation of interrupt handlers for the
+ * board.
+ */
+/*==========================================================================*/
+
+/* Includes */
+
+#include "sm.h"
+#include "dev_sm.h"
+#include "fsl_pf09.h"
+#include "fsl_pf53.h"
+
+/* Defines */
+
+/* Types */
+
+/* External variables */
+
+/*! Handle to access PF09 */
+extern PF09_Type g_pf09Dev;
+
+/*! Handle to access PF5301 */
+extern PF53_Type g_pf5301Dev;
+
+/*! Handle to access PF5302 */
+extern PF53_Type g_pf5302Dev;
+
+/*! Fault flags from the PMICs */
+extern uint32_t g_pmicFaultFlags;
+
+/* Functions */
+
+/*!
+ * Init serial devices.
+ *
+ * @return Returns the status (::SM_ERR_SUCCESS = success).
+ */
+int32_t BRD_SM_SerialDevicesInit(void);
+
+/** @} */
+
+#endif /* BRD_SM_HANDLERS_H */
+
diff --git a/boards/tdx-verdin-imx95/sm/brd_sm_sensor.c b/boards/tdx-verdin-imx95/sm/brd_sm_sensor.c
new file mode 100755
index 0000000..c6cf6bb
--- /dev/null
+++ b/boards/tdx-verdin-imx95/sm/brd_sm_sensor.c
@@ -0,0 +1,367 @@
+/*
+** ###################################################################
+**
+** Copyright 2023-2024 NXP
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** o Redistributions of source code must retain the above copyright notice, this list
+**   of conditions and the following disclaimer.
+**
+** o Redistributions in binary form must reproduce the above copyright notice, this
+**   list of conditions and the following disclaimer in the documentation and/or
+**   other materials provided with the distribution.
+**
+** o Neither the name of the copyright holder nor the names of its
+**   contributors may be used to endorse or promote products derived from this
+**   software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+** ###################################################################
+*/
+
+/*==========================================================================*/
+/* File containing the implementation of the board sensors.                 */
+/*==========================================================================*/
+
+/* Includes */
+
+#include "sm.h"
+#include "brd_sm.h"
+#include "lmm.h"
+
+/* Local defines */
+
+/* Local types */
+
+/* Local variables */
+
+static bool sensorEnb[BRD_SM_NUM_SENSOR];
+
+/*--------------------------------------------------------------------------*/
+/* Return sensor name                                                       */
+/*--------------------------------------------------------------------------*/
+int32_t BRD_SM_SensorNameGet(uint32_t sensorId, string *sensorNameAddr,
+    int32_t *len)
+{
+    int32_t status = SM_ERR_SUCCESS;
+    static int32_t s_maxLen = 0;
+
+    static string const s_name[BRD_SM_NUM_SENSOR] =
+    {
+        "temp_pf09",
+        "temp_pf53_soc",
+        "temp_pf53_arm"
+    };
+
+    /* Get max string width */
+    DEV_SM_MaxStringGet(len, &s_maxLen, s_name, BRD_SM_NUM_SENSOR);
+
+    /* Check to see if sensorId is within bounds*/
+    if (sensorId < SM_NUM_SENSOR)
+    {
+        /* Check if device or board */
+        if (sensorId < DEV_SM_NUM_SENSOR)
+        {
+            status = DEV_SM_SensorNameGet(sensorId, sensorNameAddr, len);
+        }
+        else
+        {
+            uint32_t brdSensorId = sensorId - DEV_SM_NUM_SENSOR;
+
+            /* Return pointer to name */
+            *sensorNameAddr = s_name[brdSensorId];
+        }
+    }
+    else
+    {
+        status = SM_ERR_NOT_FOUND;
+    }
+
+    /* Return status */
+    return status;
+}
+
+/*--------------------------------------------------------------------------*/
+/* Return sensor description                                                */
+/*--------------------------------------------------------------------------*/
+int32_t BRD_SM_SensorDescribe(uint32_t sensorId,
+    dev_sm_sensor_desc_t *desc)
+{
+    int32_t status = SM_ERR_SUCCESS;
+
+    /* Check to see if sensorId is within bounds*/
+    if (sensorId < SM_NUM_SENSOR)
+    {
+        /* Check if device or board */
+        if (sensorId < DEV_SM_NUM_SENSOR)
+        {
+            status = DEV_SM_SensorDescribe(sensorId, desc);
+        }
+        else
+        {
+            desc->sensorType = 2U;
+            desc->sensorExponent = 0;
+            desc->numTripPoints = 0U;
+            desc->timestampSupport = false;
+            desc->timestampExponent = 0;
+
+            /* PF09? */
+            if (sensorId == BRD_SM_SENSOR_TEMP_PF09)
+            {
+                desc->numTripPoints = 1U;
+            }
+        }
+    }
+    else
+    {
+        status = SM_ERR_NOT_FOUND;
+    }
+
+    /* Return status */
+    return status;
+}
+
+/*--------------------------------------------------------------------------*/
+/* Get sensor reading                                                       */
+/*--------------------------------------------------------------------------*/
+int32_t BRD_SM_SensorReadingGet(uint32_t sensorId, int64_t *sensorValue,
+    uint64_t *sensorTimestamp)
+{
+    int32_t status = SM_ERR_SUCCESS;
+
+    /* Check to see if sensorId is within bounds*/
+    if (sensorId < SM_NUM_SENSOR)
+    {
+        /* Check if device or board */
+        if (sensorId < DEV_SM_NUM_SENSOR)
+        {
+            status = DEV_SM_SensorReadingGet(sensorId, sensorValue,
+                sensorTimestamp);
+        }
+        else
+        {
+            uint32_t brdSensorId = sensorId - DEV_SM_NUM_SENSOR;
+
+            /* Check if enabled */
+            if (sensorEnb[brdSensorId])
+            {
+                int32_t temp;
+                bool rc = false;
+
+                /* Read sensor */
+                switch (sensorId)
+                {
+                    case BRD_SM_SENSOR_TEMP_PF09:
+                        rc = PF09_TempGet(&g_pf09Dev, &temp);
+                        break;
+                    case BRD_SM_SENSOR_TEMP_PF5301:
+                        rc = PF53_TempGet(&g_pf5301Dev, &temp);
+                        break;
+                    default:
+                        rc = PF53_TempGet(&g_pf5302Dev, &temp);
+                        break;
+                }
+
+                if (rc)
+                {
+                    *sensorValue = (int64_t) temp;
+                    *sensorTimestamp = 0ULL;
+                }
+                else
+                {
+                    status = SM_ERR_HARDWARE_ERROR;
+                }
+            }
+            else
+            {
+                status = SM_ERR_NOT_SUPPORTED;
+            }
+        }
+    }
+    else
+    {
+        status = SM_ERR_NOT_FOUND;
+    }
+
+    /* Return status */
+    return status;
+}
+
+/*--------------------------------------------------------------------------*/
+/* Set sensor trippoint                                                     */
+/*--------------------------------------------------------------------------*/
+int32_t BRD_SM_SensorTripPointSet(uint32_t sensorId, uint8_t tripPoint,
+    int64_t value, uint8_t eventControl)
+{
+    int32_t status = SM_ERR_SUCCESS;
+
+    /* Check to see if sensorId is within bounds*/
+    if (sensorId < SM_NUM_SENSOR)
+    {
+        /* Check if device or board */
+        if (sensorId < DEV_SM_NUM_SENSOR)
+        {
+            status = DEV_SM_SensorTripPointSet(sensorId, tripPoint,
+                value, eventControl);
+        }
+        else
+        {
+            uint32_t brdSensorId = sensorId - DEV_SM_NUM_SENSOR;
+
+            /* Check if enabled */
+            if ((sensorId == BRD_SM_SENSOR_TEMP_PF09)
+                && sensorEnb[brdSensorId])
+            {
+                /* Check trip point */
+                if (tripPoint == 0U)
+                {
+                    if (eventControl == DEV_SM_SENSOR_TP_NONE)
+                    {
+                        if (!PF09_TempAlarmSet(&g_pf09Dev, 500))
+                        {
+                            status = SM_ERR_HARDWARE_ERROR;
+                        }
+                    }
+                    else if (eventControl == DEV_SM_SENSOR_TP_RISING)
+                    {
+                        int32_t temp = (int32_t) value;
+
+                        if (!PF09_TempAlarmSet(&g_pf09Dev, temp))
+                        {
+                            status = SM_ERR_HARDWARE_ERROR;
+                        }
+                    }
+                    else
+                    {
+                        status = SM_ERR_INVALID_PARAMETERS;
+                    }
+                }
+                else
+                {
+                    status = SM_ERR_INVALID_PARAMETERS;
+                }
+            }
+            else
+            {
+                status = SM_ERR_NOT_SUPPORTED;
+            }
+        }
+    }
+    else
+    {
+        status = SM_ERR_NOT_FOUND;
+    }
+
+    /* Return status */
+    return status;
+}
+
+/*--------------------------------------------------------------------------*/
+/* Enable/disable sensor                                                    */
+/*--------------------------------------------------------------------------*/
+int32_t BRD_SM_SensorEnable(uint32_t sensorId, bool enable,
+    bool timestampReporting)
+{
+    int32_t status = SM_ERR_SUCCESS;
+
+    /* Check to see if sensorId is within bounds*/
+    if (sensorId < SM_NUM_SENSOR)
+    {
+        /* Check if device or board */
+        if (sensorId < DEV_SM_NUM_SENSOR)
+        {
+            status = DEV_SM_SensorEnable(sensorId, enable,
+                timestampReporting);
+        }
+        else
+        {
+            uint32_t brdSensorId = sensorId - DEV_SM_NUM_SENSOR;
+
+            /* Timestamp not supported */
+            if (timestampReporting)
+            {
+                status = SM_ERR_NOT_SUPPORTED;
+            }
+            else
+            {
+                /* Record sensor enable */
+                sensorEnb[brdSensorId] = enable;
+
+                /* Disable alarm */
+                if ((sensorId == BRD_SM_SENSOR_TEMP_PF09)
+                    && !sensorEnb[brdSensorId])
+                {
+                    if (!PF09_TempAlarmSet(&g_pf09Dev, 500))
+                    {
+                        status = SM_ERR_HARDWARE_ERROR;
+                    }
+                }
+            }
+        }
+    }
+    else
+    {
+        status = SM_ERR_NOT_FOUND;
+    }
+
+    /* Return status */
+    return status;
+}
+
+/*--------------------------------------------------------------------------*/
+/* Return sensor enable status                                              */
+/*--------------------------------------------------------------------------*/
+int32_t BRD_SM_SensorIsEnabled(uint32_t sensorId, bool *enabled,
+    bool *timestampReporting)
+{
+    int32_t status = SM_ERR_SUCCESS;
+
+    /* Check to see if sensorId is within bounds*/
+    if (sensorId < SM_NUM_SENSOR)
+    {
+        uint32_t brdSensorId = sensorId - DEV_SM_NUM_SENSOR;
+
+        /* Check if device or board */
+        if (sensorId < DEV_SM_NUM_SENSOR)
+        {
+            status = DEV_SM_SensorIsEnabled(sensorId, enabled,
+                timestampReporting);
+        }
+        else
+        {
+            /* Return sensor enable */
+            *enabled = sensorEnb[brdSensorId];
+            *timestampReporting = false;
+        }
+    }
+    else
+    {
+        status = SM_ERR_NOT_FOUND;
+    }
+
+    /* Return status */
+    return status;
+}
+
+/*--------------------------------------------------------------------------*/
+/* PMIC sensor handler                                                      */
+/*--------------------------------------------------------------------------*/
+void BRD_SM_SensorHandler(void)
+{
+    /* Send sensor event */
+    LMM_SensorEvent(BRD_SM_SENSOR_TEMP_PF09, 0U, 1U);
+}
+
diff --git a/boards/tdx-verdin-imx95/sm/brd_sm_sensor.h b/boards/tdx-verdin-imx95/sm/brd_sm_sensor.h
new file mode 100755
index 0000000..7afd460
--- /dev/null
+++ b/boards/tdx-verdin-imx95/sm/brd_sm_sensor.h
@@ -0,0 +1,210 @@
+/*
+** ###################################################################
+**
+** Copyright 2023 NXP
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** o Redistributions of source code must retain the above copyright notice, this list
+**   of conditions and the following disclaimer.
+**
+** o Redistributions in binary form must reproduce the above copyright notice, this
+**   list of conditions and the following disclaimer in the documentation and/or
+**   other materials provided with the distribution.
+**
+** o Neither the name of the copyright holder nor the names of its
+**   contributors may be used to endorse or promote products derived from this
+**   software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+** ###################################################################
+*/
+
+/*==========================================================================*/
+/*!
+ * @addtogroup BRD_SM_TDXVERDINIMX95
+ * @{
+ *
+ * @file
+ * @brief
+ *
+ * Header file containing the SM API for the board sensors.
+ */
+/*==========================================================================*/
+
+#ifndef BRD_SM_SENSOR_H
+#define BRD_SM_SENSOR_H
+
+/* Includes */
+
+#include "sm.h"
+#include "dev_sm.h"
+
+/* Defines */
+
+/*!
+ * @name Board redirection defines
+ * @{
+ */
+#define SM_SENSORNAMEGET       BRD_SM_SensorNameGet       /*!< Sensor name */
+#define SM_SENSORDESCRIBE      BRD_SM_SensorDescribe      /*!< Sensor describe */
+#define SM_SENSORREADINGGET    BRD_SM_SensorReadingGet    /*!< Sensor read */
+#define SM_SENSORTRIPPOINTSET  BRD_SM_SensorTripPointSet  /*!< Sensor trip point */
+#define SM_SENSORENABLE        BRD_SM_SensorEnable        /*!< Sensor enable */
+#define SM_SENSORISENABLED     BRD_SM_SensorIsEnabled     /*!< Sensor status */
+/** @} */
+
+/*! Number of board sensors */
+#define BRD_SM_NUM_SENSOR  3UL
+
+/*! Total number of sensors */
+#define SM_NUM_SENSOR  (DEV_SM_NUM_SENSOR + BRD_SM_NUM_SENSOR)
+
+/*!
+ * @name BRD_SM sensor domain indexes
+ */
+/** @{ */
+#define BRD_SM_SENSOR_TEMP_PF09    (DEV_SM_NUM_SENSOR + 0U)  /*!< PF09 temp sensor */
+#define BRD_SM_SENSOR_TEMP_PF5302  (DEV_SM_NUM_SENSOR + 1U)  /*!< PF5302 temp sensor */
+#define BRD_SM_SENSOR_TEMP_PF5301  (DEV_SM_NUM_SENSOR + 2U)  /*!< PF5301 temp sensor */
+/** @} */
+
+/* Types */
+
+/* Functions */
+
+/*!
+ * @name Board sensor functions
+ * @{
+ */
+
+/*!
+ * Get a board sensor name.
+ *
+ * @param[in]     sensorId        Sensor name to get
+ * @param[out]    sensorNameAddr  Return pointer to name
+ * @param[out]    len             Return max length of all sensor names
+ *
+ * This function allows the caller to get the name of a sensor.
+ *
+ * @return Returns the status (::SM_ERR_SUCCESS = success).
+ *
+ * Return errors (see @ref STATUS "SM error codes"):
+ * - ::SM_ERR_NOT_FOUND: if \a sensorId is invalid.
+ */
+int32_t BRD_SM_SensorNameGet(uint32_t sensorId, string *sensorNameAddr,
+    int32_t *len);
+
+/*!
+ * Get a board sensor description.
+ *
+ * @param[in]     sensorId   Sensor description to get
+ * @param[out]    desc       Return pointer to the description
+ *
+ * This function allows the caller to get the description of a sensor.
+ *
+ * @return Returns the status (::SM_ERR_SUCCESS = success).
+ *
+ * Return errors (see @ref STATUS "SM error codes"):
+ * - ::SM_ERR_NOT_FOUND: if \a sensorId is invalid.
+ */
+int32_t BRD_SM_SensorDescribe(uint32_t sensorId,
+    dev_sm_sensor_desc_t *desc);
+
+/*!
+ * Read a board sensor.
+ *
+ * @param[in]     sensorId         Sensor to read
+ * @param[out]    sensorValue      Return pointer to sensor value
+ * @param[out]    sensorTimestamp  Return pointer to timestamp
+ *
+ * This function allows the caller to read the value of a sensor.
+ *
+ * @return Returns the status (::SM_ERR_SUCCESS = success).
+ *
+ * Return errors (see @ref STATUS "SM error codes"):
+ * - ::SM_ERR_NOT_FOUND: if \a sensorId is invalid.
+ */
+int32_t BRD_SM_SensorReadingGet(uint32_t sensorId, int64_t *sensorValue,
+    uint64_t *sensorTimestamp);
+
+/*!
+ * Configure a trip point for a board sensor.
+ *
+ * @param[in]     sensorId      Sensor to configure TP
+ * @param[in]     tripPoint     Trip point ID
+ * @param[in]     value         Value to trip at
+ * @param[in]     eventControl  Event control (notifications)
+ *
+ * This function allows the caller to configure one of the trip
+ * points for a sensor. The caller can also configure which crossing
+ * direction will generate a notification.
+ *
+ * @return Returns the status (::SM_ERR_SUCCESS = success).
+ *
+ * Return errors (see @ref STATUS "SM error codes"):
+ * - ::SM_ERR_NOT_FOUND: if \a sensorId is invalid.
+ */
+int32_t BRD_SM_SensorTripPointSet(uint32_t sensorId, uint8_t tripPoint,
+    int64_t value, uint8_t eventControl);
+
+/*!
+ * Enable/disable a board sensor.
+ *
+ * @param[in]     sensorId            Sensor to enable/disable
+ * @param[in]     enable              True to enable
+ * @param[in]     timestampReporting  True to enable timestamp reporting
+ *
+ * This function allows the caller to enable/disable a sensor.
+ *
+ * @return Returns the status (::SM_ERR_SUCCESS = success).
+ *
+ * Return errors (see @ref STATUS "SM error codes"):
+ * - ::SM_ERR_NOT_FOUND: if \a sensorId is invalid.
+ */
+int32_t BRD_SM_SensorEnable(uint32_t sensorId, bool enable,
+    bool timestampReporting);
+
+/*!
+ * Get enable/disable state of a board sensor.
+ *
+ * @param[in]     sensorId            Sensor to get state
+ * @param[out]    enabled             Return pointer to enable
+ * @param[out]    timestampReporting  Return pointer to reporting
+ *
+ * This function allows the caller to get the enable/disable
+ * state of a sensor.
+ *
+ * @return Returns the status (::SM_ERR_SUCCESS = success).
+ *
+ * Return errors (see @ref STATUS "SM error codes"):
+ * - ::SM_ERR_NOT_FOUND: if \a sensorId is invalid.
+ */
+int32_t BRD_SM_SensorIsEnabled(uint32_t sensorId, bool *enabled,
+    bool *timestampReporting);
+
+/*!
+ * Sensor interrupt handler.
+ *
+ * Called by PF09 interrupt handler.
+ */
+void BRD_SM_SensorHandler(void);
+
+/** @} */
+
+#endif /* BRD_SM_SENSOR_H */
+
+/** @} */
+
diff --git a/boards/tdx-verdin-imx95/sm/brd_sm_voltage.c b/boards/tdx-verdin-imx95/sm/brd_sm_voltage.c
new file mode 100755
index 0000000..df36e54
--- /dev/null
+++ b/boards/tdx-verdin-imx95/sm/brd_sm_voltage.c
@@ -0,0 +1,517 @@
+/*
+** ###################################################################
+**
+**     Copyright 2023-2024 NXP
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of the copyright holder nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+** ###################################################################
+*/
+
+/*==========================================================================*/
+/* File containing the implementation of the board voltages.                */
+/*==========================================================================*/
+
+/* Includes */
+
+#include "sm.h"
+#include "brd_sm.h"
+
+/* Local defines */
+
+/* Local types */
+
+/* Local variables */
+
+static int32_t s_levelSoc = BOARD_VOLT_SOC;
+static int32_t s_levelArm = BOARD_VOLT_ARM;
+static uint32_t s_modeArm = DEV_SM_VOLT_MODE_ON;
+static uint32_t s_modeArmSave = DEV_SM_VOLT_MODE_ON;
+
+/*--------------------------------------------------------------------------*/
+/* Return voltage name                                                      */
+/*--------------------------------------------------------------------------*/
+int32_t BRD_SM_VoltageNameGet(uint32_t domainId, string *voltNameAddr,
+    int32_t *len)
+{
+    int32_t status = SM_ERR_SUCCESS;
+    static int32_t s_maxLen = 0;
+
+    static string const s_name[BRD_SM_NUM_VOLT] =
+    {
+        "vdd_gpio_3p3",
+        "vdd_ana_0p8",
+        "vdd_gpio_1p8",
+        "vddq_ddr",
+        "vdd2_ddr",
+        "sd_card",
+        "nvcc_sd2"
+    };
+
+    /* Get max string width */
+    DEV_SM_MaxStringGet(len, &s_maxLen, s_name, BRD_SM_NUM_VOLT);
+
+    /* Check to see if domain is within bounds*/
+    if (domainId < SM_NUM_VOLT)
+    {
+        /* Check if device or board */
+        if (domainId < DEV_SM_NUM_VOLT)
+        {
+            status = DEV_SM_VoltageNameGet(domainId, voltNameAddr, len);
+        }
+        else
+        {
+            /* Return pointer to name */
+            *voltNameAddr = s_name[domainId - DEV_SM_NUM_VOLT];
+        }
+    }
+    else
+    {
+        status = SM_ERR_NOT_FOUND;
+    }
+
+    /* Return status */
+    return status;
+}
+
+/*--------------------------------------------------------------------------*/
+/* Return supported voltage range                                           */
+/*--------------------------------------------------------------------------*/
+int32_t BRD_SM_VoltageDescribe(uint32_t domainId,
+    dev_sm_voltage_range_t *range)
+{
+    int32_t status = SM_ERR_HARDWARE_ERROR;
+    bool rc = false;
+    PF09_RegInfo info;
+
+    /* Get voltage range/info */
+    switch (domainId)
+    {
+        case DEV_SM_VOLT_SOC:
+            status = DEV_SM_VoltageDescribe(domainId, range);
+            break;
+        case DEV_SM_VOLT_ARM:
+            status = DEV_SM_VoltageDescribe(domainId, range);
+            break;
+        case BRD_SM_VOLT_VDD_GPIO_3P3:
+            rc = PF09_RegulatorInfoGet(PF09_REG_SW1, &info);
+            break;
+        case BRD_SM_VOLT_VDD_ANA_0P8:
+            rc = PF09_RegulatorInfoGet(PF09_REG_SW2, &info);
+            break;
+        case BRD_SM_VOLT_VDD_GPIO_1P8:
+            rc = PF09_RegulatorInfoGet(PF09_REG_SW3, &info);
+            break;
+        case BRD_SM_VOLT_VDDQ_DDR:
+            rc = PF09_RegulatorInfoGet(PF09_REG_SW4, &info);
+            break;
+        case BRD_SM_VOLT_VDD2_DDR:
+            rc = PF09_RegulatorInfoGet(PF09_REG_SW5, &info);
+            break;
+        case BRD_SM_VOLT_SD_CARD:
+            rc = PF09_RegulatorInfoGet(PF09_REG_LDO1, &info);
+            break;
+        case BRD_SM_VOLT_NVCC_SD2:
+            rc = PF09_RegulatorInfoGet(PF09_REG_LDO2, &info);
+            break;
+        default:
+            status = SM_ERR_NOT_FOUND;
+            break;
+    }
+
+    /* Return results */
+    if ((status != SM_ERR_SUCCESS) && rc)
+    {
+        range->highestVolt = (int32_t) info.maxV;
+        range->lowestVolt = (int32_t) info.minV;
+        range->stepSize= (int32_t) info.stepV;
+        status = SM_ERR_SUCCESS;
+    }
+
+    /* Return status */
+    return status;
+}
+
+/*--------------------------------------------------------------------------*/
+/* Set voltage mode                                                         */
+/*--------------------------------------------------------------------------*/
+int32_t BRD_SM_VoltageModeSet(uint32_t domainId, uint8_t voltMode)
+{
+    int32_t status = SM_ERR_SUCCESS;
+    bool enable = (voltMode == DEV_SM_VOLT_MODE_ON);
+    uint8_t mode = ((voltMode == DEV_SM_VOLT_MODE_OFF)
+        ? PF09_SW_MODE_OFF : PF09_SW_MODE_PWM);
+    bool rc;
+
+    /* Set mode */
+    switch (domainId)
+    {
+        case DEV_SM_VOLT_SOC:
+            mode = ((voltMode == DEV_SM_VOLT_MODE_OFF)
+                ? PF53_SW_MODE_OFF : PF53_SW_MODE_PWM);
+            rc = PF53_SwModeSet(&g_pf5302Dev, PF53_REG_SW1, PF53_STATE_VRUN,
+                mode);
+            break;
+        case DEV_SM_VOLT_ARM:
+            rc = PF09_GpioCtrlSet(&g_pf09Dev, PF09_GPIO4, PF53_STATE_VRUN,
+                enable);
+            if (enable && rc)
+            {
+                /* Wait for PF53 power up and ramp */
+                SystemTimeDelay(1000U);
+
+                if (s_levelArm != BOARD_VOLT_ARM)
+                {
+                    /* Restore voltage as enable resets the PF53 */
+                    status = BRD_SM_VoltageLevelSet(domainId, s_levelArm);
+                }
+            }
+            if (rc)
+            {
+                s_modeArm = voltMode;
+            }
+            break;
+        case BRD_SM_VOLT_VDD_GPIO_3P3:
+            rc = PF09_SwModeSet(&g_pf09Dev, PF09_REG_SW1, PF09_STATE_VRUN,
+                mode);
+            break;
+        case BRD_SM_VOLT_VDD_ANA_0P8:
+            rc = PF09_SwModeSet(&g_pf09Dev, PF09_REG_SW2, PF09_STATE_VRUN,
+                mode);
+            break;
+        case BRD_SM_VOLT_VDD_GPIO_1P8:
+            rc = PF09_SwModeSet(&g_pf09Dev, PF09_REG_SW3, PF09_STATE_VRUN,
+                mode);
+            break;
+        case BRD_SM_VOLT_VDDQ_DDR:
+            rc = PF09_SwModeSet(&g_pf09Dev, PF09_REG_SW4, PF09_STATE_VRUN,
+                mode);
+            break;
+        case BRD_SM_VOLT_VDD2_DDR:
+            rc = PF09_SwModeSet(&g_pf09Dev, PF09_REG_SW5, PF09_STATE_VRUN,
+                mode);
+            break;
+        case BRD_SM_VOLT_SD_CARD:
+            rc = PF09_LdoEnable(&g_pf09Dev, PF09_REG_LDO1, PF09_STATE_VRUN,
+                enable);
+            break;
+        case BRD_SM_VOLT_NVCC_SD2:
+            rc = PF09_LdoEnable(&g_pf09Dev, PF09_REG_LDO2, PF09_STATE_VRUN,
+                enable);
+            break;
+        default:
+            status = SM_ERR_NOT_FOUND;
+            break;
+    }
+
+    /* Translate error */
+    if ((status == SM_ERR_SUCCESS) && !rc)
+    {
+        status = SM_ERR_HARDWARE_ERROR;
+    }
+
+    /* Return status */
+    return status;
+}
+
+/*--------------------------------------------------------------------------*/
+/* Get voltage mode                                                         */
+/*--------------------------------------------------------------------------*/
+int32_t BRD_SM_VoltageModeGet(uint32_t domainId, uint8_t *voltMode)
+{
+    int32_t status = SM_ERR_SUCCESS;
+    bool enable;
+    uint8_t mode;
+    bool rc;
+
+    /* Get mode */
+    switch (domainId)
+    {
+        case DEV_SM_VOLT_SOC:
+            rc = PF53_SwModeGet(&g_pf5302Dev, PF53_REG_SW1, PF53_STATE_VRUN,
+                &mode);
+            enable = (mode != PF53_SW_MODE_OFF);
+            break;
+        case DEV_SM_VOLT_ARM:
+            rc = PF09_GpioCtrlGet(&g_pf09Dev, PF09_GPIO4, PF53_STATE_VRUN,
+                &enable);
+            break;
+        case BRD_SM_VOLT_VDD_GPIO_3P3:
+            rc = PF09_SwModeGet(&g_pf09Dev, PF09_REG_SW1, PF09_STATE_VRUN,
+                &mode);
+            enable = (mode != PF09_SW_MODE_OFF);
+            break;
+        case BRD_SM_VOLT_VDD_ANA_0P8:
+            rc = PF09_SwModeGet(&g_pf09Dev, PF09_REG_SW2, PF09_STATE_VRUN,
+                &mode);
+            enable = (mode != PF09_SW_MODE_OFF);
+            break;
+        case BRD_SM_VOLT_VDD_GPIO_1P8:
+            rc = PF09_SwModeGet(&g_pf09Dev, PF09_REG_SW3, PF09_STATE_VRUN,
+                &mode);
+            enable = (mode != PF09_SW_MODE_OFF);
+            break;
+        case BRD_SM_VOLT_VDDQ_DDR:
+            rc = PF09_SwModeGet(&g_pf09Dev, PF09_REG_SW4, PF09_STATE_VRUN,
+                &mode);
+            enable = (mode != PF09_SW_MODE_OFF);
+            break;
+        case BRD_SM_VOLT_VDD2_DDR:
+            rc = PF09_SwModeGet(&g_pf09Dev, PF09_REG_SW5, PF09_STATE_VRUN,
+                &mode);
+            enable = (mode != PF09_SW_MODE_OFF);
+            break;
+        case BRD_SM_VOLT_SD_CARD:
+            rc = PF09_LdoIsEnabled(&g_pf09Dev, PF09_REG_LDO1, PF09_STATE_VRUN,
+                &enable);
+            break;
+        case BRD_SM_VOLT_NVCC_SD2:
+            rc = PF09_LdoIsEnabled(&g_pf09Dev, PF09_REG_LDO2, PF09_STATE_VRUN,
+                &enable);
+            break;
+        default:
+            status = SM_ERR_NOT_FOUND;
+            break;
+    }
+
+    /* Return result */
+    if ((status == SM_ERR_SUCCESS) && rc)
+    {
+        *voltMode = enable ? DEV_SM_VOLT_MODE_ON : DEV_SM_VOLT_MODE_OFF;
+    }
+
+    /* Translate error */
+    if ((status == SM_ERR_SUCCESS) && !rc)
+    {
+        status = SM_ERR_HARDWARE_ERROR;
+    }
+
+    /* Return status */
+    return status;
+}
+
+/*--------------------------------------------------------------------------*/
+/* Set voltage level                                                        */
+/*--------------------------------------------------------------------------*/
+int32_t BRD_SM_VoltageLevelSet(uint32_t domainId, int32_t voltageLevel)
+{
+    int32_t status = SM_ERR_SUCCESS;
+    bool rc;
+    uint32_t level = (uint32_t) voltageLevel;
+
+    /* Set level */
+    switch (domainId)
+    {
+        case DEV_SM_VOLT_SOC:
+            rc = PF53_VoltageSet(&g_pf5302Dev, PF53_REG_SW1, PF53_STATE_VRUN,
+                level);
+
+            if (rc)
+            {
+                /* Save level to restore */
+                s_levelSoc = (int32_t) level;
+            }
+            break;
+        case DEV_SM_VOLT_ARM:
+            (void) PF53_VoltageSet(&g_pf5301Dev, PF53_REG_SW1, PF53_STATE_VRUN,
+                level);
+
+            /* Save level to restore */
+            s_levelArm = (int32_t) level;
+            rc = true;
+            break;
+        case BRD_SM_VOLT_VDD_GPIO_3P3:
+            rc = PF09_VoltageSet(&g_pf09Dev, PF09_REG_SW1, PF09_STATE_VRUN,
+                level);
+            break;
+        case BRD_SM_VOLT_VDD_ANA_0P8:
+            rc = PF09_VoltageSet(&g_pf09Dev, PF09_REG_SW2, PF09_STATE_VRUN,
+                level);
+            break;
+        case BRD_SM_VOLT_VDD_GPIO_1P8:
+            rc = PF09_VoltageSet(&g_pf09Dev, PF09_REG_SW3, PF09_STATE_VRUN,
+                level);
+            break;
+        case BRD_SM_VOLT_VDDQ_DDR:
+            rc = PF09_VoltageSet(&g_pf09Dev, PF09_REG_SW4, PF09_STATE_VRUN,
+                level);
+            break;
+        case BRD_SM_VOLT_VDD2_DDR:
+            rc = PF09_VoltageSet(&g_pf09Dev, PF09_REG_SW5, PF09_STATE_VRUN,
+                level);
+            break;
+        case BRD_SM_VOLT_SD_CARD:
+            rc = PF09_VoltageSet(&g_pf09Dev, PF09_REG_LDO1, PF09_STATE_VRUN,
+                level);
+            break;
+        case BRD_SM_VOLT_NVCC_SD2:
+            rc = PF09_VoltageSet(&g_pf09Dev, PF09_REG_LDO2, PF09_STATE_VRUN,
+                level);
+            break;
+        default:
+            status = SM_ERR_NOT_FOUND;
+            break;
+    }
+
+    /* Translate error */
+    if ((status == SM_ERR_SUCCESS) && !rc)
+    {
+        status = SM_ERR_HARDWARE_ERROR;
+    }
+
+    /* Return status */
+    return status;
+}
+
+/*--------------------------------------------------------------------------*/
+/* Get voltage level                                                        */
+/*--------------------------------------------------------------------------*/
+int32_t BRD_SM_VoltageLevelGet(uint32_t domainId, int32_t *voltageLevel)
+{
+    int32_t status = SM_ERR_SUCCESS;
+    bool rc;
+    uint32_t level;
+
+    /* Get level */
+    switch (domainId)
+    {
+        case DEV_SM_VOLT_SOC:
+            rc = PF53_VoltageGet(&g_pf5302Dev, PF53_REG_SW1, PF53_STATE_VRUN,
+                &level);
+            break;
+        case DEV_SM_VOLT_ARM:
+            rc = PF53_VoltageGet(&g_pf5301Dev, PF53_REG_SW1, PF53_STATE_VRUN,
+                &level);
+            if (rc)
+            {
+                /* Save level to restore */
+                s_levelArm = (int32_t) level;
+            }
+            else
+            {
+                /* Return saved level */
+                level = (uint32_t) s_levelArm;
+                rc = true;
+            }
+            break;
+        case BRD_SM_VOLT_VDD_GPIO_3P3:
+            rc = PF09_VoltageGet(&g_pf09Dev, PF09_REG_SW1, PF09_STATE_VRUN,
+                &level);
+            break;
+        case BRD_SM_VOLT_VDD_ANA_0P8:
+            rc = PF09_VoltageGet(&g_pf09Dev, PF09_REG_SW2, PF09_STATE_VRUN,
+                &level);
+            break;
+        case BRD_SM_VOLT_VDD_GPIO_1P8:
+            rc = PF09_VoltageGet(&g_pf09Dev, PF09_REG_SW3, PF09_STATE_VRUN,
+                &level);
+            break;
+        case BRD_SM_VOLT_VDDQ_DDR:
+            rc = PF09_VoltageGet(&g_pf09Dev, PF09_REG_SW4, PF09_STATE_VRUN,
+                &level);
+            break;
+        case BRD_SM_VOLT_VDD2_DDR:
+            rc = PF09_VoltageGet(&g_pf09Dev, PF09_REG_SW5, PF09_STATE_VRUN,
+                &level);
+            break;
+        case BRD_SM_VOLT_SD_CARD:
+            rc = PF09_VoltageGet(&g_pf09Dev, PF09_REG_LDO1, PF09_STATE_VRUN,
+                &level);
+            break;
+        case BRD_SM_VOLT_NVCC_SD2:
+            rc = PF09_VoltageGet(&g_pf09Dev, PF09_REG_LDO2, PF09_STATE_VRUN,
+                &level);
+            break;
+        default:
+            status = SM_ERR_NOT_FOUND;
+            break;
+    }
+
+    /* Return result */
+    if ((status == SM_ERR_SUCCESS) && rc)
+    {
+        *voltageLevel = (int32_t) level;
+    }
+
+    /* Translate error */
+    if ((status == SM_ERR_SUCCESS) && !rc)
+    {
+        status = SM_ERR_HARDWARE_ERROR;
+    }
+
+    /* Return status */
+    return status;
+}
+
+/*--------------------------------------------------------------------------*/
+/* Suspend SoC voltages                                                     */
+/*--------------------------------------------------------------------------*/
+void BRD_SM_VoltageSuspend(bool offArm)
+{
+    /* Turn off VDD_ARM */
+    if (offArm && (s_modeArm != DEV_SM_VOLT_MODE_OFF))
+    {
+        /* Save VDD_ARM mode */
+        s_modeArmSave = s_modeArm;
+
+        (void) BRD_SM_VoltageModeSet(DEV_SM_VOLT_ARM, DEV_SM_VOLT_MODE_OFF);
+    }
+}
+
+/*--------------------------------------------------------------------------*/
+/* Restore SoC voltages                                                     */
+/*--------------------------------------------------------------------------*/
+void BRD_SM_VoltageRestore(void)
+{
+    /* Restore VDD_SOC level */
+    if (s_levelSoc != BOARD_VOLT_SOC)
+    {
+        /* Restore voltage as enable resets the PF53 */
+        (void) BRD_SM_VoltageLevelSet(DEV_SM_VOLT_SOC, s_levelSoc);
+    }
+
+    /* Restore VDD_ARM mode */
+    if (s_modeArm != s_modeArmSave)
+    {
+        if (PF09_GpioCtrlSet(&g_pf09Dev, PF09_GPIO4, PF53_STATE_VRUN,
+            true))
+        {
+            /* Wait for PF53 power up and ramp */
+            SystemTimeDelay(1000U);
+
+            s_modeArm = DEV_SM_VOLT_MODE_ON;
+        }
+    }
+
+    /* Restore VDD_ARM level */
+    if (s_levelArm != BOARD_VOLT_ARM)
+    {
+        /* Restore voltage as enable resets the PF53 */
+        (void) BRD_SM_VoltageLevelSet(DEV_SM_VOLT_ARM, s_levelArm);
+    }
+}
+
diff --git a/boards/tdx-verdin-imx95/sm/brd_sm_voltage.h b/boards/tdx-verdin-imx95/sm/brd_sm_voltage.h
new file mode 100755
index 0000000..1734b6f
--- /dev/null
+++ b/boards/tdx-verdin-imx95/sm/brd_sm_voltage.h
@@ -0,0 +1,213 @@
+/*
+** ###################################################################
+**
+**     Copyright 2023-2024 NXP
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of the copyright holder nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+** ###################################################################
+*/
+
+/*==========================================================================*/
+/*!
+ * @addtogroup BRD_SM_TDXVERDINIMX95
+ * @{
+ *
+ * @file
+ * @brief
+ *
+ * Header file containing the SM API for the board voltages.
+ */
+/*==========================================================================*/
+
+#ifndef BRD_SM_VOLTAGE_H
+#define BRD_SM_VOLTAGE_H
+
+/* Includes */
+
+#include "sm.h"
+#include "dev_sm.h"
+
+/* Defines */
+
+/*!
+ * @name Board redirection defines
+ * @{
+ */
+#define SM_VOLTAGENAMEGET       BRD_SM_VoltageNameGet   /*!< Voltage name */
+#define SM_VOLTAGEDESCRIBE      BRD_SM_VoltageDescribe  /*!< Voltage describe */
+#define SM_VOLTAGEMODESET       BRD_SM_VoltageModeSet   /*!< Set voltage mode */
+#define SM_VOLTAGEMODEGET       BRD_SM_VoltageModeGet   /*!< Get coltage mode */
+#define SM_VOLTAGELEVELSET      BRD_SM_VoltageLevelSet  /*!< Set voltage level */
+#define SM_VOLTAGELEVELGET      BRD_SM_VoltageLevelGet  /*!< Get voltage level */
+/** @} */
+
+/*! Number of board voltages */
+#define BRD_SM_NUM_VOLT  7UL
+
+/*! Total number of sensors */
+#define SM_NUM_VOLT  (DEV_SM_NUM_VOLT + BRD_SM_NUM_VOLT)
+
+/*!
+ * @name BRD_SM voltage domains
+ */
+/** @{ */
+#define BRD_SM_VOLT_VDD_GPIO_3P3  (DEV_SM_NUM_VOLT + 0U)  /*!< VDD GPIO 3.3v */
+#define BRD_SM_VOLT_VDD_ANA_0P8   (DEV_SM_NUM_VOLT + 1U)  /*!< VDD ANA 0.8v */
+#define BRD_SM_VOLT_VDD_GPIO_1P8  (DEV_SM_NUM_VOLT + 2U)  /*!< VDD GPIO 1.8v */
+#define BRD_SM_VOLT_VDDQ_DDR      (DEV_SM_NUM_VOLT + 3U)  /*!< DDR VDDQ */
+#define BRD_SM_VOLT_VDD2_DDR      (DEV_SM_NUM_VOLT + 4U)  /*!< DDR VDD2 */
+#define BRD_SM_VOLT_SD_CARD       (DEV_SM_NUM_VOLT + 5U)  /*!< SD1 */
+#define BRD_SM_VOLT_NVCC_SD2      (DEV_SM_NUM_VOLT + 6U)  /*!< SD2 */
+/** @} */
+
+/* Types */
+
+/* Functions */
+
+/*!
+ * Get a board voltage domain name.
+ *
+ * @param[in]     domainId        Domain name to get
+ * @param[out]    voltNameAddr    Return pointer to name
+ * @param[out]    len             Return max length of all domain names
+ *
+ * This function allows the caller to get the name of a voltage domain.
+ *
+ * @return Returns the status (::SM_ERR_SUCCESS = success).
+ *
+ * Return errors (see @ref STATUS "SM error codes"):
+ * - ::SM_ERR_NOT_FOUND: if \a domainId is invalid.
+ */
+int32_t BRD_SM_VoltageNameGet(uint32_t domainId, string *voltNameAddr,
+    int32_t *len);
+
+/*!
+ * Get a board voltage domain description.
+ *
+ * @param[in]     domainId  Voltage description to get
+ * @param[out]    range     Pointer to return range
+ *
+ * This function allows the caller to get the voltage range for
+ * a voltage. The range contains the high, low, and step voltage
+ * in microvolts (uV).
+ *
+ * @return Returns the status (::SM_ERR_SUCCESS = success).
+ *
+ * Return errors (see @ref STATUS "SM error codes"):
+ * - ::SM_ERR_NOT_FOUND: if \a domainId is invalid.
+ */
+int32_t BRD_SM_VoltageDescribe(uint32_t domainId,
+    dev_sm_voltage_range_t *range);
+
+/*!
+ * Set a board voltage mode.
+ *
+ * @param[in]     domainId      Identifier for the voltage domain
+ * @param[in]     voltMode      Voltage mode to set
+ *
+ * This function allows the caller to set the current mode of
+ * a voltage domain.
+ *
+ * @return Returns the status (::SM_ERR_SUCCESS = success).
+ *
+ * Return errors (see @ref STATUS "SM error codes"):
+ * - ::SM_ERR_NOT_FOUND: if \a domainId is invalid.
+ */
+int32_t BRD_SM_VoltageModeSet(uint32_t domainId, uint8_t voltMode);
+
+/*!
+ * Get a board voltage mode.
+ *
+ * @param[in]     domainId      Identifier for the voltage domain
+ * @param[out]    voltMode      Pointer to return the voltage mode
+ *
+ * This function allows the caller to request the current mode of
+ * a voltage domain.
+ *
+ * @return Returns the status (::SM_ERR_SUCCESS = success).
+ *
+ * Return errors (see @ref STATUS "SM error codes"):
+ * - ::SM_ERR_NOT_FOUND: if \a domainId is invalid.
+ */
+int32_t BRD_SM_VoltageModeGet(uint32_t domainId, uint8_t *voltMode);
+
+/*!
+ * Set a board voltage level.
+ *
+ * @param[in]     domainId      Identifier for the voltage domain
+ * @param[in]     voltageLevel  Voltage level to set
+ *
+ * This function allows the caller to set the current level of
+ * a voltage domain.
+ *
+ * @return Returns the status (::SM_ERR_SUCCESS = success).
+ *
+ * Return errors (see @ref STATUS "SM error codes"):
+ * - ::SM_ERR_NOT_FOUND: if \a domainId is invalid.
+ * - ::SM_ERR_INVALID_PARAMETERS: if \a voltageLevel is negative.
+ * - other from BRD_SM_SupplyLevelSet()
+ */
+int32_t BRD_SM_VoltageLevelSet(uint32_t domainId, int32_t voltageLevel);
+
+/*!
+ * Get a board voltage level.
+ *
+ * @param[in]     domainId      Identifier for the voltage domain
+ * @param[out]    voltageLevel  Pointer to return the voltage level
+ *
+ * This function allows the caller to request the current level of
+ * a voltage domain.
+ *
+ * @return Returns the status (::SM_ERR_SUCCESS = success).
+ *
+ * Return errors (see @ref STATUS "SM error codes"):
+ * - ::SM_ERR_NOT_FOUND: if \a domainId is invalid.
+ * - other from BRD_SM_SupplyLevelGet()
+ */
+int32_t BRD_SM_VoltageLevelGet(uint32_t domainId, int32_t *voltageLevel);
+
+/*!
+ * Suspend voltage modes/levels.
+ *
+ * @param[in]     offArm        Turn off VDD_ARM if on
+ *
+ * This function saves and disabled the ARM voltage.
+ */
+void BRD_SM_VoltageSuspend(bool offArm);
+
+/*!
+ * Restore voltage modes/levels.
+ *
+ * This function writes the last set voltage levels back to the PMICs.
+ */
+void BRD_SM_VoltageRestore(void);
+
+#endif /* BRD_SM_VOLTAGE_H */
+
+/** @} */
+
diff --git a/configs/tdx-verdin-imx95.cfg b/configs/tdx-verdin-imx95.cfg
new file mode 100755
index 0000000..e6ea528
--- /dev/null
+++ b/configs/tdx-verdin-imx95.cfg
@@ -0,0 +1,994 @@
+## ###################################################################
+##
+## Copyright 2023-2024 NXP
+##
+## Redistribution and use in source and binary forms, with or without modification,
+## are permitted provided that the following conditions are met:
+##
+## o Redistributions of source code must retain the above copyright notice, this list
+##   of conditions and the following disclaimer.
+##
+## o Redistributions in binary form must reproduce the above copyright notice, this
+##   list of conditions and the following disclaimer in the documentation and/or
+##   other materials provided with the distribution.
+##
+## o Neither the name of the copyright holder nor the names of its
+##   contributors may be used to endorse or promote products derived from this
+##   software without specific prior written permission.
+##
+## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+## WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+## ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+## (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+## ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+## (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+## SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+##
+##
+## ###################################################################
+
+# SM configuration file for the Toradex Verdin iMX95
+
+MAKE    soc=MIMX95, board=tdx-verdin-imx95, build=gcc_cross
+DOX     name=TDXVERDINIMX95, desc="Toradex Verdin iMX95 Configuration Data"
+
+include ../devices/MIMX95/configtool/device.cfg
+
+#==========================================================================#
+# Board                                                                    #
+#==========================================================================#
+
+BOARD               DEBUG_UART_INSTANCE=2
+BOARD               DEBUG_UART_BAUDRATE=115200
+
+BOARD               I2C_INSTANCE=1
+BOARD               I2C_BAUDRATE=400000
+
+#==========================================================================#
+# Common Defines                                                           #
+#==========================================================================#
+
+NOTIFY:             api=notify
+GET:                api=get
+SET:                api=set
+PRIV:               api=priv
+ALL:                api=all
+READONLY:           perm=ro
+
+#==========================================================================#
+# ELE Domain                                                               #
+#==========================================================================#
+
+DOM0                did=0
+
+DATA:               perm=rw
+
+# Resources
+
+# Memory
+
+M33_TCM_SYS         DATA, begin=0x020200000, size=256K
+OCRAM               DATA, begin=0x020480000, size=352K
+DDR                 DATA, begin=0x080000000, end=0x87FFFFFFF
+
+#==========================================================================#
+# ISP Domain                                                               #
+#==========================================================================#
+
+DOM10               did=10
+
+OWNER:              perm=rw
+
+#==========================================================================#
+# V2X Domain                                                               #
+#==========================================================================#
+
+DOM12               did=12
+
+DFMT1:              sa=bypass, pa=bypass
+OWNER:
+
+V2X_FH              OWNER
+
+#==========================================================================#
+# SM M33 EENV                                                              #
+#==========================================================================#
+
+LM0                 name="SM", rpc=none, boot=1, did=2, safe=feenv
+
+DFMT0:              sa=secure
+DFMT1:              sa=secure, pa=privileged
+OWNER:              perm=sec_rw, api=all
+ACCESS:             perm=sec_rw, api=all, mdid=none
+TEST_MU:            perm=sec_rw
+
+EXEC:               perm=sec_rwx
+DATA:               perm=sec_rw
+
+MODE                msel=1, boot=1
+MODE                msel=2, boot=1
+
+# API
+
+# Modified via PERF protocol
+CLK_A55MTRBUS            ALL
+CLK_ADC                  ALL
+CLK_BUSAON               ALL
+CLK_BUSM7                ALL
+CLK_BUSNETCMIX           ALL
+CLK_BUSWAKEUP            ALL
+CLK_CAMAPB               ALL
+CLK_CAMAXI               ALL
+CLK_CAMCM0               ALL
+CLK_CAMISI               ALL
+CLK_DISPAPB              ALL
+CLK_DISPAXI              ALL
+CLK_ELE                  ALL
+CLK_ENET                 ALL
+CLK_ENETPHYTEST200M      ALL
+CLK_ENETPHYTEST500M      ALL
+CLK_ENETPHYTEST667M      ALL
+CLK_FRO                  ALL
+CLK_GPU                  ALL
+CLK_GPUAPB               ALL
+CLK_HSIO                 ALL
+CLK_HSIOACSCAN480M       ALL
+CLK_HSIOACSCAN80M        ALL
+CLK_HSIOPCIETEST160M     ALL
+CLK_HSIOPCIETEST400M     ALL
+CLK_HSIOPCIETEST500M     ALL
+CLK_HSIOUSBTEST50M       ALL
+CLK_HSIOUSBTEST60M       ALL
+CLK_NOC                  ALL
+CLK_NOCAPB               ALL
+CLK_NPU                  ALL
+CLK_NPUAPB               ALL
+CLK_OSC24M               ALL
+CLK_OSC32K               ALL
+CLK_SYSPLL1_PFD0         ALL
+CLK_SYSPLL1_PFD0_DIV2    ALL
+CLK_SYSPLL1_PFD0_UNGATED ALL
+CLK_SYSPLL1_PFD1         ALL
+CLK_SYSPLL1_PFD1_DIV2    ALL
+CLK_SYSPLL1_PFD1_UNGATED ALL
+CLK_SYSPLL1_PFD2         ALL
+CLK_SYSPLL1_PFD2_DIV2    ALL
+CLK_SYSPLL1_PFD2_UNGATED ALL
+CLK_SYSPLL1_VCO          ALL
+CLK_TEMPSENSE_GPR_SEL    ALL
+CLK_TMU                  ALL
+CLK_V2XPK                ALL
+CLK_VPU                  ALL
+CLK_VPUAPB               ALL
+CLK_VPUJPEG              ALL
+CLK_WAKEUPAXI            ALL
+
+# Resources
+
+M33P                OWNER  # CPUs must be first
+ANATOP              OWNER
+ATU_A               OWNER
+ATU_M               OWNER
+AXBS_AON            OWNER
+BBNSM               OWNER
+BLK_CTRL_BBSMMIX    OWNER
+BLK_CTRL_DDRMIX     OWNER
+BLK_CTRL_NOCMIX     OWNER
+BLK_CTRL_NS_AONMIX  OWNER
+BLK_CTRL_S_AONMIX   OWNER
+BLK_CTRL_WAKEUPMIX  OWNER
+CCM                 OWNER
+DAP                 OWNER
+DDR_CTRL            OWNER
+DDR_PHY             OWNER
+DDR_PM              OWNER
+DRAM_PLL            OWNER
+ELE                 OWNER
+FSB                 READONLY
+GIC                 ACCESS
+GPC                 OWNER
+GPIO1               ACCESS
+GPR0                OWNER
+GPR1                OWNER
+GPR2                OWNER
+GPR3                OWNER
+GPV_CAMERA          OWNER
+GPV_CENTRAL         OWNER
+GPV_DISPLAY         OWNER
+GPV_HSIO            OWNER
+GPV_MAIN            OWNER
+GPV_MEGA            OWNER
+GPV_VPU             OWNER
+IOMUXC              OWNER
+IOMUX_GPR           OWNER
+JTAG                OWNER
+LPI2C1              OWNER
+LPUART2             OWNER
+M33_CACHE_CTRL      OWNER
+M33_PCF             OWNER
+M33_PSF             OWNER
+M33_TCM_ECC         OWNER
+MU1_A               TEST_MU
+MU1_B               OWNER
+MU2_A               TEST_MU
+MU2_B               OWNER
+MU3_A               TEST_MU
+MU3_B               OWNER
+MU4_A               TEST_MU
+MU4_B               OWNER
+MU5_A               TEST_MU
+MU5_B               OWNER
+MU6_A               TEST_MU
+MU6_B               OWNER
+MU_ELE0             OWNER
+ROMCP_M33           OWNER
+SRAM_CTL_1          OWNER
+SRAM_CTL_N          OWNER
+SRC                 OWNER
+SYSCTR_CTL          OWNER
+SYSCTR_RD           OWNER
+TEMP_A55            OWNER
+TRDC_A              OWNER
+TRDC_C              OWNER
+TRDC_D              OWNER
+TRDC_E              OWNER
+TRDC_G              OWNER
+TRDC_H              OWNER
+TRDC_M              OWNER
+TRDC_N              OWNER
+TRDC_V              OWNER
+TRDC_W              OWNER
+TSTMR1              OWNER
+WDOG1               OWNER
+WDOG2               OWNER
+
+# SAF
+
+CMU_A1              OWNER
+CMU_A2              OWNER
+CMU_ANA             OWNER
+CMU_DDR1            OWNER
+CMU_DDR2            OWNER
+CMU_N1              OWNER
+CMU_N2              OWNER
+CMU_W1              OWNER
+CMU_W2              OWNER
+CRC_A               OWNER
+C_STCU              OWNER
+DMA_CRC             OWNER
+EIM_A               OWNER
+EIM_N               OWNER
+EIM_NPU             OWNER
+EIM_W               OWNER
+ERM_A               OWNER
+ERM_NPU             OWNER
+ERM_W               OWNER
+FCCU                OWNER
+FCCU_FHID           OWNER
+INTM                OWNER
+L_STCU_A            OWNER
+L_STCU_DDR          OWNER
+L_STCU_N            OWNER
+L_STCU_NPUMIX       OWNER
+
+# Pins
+
+PIN_FCCU_ERR0         OWNER
+PIN_I2C1_SCL          OWNER
+PIN_I2C1_SDA          OWNER
+PIN_PDM_BIT_STREAM1   OWNER
+PIN_UART2_RXD         ACCESS
+PIN_UART2_TXD         ACCESS
+PIN_WDOG_ANY          OWNER
+
+# Memory
+
+M33_ROM             EXEC, begin=0x000000000, end=0x00003FFFF
+M33_TCM_CODE        EXEC, begin=0x0201C0000, size=256K
+M33_TCM_SYS         EXEC, begin=0x020200000, size=256K
+M7MIX               DATA, begin=0x04A050000, end=0x04A0AFFFF
+
+# Faults
+
+FAULT_SW3           OWNER, reaction=grp_reset
+FAULT_SW4           OWNER, reaction=sys_reset
+
+#==========================================================================#
+# M7 EENV                                                                  #
+#==========================================================================#
+
+LM1                 name="M7", rpc=scmi, boot=2, skip=1, did=4, safe=seenv
+
+DFMT0:              sa=secure
+DFMT1:              sa=secure, pa=privileged
+OWNER:              perm=rw, api=all
+ACCESS:             perm=sec_rw, api=all, mdid=none
+
+EXEC:               perm=full
+DATA:               perm=rw
+
+# Start/Stop (mSel=0)
+
+PD_M7               stop=2
+CPU_M7P             start=1, stop=1
+
+# Start/Stop (mSel=1)
+
+MODE                msel=1, boot=2
+
+PD_M7               msel=1, stop=2
+CPU_M7P             msel=1, start=1, stop=1
+
+# Start/Stop (mSel=2)
+
+PD_M7               msel=2, stop=2
+CPU_M7P             msel=2, start=1, stop=1
+
+# RPC Interface
+
+SCMI_AGENT0         name="M7"
+MAILBOX             type=mu, mu=9, test=8, priority=high
+CHANNEL             db=0, xport=smt, check=crc32, rpc=scmi, type=a2p, \
+                    test=default
+CHANNEL             db=1, xport=smt, check=crc32, rpc=scmi, \
+                    type=p2a_notify, notify=24
+CHANNEL             db=2, xport=smt, check=crc32, rpc=scmi, \
+                    type=p2a_priority
+
+# API
+
+BRD_SM_CTRL_TEST          ALL
+BRD_SM_SENSOR_TEMP_PF09   SET
+BRD_SM_SENSOR_TEMP_PF5301 SET
+BRD_SM_SENSOR_TEMP_PF5302 SET
+BUTTON                    NOTIFY
+FUSA                      ALL
+LMM_2                     ALL
+PERLPI_LPUART3            ALL
+RTC                       PRIV
+SENSOR_TEMP_ANA           ALL, test
+SYS                       ALL
+
+# Resources
+
+M7P                 OWNER  # CPUs must be first
+CAN_FD1             ACCESS
+FSB                 READONLY
+IRQSTEER_M7         OWNER
+LPIT1               OWNER
+LPTMR1              OWNER
+LPTMR2              OWNER
+LPTPM1              OWNER
+LPUART3             OWNER, test
+MSGINTR1            OWNER
+MSGINTR2            OWNER
+MU5_A               OWNER
+MU7_B               OWNER
+MU8_B               OWNER
+MU_ELE5             OWNER
+PD_M7               test
+SYSCTR_RD           READONLY
+TSTMR2              OWNER
+V2X_SHE1            OWNER
+WDOG5               OWNER
+
+# Pins
+
+PIN_GPIO_IO14       ACCESS
+PIN_GPIO_IO15       ACCESS
+
+# Memory
+
+M7MIX               DATA, begin=0x020380000, end=0x02047FFFF
+M7MIX               DATA, begin=0x04A060000, end=0x04A09FFFF
+DDR                 EXEC, begin=0x080000000, end=0x089FFFFFF
+
+# Faults
+
+FAULT_M7_LOCKUP     OWNER, reaction=lm_reset
+FAULT_M7_RESET      OWNER, reaction=lm_reset
+FAULT_SW0           OWNER, reaction=fusa
+FAULT_SW1           OWNER, reaction=lm_reset
+FAULT_WDOG5         OWNER, reaction=lm_reset
+
+#==========================================================================#
+# A55 secure EENV                                                          #
+#==========================================================================#
+
+LM2                 name="AP", rpc=scmi, boot=3, skip=1, did=3, default
+
+DFMT0:              sa=bypass
+DFMT1:              sa=secure, pa=privileged
+OWNER:              perm=sec_rw, api=all
+
+EXEC:               perm=sec_rwx
+DATA:               perm=rw
+
+# Start/Stop (mSel=0)
+
+VOLT_ARM            start=1|1, stop=9
+PD_A55P             start=2, stop=8, test
+PD_A55C0            stop=7
+PD_A55C1            stop=6
+PD_A55C2            stop=5
+PD_A55C3            stop=4
+PD_A55C4            stop=3
+PD_A55C5            stop=2
+PERF_A55            start=3|3
+CPU_A55C0           start=4
+CPU_A55P            stop=1
+
+# Start/Stop (mSel=1)
+
+VOLT_ARM            msel=1, start=1|1, stop=9
+PD_A55P             msel=1, start=2, stop=8
+PD_A55C0            msel=1, stop=7
+PD_A55C1            msel=1, stop=6
+PD_A55C2            msel=1, stop=5
+PD_A55C3            msel=1, stop=4
+PD_A55C4            msel=1, stop=3
+PD_A55C5            msel=1, stop=2
+PERF_A55            msel=1, start=3|3
+CPU_A55C0           msel=1, start=4
+CPU_A55P            msel=1, stop=1
+
+# Start/Stop (mSel=2)
+
+VOLT_ARM            msel=2, start=1|1, stop=9
+PD_A55P             msel=2, start=2, stop=8
+PD_A55C0            msel=2, stop=7
+PD_A55C1            msel=2, stop=6
+PD_A55C2            msel=2, stop=5
+PD_A55C3            msel=2, stop=4
+PD_A55C4            msel=2, stop=3
+PD_A55C5            msel=2, stop=2
+PERF_A55            msel=2, start=3|3
+CPU_A55C0           msel=2, start=4
+CPU_A55P            msel=2, stop=1
+
+# RPC Interface
+
+SCMI_AGENT1         name="AP-S", secure
+MAILBOX             type=mu, mu=1, test=0
+CHANNEL             db=0, xport=smt, rpc=scmi, type=a2p
+CHANNEL             db=1, xport=smt, rpc=scmi, type=p2a_notify, notify=24
+
+# API
+
+PERF_A55            ALL
+PERF_DRAM           ALL
+PERLPI_CAN1         ALL
+PERLPI_CAN2         ALL
+PERLPI_CAN3         ALL
+PERLPI_CAN4         ALL
+PERLPI_CAN5         ALL
+PERLPI_GPIO2        ALL
+PERLPI_GPIO3        ALL
+PERLPI_GPIO4        ALL
+PERLPI_GPIO5        ALL
+PERLPI_LPUART1      ALL
+PERLPI_LPUART2      ALL
+PERLPI_LPUART3      ALL
+PERLPI_LPUART4      ALL
+PERLPI_LPUART5      ALL
+PERLPI_LPUART6      ALL
+PERLPI_LPUART7      ALL
+PERLPI_LPUART8      ALL
+PERLPI_WDOG3        ALL
+PERLPI_WDOG4        ALL
+SYS                 ALL
+
+# Resources
+
+A55C0               OWNER  # CPUs must be first
+A55C1               OWNER  # CPUs must be first
+A55C2               OWNER  # CPUs must be first
+A55C3               OWNER  # CPUs must be first
+A55C4               OWNER  # CPUs must be first
+A55C5               OWNER  # CPUs must be first
+A55P                OWNER, sema=0x442313F8
+ARM_PLL             OWNER
+MU1_A               OWNER
+MU_ELE1             OWNER
+MU_ELE2             OWNER
+
+# Pins
+
+# Memory
+
+OCRAM               EXEC, begin=0x020480000, size=256K
+DDR                 EXEC, begin=0x08A000000, end=0x08DFFFFFF
+
+# Faults
+
+FAULT_SW2           OWNER, reaction=lm_reset
+FAULT_WDOG3         OWNER, reaction=lm_reset
+FAULT_WDOG4         OWNER, reaction=lm_reset
+
+#==========================================================================#
+# A55 non-secure EENV                                                      #
+#==========================================================================#
+
+DFMT0:              sa=nonsecure
+DFMT1:              sa=nonsecure, pa=privileged
+
+OWNER:              perm=rw, api=all
+ACCESS:             perm=rw, api=all, mdid=none
+
+EXEC:               perm=full
+DATA:               perm=rw
+
+# RPC Interface
+
+SCMI_AGENT2         name="AP-NS"
+MAILBOX             type=mu, mu=3, test=2
+CHANNEL             db=0, xport=smt, rpc=scmi, type=a2p
+CHANNEL             db=1, xport=smt, rpc=scmi, type=p2a_notify
+
+# API
+
+AUDIO_PLL1                ALL
+AUDIO_PLL2                ALL
+BRD_SM_SENSOR_TEMP_PF09   ALL
+BRD_SM_SENSOR_TEMP_PF5301 SET
+BRD_SM_SENSOR_TEMP_PF5302 SET
+BUTTON                    ALL, test
+CLOCK_DISP1PIX            ALL
+CLOCK_DISP2PIX            ALL
+CLOCK_DISP3PIX            ALL
+CLOCK_EXT                 ALL
+CLOCK_EXT1                ALL
+CLOCK_EXT2                ALL
+CLOCK_HSIOPCIEAUX         ALL
+CLOCK_OUT1                ALL
+CLOCK_OUT2                ALL
+CLOCK_OUT3                ALL
+CLOCK_OUT4                ALL
+CLOCK_USBPHYBURUNIN       ALL
+CLOCK_VPUDSP              ALL
+HSIO_PLL                  ALL
+LDB_PLL                   ALL
+LMM_1                     NOTIFY
+PERF_A55                  ALL
+PERF_DRAM                 ALL
+RTC                       ALL, test
+SENSOR_TEMP_A55           ALL
+SENSOR_TEMP_ANA           SET
+SYS                       NOTIFY
+
+# Resources
+
+ADC                 OWNER
+BLK_CTRL_CAMERAMIX  OWNER
+BLK_CTRL_DISPLAYMIX OWNER
+BLK_CTRL_GPUMIX     OWNER
+BLK_CTRL_HSIOMIX    OWNER
+BLK_CTRL_NETCMIX    OWNER
+BLK_CTRL_NPUMIX     OWNER
+BLK_CTRL_VPUMIX     OWNER
+CAMERA1             OWNER
+CAMERA2             OWNER
+CAMERA3             OWNER
+CAMERA4             OWNER
+CAMERA5             OWNER
+CAMERA6             OWNER
+CAMERA7             OWNER
+CAMERA8             OWNER
+CAN_FD1             ACCESS
+CAN_FD2             OWNER
+CAN_FD3             OWNER
+CAN_FD4             OWNER
+CAN_FD5             OWNER
+DC                  OWNER, test
+DC0                 OWNER
+DC1                 OWNER
+DC_2DBLIT           OWNER
+DC_BLITINT          OWNER
+DC_CMDSEQ           OWNER
+DC_DISPENG          OWNER
+DC_DISPENG_INT      OWNER
+DC_FL0              OWNER
+DC_FL1              OWNER
+DC_INT_CTL          OWNER
+DC_PIXENGINE        OWNER
+DC_XPC              OWNER
+DC_YUV0             OWNER
+DC_YUV1             OWNER
+DC_YUV2             OWNER
+DC_YUV3             OWNER
+DDR_PM              ACCESS
+EDMA1_MP            OWNER
+EDMA1_CH0           OWNER
+EDMA1_CH1           OWNER
+EDMA1_CH2           OWNER
+EDMA1_CH3           OWNER
+EDMA1_CH4           OWNER
+EDMA1_CH5           OWNER
+EDMA1_CH6           OWNER
+EDMA1_CH7           OWNER
+EDMA1_CH8           OWNER
+EDMA1_CH9           OWNER
+EDMA1_CH10          OWNER
+EDMA1_CH11          OWNER
+EDMA1_CH12          OWNER
+EDMA1_CH13          OWNER
+EDMA1_CH14          OWNER
+EDMA1_CH15          OWNER
+EDMA1_CH16          OWNER
+EDMA1_CH17          OWNER
+EDMA1_CH18          OWNER
+EDMA1_CH19          OWNER
+EDMA1_CH20          OWNER
+EDMA1_CH21          OWNER
+EDMA1_CH22          OWNER
+EDMA1_CH23          OWNER
+EDMA1_CH24          OWNER
+EDMA1_CH25          OWNER
+EDMA1_CH26          OWNER
+EDMA1_CH27          OWNER
+EDMA1_CH28          OWNER
+EDMA1_CH29          OWNER
+EDMA1_CH30          OWNER
+EDMA1_CH31          OWNER
+EDMA2_MP            OWNER
+EDMA2_CH0_1         OWNER
+EDMA2_CH2_3         OWNER
+EDMA2_CH4_5         OWNER
+EDMA2_CH6_7         OWNER
+EDMA2_CH8_9         OWNER
+EDMA2_CH10_11       OWNER
+EDMA2_CH12_13       OWNER
+EDMA2_CH14_15       OWNER
+EDMA2_CH16_17       OWNER
+EDMA2_CH18_19       OWNER
+EDMA2_CH20_21       OWNER
+EDMA2_CH22_23       OWNER
+EDMA2_CH24_25       OWNER
+EDMA2_CH26_27       OWNER
+EDMA2_CH28_29       OWNER
+EDMA2_CH30_31       OWNER
+EDMA2_CH32_33       OWNER
+EDMA2_CH34_35       OWNER
+EDMA2_CH36_37       OWNER
+EDMA2_CH38_39       OWNER
+EDMA2_CH40_41       OWNER
+EDMA2_CH42_43       OWNER
+EDMA2_CH44_45       OWNER
+EDMA2_CH46_47       OWNER
+EDMA2_CH48_49       OWNER
+EDMA2_CH50_51       OWNER
+EDMA2_CH52_53       OWNER
+EDMA2_CH54_55       OWNER
+EDMA2_CH56_57       OWNER
+EDMA2_CH58_59       OWNER
+EDMA2_CH60_61       OWNER
+EDMA2_CH62_63       OWNER
+EDMA3_MP            OWNER
+EDMA3_CH0_1         OWNER
+EDMA3_CH2_3         OWNER
+EDMA3_CH4_5         OWNER
+EDMA3_CH6_7         OWNER
+EDMA3_CH8_9         OWNER
+EDMA3_CH10_11       OWNER
+EDMA3_CH12_13       OWNER
+EDMA3_CH14_15       OWNER
+EDMA3_CH16_17       OWNER
+EDMA3_CH18_19       OWNER
+EDMA3_CH20_21       OWNER
+EDMA3_CH22_23       OWNER
+EDMA3_CH24_25       OWNER
+EDMA3_CH26_27       OWNER
+EDMA3_CH28_29       OWNER
+EDMA3_CH30_31       OWNER
+EDMA3_CH32_33       OWNER
+EDMA3_CH34_35       OWNER
+EDMA3_CH36_37       OWNER
+EDMA3_CH38_39       OWNER
+EDMA3_CH40_41       OWNER
+EDMA3_CH42_43       OWNER
+EDMA3_CH44_45       OWNER
+EDMA3_CH46_47       OWNER
+EDMA3_CH48_49       OWNER
+EDMA3_CH50_51       OWNER
+EDMA3_CH52_53       OWNER
+EDMA3_CH54_55       OWNER
+EDMA3_CH56_57       OWNER
+EDMA3_CH58_59       OWNER
+EDMA3_CH60_61       OWNER
+EDMA3_CH62_63       OWNER
+FLEXIO1             OWNER
+FLEXIO2             OWNER
+FLEXSPI1            OWNER
+FSB                 READONLY
+GIC                 OWNER
+GPIO1               ACCESS
+GPIO2               OWNER
+GPIO3               OWNER
+GPIO4               OWNER
+GPIO5               OWNER
+GPR4                OWNER, test
+GPR5                OWNER
+GPR6                OWNER
+GPR7                OWNER
+GPU_NPROT           OWNER
+GPU_PROT            OWNER, test
+I3C1                OWNER
+I3C2                OWNER
+ISI1                OWNER
+ISI2                OWNER
+ISI3                OWNER
+ISI4                OWNER
+ISI5                OWNER
+ISI6                OWNER
+ISI7                OWNER
+ISI8                OWNER
+ISP_CPU             OWNER
+ISP_MGR             OWNER, test
+JPEG_DEC            OWNER
+LPI2C2              OWNER
+LPI2C3              OWNER
+LPI2C4              OWNER
+LPI2C5              OWNER
+LPI2C6              OWNER
+LPI2C7              OWNER
+LPI2C8              OWNER
+LPIT2               OWNER
+LPSPI1              OWNER
+LPSPI2              OWNER
+LPSPI3              OWNER
+LPSPI4              OWNER
+LPSPI5              OWNER
+LPSPI6              OWNER
+LPSPI7              OWNER
+LPSPI8              OWNER
+LPTPM2              OWNER
+LPTPM3              OWNER
+LPTPM4              OWNER
+LPTPM5              OWNER
+LPTPM6              OWNER
+LPUART1             OWNER
+LPUART2             ACCESS
+LPUART3             ACCESS
+LPUART4             OWNER
+LPUART5             OWNER
+LPUART6             OWNER
+LPUART7             OWNER
+LPUART8             OWNER, test
+LVDS                OWNER
+MIPI_CSI0           OWNER
+MIPI_CSI1           OWNER
+MIPI_DSI            OWNER
+MIPI_PHY            OWNER
+MJPEG_DEC1          OWNER
+MJPEG_DEC2          OWNER
+MJPEG_DEC3          OWNER
+MJPEG_DEC4          OWNER
+MJPEG_ENC           OWNER
+MJPEG_ENC1          OWNER
+MJPEG_ENC2          OWNER
+MJPEG_ENC3          OWNER
+MJPEG_ENC4          OWNER
+MU2_A               OWNER
+MU3_A               OWNER
+MU4_A               OWNER
+MU6_A               OWNER
+MU7_A               OWNER
+MU8_A               OWNER
+MU_ELE3             OWNER
+MU_ELE4             OWNER
+NETC                OWNER, test
+NETC0               OWNER
+NETC1               OWNER
+NETC2               OWNER
+NETC_ECAM           OWNER
+NETC_EMDIO0         OWNER
+NETC_IERB           OWNER
+NETC_LDID1          OWNER, kpa=1, sid=0x20
+NETC_LDID2          OWNER, kpa=1, sid=0x21
+NETC_LDID3          OWNER, kpa=1, sid=0x22
+NETC_LDID4          OWNER, kpa=1, sid=0x23
+NETC_LDID5          OWNER, kpa=1, sid=0x24
+NETC_LDID6          OWNER, kpa=1, sid=0x25
+NETC_LDID7          OWNER, kpa=1, sid=0x26
+NETC_LDID8          OWNER, kpa=1, sid=0x27
+NETC_PRB            OWNER
+NETC_TIMER0         OWNER
+NETC_VSI0           OWNER
+NETC_VSI1           OWNER
+NETC_VSI2           OWNER
+NETC_VSI3           OWNER
+NETC_VSI4           OWNER
+NETC_VSI5           OWNER
+NPU                 OWNER, test
+PCI1_LUT0           OWNER, kpa=0, sid=0x10
+PCI1_LUT1           OWNER, kpa=0, sid=0x11
+PCI1_LUT2           OWNER, kpa=0, sid=0x12
+PCI1_LUT3           OWNER, kpa=0, sid=0x13
+PCI1_LUT4           OWNER, kpa=0, sid=0x14
+PCI1_LUT5           OWNER, kpa=0, sid=0x15
+PCI1_LUT6           OWNER, kpa=0, sid=0x16
+PCI1_LUT7           OWNER, kpa=0, sid=0x17
+PCI2_LUT0           OWNER, kpa=0, sid=0x18
+PCI2_LUT1           OWNER, kpa=0, sid=0x19
+PCI2_LUT2           OWNER, kpa=0, sid=0x1a
+PCI2_LUT3           OWNER, kpa=0, sid=0x1b
+PCI2_LUT4           OWNER, kpa=0, sid=0x1c
+PCI2_LUT5           OWNER, kpa=0, sid=0x1d
+PCI2_LUT6           OWNER, kpa=0, sid=0x1e
+PCI2_LUT7           OWNER, kpa=0, sid=0x1f
+PCIE1_OUT           OWNER
+PCIE1_ROOT          OWNER
+PCIE2_OUT           OWNER
+PCIE2_ROOT          OWNER
+PDM                 OWNER
+SAI1                OWNER, test
+SAI2                OWNER
+SAI3                OWNER
+SAI4                OWNER
+SAI5                OWNER
+SEMA41              OWNER
+SEMA42              OWNER
+SMMU                OWNER
+SPDIF1              OWNER
+SYSCTR_CMP          OWNER
+SYSCTR_RD_STOP      READONLY
+USB1                OWNER, test, kpa=0, sid=0xe
+USB2                OWNER, kpa=0, sid=0xf
+USDHC1              OWNER
+USDHC2              OWNER
+USDHC3              OWNER
+V2X_APP0            OWNER
+V2X_DEBUG           OWNER
+V2X_FH              ACCESS
+V2X_HSM1            OWNER
+V2X_HSM2            OWNER
+V2X_SHE0            OWNER
+VIDEO_PLL1          OWNER
+VPU                 OWNER, test
+VPU1                OWNER
+VPU2                OWNER
+VPU3                OWNER
+VPU4                OWNER
+WDOG3               OWNER
+WDOG4               OWNER
+XSPI                OWNER
+
+# Pins
+
+PIN_CCM_CLKO1        OWNER
+PIN_CCM_CLKO2        OWNER
+PIN_CCM_CLKO3        OWNER
+PIN_CCM_CLKO4        OWNER
+PIN_DAP_TCLK_SWCLK   OWNER
+PIN_DAP_TDI          OWNER
+PIN_DAP_TDO_TRACESWO OWNER
+PIN_DAP_TMS_SWDIO    OWNER
+PIN_ENET1_MDC        OWNER
+PIN_ENET1_MDIO       OWNER
+PIN_ENET1_RD0        OWNER
+PIN_ENET1_RD1        OWNER
+PIN_ENET1_RD2        OWNER
+PIN_ENET1_RD3        OWNER
+PIN_ENET1_RX_CTL     OWNER
+PIN_ENET1_RXC        OWNER
+PIN_ENET1_TD0        OWNER
+PIN_ENET1_TD1        OWNER
+PIN_ENET1_TD2        OWNER
+PIN_ENET1_TD3        OWNER
+PIN_ENET1_TX_CTL     OWNER
+PIN_ENET1_TXC        OWNER
+PIN_ENET2_MDC        OWNER
+PIN_ENET2_MDIO       OWNER
+PIN_ENET2_RD0        OWNER
+PIN_ENET2_RD1        OWNER
+PIN_ENET2_RD2        OWNER
+PIN_ENET2_RD3        OWNER
+PIN_ENET2_RX_CTL     OWNER
+PIN_ENET2_RXC        OWNER
+PIN_ENET2_TD0        OWNER
+PIN_ENET2_TD1        OWNER
+PIN_ENET2_TD2        OWNER
+PIN_ENET2_TD3        OWNER
+PIN_ENET2_TX_CTL     OWNER
+PIN_ENET2_TXC        OWNER
+PIN_GPIO_IO00        OWNER
+PIN_GPIO_IO01        OWNER
+PIN_GPIO_IO02        OWNER
+PIN_GPIO_IO03        OWNER
+PIN_GPIO_IO04        OWNER
+PIN_GPIO_IO05        OWNER
+PIN_GPIO_IO06        OWNER
+PIN_GPIO_IO07        OWNER
+PIN_GPIO_IO08        OWNER
+PIN_GPIO_IO09        OWNER
+PIN_GPIO_IO10        OWNER
+PIN_GPIO_IO11        OWNER
+PIN_GPIO_IO12        OWNER
+PIN_GPIO_IO13        OWNER
+PIN_GPIO_IO14        ACCESS
+PIN_GPIO_IO15        ACCESS
+PIN_GPIO_IO16        OWNER
+PIN_GPIO_IO17        OWNER
+PIN_GPIO_IO18        OWNER
+PIN_GPIO_IO19        OWNER
+PIN_GPIO_IO20        OWNER
+PIN_GPIO_IO21        OWNER
+PIN_GPIO_IO22        OWNER
+PIN_GPIO_IO23        OWNER
+PIN_GPIO_IO24        OWNER
+PIN_GPIO_IO25        OWNER
+PIN_GPIO_IO26        OWNER
+PIN_GPIO_IO27        OWNER
+PIN_GPIO_IO28        OWNER
+PIN_GPIO_IO29        OWNER
+PIN_GPIO_IO30        OWNER
+PIN_GPIO_IO31        OWNER
+PIN_GPIO_IO32        OWNER
+PIN_GPIO_IO33        OWNER
+PIN_GPIO_IO34        OWNER
+PIN_GPIO_IO35        OWNER
+PIN_GPIO_IO36        OWNER
+PIN_GPIO_IO37        OWNER
+PIN_I2C2_SCL         OWNER
+PIN_I2C2_SDA         OWNER
+PIN_PDM_BIT_STREAM0  OWNER
+PIN_PDM_CLK          OWNER
+PIN_SAI1_RXD0        OWNER
+PIN_SAI1_TXC         OWNER
+PIN_SAI1_TXD0        OWNER
+PIN_SAI1_TXFS        OWNER
+PIN_SD1_CLK          OWNER
+PIN_SD1_CMD          OWNER
+PIN_SD1_DATA0        OWNER
+PIN_SD1_DATA1        OWNER
+PIN_SD1_DATA2        OWNER
+PIN_SD1_DATA3        OWNER
+PIN_SD1_DATA4        OWNER
+PIN_SD1_DATA5        OWNER
+PIN_SD1_DATA6        OWNER
+PIN_SD1_DATA7        OWNER
+PIN_SD1_STROBE       OWNER
+PIN_SD2_CD_B         OWNER
+PIN_SD2_CLK          OWNER
+PIN_SD2_CMD          OWNER
+PIN_SD2_DATA0        OWNER
+PIN_SD2_DATA1        OWNER
+PIN_SD2_DATA2        OWNER
+PIN_SD2_DATA3        OWNER
+PIN_SD2_RESET_B      OWNER
+PIN_SD2_VSELECT      OWNER
+PIN_SD3_CLK          OWNER
+PIN_SD3_CMD          OWNER
+PIN_SD3_DATA0        OWNER
+PIN_SD3_DATA1        OWNER
+PIN_SD3_DATA2        OWNER
+PIN_SD3_DATA3        OWNER
+PIN_UART1_RXD        OWNER, test
+PIN_UART1_TXD        OWNER
+PIN_UART2_RXD        ACCESS
+PIN_UART2_TXD        ACCESS
+PIN_XSPI1_DATA0      OWNER
+PIN_XSPI1_DATA1      OWNER
+PIN_XSPI1_DATA2      OWNER
+PIN_XSPI1_DATA3      OWNER
+PIN_XSPI1_DATA4      OWNER
+PIN_XSPI1_DATA5      OWNER
+PIN_XSPI1_DATA6      OWNER
+PIN_XSPI1_DATA7      OWNER
+PIN_XSPI1_DQS        OWNER
+PIN_XSPI1_SCLK       OWNER
+PIN_XSPI1_SS0_B      OWNER
+PIN_XSPI1_SS1_B      OWNER
+
+# Memory
+
+FLEXSPI1_MEM        EXEC, begin=0x000000000, end=0x0FFFFFFFF
+OCRAM_C             EXEC, begin=0x001000000, end=0x001017FFF
+OCRAM               EXEC, begin=0x0204C0000, size=96K
+GPU                 DATA, begin=0x04D900000, end=0x04DD7FFFF
+DDR                 EXEC, begin=0x088000000, end=0x089FFFFFF
+DDR                 EXEC, begin=0x08E000000, end=0x87FFFFFFF
+
diff --git a/configs/tdx-verdin-imx95/config.dox b/configs/tdx-verdin-imx95/config.dox
new file mode 100755
index 0000000..c50f58b
--- /dev/null
+++ b/configs/tdx-verdin-imx95/config.dox
@@ -0,0 +1,49 @@
+/*
+** ###################################################################
+**
+** Copyright 2023-2024 NXP
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** o Redistributions of source code must retain the above copyright notice, this list
+**   of conditions and the following disclaimer.
+**
+** o Redistributions in binary form must reproduce the above copyright notice, this
+**   list of conditions and the following disclaimer in the documentation and/or
+**   other materials provided with the distribution.
+**
+** o Neither the name of the copyright holder nor the names of its
+**   contributors may be used to endorse or promote products derived from this
+**   software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+** ###################################################################
+*/
+
+/*!
+ * @addtogroup SM_CONFIG
+ * @{
+ */
+
+/*!
+
+@defgroup CONFIG_TDXVERDINIMX95 CONFIG_TDXVERDINIMX95: Toradex Verdin iMX95 Configuration Data
+
+@brief Module for Toradex Verdin iMX95 Configuration Data.
+
+*/
+
+/** @} */
+
diff --git a/configs/tdx-verdin-imx95/config.mak b/configs/tdx-verdin-imx95/config.mak
new file mode 100755
index 0000000..1d85c22
--- /dev/null
+++ b/configs/tdx-verdin-imx95/config.mak
@@ -0,0 +1,44 @@
+## ###################################################################
+##
+## Copyright 2023-2024 NXP
+##
+## Redistribution and use in source and binary forms, with or without modification,
+## are permitted provided that the following conditions are met:
+##
+## o Redistributions of source code must retain the above copyright notice, this list
+##   of conditions and the following disclaimer.
+##
+## o Redistributions in binary form must reproduce the above copyright notice, this
+##   list of conditions and the following disclaimer in the documentation and/or
+##   other materials provided with the distribution.
+##
+## o Neither the name of the copyright holder nor the names of its
+##   contributors may be used to endorse or promote products derived from this
+##   software without specific prior written permission.
+##
+## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+## WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+## ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+## (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+## ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+## (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+## SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+##
+##
+## ###################################################################
+
+BOARD ?= tdx-verdin-imx95
+
+USES_FUSA ?= 1
+
+include ./devices/MIMX95/sm/Makefile
+include ./boards/$(BOARD)/sm/Makefile
+include ./sm/lmm/Makefile
+include ./sm/rpc/mb_mu/Makefile
+include ./sm/rpc/scmi/Makefile
+include ./sm/rpc/smt/Makefile
+include ./sm/makefiles/gcc_cross.mak
+
diff --git a/configs/tdx-verdin-imx95/config_bctrl.h b/configs/tdx-verdin-imx95/config_bctrl.h
new file mode 100755
index 0000000..0ff0171
--- /dev/null
+++ b/configs/tdx-verdin-imx95/config_bctrl.h
@@ -0,0 +1,100 @@
+/*
+** ###################################################################
+**
+** Copyright 2023-2024 NXP
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** o Redistributions of source code must retain the above copyright notice, this list
+**   of conditions and the following disclaimer.
+**
+** o Redistributions in binary form must reproduce the above copyright notice, this
+**   list of conditions and the following disclaimer in the documentation and/or
+**   other materials provided with the distribution.
+**
+** o Neither the name of the copyright holder nor the names of its
+**   contributors may be used to endorse or promote products derived from this
+**   software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+** ###################################################################
+*/
+
+/*==========================================================================*/
+/*!
+ * @addtogroup CONFIG_TDXVERDINIMX95
+ * @{
+ *
+ * @file
+ * @brief
+ *
+ * Header file containing configuration info for the device block controls.
+ */
+/*==========================================================================*/
+
+#ifndef CONFIG_BCTRL_H
+#define CONFIG_BCTRL_H
+
+/* Includes */
+
+#include "config_user.h"
+
+/* Defines */
+
+/*--------------------------------------------------------------------------*/
+/* BCTRL A Config                                                           */
+/*--------------------------------------------------------------------------*/
+
+/*! Config for BCTRL A */
+#define SM_BCTRL_A_CONFIG \
+    { \
+        SM_CFG_W1(0x00000008U), 0x00001804U, \
+        SM_CFG_W1(0x0000000CU), 0x0000E56BU, \
+        SM_CFG_W1(0x00000010U), 0x0000E56BU, \
+        SM_CFG_W1(0x00000014U), 0x0000E56BU, \
+        SM_CFG_W1(0x00000018U), 0x0000E56BU, \
+        SM_CFG_W1(0x0000001CU), 0x0000E56BU, \
+        SM_CFG_W1(0x00000020U), 0x0000E56BU, \
+        SM_CFG_W1(0x00000024U), 0x00000291U, \
+        SM_CFG_END \
+    }
+
+/*--------------------------------------------------------------------------*/
+/* BCTRL W Config                                                           */
+/*--------------------------------------------------------------------------*/
+
+/*! Config for BCTRL W */
+#define SM_BCTRL_W_CONFIG \
+    { \
+        SM_CFG_W1(0x00000030U), 0xFBF7FFFFU, \
+        SM_CFG_W1(0x00000034U), 0xFBF7FFFFU, \
+        SM_CFG_W1(0x00000038U), 0xFBF7FFFFU, \
+        SM_CFG_W1(0x0000003CU), 0xFBF7FFFFU, \
+        SM_CFG_W1(0x00000040U), 0xFBF7FFFFU, \
+        SM_CFG_W1(0x00000044U), 0xFBF7FFFFU, \
+        SM_CFG_W1(0x00000048U), 0x04080000U, \
+        SM_CFG_W1(0x00000050U), 0x00000001U, \
+        SM_CFG_W1(0x00000054U), 0x00000001U, \
+        SM_CFG_W1(0x00000058U), 0x00000001U, \
+        SM_CFG_W1(0x0000005CU), 0x00000001U, \
+        SM_CFG_W1(0x00000060U), 0x00000001U, \
+        SM_CFG_W1(0x00000064U), 0x00000001U, \
+        SM_CFG_END \
+    }
+
+#endif /* CONFIG_BCTRL_H */
+
+/** @} */
+
diff --git a/configs/tdx-verdin-imx95/config_board.h b/configs/tdx-verdin-imx95/config_board.h
new file mode 100755
index 0000000..9d8eae2
--- /dev/null
+++ b/configs/tdx-verdin-imx95/config_board.h
@@ -0,0 +1,69 @@
+/*
+** ###################################################################
+**
+** Copyright 2023-2024 NXP
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** o Redistributions of source code must retain the above copyright notice, this list
+**   of conditions and the following disclaimer.
+**
+** o Redistributions in binary form must reproduce the above copyright notice, this
+**   list of conditions and the following disclaimer in the documentation and/or
+**   other materials provided with the distribution.
+**
+** o Neither the name of the copyright holder nor the names of its
+**   contributors may be used to endorse or promote products derived from this
+**   software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+** ###################################################################
+*/
+
+/*==========================================================================*/
+/*!
+ * @addtogroup CONFIG_TDXVERDINIMX95
+ * @{
+ *
+ * @file
+ * @brief
+ *
+ * Header file containing configuration info for the board abstraction.
+ */
+/*==========================================================================*/
+
+#ifndef CONFIG_BOARD_H
+#define CONFIG_BOARD_H
+
+/* Includes */
+
+#include "config_user.h"
+
+/* Defines */
+
+/*! Config for UART instance */
+#define BOARD_DEBUG_UART_INSTANCE    2U
+/*! Config for UART baudrate */
+#define BOARD_DEBUG_UART_BAUDRATE    115200U
+
+/*! Config for PMIC I2C instance */
+#define BOARD_I2C_INSTANCE           1U
+/*! Config for PMIC I2C baudrate */
+#define BOARD_I2C_BAUDRATE           400000U
+
+#endif /* CONFIG_BOARD_H */
+
+/** @} */
+
diff --git a/configs/tdx-verdin-imx95/config_dev.h b/configs/tdx-verdin-imx95/config_dev.h
new file mode 100644
index 0000000..125a124
--- /dev/null
+++ b/configs/tdx-verdin-imx95/config_dev.h
@@ -0,0 +1,65 @@
+/*
+** ###################################################################
+**
+** Copyright 2023-2024 NXP
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** o Redistributions of source code must retain the above copyright notice, this list
+**   of conditions and the following disclaimer.
+**
+** o Redistributions in binary form must reproduce the above copyright notice, this
+**   list of conditions and the following disclaimer in the documentation and/or
+**   other materials provided with the distribution.
+**
+** o Neither the name of the copyright holder nor the names of its
+**   contributors may be used to endorse or promote products derived from this
+**   software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+** ###################################################################
+*/
+
+/*==========================================================================*/
+/*!
+ * @addtogroup CONFIG_TDXVERDINIMX95
+ * @{
+ *
+ * @file
+ * @brief
+ *
+ * Header file containing configuration info for the device abstraction.
+ */
+/*==========================================================================*/
+
+#ifndef CONFIG_DEV_H
+#define CONFIG_DEV_H
+
+/* Includes */
+
+#include "config_user.h"
+
+/* Defines */
+
+/*! Config for device */
+#define SM_DEV_CONFIG_DATA \
+    { \
+        .cpuSemaAddr[DEV_SM_CPU_A55P] = 0x442313F8U, \
+    }
+
+#endif /* CONFIG_DEV_H */
+
+/** @} */
+
diff --git a/configs/tdx-verdin-imx95/config_lmm.h b/configs/tdx-verdin-imx95/config_lmm.h
new file mode 100755
index 0000000..36fdf63
--- /dev/null
+++ b/configs/tdx-verdin-imx95/config_lmm.h
@@ -0,0 +1,220 @@
+/*
+** ###################################################################
+**
+** Copyright 2023-2024 NXP
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** o Redistributions of source code must retain the above copyright notice, this list
+**   of conditions and the following disclaimer.
+**
+** o Redistributions in binary form must reproduce the above copyright notice, this
+**   list of conditions and the following disclaimer in the documentation and/or
+**   other materials provided with the distribution.
+**
+** o Neither the name of the copyright holder nor the names of its
+**   contributors may be used to endorse or promote products derived from this
+**   software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+** ###################################################################
+*/
+
+/*==========================================================================*/
+/*!
+ * @addtogroup CONFIG_TDXVERDINIMX95
+ * @{
+ *
+ * @file
+ * @brief
+ *
+ * Header file containing configuration info for the logical machine manager.
+ */
+/*==========================================================================*/
+
+#ifndef CONFIG_LMM_H
+#define CONFIG_LMM_H
+
+/* Includes */
+
+#include "config_user.h"
+
+/* Defines */
+
+/*--------------------------------------------------------------------------*/
+/* LM0 Config (SM)                                                          */
+/*--------------------------------------------------------------------------*/
+
+/*! Config for LM0 */
+#define SM_LM0_CONFIG \
+    { \
+        .name = "SM", \
+        .rpcType = SM_RPC_NONE, \
+        .boot[0] = 1U, \
+        .safeType = LMM_SAFE_TYPE_FEENV, \
+        .boot[1] = 1U, \
+        .boot[2] = 1U, \
+    }
+
+/*--------------------------------------------------------------------------*/
+/* LM1 Config (M7)                                                          */
+/*--------------------------------------------------------------------------*/
+
+/*! Config for LM1 */
+#define SM_LM1_CONFIG \
+    { \
+        .name = "M7", \
+        .rpcType = SM_RPC_SCMI, \
+        .rpcInst = 0U, \
+        .boot[0] = 2U, \
+        .bootSkip[0] = 1U, \
+        .safeType = LMM_SAFE_TYPE_SEENV, \
+        .start = 1U, \
+        .stop = 1U, \
+        .boot[1] = 2U, \
+    }
+
+/*--------------------------------------------------------------------------*/
+/* LM2 Config (AP)                                                          */
+/*--------------------------------------------------------------------------*/
+
+/*! Config for LM2 */
+#define SM_LM2_CONFIG \
+    { \
+        .name = "AP", \
+        .rpcType = SM_RPC_SCMI, \
+        .rpcInst = 1U, \
+        .boot[0] = 3U, \
+        .bootSkip[0] = 1U, \
+        .start = 4U, \
+        .stop = 7U, \
+    }
+
+/*--------------------------------------------------------------------------*/
+/* LM Config                                                                */
+/*--------------------------------------------------------------------------*/
+
+/*! Config for number of LM */
+#define SM_NUM_LM  3U
+
+/*! Config data array for LM */
+#define SM_LM_CONFIG_DATA \
+    SM_LM0_CONFIG, \
+    SM_LM1_CONFIG, \
+    SM_LM2_CONFIG
+
+/*! Number of  mSel */
+#define SM_LM_NUM_MSEL  3U
+
+/*! Number of  S-EENV */
+#define SM_LM_NUM_SEENV  1U
+
+/*! Config name */
+#define SM_LM_CFG_NAME  "tdx-verdin-imx95"
+
+/*! Default LM for monitor */
+#define SM_LM_DEFAULT  2U
+
+/*--------------------------------------------------------------------------*/
+/* LM Start/Stop Lists                                                      */
+/*--------------------------------------------------------------------------*/
+
+/*! Config for number of start */
+#define SM_LM_NUM_START  15U
+
+/*! LM start list */
+#define SM_LM_START_DATA \
+    {.lmId = 1U, .mSel = 0U, .ss = LMM_SS_CPU, .rsrc = DEV_SM_CPU_M7P}, \
+    {.lmId = 1U, .mSel = 1U, .ss = LMM_SS_CPU, .rsrc = DEV_SM_CPU_M7P}, \
+    {.lmId = 1U, .mSel = 2U, .ss = LMM_SS_CPU, .rsrc = DEV_SM_CPU_M7P}, \
+    {.lmId = 2U, .mSel = 0U, .ss = LMM_SS_VOLT, .rsrc = DEV_SM_VOLT_ARM, \
+     .numArg = 1, .arg[0] = 1U,}, \
+    {.lmId = 2U, .mSel = 1U, .ss = LMM_SS_VOLT, .rsrc = DEV_SM_VOLT_ARM, \
+     .numArg = 1, .arg[0] = 1U,}, \
+    {.lmId = 2U, .mSel = 2U, .ss = LMM_SS_VOLT, .rsrc = DEV_SM_VOLT_ARM, \
+     .numArg = 1, .arg[0] = 1U,}, \
+    {.lmId = 2U, .mSel = 0U, .ss = LMM_SS_PD, .rsrc = DEV_SM_PD_A55P}, \
+    {.lmId = 2U, .mSel = 1U, .ss = LMM_SS_PD, .rsrc = DEV_SM_PD_A55P}, \
+    {.lmId = 2U, .mSel = 2U, .ss = LMM_SS_PD, .rsrc = DEV_SM_PD_A55P}, \
+    {.lmId = 2U, .mSel = 0U, .ss = LMM_SS_PERF, .rsrc = DEV_SM_PERF_A55, \
+     .numArg = 1, .arg[0] = 3U,}, \
+    {.lmId = 2U, .mSel = 1U, .ss = LMM_SS_PERF, .rsrc = DEV_SM_PERF_A55, \
+     .numArg = 1, .arg[0] = 3U,}, \
+    {.lmId = 2U, .mSel = 2U, .ss = LMM_SS_PERF, .rsrc = DEV_SM_PERF_A55, \
+     .numArg = 1, .arg[0] = 3U,}, \
+    {.lmId = 2U, .mSel = 0U, .ss = LMM_SS_CPU, .rsrc = DEV_SM_CPU_A55C0}, \
+    {.lmId = 2U, .mSel = 1U, .ss = LMM_SS_CPU, .rsrc = DEV_SM_CPU_A55C0}, \
+    {.lmId = 2U, .mSel = 2U, .ss = LMM_SS_CPU, .rsrc = DEV_SM_CPU_A55C0},
+
+/*! Config for number of stop */
+#define SM_LM_NUM_STOP  33U
+
+/*! LM stop list */
+#define SM_LM_STOP_DATA \
+    {.lmId = 1U, .mSel = 0U, .ss = LMM_SS_CPU, .rsrc = DEV_SM_CPU_M7P}, \
+    {.lmId = 1U, .mSel = 1U, .ss = LMM_SS_CPU, .rsrc = DEV_SM_CPU_M7P}, \
+    {.lmId = 1U, .mSel = 2U, .ss = LMM_SS_CPU, .rsrc = DEV_SM_CPU_M7P}, \
+    {.lmId = 1U, .mSel = 0U, .ss = LMM_SS_PD, .rsrc = DEV_SM_PD_M7}, \
+    {.lmId = 1U, .mSel = 1U, .ss = LMM_SS_PD, .rsrc = DEV_SM_PD_M7}, \
+    {.lmId = 1U, .mSel = 2U, .ss = LMM_SS_PD, .rsrc = DEV_SM_PD_M7}, \
+    {.lmId = 2U, .mSel = 0U, .ss = LMM_SS_CPU, .rsrc = DEV_SM_CPU_A55P}, \
+    {.lmId = 2U, .mSel = 1U, .ss = LMM_SS_CPU, .rsrc = DEV_SM_CPU_A55P}, \
+    {.lmId = 2U, .mSel = 2U, .ss = LMM_SS_CPU, .rsrc = DEV_SM_CPU_A55P}, \
+    {.lmId = 2U, .mSel = 0U, .ss = LMM_SS_PD, .rsrc = DEV_SM_PD_A55C5}, \
+    {.lmId = 2U, .mSel = 1U, .ss = LMM_SS_PD, .rsrc = DEV_SM_PD_A55C5}, \
+    {.lmId = 2U, .mSel = 2U, .ss = LMM_SS_PD, .rsrc = DEV_SM_PD_A55C5}, \
+    {.lmId = 2U, .mSel = 0U, .ss = LMM_SS_PD, .rsrc = DEV_SM_PD_A55C4}, \
+    {.lmId = 2U, .mSel = 1U, .ss = LMM_SS_PD, .rsrc = DEV_SM_PD_A55C4}, \
+    {.lmId = 2U, .mSel = 2U, .ss = LMM_SS_PD, .rsrc = DEV_SM_PD_A55C4}, \
+    {.lmId = 2U, .mSel = 0U, .ss = LMM_SS_PD, .rsrc = DEV_SM_PD_A55C3}, \
+    {.lmId = 2U, .mSel = 1U, .ss = LMM_SS_PD, .rsrc = DEV_SM_PD_A55C3}, \
+    {.lmId = 2U, .mSel = 2U, .ss = LMM_SS_PD, .rsrc = DEV_SM_PD_A55C3}, \
+    {.lmId = 2U, .mSel = 0U, .ss = LMM_SS_PD, .rsrc = DEV_SM_PD_A55C2}, \
+    {.lmId = 2U, .mSel = 1U, .ss = LMM_SS_PD, .rsrc = DEV_SM_PD_A55C2}, \
+    {.lmId = 2U, .mSel = 2U, .ss = LMM_SS_PD, .rsrc = DEV_SM_PD_A55C2}, \
+    {.lmId = 2U, .mSel = 0U, .ss = LMM_SS_PD, .rsrc = DEV_SM_PD_A55C1}, \
+    {.lmId = 2U, .mSel = 1U, .ss = LMM_SS_PD, .rsrc = DEV_SM_PD_A55C1}, \
+    {.lmId = 2U, .mSel = 2U, .ss = LMM_SS_PD, .rsrc = DEV_SM_PD_A55C1}, \
+    {.lmId = 2U, .mSel = 0U, .ss = LMM_SS_PD, .rsrc = DEV_SM_PD_A55C0}, \
+    {.lmId = 2U, .mSel = 1U, .ss = LMM_SS_PD, .rsrc = DEV_SM_PD_A55C0}, \
+    {.lmId = 2U, .mSel = 2U, .ss = LMM_SS_PD, .rsrc = DEV_SM_PD_A55C0}, \
+    {.lmId = 2U, .mSel = 0U, .ss = LMM_SS_PD, .rsrc = DEV_SM_PD_A55P}, \
+    {.lmId = 2U, .mSel = 1U, .ss = LMM_SS_PD, .rsrc = DEV_SM_PD_A55P}, \
+    {.lmId = 2U, .mSel = 2U, .ss = LMM_SS_PD, .rsrc = DEV_SM_PD_A55P}, \
+    {.lmId = 2U, .mSel = 0U, .ss = LMM_SS_VOLT, .rsrc = DEV_SM_VOLT_ARM}, \
+    {.lmId = 2U, .mSel = 1U, .ss = LMM_SS_VOLT, .rsrc = DEV_SM_VOLT_ARM}, \
+    {.lmId = 2U, .mSel = 2U, .ss = LMM_SS_VOLT, .rsrc = DEV_SM_VOLT_ARM},
+
+/*--------------------------------------------------------------------------*/
+/* LM Fault Lists                                                           */
+/*--------------------------------------------------------------------------*/
+
+/*! LM fault reactions */
+#define SM_LM_FAULT_DATA \
+    [DEV_SM_FAULT_SW3] = {.reaction = LMM_REACT_GRP_RESET, .lm = 0U}, \
+    [DEV_SM_FAULT_SW4] = {.reaction = LMM_REACT_SYS_RESET, .lm = 0U}, \
+    [DEV_SM_FAULT_M7_LOCKUP] = {.reaction = LMM_REACT_LM_RESET, .lm = 1U}, \
+    [DEV_SM_FAULT_M7_RESET] = {.reaction = LMM_REACT_LM_RESET, .lm = 1U}, \
+    [DEV_SM_FAULT_SW0] = {.reaction = LMM_REACT_FUSA, .lm = 1U}, \
+    [DEV_SM_FAULT_SW1] = {.reaction = LMM_REACT_LM_RESET, .lm = 1U}, \
+    [DEV_SM_FAULT_WDOG5] = {.reaction = LMM_REACT_LM_RESET, .lm = 1U}, \
+    [DEV_SM_FAULT_SW2] = {.reaction = LMM_REACT_LM_RESET, .lm = 2U}, \
+    [DEV_SM_FAULT_WDOG3] = {.reaction = LMM_REACT_LM_RESET, .lm = 2U}, \
+    [DEV_SM_FAULT_WDOG4] = {.reaction = LMM_REACT_LM_RESET, .lm = 2U},
+
+#endif /* CONFIG_LMM_H */
+
+/** @} */
+
diff --git a/configs/tdx-verdin-imx95/config_mb_mu.h b/configs/tdx-verdin-imx95/config_mb_mu.h
new file mode 100755
index 0000000..9c1b823
--- /dev/null
+++ b/configs/tdx-verdin-imx95/config_mb_mu.h
@@ -0,0 +1,118 @@
+/*
+** ###################################################################
+**
+** Copyright 2023-2024 NXP
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** o Redistributions of source code must retain the above copyright notice, this list
+**   of conditions and the following disclaimer.
+**
+** o Redistributions in binary form must reproduce the above copyright notice, this
+**   list of conditions and the following disclaimer in the documentation and/or
+**   other materials provided with the distribution.
+**
+** o Neither the name of the copyright holder nor the names of its
+**   contributors may be used to endorse or promote products derived from this
+**   software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+** ###################################################################
+*/
+
+/*==========================================================================*/
+/*!
+ * @addtogroup CONFIG_TDXVERDINIMX95
+ * @{
+ *
+ * @file
+ * @brief
+ *
+ * Header file containing configuration info for the MB_MU.
+ */
+/*==========================================================================*/
+
+#ifndef CONFIG_MB_MU_H
+#define CONFIG_MB_MU_H
+
+/* Includes */
+
+#include "config_user.h"
+#include "mb_mu_config.h"
+
+/* Defines */
+
+/*--------------------------------------------------------------------------*/
+/* LM0 MB_MU Config (SM)                                                    */
+/*--------------------------------------------------------------------------*/
+
+/*--------------------------------------------------------------------------*/
+/* LM1 MB_MU Config (M7)                                                    */
+/*--------------------------------------------------------------------------*/
+
+/*! Config for MU9 MB */
+#define SM_MB_MU9_CONFIG \
+    { \
+        .mu = 9U, \
+        .priority = IRQ_PRIO_NOPREEMPT_HIGH, \
+        .xportType[0] = SM_XPORT_SMT, \
+        .xportChannel[0] = 0U, \
+        .xportType[1] = SM_XPORT_SMT, \
+        .xportChannel[1] = 1U, \
+        .xportType[2] = SM_XPORT_SMT, \
+        .xportChannel[2] = 2U, \
+    }
+
+/*--------------------------------------------------------------------------*/
+/* LM2 MB_MU Config (AP)                                                    */
+/*--------------------------------------------------------------------------*/
+
+/*! Config for MU1 MB */
+#define SM_MB_MU1_CONFIG \
+    { \
+        .mu = 1U, \
+        .xportType[0] = SM_XPORT_SMT, \
+        .xportChannel[0] = 3U, \
+        .xportType[1] = SM_XPORT_SMT, \
+        .xportChannel[1] = 4U, \
+    }
+
+/*! Config for MU3 MB */
+#define SM_MB_MU3_CONFIG \
+    { \
+        .mu = 3U, \
+        .xportType[0] = SM_XPORT_SMT, \
+        .xportChannel[0] = 5U, \
+        .xportType[1] = SM_XPORT_SMT, \
+        .xportChannel[1] = 6U, \
+    }
+
+/*--------------------------------------------------------------------------*/
+/* MB MU Config                                                             */
+/*--------------------------------------------------------------------------*/
+
+/*! Config for number of MU MB */
+#define SM_NUM_MB_MU  3U
+
+/*! Config data array for MU MB */
+#define SM_MB_MU_CONFIG_DATA \
+    SM_MB_MU9_CONFIG, \
+    SM_MB_MU1_CONFIG, \
+    SM_MB_MU3_CONFIG
+
+#endif /* CONFIG_MB_MU_H */
+
+/** @} */
+
diff --git a/configs/tdx-verdin-imx95/config_scmi.h b/configs/tdx-verdin-imx95/config_scmi.h
new file mode 100755
index 0000000..7e77fc8
--- /dev/null
+++ b/configs/tdx-verdin-imx95/config_scmi.h
@@ -0,0 +1,714 @@
+/*
+** ###################################################################
+**
+** Copyright 2023-2024 NXP
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** o Redistributions of source code must retain the above copyright notice, this list
+**   of conditions and the following disclaimer.
+**
+** o Redistributions in binary form must reproduce the above copyright notice, this
+**   list of conditions and the following disclaimer in the documentation and/or
+**   other materials provided with the distribution.
+**
+** o Neither the name of the copyright holder nor the names of its
+**   contributors may be used to endorse or promote products derived from this
+**   software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+** ###################################################################
+*/
+
+/*==========================================================================*/
+/*!
+ * @addtogroup CONFIG_TDXVERDINIMX95
+ * @{
+ *
+ * @file
+ * @brief
+ *
+ * Header file containing configuration info for the SCMI RPC.
+ */
+/*==========================================================================*/
+
+#ifndef CONFIG_SCMI_H
+#define CONFIG_SCMI_H
+
+/* Includes */
+
+#include "config_user.h"
+
+/* Defines */
+
+/*--------------------------------------------------------------------------*/
+/* SCMI AGENT0 Config (M7)                                                  */
+/*--------------------------------------------------------------------------*/
+
+/*! Config for SCMI agent 0 */
+#define SM_SCMI_AGNT0_CONFIG \
+    { \
+        .name = "M7", \
+        .scmiInst = 0U, \
+        .domId = 4U, \
+        .secure = 0U, \
+        .seenvId = 1U, \
+        .buttonPerms[DEV_SM_BUTTON_0] = SM_SCMI_PERM_NOTIFY, \
+        .clkPerms[DEV_SM_CLK_CAN1] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_LPTMR1] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_LPTMR2] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_LPUART3] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_M7SYSTICK] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_M7] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_TSTMR2] = SM_SCMI_PERM_ALL, \
+        .cpuPerms[DEV_SM_CPU_M7P] = SM_SCMI_PERM_ALL, \
+        .ctrlPerms[BRD_SM_CTRL_TEST] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_CAN1_RX] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_LPTMR2_0] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_LPTMR2_1] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_LPTMR2_2] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_LPUART3_CTS] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_LPUART3_RXD] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_LPUART3_TXD] = SM_SCMI_PERM_ALL, \
+        .faultPerms[DEV_SM_FAULT_M7_LOCKUP] = SM_SCMI_PERM_ALL, \
+        .faultPerms[DEV_SM_FAULT_M7_RESET] = SM_SCMI_PERM_ALL, \
+        .faultPerms[DEV_SM_FAULT_SW0] = SM_SCMI_PERM_ALL, \
+        .faultPerms[DEV_SM_FAULT_SW1] = SM_SCMI_PERM_ALL, \
+        .faultPerms[DEV_SM_FAULT_WDOG5] = SM_SCMI_PERM_ALL, \
+        .fusaPerms = SM_SCMI_PERM_ALL, \
+        .lmmPerms[2] = SM_SCMI_PERM_ALL, \
+        .pdPerms[DEV_SM_PD_M7] = SM_SCMI_PERM_ALL, \
+        .perfPerms[DEV_SM_PERF_M7] = SM_SCMI_PERM_ALL, \
+        .perlpiPerms[DEV_SM_PERLPI_CAN1] = SM_SCMI_PERM_ALL, \
+        .perlpiPerms[DEV_SM_PERLPI_LPUART3] = SM_SCMI_PERM_ALL, \
+        .perlpiPerms[DEV_SM_PERLPI_WDOG5] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_GPIO_IO14] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_GPIO_IO15] = SM_SCMI_PERM_ALL, \
+        .rtcPerms[DEV_SM_RTC_BBNSM] = SM_SCMI_PERM_PRIV, \
+        .sensorPerms[BRD_SM_SENSOR_TEMP_PF09] = SM_SCMI_PERM_SET, \
+        .sensorPerms[BRD_SM_SENSOR_TEMP_PF5301] = SM_SCMI_PERM_SET, \
+        .sensorPerms[BRD_SM_SENSOR_TEMP_PF5302] = SM_SCMI_PERM_SET, \
+        .sensorPerms[DEV_SM_SENSOR_TEMP_ANA] = SM_SCMI_PERM_ALL, \
+        .sysPerms = SM_SCMI_PERM_ALL, \
+    }
+
+/*! Config for SCMI channel 0 */
+#define SM_SCMI_CHN0_CONFIG \
+    { \
+        .agentId = 0U, \
+        .type = SM_SCMI_CHN_A2P, \
+        .xportType = SM_XPORT_SMT, \
+        .xportChannel = 0U, \
+    }
+
+/*! Config for SCMI channel 1 */
+#define SM_SCMI_CHN1_CONFIG \
+    { \
+        .agentId = 0U, \
+        .type = SM_SCMI_CHN_P2A_NOTIFY, \
+        .xportType = SM_XPORT_SMT, \
+        .xportChannel = 1U, \
+    }
+
+/*! Config for SCMI channel 2 */
+#define SM_SCMI_CHN2_CONFIG \
+    { \
+        .agentId = 0U, \
+        .type = SM_SCMI_CHN_P2A_PRIORITY, \
+        .xportType = SM_XPORT_SMT, \
+        .xportChannel = 2U, \
+    }
+
+/*--------------------------------------------------------------------------*/
+/* SCMI Instance 0 Config (M7)                                              */
+/*--------------------------------------------------------------------------*/
+
+/*! Config for SCMI instance 0 */
+#define SM_SCMI0_CONFIG \
+    { \
+        .lmId = 1U, \
+        .numAgents = 1U, \
+        .firstAgent = 0U, \
+    }
+
+/*--------------------------------------------------------------------------*/
+/* SCMI AGENT1 Config (AP-S)                                                */
+/*--------------------------------------------------------------------------*/
+
+/*! Config for SCMI agent 1 */
+#define SM_SCMI_AGNT1_CONFIG \
+    { \
+        .name = "AP-S", \
+        .scmiInst = 1U, \
+        .domId = 3U, \
+        .secure = 1U, \
+        .clkPerms[DEV_SM_CLK_A55C0_GPR_SEL] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_A55C1_GPR_SEL] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_A55C2_GPR_SEL] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_A55C3_GPR_SEL] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_A55C4_GPR_SEL] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_A55C5_GPR_SEL] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_A55PERIPH] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_A55P_GPR_SEL] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_A55] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_ARMPLL_PFD0] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_ARMPLL_PFD0_UNGATED] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_ARMPLL_PFD1] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_ARMPLL_PFD1_UNGATED] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_ARMPLL_PFD2] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_ARMPLL_PFD2_UNGATED] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_ARMPLL_PFD3] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_ARMPLL_PFD3_UNGATED] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_ARMPLL_VCO] = SM_SCMI_PERM_ALL, \
+        .cpuPerms[DEV_SM_CPU_A55C0] = SM_SCMI_PERM_ALL, \
+        .cpuPerms[DEV_SM_CPU_A55C1] = SM_SCMI_PERM_ALL, \
+        .cpuPerms[DEV_SM_CPU_A55C2] = SM_SCMI_PERM_ALL, \
+        .cpuPerms[DEV_SM_CPU_A55C3] = SM_SCMI_PERM_ALL, \
+        .cpuPerms[DEV_SM_CPU_A55C4] = SM_SCMI_PERM_ALL, \
+        .cpuPerms[DEV_SM_CPU_A55C5] = SM_SCMI_PERM_ALL, \
+        .cpuPerms[DEV_SM_CPU_A55P] = SM_SCMI_PERM_ALL, \
+        .faultPerms[DEV_SM_FAULT_SW2] = SM_SCMI_PERM_ALL, \
+        .faultPerms[DEV_SM_FAULT_WDOG3] = SM_SCMI_PERM_ALL, \
+        .faultPerms[DEV_SM_FAULT_WDOG4] = SM_SCMI_PERM_ALL, \
+        .pdPerms[DEV_SM_PD_A55C0] = SM_SCMI_PERM_ALL, \
+        .pdPerms[DEV_SM_PD_A55C1] = SM_SCMI_PERM_ALL, \
+        .pdPerms[DEV_SM_PD_A55C2] = SM_SCMI_PERM_ALL, \
+        .pdPerms[DEV_SM_PD_A55C3] = SM_SCMI_PERM_ALL, \
+        .pdPerms[DEV_SM_PD_A55C4] = SM_SCMI_PERM_ALL, \
+        .pdPerms[DEV_SM_PD_A55C5] = SM_SCMI_PERM_ALL, \
+        .pdPerms[DEV_SM_PD_A55P] = SM_SCMI_PERM_ALL, \
+        .perfPerms[DEV_SM_PERF_A55] = SM_SCMI_PERM_ALL, \
+        .perfPerms[DEV_SM_PERF_DRAM] = SM_SCMI_PERM_ALL, \
+        .perlpiPerms[DEV_SM_PERLPI_CAN1] = SM_SCMI_PERM_ALL, \
+        .perlpiPerms[DEV_SM_PERLPI_CAN2] = SM_SCMI_PERM_ALL, \
+        .perlpiPerms[DEV_SM_PERLPI_CAN3] = SM_SCMI_PERM_ALL, \
+        .perlpiPerms[DEV_SM_PERLPI_CAN4] = SM_SCMI_PERM_ALL, \
+        .perlpiPerms[DEV_SM_PERLPI_CAN5] = SM_SCMI_PERM_ALL, \
+        .perlpiPerms[DEV_SM_PERLPI_GPIO2] = SM_SCMI_PERM_ALL, \
+        .perlpiPerms[DEV_SM_PERLPI_GPIO3] = SM_SCMI_PERM_ALL, \
+        .perlpiPerms[DEV_SM_PERLPI_GPIO4] = SM_SCMI_PERM_ALL, \
+        .perlpiPerms[DEV_SM_PERLPI_GPIO5] = SM_SCMI_PERM_ALL, \
+        .perlpiPerms[DEV_SM_PERLPI_LPUART1] = SM_SCMI_PERM_ALL, \
+        .perlpiPerms[DEV_SM_PERLPI_LPUART2] = SM_SCMI_PERM_ALL, \
+        .perlpiPerms[DEV_SM_PERLPI_LPUART3] = SM_SCMI_PERM_ALL, \
+        .perlpiPerms[DEV_SM_PERLPI_LPUART4] = SM_SCMI_PERM_ALL, \
+        .perlpiPerms[DEV_SM_PERLPI_LPUART5] = SM_SCMI_PERM_ALL, \
+        .perlpiPerms[DEV_SM_PERLPI_LPUART6] = SM_SCMI_PERM_ALL, \
+        .perlpiPerms[DEV_SM_PERLPI_LPUART7] = SM_SCMI_PERM_ALL, \
+        .perlpiPerms[DEV_SM_PERLPI_LPUART8] = SM_SCMI_PERM_ALL, \
+        .perlpiPerms[DEV_SM_PERLPI_WDOG3] = SM_SCMI_PERM_ALL, \
+        .perlpiPerms[DEV_SM_PERLPI_WDOG4] = SM_SCMI_PERM_ALL, \
+        .sysPerms = SM_SCMI_PERM_ALL, \
+    }
+
+/*! Config for SCMI channel 3 */
+#define SM_SCMI_CHN3_CONFIG \
+    { \
+        .agentId = 1U, \
+        .type = SM_SCMI_CHN_A2P, \
+        .xportType = SM_XPORT_SMT, \
+        .xportChannel = 3U, \
+    }
+
+/*! Config for SCMI channel 4 */
+#define SM_SCMI_CHN4_CONFIG \
+    { \
+        .agentId = 1U, \
+        .type = SM_SCMI_CHN_P2A_NOTIFY, \
+        .xportType = SM_XPORT_SMT, \
+        .xportChannel = 4U, \
+    }
+
+/*--------------------------------------------------------------------------*/
+/* SCMI AGENT2 Config (AP-NS)                                               */
+/*--------------------------------------------------------------------------*/
+
+/*! Config for SCMI agent 2 */
+#define SM_SCMI_AGNT2_CONFIG \
+    { \
+        .name = "AP-NS", \
+        .scmiInst = 1U, \
+        .domId = 3U, \
+        .secure = 0U, \
+        .buttonPerms[DEV_SM_BUTTON_0] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_AUDIOPLL1] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_AUDIOPLL1_VCO] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_AUDIOPLL2] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_AUDIOPLL2_VCO] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_AUDIOXCVR] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_CAN1] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_CAN2] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_CAN3] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_CAN4] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_CAN5] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_CCMCKO1] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_CCMCKO2] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_CCMCKO3] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_CCMCKO4] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_DISP1PIX] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_DISP2PIX] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_DISP3PIX] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_DISPOCRAM] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_ENETREF] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_ENETTIMER1] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_EXT1] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_EXT2] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_EXT] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_EXT_GPR_SEL] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_FLEXIO1] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_FLEXIO2] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_FLEXSPI1] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_GPU_CGC] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_HSIOPCIEAUX] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_HSIOPLL] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_HSIOPLL_VCO] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_I3C1SLOW] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_I3C1] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_I3C2SLOW] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_I3C2] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_LDBPLL] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_LDBPLL_VCO] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_LPI2C2] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_LPI2C3] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_LPI2C4] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_LPI2C5] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_LPI2C6] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_LPI2C7] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_LPI2C8] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_LPSPI1] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_LPSPI2] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_LPSPI3] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_LPSPI4] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_LPSPI5] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_LPSPI6] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_LPSPI7] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_LPSPI8] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_LPUART1] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_LPUART2] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_LPUART3] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_LPUART4] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_LPUART5] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_LPUART6] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_LPUART7] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_LPUART8] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_MIPIPHYCFG] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_MIPIPHYPLLBYPASS] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_MIPIPHYPLLREF] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_MIPITESTBYTE] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_MQS1] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_MQS2] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_PDM] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_SAI1] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_SAI2] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_SAI3] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_SAI4] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_SAI5] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_SPDIF] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_TPM2] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_TPM4] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_TPM5] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_TPM6] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_USBPHYBURUNIN] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_USDHC1] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_USDHC2] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_USDHC3] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_VIDEOPLL1] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_VIDEOPLL1_VCO] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_VPUDSP] = SM_SCMI_PERM_ALL, \
+        .clkPerms[DEV_SM_CLK_XSPISLVROOT] = SM_SCMI_PERM_ALL, \
+        .ctrlPerms[DEV_SM_CTRL_ADC_TEST] = SM_SCMI_PERM_ALL, \
+        .ctrlPerms[DEV_SM_CTRL_MQS1_SETTINGS] = SM_SCMI_PERM_ALL, \
+        .ctrlPerms[DEV_SM_CTRL_PDM_CLK_SEL] = SM_SCMI_PERM_ALL, \
+        .ctrlPerms[DEV_SM_CTRL_SAI1_MCLK] = SM_SCMI_PERM_ALL, \
+        .ctrlPerms[DEV_SM_CTRL_SAI3_MCLK] = SM_SCMI_PERM_ALL, \
+        .ctrlPerms[DEV_SM_CTRL_SAI4_MCLK] = SM_SCMI_PERM_ALL, \
+        .ctrlPerms[DEV_SM_CTRL_SAI5_MCLK] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_CAN1_RX] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_CAN2_RX] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_CAN3_RX] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_CAN4_RX] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_CAN5_RX] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_EARC_PHY_SPDIF] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_EXT1_CLK] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_FLEXIO1_0] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_FLEXIO1_10] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_FLEXIO1_11] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_FLEXIO1_12] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_FLEXIO1_13] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_FLEXIO1_14] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_FLEXIO1_15] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_FLEXIO1_16] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_FLEXIO1_17] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_FLEXIO1_18] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_FLEXIO1_19] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_FLEXIO1_1] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_FLEXIO1_20] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_FLEXIO1_21] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_FLEXIO1_22] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_FLEXIO1_23] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_FLEXIO1_24] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_FLEXIO1_25] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_FLEXIO1_26] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_FLEXIO1_27] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_FLEXIO1_2] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_FLEXIO1_30] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_FLEXIO1_31] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_FLEXIO1_3] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_FLEXIO1_4] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_FLEXIO1_5] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_FLEXIO1_6] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_FLEXIO1_7] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_FLEXIO1_8] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_FLEXIO1_9] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_FLEXSPI1_0] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_FLEXSPI1_1] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_FLEXSPI1_2] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_FLEXSPI1_3] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_FLEXSPI1_4] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_FLEXSPI1_5] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_FLEXSPI1_6] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_FLEXSPI1_7] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_FLEXSPI1_DQS] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_FLEXSPI1_SCK] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_I3C2_SCL] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_I3C2_SDA] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_LPI2C3_SCL] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_LPI2C3_SDA] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_LPI2C4_SCL] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_LPI2C4_SDA] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_LPI2C5_SCL] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_LPI2C5_SDA] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_LPI2C6_SCL] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_LPI2C6_SDA] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_LPI2C7_SCL] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_LPI2C7_SDA] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_LPI2C8_SCL] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_LPI2C8_SDA] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_LPSPI4_PCS_0] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_LPSPI4_PCS_1] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_LPSPI4_PCS_2] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_LPSPI4_SCK] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_LPSPI4_SDI] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_LPSPI4_SDO] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_LPUART3_CTS] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_LPUART3_RXD] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_LPUART3_TXD] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_LPUART4_CTS] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_LPUART4_RXD] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_LPUART4_TXD] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_LPUART5_CTS] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_LPUART5_RXD] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_LPUART5_TXD] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_LPUART6_CTS] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_LPUART6_RXD] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_LPUART6_TXD] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_LPUART7_RXD] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_LPUART7_TXD] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_NETC_EMDC] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_NETC_EMDIO] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_NETC_ETH0_RMII_RX_ER] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_NETC_ETH1_RMII_RX_ER] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_NETC_TMR_1588_TRIG1] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_NETC_TMR_1588_TRIG2] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_PDM_BITSTREAM_0] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_PDM_BITSTREAM_1] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_PDM_BITSTREAM_2] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_PDM_BITSTREAM_3] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_SAI1_MCLK] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_SAI2_RXDATA_6] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_SAI2_RXDATA_7] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_SAI3_RXBCLK] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_SAI3_RXSYNC] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_SAI4_RXBCLK] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_SAI4_RXDATA_0] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_SAI4_RXSYNC] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_SAI4_TXBCLK] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_SAI4_TXSYNC] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_SAI5_RXBCLK] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_SAI5_RXDATA_0] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_SAI5_RXDATA_1] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_SAI5_RXDATA_2] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_SAI5_RXDATA_3] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_SAI5_RXSYNC] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_SAI5_TXBCLK] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_SAI5_TXSYNC] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_USDHC3_CLK] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_USDHC3_CMD] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_USDHC3_DAT0] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_USDHC3_DAT1] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_USDHC3_DAT2] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_USDHC3_DAT3] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_XSPI_0] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_XSPI_1] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_XSPI_2] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_XSPI_3] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_XSPI_4] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_XSPI_5] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_XSPI_6] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_XSPI_7] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_XSPI_CS] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_XSPI_DQS] = SM_SCMI_PERM_ALL, \
+        .daisyPerms[DEV_SM_DAISY_XSPI_SCK] = SM_SCMI_PERM_ALL, \
+        .gprPerms[DEV_SM_GPR_4] = SM_SCMI_PERM_ALL, \
+        .gprPerms[DEV_SM_GPR_5] = SM_SCMI_PERM_ALL, \
+        .gprPerms[DEV_SM_GPR_6] = SM_SCMI_PERM_ALL, \
+        .gprPerms[DEV_SM_GPR_7] = SM_SCMI_PERM_ALL, \
+        .lmmPerms[1] = SM_SCMI_PERM_NOTIFY, \
+        .pdPerms[DEV_SM_PD_CAMERA] = SM_SCMI_PERM_ALL, \
+        .pdPerms[DEV_SM_PD_DISPLAY] = SM_SCMI_PERM_ALL, \
+        .pdPerms[DEV_SM_PD_GPU] = SM_SCMI_PERM_ALL, \
+        .pdPerms[DEV_SM_PD_HSIO_TOP] = SM_SCMI_PERM_ALL, \
+        .pdPerms[DEV_SM_PD_NETC] = SM_SCMI_PERM_ALL, \
+        .pdPerms[DEV_SM_PD_NPU] = SM_SCMI_PERM_ALL, \
+        .pdPerms[DEV_SM_PD_VPU] = SM_SCMI_PERM_ALL, \
+        .perfPerms[DEV_SM_PERF_A55] = SM_SCMI_PERM_ALL, \
+        .perfPerms[DEV_SM_PERF_CAM] = SM_SCMI_PERM_ALL, \
+        .perfPerms[DEV_SM_PERF_DISP] = SM_SCMI_PERM_ALL, \
+        .perfPerms[DEV_SM_PERF_DRAM] = SM_SCMI_PERM_ALL, \
+        .perfPerms[DEV_SM_PERF_GPU] = SM_SCMI_PERM_ALL, \
+        .perfPerms[DEV_SM_PERF_NPU] = SM_SCMI_PERM_ALL, \
+        .perfPerms[DEV_SM_PERF_VPU] = SM_SCMI_PERM_ALL, \
+        .perlpiPerms[DEV_SM_PERLPI_CAN1] = SM_SCMI_PERM_ALL, \
+        .perlpiPerms[DEV_SM_PERLPI_CAN2] = SM_SCMI_PERM_ALL, \
+        .perlpiPerms[DEV_SM_PERLPI_CAN3] = SM_SCMI_PERM_ALL, \
+        .perlpiPerms[DEV_SM_PERLPI_CAN4] = SM_SCMI_PERM_ALL, \
+        .perlpiPerms[DEV_SM_PERLPI_CAN5] = SM_SCMI_PERM_ALL, \
+        .perlpiPerms[DEV_SM_PERLPI_GPIO1] = SM_SCMI_PERM_ALL, \
+        .perlpiPerms[DEV_SM_PERLPI_GPIO2] = SM_SCMI_PERM_ALL, \
+        .perlpiPerms[DEV_SM_PERLPI_GPIO3] = SM_SCMI_PERM_ALL, \
+        .perlpiPerms[DEV_SM_PERLPI_GPIO4] = SM_SCMI_PERM_ALL, \
+        .perlpiPerms[DEV_SM_PERLPI_GPIO5] = SM_SCMI_PERM_ALL, \
+        .perlpiPerms[DEV_SM_PERLPI_LPUART1] = SM_SCMI_PERM_ALL, \
+        .perlpiPerms[DEV_SM_PERLPI_LPUART2] = SM_SCMI_PERM_ALL, \
+        .perlpiPerms[DEV_SM_PERLPI_LPUART3] = SM_SCMI_PERM_ALL, \
+        .perlpiPerms[DEV_SM_PERLPI_LPUART4] = SM_SCMI_PERM_ALL, \
+        .perlpiPerms[DEV_SM_PERLPI_LPUART5] = SM_SCMI_PERM_ALL, \
+        .perlpiPerms[DEV_SM_PERLPI_LPUART6] = SM_SCMI_PERM_ALL, \
+        .perlpiPerms[DEV_SM_PERLPI_LPUART7] = SM_SCMI_PERM_ALL, \
+        .perlpiPerms[DEV_SM_PERLPI_LPUART8] = SM_SCMI_PERM_ALL, \
+        .perlpiPerms[DEV_SM_PERLPI_WDOG3] = SM_SCMI_PERM_ALL, \
+        .perlpiPerms[DEV_SM_PERLPI_WDOG4] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_CCM_CLKO1] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_CCM_CLKO2] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_CCM_CLKO3] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_CCM_CLKO4] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_DAP_TCLK_SWCLK] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_DAP_TDI] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_DAP_TDO_TRACESWO] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_DAP_TMS_SWDIO] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_ENET1_MDC] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_ENET1_MDIO] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_ENET1_RD0] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_ENET1_RD1] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_ENET1_RD2] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_ENET1_RD3] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_ENET1_RXC] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_ENET1_RX_CTL] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_ENET1_TD0] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_ENET1_TD1] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_ENET1_TD2] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_ENET1_TD3] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_ENET1_TXC] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_ENET1_TX_CTL] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_ENET2_MDC] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_ENET2_MDIO] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_ENET2_RD0] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_ENET2_RD1] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_ENET2_RD2] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_ENET2_RD3] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_ENET2_RXC] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_ENET2_RX_CTL] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_ENET2_TD0] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_ENET2_TD1] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_ENET2_TD2] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_ENET2_TD3] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_ENET2_TXC] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_ENET2_TX_CTL] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_GPIO_IO00] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_GPIO_IO01] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_GPIO_IO02] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_GPIO_IO03] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_GPIO_IO04] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_GPIO_IO05] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_GPIO_IO06] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_GPIO_IO07] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_GPIO_IO08] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_GPIO_IO09] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_GPIO_IO10] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_GPIO_IO11] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_GPIO_IO12] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_GPIO_IO13] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_GPIO_IO14] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_GPIO_IO15] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_GPIO_IO16] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_GPIO_IO17] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_GPIO_IO18] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_GPIO_IO19] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_GPIO_IO20] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_GPIO_IO21] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_GPIO_IO22] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_GPIO_IO23] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_GPIO_IO24] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_GPIO_IO25] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_GPIO_IO26] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_GPIO_IO27] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_GPIO_IO28] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_GPIO_IO29] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_GPIO_IO30] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_GPIO_IO31] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_GPIO_IO32] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_GPIO_IO33] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_GPIO_IO34] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_GPIO_IO35] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_GPIO_IO36] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_GPIO_IO37] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_I2C2_SCL] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_I2C2_SDA] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_PDM_BIT_STREAM0] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_PDM_CLK] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_SAI1_RXD0] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_SAI1_TXC] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_SAI1_TXD0] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_SAI1_TXFS] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_SD1_CLK] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_SD1_CMD] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_SD1_DATA0] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_SD1_DATA1] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_SD1_DATA2] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_SD1_DATA3] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_SD1_DATA4] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_SD1_DATA5] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_SD1_DATA6] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_SD1_DATA7] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_SD1_STROBE] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_SD2_CD_B] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_SD2_CLK] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_SD2_CMD] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_SD2_DATA0] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_SD2_DATA1] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_SD2_DATA2] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_SD2_DATA3] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_SD2_RESET_B] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_SD2_VSELECT] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_SD3_CLK] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_SD3_CMD] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_SD3_DATA0] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_SD3_DATA1] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_SD3_DATA2] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_SD3_DATA3] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_UART1_RXD] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_UART1_TXD] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_UART2_RXD] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_UART2_TXD] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_XSPI1_DATA0] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_XSPI1_DATA1] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_XSPI1_DATA2] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_XSPI1_DATA3] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_XSPI1_DATA4] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_XSPI1_DATA5] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_XSPI1_DATA6] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_XSPI1_DATA7] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_XSPI1_DQS] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_XSPI1_SCLK] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_XSPI1_SS0_B] = SM_SCMI_PERM_ALL, \
+        .pinPerms[DEV_SM_PIN_XSPI1_SS1_B] = SM_SCMI_PERM_ALL, \
+        .rtcPerms[DEV_SM_RTC_BBNSM] = SM_SCMI_PERM_ALL, \
+        .sensorPerms[BRD_SM_SENSOR_TEMP_PF09] = SM_SCMI_PERM_ALL, \
+        .sensorPerms[BRD_SM_SENSOR_TEMP_PF5301] = SM_SCMI_PERM_SET, \
+        .sensorPerms[BRD_SM_SENSOR_TEMP_PF5302] = SM_SCMI_PERM_SET, \
+        .sensorPerms[DEV_SM_SENSOR_TEMP_A55] = SM_SCMI_PERM_ALL, \
+        .sensorPerms[DEV_SM_SENSOR_TEMP_ANA] = SM_SCMI_PERM_SET, \
+        .sysPerms = SM_SCMI_PERM_NOTIFY, \
+    }
+
+/*! Config for SCMI channel 5 */
+#define SM_SCMI_CHN5_CONFIG \
+    { \
+        .agentId = 2U, \
+        .type = SM_SCMI_CHN_A2P, \
+        .xportType = SM_XPORT_SMT, \
+        .xportChannel = 5U, \
+    }
+
+/*! Config for SCMI channel 6 */
+#define SM_SCMI_CHN6_CONFIG \
+    { \
+        .agentId = 2U, \
+        .type = SM_SCMI_CHN_P2A_NOTIFY, \
+        .xportType = SM_XPORT_SMT, \
+        .xportChannel = 6U, \
+    }
+
+/*--------------------------------------------------------------------------*/
+/* SCMI Instance 1 Config (AP)                                              */
+/*--------------------------------------------------------------------------*/
+
+/*! Config for SCMI instance 1 */
+#define SM_SCMI1_CONFIG \
+    { \
+        .lmId = 2U, \
+        .numAgents = 2U, \
+        .firstAgent = 1U, \
+    }
+
+/*--------------------------------------------------------------------------*/
+/* SCMI Agent Config                                                        */
+/*--------------------------------------------------------------------------*/
+
+/*! Config for number of SCMI agents */
+#define SM_SCMI_NUM_AGNT  3U
+
+/*! Config data array for SCMI agents */
+#define SM_SCMI_AGNT_CONFIG_DATA \
+    SM_SCMI_AGNT0_CONFIG, \
+    SM_SCMI_AGNT1_CONFIG, \
+    SM_SCMI_AGNT2_CONFIG
+
+/*--------------------------------------------------------------------------*/
+/* SCMI Channel Config                                                      */
+/*--------------------------------------------------------------------------*/
+
+/*! Config for number of SCMI channels */
+#define SM_SCMI_NUM_CHN  7U
+
+/*! Config data array for SCMI channels */
+#define SM_SCMI_CHN_CONFIG_DATA \
+    SM_SCMI_CHN0_CONFIG, \
+    SM_SCMI_CHN1_CONFIG, \
+    SM_SCMI_CHN2_CONFIG, \
+    SM_SCMI_CHN3_CONFIG, \
+    SM_SCMI_CHN4_CONFIG, \
+    SM_SCMI_CHN5_CONFIG, \
+    SM_SCMI_CHN6_CONFIG
+
+/*--------------------------------------------------------------------------*/
+/* SCMI Config                                                              */
+/*--------------------------------------------------------------------------*/
+
+/*! Config for number of SCMI instances */
+#define SM_NUM_SCMI  2U
+
+/*! Config data array for SCMI instances */
+#define SM_SCMI_CONFIG_DATA \
+    SM_SCMI0_CONFIG, \
+    SM_SCMI1_CONFIG
+
+/*! Max words to buffer for notification messages */
+#define SM_SCMI_MAX_NOTIFY  24U
+
+#endif /* CONFIG_SCMI_H */
+
+/** @} */
+
diff --git a/configs/tdx-verdin-imx95/config_smt.h b/configs/tdx-verdin-imx95/config_smt.h
new file mode 100755
index 0000000..bc6efb0
--- /dev/null
+++ b/configs/tdx-verdin-imx95/config_smt.h
@@ -0,0 +1,168 @@
+/*
+** ###################################################################
+**
+** Copyright 2023-2024 NXP
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** o Redistributions of source code must retain the above copyright notice, this list
+**   of conditions and the following disclaimer.
+**
+** o Redistributions in binary form must reproduce the above copyright notice, this
+**   list of conditions and the following disclaimer in the documentation and/or
+**   other materials provided with the distribution.
+**
+** o Neither the name of the copyright holder nor the names of its
+**   contributors may be used to endorse or promote products derived from this
+**   software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+** ###################################################################
+*/
+
+/*==========================================================================*/
+/*!
+ * @addtogroup CONFIG_TDXVERDINIMX95
+ * @{
+ *
+ * @file
+ * @brief
+ *
+ * Header file containing configuration info for the SMT.
+ */
+/*==========================================================================*/
+
+#ifndef CONFIG_SMT_H
+#define CONFIG_SMT_H
+
+/* Includes */
+
+#include "config_user.h"
+#include "rpc_smt_config.h"
+
+/* Defines */
+
+/*--------------------------------------------------------------------------*/
+/* LM0 SMT Config (SM)                                                      */
+/*--------------------------------------------------------------------------*/
+
+/*--------------------------------------------------------------------------*/
+/* LM1 SMT Config (M7)                                                      */
+/*--------------------------------------------------------------------------*/
+
+/*! Config for SMT channel 0 */
+#define SM_SMT_CHN0_CONFIG \
+    { \
+        .rpcType = SM_RPC_SCMI, \
+        .rpcChannel = 0U, \
+        .mbType = SM_MB_MU, \
+        .mbInst = 0U, \
+        .mbDoorbell = 0U, \
+        .crc = SM_SMT_CRC_CRC32, \
+    }
+
+/*! Config for SMT channel 1 */
+#define SM_SMT_CHN1_CONFIG \
+    { \
+        .rpcType = SM_RPC_SCMI, \
+        .rpcChannel = 1U, \
+        .mbType = SM_MB_MU, \
+        .mbInst = 0U, \
+        .mbDoorbell = 1U, \
+        .crc = SM_SMT_CRC_CRC32, \
+    }
+
+/*! Config for SMT channel 2 */
+#define SM_SMT_CHN2_CONFIG \
+    { \
+        .rpcType = SM_RPC_SCMI, \
+        .rpcChannel = 2U, \
+        .mbType = SM_MB_MU, \
+        .mbInst = 0U, \
+        .mbDoorbell = 2U, \
+        .crc = SM_SMT_CRC_CRC32, \
+    }
+
+/*--------------------------------------------------------------------------*/
+/* LM2 SMT Config (AP)                                                      */
+/*--------------------------------------------------------------------------*/
+
+/*! Config for SMT channel 3 */
+#define SM_SMT_CHN3_CONFIG \
+    { \
+        .rpcType = SM_RPC_SCMI, \
+        .rpcChannel = 3U, \
+        .mbType = SM_MB_MU, \
+        .mbInst = 1U, \
+        .mbDoorbell = 0U, \
+    }
+
+/*! Config for SMT channel 4 */
+#define SM_SMT_CHN4_CONFIG \
+    { \
+        .rpcType = SM_RPC_SCMI, \
+        .rpcChannel = 4U, \
+        .mbType = SM_MB_MU, \
+        .mbInst = 1U, \
+        .mbDoorbell = 1U, \
+    }
+
+/*! Config for SMT channel 5 */
+#define SM_SMT_CHN5_CONFIG \
+    { \
+        .rpcType = SM_RPC_SCMI, \
+        .rpcChannel = 5U, \
+        .mbType = SM_MB_MU, \
+        .mbInst = 2U, \
+        .mbDoorbell = 0U, \
+    }
+
+/*! Config for SMT channel 6 */
+#define SM_SMT_CHN6_CONFIG \
+    { \
+        .rpcType = SM_RPC_SCMI, \
+        .rpcChannel = 6U, \
+        .mbType = SM_MB_MU, \
+        .mbInst = 2U, \
+        .mbDoorbell = 1U, \
+    }
+
+/*--------------------------------------------------------------------------*/
+/* SMT Config                                                               */
+/*--------------------------------------------------------------------------*/
+
+/*! Config for number of SMT channels */
+#define SM_NUM_SMT_CHN  7U
+
+/*! Config data array for SMT channels */
+#define SM_SMT_CHN_CONFIG_DATA \
+    SM_SMT_CHN0_CONFIG, \
+    SM_SMT_CHN1_CONFIG, \
+    SM_SMT_CHN2_CONFIG, \
+    SM_SMT_CHN3_CONFIG, \
+    SM_SMT_CHN4_CONFIG, \
+    SM_SMT_CHN5_CONFIG, \
+    SM_SMT_CHN6_CONFIG
+
+/* Mailbox and CRC types to support */
+/*! Config for MB_MU USE */
+#define USES_MB_MU
+/*! Config for CRC32 CRC USE */
+#define USES_CRC_CRC32
+
+#endif /* CONFIG_SMT_H */
+
+/** @} */
+
diff --git a/configs/tdx-verdin-imx95/config_test.h b/configs/tdx-verdin-imx95/config_test.h
new file mode 100755
index 0000000..1091ae6
--- /dev/null
+++ b/configs/tdx-verdin-imx95/config_test.h
@@ -0,0 +1,197 @@
+/*
+** ###################################################################
+**
+** Copyright 2023-2024 NXP
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** o Redistributions of source code must retain the above copyright notice, this list
+**   of conditions and the following disclaimer.
+**
+** o Redistributions in binary form must reproduce the above copyright notice, this
+**   list of conditions and the following disclaimer in the documentation and/or
+**   other materials provided with the distribution.
+**
+** o Neither the name of the copyright holder nor the names of its
+**   contributors may be used to endorse or promote products derived from this
+**   software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+** ###################################################################
+*/
+
+/*==========================================================================*/
+/*!
+ * @addtogroup CONFIG_TDXVERDINIMX95
+ * @{
+ *
+ * @file
+ * @brief
+ *
+ * Header file containing configuration info for the unit tests.
+ */
+/*==========================================================================*/
+
+#ifndef CONFIG_TEST_H
+#define CONFIG_TEST_H
+
+/* Includes */
+
+#include "config_user.h"
+
+/* Defines */
+
+/*--------------------------------------------------------------------------*/
+/* LM0 Test Config (SM)                                                     */
+/*--------------------------------------------------------------------------*/
+
+/*--------------------------------------------------------------------------*/
+/* LM1 Test Config (M7)                                                     */
+/*--------------------------------------------------------------------------*/
+
+/*! Config for test channel 0 */
+#define SM_TEST_CHN0_CONFIG \
+    { \
+        .mbInst = 8U, \
+        .mbDoorbell = 0U, \
+        .agentId = 0U, \
+    }
+
+/*! Config for test channel 1 */
+#define SM_TEST_CHN1_CONFIG \
+    { \
+        .mbInst = 8U, \
+        .mbDoorbell = 1U, \
+        .agentId = 0U, \
+    }
+
+/*! Config for test channel 2 */
+#define SM_TEST_CHN2_CONFIG \
+    { \
+        .mbInst = 8U, \
+        .mbDoorbell = 2U, \
+        .agentId = 0U, \
+    }
+
+/*--------------------------------------------------------------------------*/
+/* LM2 Test Config (AP)                                                     */
+/*--------------------------------------------------------------------------*/
+
+/*! Config for test channel 3 */
+#define SM_TEST_CHN3_CONFIG \
+    { \
+        .mbInst = 0U, \
+        .mbDoorbell = 0U, \
+        .agentId = 1U, \
+    }
+
+/*! Config for test channel 4 */
+#define SM_TEST_CHN4_CONFIG \
+    { \
+        .mbInst = 0U, \
+        .mbDoorbell = 1U, \
+        .agentId = 1U, \
+    }
+
+/*! Config for test channel 5 */
+#define SM_TEST_CHN5_CONFIG \
+    { \
+        .mbInst = 2U, \
+        .mbDoorbell = 0U, \
+        .agentId = 2U, \
+    }
+
+/*! Config for test channel 6 */
+#define SM_TEST_CHN6_CONFIG \
+    { \
+        .mbInst = 2U, \
+        .mbDoorbell = 1U, \
+        .agentId = 2U, \
+    }
+
+/*--------------------------------------------------------------------------*/
+/* Test Channel Config                                                      */
+/*--------------------------------------------------------------------------*/
+
+/*! Config for number of test channels */
+#define SM_NUM_TEST_CHN  7U
+
+/*! Config data array for test channels */
+#define SM_TEST_CHN_CONFIG_DATA \
+    SM_TEST_CHN0_CONFIG, \
+    SM_TEST_CHN1_CONFIG, \
+    SM_TEST_CHN2_CONFIG, \
+    SM_TEST_CHN3_CONFIG, \
+    SM_TEST_CHN4_CONFIG, \
+    SM_TEST_CHN5_CONFIG, \
+    SM_TEST_CHN6_CONFIG
+
+/*--------------------------------------------------------------------------*/
+/* Test Config                                                              */
+/*--------------------------------------------------------------------------*/
+
+/*! Config for number of tests */
+#define SM_SCMI_NUM_TEST  40U
+
+/*! Config data array for tests */
+#define SM_SCMI_TEST_CONFIG_DATA \
+    {.testId = TEST_BUTTON, .channel = 5U, .rsrc = DEV_SM_BUTTON_0}, \
+    {.testId = TEST_CLK, .channel = 0U, .rsrc = DEV_SM_CLK_LPUART3}, \
+    {.testId = TEST_CLK, .channel = 5U, .rsrc = DEV_SM_CLK_DISPOCRAM}, \
+    {.testId = TEST_CLK, .channel = 5U, .rsrc = DEV_SM_CLK_ENETREF}, \
+    {.testId = TEST_CLK, .channel = 5U, .rsrc = DEV_SM_CLK_ENETTIMER1}, \
+    {.testId = TEST_CLK, .channel = 5U, .rsrc = DEV_SM_CLK_LPUART8}, \
+    {.testId = TEST_CLK, .channel = 5U, .rsrc = DEV_SM_CLK_MQS1}, \
+    {.testId = TEST_CLK, .channel = 5U, .rsrc = DEV_SM_CLK_SAI1}, \
+    {.testId = TEST_CTRL, .channel = 5U, .rsrc = DEV_SM_CTRL_MQS1_SETTINGS}, \
+    {.testId = TEST_CTRL, .channel = 5U, .rsrc = DEV_SM_CTRL_SAI1_MCLK}, \
+    {.testId = TEST_DAISY, .channel = 0U, .rsrc = DEV_SM_DAISY_LPUART3_CTS}, \
+    {.testId = TEST_DAISY, .channel = 0U, .rsrc = DEV_SM_DAISY_LPUART3_RXD}, \
+    {.testId = TEST_DAISY, .channel = 0U, .rsrc = DEV_SM_DAISY_LPUART3_TXD}, \
+    {.testId = TEST_DAISY, .channel = 5U, .rsrc = DEV_SM_DAISY_NETC_EMDC}, \
+    {.testId = TEST_DAISY, .channel = 5U, .rsrc = DEV_SM_DAISY_NETC_EMDIO}, \
+    {.testId = TEST_DAISY, .channel = 5U, .rsrc = DEV_SM_DAISY_NETC_ETH0_RMII_RX_ER}, \
+    {.testId = TEST_DAISY, .channel = 5U, .rsrc = DEV_SM_DAISY_NETC_ETH1_RMII_RX_ER}, \
+    {.testId = TEST_DAISY, .channel = 5U, .rsrc = DEV_SM_DAISY_NETC_TMR_1588_TRIG1}, \
+    {.testId = TEST_DAISY, .channel = 5U, .rsrc = DEV_SM_DAISY_NETC_TMR_1588_TRIG2}, \
+    {.testId = TEST_DAISY, .channel = 5U, .rsrc = DEV_SM_DAISY_SAI1_MCLK}, \
+    {.testId = TEST_GPR, .channel = 5U, .rsrc = DEV_SM_GPR_4}, \
+    {.testId = TEST_PD, .channel = 0U, .rsrc = DEV_SM_PD_A55P}, \
+    {.testId = TEST_PD, .channel = 0U, .rsrc = DEV_SM_PD_M7}, \
+    {.testId = TEST_PD, .channel = 5U, .rsrc = DEV_SM_PD_CAMERA}, \
+    {.testId = TEST_PD, .channel = 5U, .rsrc = DEV_SM_PD_CAMERA}, \
+    {.testId = TEST_PD, .channel = 5U, .rsrc = DEV_SM_PD_DISPLAY}, \
+    {.testId = TEST_PD, .channel = 5U, .rsrc = DEV_SM_PD_GPU}, \
+    {.testId = TEST_PD, .channel = 5U, .rsrc = DEV_SM_PD_HSIO_TOP}, \
+    {.testId = TEST_PD, .channel = 5U, .rsrc = DEV_SM_PD_NPU}, \
+    {.testId = TEST_PD, .channel = 5U, .rsrc = DEV_SM_PD_VPU}, \
+    {.testId = TEST_PERF, .channel = 5U, .rsrc = DEV_SM_PERF_CAM}, \
+    {.testId = TEST_PERF, .channel = 5U, .rsrc = DEV_SM_PERF_DISP}, \
+    {.testId = TEST_PERF, .channel = 5U, .rsrc = DEV_SM_PERF_GPU}, \
+    {.testId = TEST_PERF, .channel = 5U, .rsrc = DEV_SM_PERF_NPU}, \
+    {.testId = TEST_PERF, .channel = 5U, .rsrc = DEV_SM_PERF_VPU}, \
+    {.testId = TEST_PERLPI, .channel = 0U, .rsrc = DEV_SM_PERLPI_LPUART3}, \
+    {.testId = TEST_PERLPI, .channel = 5U, .rsrc = DEV_SM_PERLPI_LPUART8}, \
+    {.testId = TEST_PIN, .channel = 5U, .rsrc = DEV_SM_PIN_UART1_RXD}, \
+    {.testId = TEST_RTC, .channel = 5U, .rsrc = DEV_SM_RTC_BBNSM}, \
+    {.testId = TEST_SENSOR, .channel = 0U, .rsrc = DEV_SM_SENSOR_TEMP_ANA}
+
+/*! Default channel for non-agent specific tests */
+#define SM_TEST_DEFAULT_CHN  0U
+
+#endif /* CONFIG_TEST_H */
+
+/** @} */
+
diff --git a/configs/tdx-verdin-imx95/config_trdc.h b/configs/tdx-verdin-imx95/config_trdc.h
new file mode 100755
index 0000000..c38f20c
--- /dev/null
+++ b/configs/tdx-verdin-imx95/config_trdc.h
@@ -0,0 +1,1364 @@
+/*
+** ###################################################################
+**
+** Copyright 2023-2024 NXP
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** o Redistributions of source code must retain the above copyright notice, this list
+**   of conditions and the following disclaimer.
+**
+** o Redistributions in binary form must reproduce the above copyright notice, this
+**   list of conditions and the following disclaimer in the documentation and/or
+**   other materials provided with the distribution.
+**
+** o Neither the name of the copyright holder nor the names of its
+**   contributors may be used to endorse or promote products derived from this
+**   software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+** ###################################################################
+*/
+
+/*==========================================================================*/
+/*!
+ * @addtogroup CONFIG_TDXVERDINIMX95
+ * @{
+ *
+ * @file
+ * @brief
+ *
+ * Header file containing configuration info for the TRDC SM abstraction.
+ */
+/*==========================================================================*/
+
+#ifndef CONFIG_TRDC_H
+#define CONFIG_TRDC_H
+
+/* Includes */
+
+#include "config_user.h"
+
+/* Defines */
+
+/*--------------------------------------------------------------------------*/
+/* TRDC A Config                                                            */
+/*--------------------------------------------------------------------------*/
+
+/*! Config for TRDC A */
+#define SM_TRDC_A_CONFIG \
+    { \
+        SM_CFG_W1(0x00000800U), 0xB00000A0U, \
+        SM_CFG_W1(0x00000820U), 0xB0000012U, \
+        SM_CFG_W1(0x00000840U), 0xB0000013U, \
+        SM_CFG_W1(0x00000860U), 0xB0000013U, \
+        SM_CFG_W1(0x00000880U), 0xB0000053U, \
+        SM_CFG_W1(0x000008a0U), 0xB0000053U, \
+        SM_CFG_W1(0x000008c0U), 0xB0000014U, \
+        SM_CFG_W1(0x00000a00U), 0x90000002U, \
+        SM_CFG_W1(0x00000a04U), 0x90000002U, \
+        SM_CFG_W1(0x00000a08U), 0x90000002U, \
+        SM_CFG_W1(0x00000a20U), 0xB0000053U, \
+        SM_CFG_W1(0x00000a40U), 0xB0000053U, \
+        SM_CFG_W1(0x00000a60U), 0xB0000053U, \
+        SM_CFG_W1(0x00000a80U), 0xB0000053U, \
+        SM_CFG_W1(0x00000aa0U), 0xB0000053U, \
+        SM_CFG_W1(0x00000ac0U), 0xB0000053U, \
+        SM_CFG_W1(0x00000ae0U), 0xB0000053U, \
+        SM_CFG_W1(0x00000b00U), 0xB0000053U, \
+        SM_CFG_W1(0x00000b20U), 0xB0000053U, \
+        SM_CFG_W1(0x00000b40U), 0xB0000053U, \
+        SM_CFG_W1(0x00000b60U), 0xB0000053U, \
+        SM_CFG_W1(0x00000b80U), 0xB0000053U, \
+        SM_CFG_W1(0x00000ba0U), 0xB0000053U, \
+        SM_CFG_W1(0x00000bc0U), 0xB0000053U, \
+        SM_CFG_W1(0x00000be0U), 0xB0000053U, \
+        SM_CFG_W1(0x00000c00U), 0xB0000053U, \
+        SM_CFG_W1(0x00000c20U), 0xB0000053U, \
+        SM_CFG_W1(0x00000c40U), 0xB0000053U, \
+        SM_CFG_W1(0x00000c60U), 0xB0000053U, \
+        SM_CFG_W1(0x00000c80U), 0xB0000053U, \
+        SM_CFG_W1(0x00000ca0U), 0xB00000A1U, \
+        SM_CFG_W1(0x00000cc0U), 0xB00000A1U, \
+        SM_CFG_W1(0x00010024U), 0x6666U, \
+        SM_CFG_W1(0x00010028U), 0x7777U, \
+        SM_CFG_W1(0x0001002cU), 0x6600U, \
+        SM_CFG_W1(0x00010030U), 0x4444U, \
+        SM_CFG_Z1(0x00010050U), \
+        SM_CFG_Z1(0x00010054U), \
+        SM_CFG_W1(0x00010064U), 0x00000003U, \
+        SM_CFG_W1(0x00010068U), 0x00000003U, \
+        SM_CFG_W1(0x00010180U), 0x000000C0U, \
+        SM_CFG_Z1(0x00010250U), \
+        SM_CFG_Z1(0x00010254U), \
+        SM_CFG_W1(0x00010264U), 0x00000900U, \
+        SM_CFG_W1(0x00010380U), 0x000000C0U, \
+        SM_CFG_W1(0x00010450U), 0x30003330U, \
+        SM_CFG_W1(0x00010454U), 0x03333033U, \
+        SM_CFG_W1(0x00010458U), 0x00030000U, \
+        SM_CFG_W1(0x0001045cU), 0x33330030U, \
+        SM_CFG_W1(0x00010460U), 0x33333333U, \
+        SM_CFG_W1(0x00010464U), 0x30000003U, \
+        SM_CFG_W1(0x00010468U), 0x33330030U, \
+        SM_CFG_W1(0x0001046cU), 0x33333333U, \
+        SM_CFG_W1(0x00010470U), 0x33333333U, \
+        SM_CFG_W1(0x00010474U), 0x00003000U, \
+        SM_CFG_W1(0x00010580U), 0x000003C0U, \
+        SM_CFG_W1(0x000105a8U), 0x00000003U, \
+        SM_CFG_W1(0x00010640U), 0x99999999U, \
+        SM_CFG_W1(0x00010644U), 0x99999999U, \
+        SM_CFG_W1(0x00010648U), 0x99999999U, \
+        SM_CFG_W1(0x0001064cU), 0x99999999U, \
+        SM_CFG_W1(0x00010650U), 0x09000309U, \
+        SM_CFG_W1(0x00010654U), 0x0000C900U, \
+        SM_CFG_W1(0x00010658U), 0x99909900U, \
+        SM_CFG_W1(0x0001065cU), 0x00009999U, \
+        SM_CFG_W1(0x00010668U), 0x00009900U, \
+        SM_CFG_W1(0x0001066cU), 0x90909000U, \
+        SM_CFG_W1(0x00010670U), 0x00009000U, \
+        SM_CFG_W1(0x00010780U), 0x099330C0U, \
+        SM_CFG_W1(0x000107a8U), 0x00000009U, \
+        SM_CFG_Z1(0x00010850U), \
+        SM_CFG_W1(0x00010854U), 0x9000C000U, \
+        SM_CFG_W1(0x00010858U), 0x00000099U, \
+        SM_CFG_W1(0x0001085cU), 0x00000300U, \
+        SM_CFG_W1(0x00010870U), 0x00000090U, \
+        SM_CFG_W1(0x00010874U), 0x00000999U, \
+        SM_CFG_W1(0x00010980U), 0x900000C0U, \
+        SM_CFG_Z1(0x00010a50U), \
+        SM_CFG_Z1(0x00010a54U), \
+        SM_CFG_W1(0x00010b80U), 0x000000C0U, \
+        SM_CFG_Z1(0x00010c50U), \
+        SM_CFG_Z1(0x00010c54U), \
+        SM_CFG_W1(0x00010d80U), 0x000000C0U, \
+        SM_CFG_Z1(0x00010e50U), \
+        SM_CFG_Z1(0x00010e54U), \
+        SM_CFG_W1(0x00010f80U), 0x000000C0U, \
+        SM_CFG_Z1(0x00011050U), \
+        SM_CFG_Z1(0x00011054U), \
+        SM_CFG_W1(0x00011064U), 0x09999000U, \
+        SM_CFG_W1(0x00011180U), 0x000000C0U, \
+        SM_CFG_W1(0x00011240U), 0x33333333U, \
+        SM_CFG_W1(0x00011244U), 0x33333333U, \
+        SM_CFG_W1(0x00011248U), 0x33333333U, \
+        SM_CFG_W1(0x0001124cU), 0x33333333U, \
+        SM_CFG_W1(0x00011250U), 0x33003333U, \
+        SM_CFG_W1(0x00011254U), 0x33333333U, \
+        SM_CFG_W1(0x00011258U), 0x33333333U, \
+        SM_CFG_W1(0x0001125cU), 0x33333333U, \
+        SM_CFG_W1(0x00011260U), 0x33333333U, \
+        SM_CFG_W1(0x00011264U), 0x33333303U, \
+        SM_CFG_W1(0x00011268U), 0x33333333U, \
+        SM_CFG_W1(0x0001126cU), 0x33333333U, \
+        SM_CFG_W1(0x00011270U), 0x33333333U, \
+        SM_CFG_W1(0x00011274U), 0x00003333U, \
+        SM_CFG_W1(0x00011380U), 0x333333F0U, \
+        SM_CFG_W1(0x000113a8U), 0x00000003U, \
+        SM_CFG_Z1(0x00011450U), \
+        SM_CFG_Z1(0x00011454U), \
+        SM_CFG_W1(0x00011580U), 0x000000C0U, \
+        SM_CFG_Z1(0x00011650U), \
+        SM_CFG_Z1(0x00011654U), \
+        SM_CFG_W1(0x00011780U), 0x000000C0U, \
+        SM_CFG_Z1(0x00011850U), \
+        SM_CFG_Z1(0x00011854U), \
+        SM_CFG_W1(0x00011980U), 0x000000C0U, \
+        SM_CFG_Z1(0x00011a50U), \
+        SM_CFG_Z1(0x00011a54U), \
+        SM_CFG_W1(0x00011b80U), 0x000000C0U, \
+        SM_CFG_Z1(0x00011c50U), \
+        SM_CFG_Z1(0x00011c54U), \
+        SM_CFG_W1(0x00011d80U), 0x000000C0U, \
+        SM_CFG_Z1(0x00011e50U), \
+        SM_CFG_Z1(0x00011e54U), \
+        SM_CFG_W1(0x00011f80U), 0x000000C0U, \
+        SM_CFG_W1(0x00012024U), 0x6666U, \
+        SM_CFG_W1(0x00012028U), 0x7777U, \
+        SM_CFG_W1(0x0001202cU), 0x7700U, \
+        SM_CFG_W1(0x00012030U), 0x6600U, \
+        SM_CFG_W1(0x00012180U), 0x99999999U, \
+        SM_CFG_W1(0x00012184U), 0x99999999U, \
+        SM_CFG_W1(0x00012188U), 0x99999999U, \
+        SM_CFG_W1(0x0001218cU), 0x99999999U, \
+        SM_CFG_W1(0x00012440U), 0x33333333U, \
+        SM_CFG_W1(0x00012444U), 0x33333333U, \
+        SM_CFG_W1(0x00012448U), 0x33333333U, \
+        SM_CFG_W1(0x0001244cU), 0x33333333U, \
+        SM_CFG_W1(0x00012580U), 0x33333333U, \
+        SM_CFG_W1(0x00012584U), 0x33333333U, \
+        SM_CFG_W1(0x00012588U), 0x33333333U, \
+        SM_CFG_W1(0x0001258cU), 0x33333333U, \
+        SM_CFG_Z1(0x00012640U), \
+        SM_CFG_Z1(0x00012644U), \
+        SM_CFG_Z1(0x00012648U), \
+        SM_CFG_Z1(0x0001264cU), \
+        SM_CFG_Z1(0x00012780U), \
+        SM_CFG_Z1(0x00012784U), \
+        SM_CFG_Z1(0x00012788U), \
+        SM_CFG_Z1(0x0001278cU), \
+        SM_CFG_Z1(0x00012840U), \
+        SM_CFG_Z1(0x00012844U), \
+        SM_CFG_Z1(0x00012848U), \
+        SM_CFG_Z1(0x0001284cU), \
+        SM_CFG_Z1(0x00012980U), \
+        SM_CFG_Z1(0x00012984U), \
+        SM_CFG_Z1(0x00012988U), \
+        SM_CFG_Z1(0x0001298cU), \
+        SM_CFG_Z1(0x00012a40U), \
+        SM_CFG_Z1(0x00012a44U), \
+        SM_CFG_Z1(0x00012a48U), \
+        SM_CFG_Z1(0x00012a4cU), \
+        SM_CFG_Z1(0x00012b80U), \
+        SM_CFG_Z1(0x00012b84U), \
+        SM_CFG_Z1(0x00012b88U), \
+        SM_CFG_Z1(0x00012b8cU), \
+        SM_CFG_Z1(0x00012c40U), \
+        SM_CFG_Z1(0x00012c44U), \
+        SM_CFG_Z1(0x00012c48U), \
+        SM_CFG_Z1(0x00012c4cU), \
+        SM_CFG_Z1(0x00012d80U), \
+        SM_CFG_Z1(0x00012d84U), \
+        SM_CFG_Z1(0x00012d88U), \
+        SM_CFG_Z1(0x00012d8cU), \
+        SM_CFG_Z1(0x00012e40U), \
+        SM_CFG_Z1(0x00012e44U), \
+        SM_CFG_Z1(0x00012e48U), \
+        SM_CFG_Z1(0x00012e4cU), \
+        SM_CFG_Z1(0x00012f80U), \
+        SM_CFG_Z1(0x00012f84U), \
+        SM_CFG_Z1(0x00012f88U), \
+        SM_CFG_Z1(0x00012f8cU), \
+        SM_CFG_W1(0x00013240U), 0x44444444U, \
+        SM_CFG_W1(0x00013244U), 0x44444444U, \
+        SM_CFG_W1(0x00013248U), 0x44444444U, \
+        SM_CFG_W1(0x0001324cU), 0x44444444U, \
+        SM_CFG_W1(0x00013380U), 0x44444444U, \
+        SM_CFG_W1(0x00013384U), 0x44444444U, \
+        SM_CFG_W1(0x00013388U), 0x44444444U, \
+        SM_CFG_W1(0x0001338cU), 0x44444444U, \
+        SM_CFG_Z1(0x00013440U), \
+        SM_CFG_Z1(0x00013444U), \
+        SM_CFG_Z1(0x00013448U), \
+        SM_CFG_Z1(0x0001344cU), \
+        SM_CFG_Z1(0x00013580U), \
+        SM_CFG_Z1(0x00013584U), \
+        SM_CFG_Z1(0x00013588U), \
+        SM_CFG_Z1(0x0001358cU), \
+        SM_CFG_Z1(0x00013640U), \
+        SM_CFG_Z1(0x00013644U), \
+        SM_CFG_Z1(0x00013648U), \
+        SM_CFG_Z1(0x0001364cU), \
+        SM_CFG_Z1(0x00013780U), \
+        SM_CFG_Z1(0x00013784U), \
+        SM_CFG_Z1(0x00013788U), \
+        SM_CFG_Z1(0x0001378cU), \
+        SM_CFG_Z1(0x00013840U), \
+        SM_CFG_Z1(0x00013844U), \
+        SM_CFG_Z1(0x00013848U), \
+        SM_CFG_Z1(0x0001384cU), \
+        SM_CFG_Z1(0x00013980U), \
+        SM_CFG_Z1(0x00013984U), \
+        SM_CFG_Z1(0x00013988U), \
+        SM_CFG_Z1(0x0001398cU), \
+        SM_CFG_W1(0x00014024U), 0x6600U, \
+        SM_CFG_Z1(0x00014240U), \
+        SM_CFG_W1(0x00014244U), 0x0003C001U, \
+        SM_CFG_Z1(0x0001424cU), \
+        SM_CFG_Z1(0x00014254U), \
+        SM_CFG_Z1(0x0001425cU), \
+        SM_CFG_W1(0x00014940U), 0x00000001U, \
+        SM_CFG_W1(0x00014944U), 0x0003C001U, \
+        SM_CFG_Z1(0x0001494cU), \
+        SM_CFG_Z1(0x00014954U), \
+        SM_CFG_Z1(0x0001495cU), \
+        SM_CFG_Z1(0x00010020U), \
+        SM_CFG_Z1(0x00012020U), \
+        SM_CFG_W1(0x00014020U), 0x7700U, \
+        SM_CFG_C1(0x00000000U), 0x0000C001U, \
+        SM_CFG_END \
+    }
+
+/*--------------------------------------------------------------------------*/
+/* TRDC C Config                                                            */
+/*--------------------------------------------------------------------------*/
+
+/*! Config for TRDC C */
+#define SM_TRDC_C_CONFIG \
+    { \
+        SM_CFG_W1(0x00000800U), 0xB0000053U, \
+        SM_CFG_W1(0x00000820U), 0xB0000053U, \
+        SM_CFG_W1(0x00000840U), 0xB0000053U, \
+        SM_CFG_W1(0x00000860U), 0xB0000053U, \
+        SM_CFG_W1(0x00000880U), 0xB0000053U, \
+        SM_CFG_W1(0x000008a0U), 0xB0000053U, \
+        SM_CFG_W1(0x000008c0U), 0xB0000053U, \
+        SM_CFG_W1(0x000008e0U), 0xB0000053U, \
+        SM_CFG_W1(0x00000900U), 0xB0000053U, \
+        SM_CFG_W1(0x00000920U), 0xB0000053U, \
+        SM_CFG_W1(0x00000940U), 0xB0000053U, \
+        SM_CFG_W1(0x00000960U), 0xB0000053U, \
+        SM_CFG_W1(0x00000980U), 0xB0000053U, \
+        SM_CFG_W1(0x000009a0U), 0xB0000053U, \
+        SM_CFG_W1(0x000009c0U), 0xB0000053U, \
+        SM_CFG_W1(0x000009e0U), 0xB0000053U, \
+        SM_CFG_W1(0x00000a00U), 0xB0000053U, \
+        SM_CFG_W1(0x00000a20U), 0xB0000053U, \
+        SM_CFG_W1(0x00000a40U), 0xB0000053U, \
+        SM_CFG_W1(0x00000a60U), 0xB0000053U, \
+        SM_CFG_W1(0x00000a80U), 0xB0000053U, \
+        SM_CFG_W1(0x00000aa0U), 0xB0000053U, \
+        SM_CFG_W1(0x00000ac0U), 0xB0000053U, \
+        SM_CFG_W1(0x00000ae0U), 0xB0000053U, \
+        SM_CFG_W1(0x00000b00U), 0xB0000053U, \
+        SM_CFG_W1(0x00000b20U), 0xB0000053U, \
+        SM_CFG_W1(0x00010024U), 0x6666U, \
+        SM_CFG_W1(0x00010028U), 0x7777U, \
+        SM_CFG_W1(0x0001002cU), 0x6600U, \
+        SM_CFG_W1(0x00010040U), 0x00003000U, \
+        SM_CFG_W1(0x00010240U), 0x00000900U, \
+        SM_CFG_W1(0x00010440U), 0x00330000U, \
+        SM_CFG_W1(0x00010640U), 0x99000090U, \
+        SM_CFG_W1(0x00010644U), 0x99999999U, \
+        SM_CFG_W1(0x00010648U), 0x99999999U, \
+        SM_CFG_W1(0x0001064cU), 0x09999999U, \
+        SM_CFG_W1(0x00010650U), 0x99999999U, \
+        SM_CFG_W1(0x00010654U), 0x99999999U, \
+        SM_CFG_W1(0x00010658U), 0x00000999U, \
+        SM_CFG_Z1(0x00010840U), \
+        SM_CFG_Z1(0x00010a40U), \
+        SM_CFG_Z1(0x00010c40U), \
+        SM_CFG_Z1(0x00010e40U), \
+        SM_CFG_W1(0x00011040U), 0x00000009U, \
+        SM_CFG_W1(0x00011240U), 0x33333333U, \
+        SM_CFG_W1(0x00011244U), 0x33333333U, \
+        SM_CFG_W1(0x00011248U), 0x33333333U, \
+        SM_CFG_W1(0x0001124cU), 0x03333333U, \
+        SM_CFG_W1(0x00011250U), 0x33333333U, \
+        SM_CFG_W1(0x00011254U), 0x33333333U, \
+        SM_CFG_W1(0x00011258U), 0x00000333U, \
+        SM_CFG_Z1(0x00011440U), \
+        SM_CFG_Z1(0x00011640U), \
+        SM_CFG_Z1(0x00011840U), \
+        SM_CFG_Z1(0x00011a40U), \
+        SM_CFG_Z1(0x00011c40U), \
+        SM_CFG_Z1(0x00011e40U), \
+        SM_CFG_W1(0x00012024U), 0x6666U, \
+        SM_CFG_W1(0x00012028U), 0x7777U, \
+        SM_CFG_W1(0x0001202cU), 0x6600U, \
+        SM_CFG_W1(0x00012440U), 0x00000003U, \
+        SM_CFG_W1(0x00013240U), 0x00000003U, \
+        SM_CFG_W1(0x00014024U), 0x6666U, \
+        SM_CFG_W1(0x00014028U), 0x7777U, \
+        SM_CFG_W1(0x0001402cU), 0x6600U, \
+        SM_CFG_W1(0x00014640U), 0x00000009U, \
+        SM_CFG_W1(0x00015240U), 0x00000003U, \
+        SM_CFG_W1(0x00016024U), 0x6600U, \
+        SM_CFG_W1(0x00016340U), 0x01000000U, \
+        SM_CFG_W1(0x00016344U), 0x01014011U, \
+        SM_CFG_Z1(0x0001634cU), \
+        SM_CFG_W1(0x00016940U), 0x01000001U, \
+        SM_CFG_W1(0x00016944U), 0x01014001U, \
+        SM_CFG_Z1(0x0001694cU), \
+        SM_CFG_Z1(0x00010020U), \
+        SM_CFG_Z1(0x00012020U), \
+        SM_CFG_Z1(0x00014020U), \
+        SM_CFG_W1(0x00016020U), 0x7777U, \
+        SM_CFG_C1(0x00000000U), 0x0000C001U, \
+        SM_CFG_END \
+    }
+
+/*--------------------------------------------------------------------------*/
+/* TRDC D Config                                                            */
+/*--------------------------------------------------------------------------*/
+
+/*! Config for TRDC D */
+#define SM_TRDC_D_CONFIG \
+    { \
+        SM_CFG_W1(0x00000800U), 0xB0000053U, \
+        SM_CFG_W1(0x00000820U), 0xB0000053U, \
+        SM_CFG_W1(0x00000840U), 0xB0000053U, \
+        SM_CFG_W1(0x00000860U), 0xB0000053U, \
+        SM_CFG_W1(0x00000880U), 0xB0000053U, \
+        SM_CFG_W1(0x000008a0U), 0xB0000053U, \
+        SM_CFG_W1(0x000008c0U), 0xB0000053U, \
+        SM_CFG_W1(0x000008e0U), 0xB0000053U, \
+        SM_CFG_W1(0x00010024U), 0x6666U, \
+        SM_CFG_W1(0x00010028U), 0x7777U, \
+        SM_CFG_W1(0x0001002cU), 0x6600U, \
+        SM_CFG_W1(0x00010040U), 0x00003000U, \
+        SM_CFG_W1(0x00010180U), 0x00003000U, \
+        SM_CFG_W1(0x00010240U), 0x00000900U, \
+        SM_CFG_W1(0x00010380U), 0x00000900U, \
+        SM_CFG_W1(0x00010440U), 0x00330000U, \
+        SM_CFG_W1(0x0001045cU), 0x30000000U, \
+        SM_CFG_W1(0x00010580U), 0x00330000U, \
+        SM_CFG_W1(0x0001059cU), 0x30000000U, \
+        SM_CFG_W1(0x00010640U), 0x90000090U, \
+        SM_CFG_W1(0x00010644U), 0x99999999U, \
+        SM_CFG_W1(0x00010648U), 0x00000009U, \
+        SM_CFG_W1(0x00010658U), 0x00000009U, \
+        SM_CFG_W1(0x00010780U), 0x90000090U, \
+        SM_CFG_W1(0x00010784U), 0x99999999U, \
+        SM_CFG_W1(0x00010788U), 0x00000009U, \
+        SM_CFG_W1(0x00010798U), 0x00000009U, \
+        SM_CFG_W1(0x000107a8U), 0x99999999U, \
+        SM_CFG_W1(0x000107acU), 0x99999999U, \
+        SM_CFG_W1(0x000107b0U), 0x99999999U, \
+        SM_CFG_W1(0x000107b4U), 0x99999999U, \
+        SM_CFG_W1(0x000107b8U), 0x99999999U, \
+        SM_CFG_W1(0x000107bcU), 0x99999999U, \
+        SM_CFG_W1(0x000107c0U), 0x99999999U, \
+        SM_CFG_W1(0x000107c4U), 0x99999999U, \
+        SM_CFG_W1(0x000107d0U), 0x99999999U, \
+        SM_CFG_W1(0x000107d4U), 0x99999999U, \
+        SM_CFG_W1(0x000107d8U), 0x99999999U, \
+        SM_CFG_W1(0x000107dcU), 0x99999999U, \
+        SM_CFG_W1(0x000107e0U), 0x99999999U, \
+        SM_CFG_W1(0x000107e4U), 0x99999999U, \
+        SM_CFG_W1(0x000107e8U), 0x99999999U, \
+        SM_CFG_W1(0x000107ecU), 0x99999999U, \
+        SM_CFG_Z1(0x00010840U), \
+        SM_CFG_Z1(0x00010980U), \
+        SM_CFG_Z1(0x00010a40U), \
+        SM_CFG_Z1(0x00010b80U), \
+        SM_CFG_Z1(0x00010c40U), \
+        SM_CFG_Z1(0x00010d80U), \
+        SM_CFG_Z1(0x00010e40U), \
+        SM_CFG_Z1(0x00010f80U), \
+        SM_CFG_W1(0x00011040U), 0x00000009U, \
+        SM_CFG_W1(0x00011180U), 0x00000009U, \
+        SM_CFG_W1(0x00011240U), 0x30333333U, \
+        SM_CFG_W1(0x00011244U), 0x33333333U, \
+        SM_CFG_W1(0x00011248U), 0x00000003U, \
+        SM_CFG_W1(0x00011258U), 0x00000003U, \
+        SM_CFG_W1(0x0001125cU), 0x30000000U, \
+        SM_CFG_W1(0x00011380U), 0x30333333U, \
+        SM_CFG_W1(0x00011384U), 0x33333333U, \
+        SM_CFG_W1(0x00011388U), 0x00000003U, \
+        SM_CFG_W1(0x00011398U), 0x00000003U, \
+        SM_CFG_W1(0x0001139cU), 0x30000000U, \
+        SM_CFG_W1(0x000113a8U), 0x33333333U, \
+        SM_CFG_W1(0x000113acU), 0x33333333U, \
+        SM_CFG_W1(0x000113b0U), 0x33333333U, \
+        SM_CFG_W1(0x000113b4U), 0x33333333U, \
+        SM_CFG_W1(0x000113b8U), 0x33333333U, \
+        SM_CFG_W1(0x000113bcU), 0x33333333U, \
+        SM_CFG_W1(0x000113c0U), 0x33333333U, \
+        SM_CFG_W1(0x000113c4U), 0x33333333U, \
+        SM_CFG_W1(0x000113d0U), 0x33333333U, \
+        SM_CFG_W1(0x000113d4U), 0x33333333U, \
+        SM_CFG_W1(0x000113d8U), 0x33333333U, \
+        SM_CFG_W1(0x000113dcU), 0x33333333U, \
+        SM_CFG_W1(0x000113e0U), 0x33333333U, \
+        SM_CFG_W1(0x000113e4U), 0x33333333U, \
+        SM_CFG_W1(0x000113e8U), 0x33333333U, \
+        SM_CFG_W1(0x000113ecU), 0x33333333U, \
+        SM_CFG_Z1(0x00011440U), \
+        SM_CFG_Z1(0x00011580U), \
+        SM_CFG_Z1(0x00011640U), \
+        SM_CFG_Z1(0x00011780U), \
+        SM_CFG_Z1(0x00011840U), \
+        SM_CFG_Z1(0x00011980U), \
+        SM_CFG_Z1(0x00011a40U), \
+        SM_CFG_Z1(0x00011b80U), \
+        SM_CFG_Z1(0x00011c40U), \
+        SM_CFG_Z1(0x00011d80U), \
+        SM_CFG_Z1(0x00011e40U), \
+        SM_CFG_Z1(0x00011f80U), \
+        SM_CFG_Z1(0x00010020U), \
+        SM_CFG_C1(0x00000000U), 0x0000C001U, \
+        SM_CFG_END \
+    }
+
+/*--------------------------------------------------------------------------*/
+/* TRDC E Config                                                            */
+/*--------------------------------------------------------------------------*/
+
+/*! Config for TRDC E */
+#define SM_TRDC_E_CONFIG \
+    { \
+        SM_CFG_W1(0x00000800U), 0xB8000053U, \
+        SM_CFG_W1(0x00000820U), 0xB8400053U, \
+        SM_CFG_W1(0x00000840U), 0xB8800053U, \
+        SM_CFG_W1(0x00000860U), 0xB8C00053U, \
+        SM_CFG_W1(0x00000880U), 0xB9000053U, \
+        SM_CFG_W1(0x000008a0U), 0xB9400053U, \
+        SM_CFG_W1(0x000008c0U), 0xB9800053U, \
+        SM_CFG_W1(0x000008e0U), 0xB9C00053U, \
+        SM_CFG_W1(0x00010024U), 0x6666U, \
+        SM_CFG_W1(0x00010028U), 0x7777U, \
+        SM_CFG_W1(0x0001002cU), 0x6600U, \
+        SM_CFG_W1(0x000101a8U), 0x00003000U, \
+        SM_CFG_W1(0x000103a8U), 0x00000900U, \
+        SM_CFG_W1(0x000105a8U), 0x00330000U, \
+        SM_CFG_W1(0x00010640U), 0x99999999U, \
+        SM_CFG_W1(0x00010644U), 0x99999999U, \
+        SM_CFG_W1(0x00010648U), 0x99999999U, \
+        SM_CFG_W1(0x0001064cU), 0x99999999U, \
+        SM_CFG_W1(0x00010780U), 0x99999999U, \
+        SM_CFG_W1(0x000107a8U), 0x00000090U, \
+        SM_CFG_W1(0x000107acU), 0x00009909U, \
+        SM_CFG_Z1(0x000109a8U), \
+        SM_CFG_Z1(0x00010ba8U), \
+        SM_CFG_Z1(0x00010da8U), \
+        SM_CFG_Z1(0x00010fa8U), \
+        SM_CFG_W1(0x000111a8U), 0x00000009U, \
+        SM_CFG_W1(0x00011240U), 0x33333333U, \
+        SM_CFG_W1(0x00011244U), 0x33333333U, \
+        SM_CFG_W1(0x00011248U), 0x33333333U, \
+        SM_CFG_W1(0x0001124cU), 0x33333333U, \
+        SM_CFG_W1(0x00011380U), 0x33333333U, \
+        SM_CFG_W1(0x000113a8U), 0x00333333U, \
+        SM_CFG_W1(0x000113acU), 0x00003303U, \
+        SM_CFG_Z1(0x000115a8U), \
+        SM_CFG_Z1(0x000117a8U), \
+        SM_CFG_Z1(0x000119a8U), \
+        SM_CFG_Z1(0x00011ba8U), \
+        SM_CFG_Z1(0x00011da8U), \
+        SM_CFG_Z1(0x00011fa8U), \
+        SM_CFG_Z1(0x00010020U), \
+        SM_CFG_C1(0x00000000U), 0x0000C001U, \
+        SM_CFG_END \
+    }
+
+/*--------------------------------------------------------------------------*/
+/* TRDC G Config                                                            */
+/*--------------------------------------------------------------------------*/
+
+/*! Config for TRDC G */
+#define SM_TRDC_G_CONFIG \
+    { \
+        SM_CFG_W1(0x00000800U), 0xB0000053U, \
+        SM_CFG_W1(0x00000820U), 0xB0000053U, \
+        SM_CFG_W1(0x00010024U), 0x6666U, \
+        SM_CFG_W1(0x00010028U), 0x7777U, \
+        SM_CFG_W1(0x0001002cU), 0x6600U, \
+        SM_CFG_W1(0x00010040U), 0x00003000U, \
+        SM_CFG_W1(0x00010240U), 0x00000900U, \
+        SM_CFG_W1(0x00010440U), 0x00330000U, \
+        SM_CFG_W1(0x00010640U), 0x00000090U, \
+        SM_CFG_Z1(0x00010840U), \
+        SM_CFG_Z1(0x00010a40U), \
+        SM_CFG_Z1(0x00010c40U), \
+        SM_CFG_Z1(0x00010e40U), \
+        SM_CFG_W1(0x00011040U), 0x00000009U, \
+        SM_CFG_W1(0x00011240U), 0x00333333U, \
+        SM_CFG_Z1(0x00011440U), \
+        SM_CFG_Z1(0x00011640U), \
+        SM_CFG_Z1(0x00011840U), \
+        SM_CFG_Z1(0x00011a40U), \
+        SM_CFG_Z1(0x00011c40U), \
+        SM_CFG_Z1(0x00011e40U), \
+        SM_CFG_W1(0x00012024U), 0x6600U, \
+        SM_CFG_W1(0x00012340U), 0x4D900000U, \
+        SM_CFG_W1(0x00012344U), 0x4DD7C011U, \
+        SM_CFG_Z1(0x0001234cU), \
+        SM_CFG_Z1(0x00012354U), \
+        SM_CFG_Z1(0x0001235cU), \
+        SM_CFG_W1(0x00012940U), 0x4D900001U, \
+        SM_CFG_W1(0x00012944U), 0x4DD7C001U, \
+        SM_CFG_Z1(0x0001294cU), \
+        SM_CFG_Z1(0x00012954U), \
+        SM_CFG_Z1(0x0001295cU), \
+        SM_CFG_Z1(0x00010020U), \
+        SM_CFG_W1(0x00012020U), 0x6666U, \
+        SM_CFG_C1(0x00000000U), 0x0000C001U, \
+        SM_CFG_END \
+    }
+
+/*--------------------------------------------------------------------------*/
+/* TRDC H Config                                                            */
+/*--------------------------------------------------------------------------*/
+
+/*! Config for TRDC H */
+#define SM_TRDC_H_CONFIG \
+    { \
+        SM_CFG_W1(0x00000800U), 0xA3800053U, \
+        SM_CFG_W1(0x00000820U), 0xA3C00053U, \
+        SM_CFG_W1(0x00000840U), 0xA4000053U, \
+        SM_CFG_W1(0x00000860U), 0xA4400053U, \
+        SM_CFG_W1(0x00000880U), 0xA4800053U, \
+        SM_CFG_W1(0x000008a0U), 0xA4C00053U, \
+        SM_CFG_W1(0x000008c0U), 0xA5000053U, \
+        SM_CFG_W1(0x000008e0U), 0xA5400053U, \
+        SM_CFG_W1(0x00000900U), 0xA5800053U, \
+        SM_CFG_W1(0x00000920U), 0xA5C00053U, \
+        SM_CFG_W1(0x00000940U), 0xA6000053U, \
+        SM_CFG_W1(0x00000960U), 0xA6400053U, \
+        SM_CFG_W1(0x00000980U), 0xA6800053U, \
+        SM_CFG_W1(0x000009a0U), 0xA6C00053U, \
+        SM_CFG_W1(0x000009c0U), 0xA7000053U, \
+        SM_CFG_W1(0x000009e0U), 0xA7400053U, \
+        SM_CFG_W1(0x00000a00U), 0xA7800053U, \
+        SM_CFG_W1(0x00000a20U), 0xA7C00053U, \
+        SM_CFG_W1(0x00010024U), 0x6666U, \
+        SM_CFG_W1(0x00010028U), 0x7777U, \
+        SM_CFG_W1(0x0001002cU), 0x6600U, \
+        SM_CFG_W1(0x000101a8U), 0x00003000U, \
+        SM_CFG_W1(0x000103a8U), 0x00000900U, \
+        SM_CFG_W1(0x000105a8U), 0x03330000U, \
+        SM_CFG_W1(0x00010640U), 0x99999999U, \
+        SM_CFG_W1(0x00010644U), 0x99999999U, \
+        SM_CFG_W1(0x00010780U), 0x99999999U, \
+        SM_CFG_W1(0x00010784U), 0x99999999U, \
+        SM_CFG_W1(0x000107a8U), 0x00000090U, \
+        SM_CFG_W1(0x000107d0U), 0x99999999U, \
+        SM_CFG_W1(0x000107d4U), 0x99999999U, \
+        SM_CFG_W1(0x000107d8U), 0x99999999U, \
+        SM_CFG_Z1(0x000109a8U), \
+        SM_CFG_Z1(0x00010ba8U), \
+        SM_CFG_Z1(0x00010da8U), \
+        SM_CFG_Z1(0x00010fa8U), \
+        SM_CFG_W1(0x000111a8U), 0x00000009U, \
+        SM_CFG_W1(0x00011240U), 0x33333333U, \
+        SM_CFG_W1(0x00011244U), 0x33333333U, \
+        SM_CFG_W1(0x00011380U), 0x33333333U, \
+        SM_CFG_W1(0x00011384U), 0x33333333U, \
+        SM_CFG_W1(0x000113a8U), 0x03333333U, \
+        SM_CFG_W1(0x000113d0U), 0x33333333U, \
+        SM_CFG_W1(0x000113d4U), 0x33333333U, \
+        SM_CFG_W1(0x000113d8U), 0x33333333U, \
+        SM_CFG_Z1(0x000115a8U), \
+        SM_CFG_Z1(0x000117a8U), \
+        SM_CFG_Z1(0x000119a8U), \
+        SM_CFG_Z1(0x00011ba8U), \
+        SM_CFG_Z1(0x00011da8U), \
+        SM_CFG_Z1(0x00011fa8U), \
+        SM_CFG_W1(0x00012024U), 0x6666U, \
+        SM_CFG_W1(0x00012028U), 0x7777U, \
+        SM_CFG_W1(0x0001202cU), 0x6600U, \
+        SM_CFG_W1(0x00012640U), 0x00099999U, \
+        SM_CFG_W1(0x00012780U), 0x00099999U, \
+        SM_CFG_W1(0x000127a8U), 0x00099999U, \
+        SM_CFG_W1(0x000127d0U), 0x00099999U, \
+        SM_CFG_W1(0x00013240U), 0x00033333U, \
+        SM_CFG_W1(0x00013380U), 0x00033333U, \
+        SM_CFG_W1(0x000133a8U), 0x00033333U, \
+        SM_CFG_W1(0x000133d0U), 0x00033333U, \
+        SM_CFG_W1(0x00014024U), 0x6666U, \
+        SM_CFG_W1(0x00014028U), 0x7777U, \
+        SM_CFG_W1(0x0001402cU), 0x6600U, \
+        SM_CFG_W1(0x00014640U), 0x99999999U, \
+        SM_CFG_W1(0x00014644U), 0x99999999U, \
+        SM_CFG_W1(0x00014648U), 0x99999999U, \
+        SM_CFG_W1(0x00015240U), 0x33333333U, \
+        SM_CFG_W1(0x00015244U), 0x33333333U, \
+        SM_CFG_W1(0x00015248U), 0x33333333U, \
+        SM_CFG_Z1(0x00010020U), \
+        SM_CFG_Z1(0x00012020U), \
+        SM_CFG_Z1(0x00014020U), \
+        SM_CFG_C1(0x00000000U), 0x0000C001U, \
+        SM_CFG_END \
+    }
+
+/*--------------------------------------------------------------------------*/
+/* TRDC M Config                                                            */
+/*--------------------------------------------------------------------------*/
+
+/*! Config for TRDC M */
+#define SM_TRDC_M_CONFIG \
+    { \
+        SM_CFG_W1(0x00000800U), 0xB0000053U, \
+        SM_CFG_W1(0x00000820U), 0xB0000053U, \
+        SM_CFG_W1(0x00000840U), 0xB00000A8U, \
+        SM_CFG_W1(0x00000860U), 0xB0000053U, \
+        SM_CFG_W1(0x00000880U), 0xB0000053U, \
+        SM_CFG_W1(0x000008a0U), 0xB00000A9U, \
+        SM_CFG_W1(0x000008c0U), 0xB00000A9U, \
+        SM_CFG_W1(0x000008e0U), 0xB00000ACU, \
+        SM_CFG_W1(0x00000900U), 0x90000004U, \
+        SM_CFG_W1(0x00000920U), 0xB0000053U, \
+        SM_CFG_W1(0x00000940U), 0xB0000053U, \
+        SM_CFG_W1(0x00000960U), 0xB0000053U, \
+        SM_CFG_W1(0x00000980U), 0xB0000053U, \
+        SM_CFG_W1(0x000009a0U), 0xB0000053U, \
+        SM_CFG_W1(0x000009c0U), 0xB0000053U, \
+        SM_CFG_W1(0x000009e0U), 0xB0000053U, \
+        SM_CFG_W1(0x00000a00U), 0xB0000053U, \
+        SM_CFG_W1(0x00000a20U), 0xB0000053U, \
+        SM_CFG_W1(0x00000a40U), 0xB0000053U, \
+        SM_CFG_W1(0x00000a60U), 0xB0000053U, \
+        SM_CFG_W1(0x00000a80U), 0xB0000053U, \
+        SM_CFG_W1(0x00000aa0U), 0xB0000053U, \
+        SM_CFG_W1(0x00000ac0U), 0xB0000053U, \
+        SM_CFG_W1(0x00000ae0U), 0xB0000053U, \
+        SM_CFG_W1(0x00000b00U), 0xB0000053U, \
+        SM_CFG_W1(0x00000b20U), 0xB0000053U, \
+        SM_CFG_W1(0x00000b40U), 0xB0000053U, \
+        SM_CFG_W1(0x00000b60U), 0xB0000053U, \
+        SM_CFG_W1(0x00000b80U), 0xB0000053U, \
+        SM_CFG_W1(0x00000ba0U), 0xB0000053U, \
+        SM_CFG_W1(0x00000bc0U), 0xB0000053U, \
+        SM_CFG_W1(0x00000be0U), 0xB0000053U, \
+        SM_CFG_W1(0x00000c00U), 0xB0000053U, \
+        SM_CFG_W1(0x00000c20U), 0xB0000053U, \
+        SM_CFG_W1(0x00000c40U), 0xB0000053U, \
+        SM_CFG_W1(0x00000c60U), 0xB0000053U, \
+        SM_CFG_W1(0x00000c80U), 0xB0000053U, \
+        SM_CFG_W1(0x00000ca0U), 0xB0000053U, \
+        SM_CFG_W1(0x00000cc0U), 0xB0000053U, \
+        SM_CFG_W1(0x00000ce0U), 0xB0000053U, \
+        SM_CFG_W1(0x00000d00U), 0xB0000053U, \
+        SM_CFG_W1(0x00000d20U), 0xB0000053U, \
+        SM_CFG_W1(0x00000d40U), 0xB0000053U, \
+        SM_CFG_W1(0x00000d60U), 0xB00000ACU, \
+        SM_CFG_W1(0x00000d80U), 0xB0000053U, \
+        SM_CFG_W1(0x00000da0U), 0xB0000014U, \
+        SM_CFG_W1(0x00000dc0U), 0xB0000053U, \
+        SM_CFG_W1(0x00000de0U), 0xB0000053U, \
+        SM_CFG_W1(0x00000e00U), 0xB0000053U, \
+        SM_CFG_W1(0x00000e20U), 0xB0000053U, \
+        SM_CFG_C1(0x00000000U), 0x0000C001U, \
+        SM_CFG_END \
+    }
+
+/*--------------------------------------------------------------------------*/
+/* TRDC N Config                                                            */
+/*--------------------------------------------------------------------------*/
+
+/*! Config for TRDC N */
+#define SM_TRDC_N_CONFIG \
+    { \
+        SM_CFG_W1(0x00000800U), 0x90008003U, \
+        SM_CFG_W1(0x00000804U), 0x90008003U, \
+        SM_CFG_W1(0x00000808U), 0x90008003U, \
+        SM_CFG_W1(0x0000080cU), 0x90008003U, \
+        SM_CFG_W1(0x00000820U), 0x90008003U, \
+        SM_CFG_W1(0x00000824U), 0x90008003U, \
+        SM_CFG_W1(0x00000828U), 0x90008003U, \
+        SM_CFG_W1(0x0000082cU), 0x90008003U, \
+        SM_CFG_W1(0x00000840U), 0x90008003U, \
+        SM_CFG_W1(0x00000844U), 0x90008003U, \
+        SM_CFG_W1(0x00000848U), 0x90008003U, \
+        SM_CFG_W1(0x0000084cU), 0x90008003U, \
+        SM_CFG_W1(0x00000860U), 0x90008003U, \
+        SM_CFG_W1(0x00000864U), 0x90008003U, \
+        SM_CFG_W1(0x00000868U), 0x90008003U, \
+        SM_CFG_W1(0x0000086cU), 0x90008003U, \
+        SM_CFG_W1(0x00000880U), 0xB0000053U, \
+        SM_CFG_W1(0x000008a0U), 0xB0000053U, \
+        SM_CFG_W1(0x000008c0U), 0xB0000053U, \
+        SM_CFG_W1(0x00010024U), 0x6666U, \
+        SM_CFG_W1(0x00010028U), 0x7777U, \
+        SM_CFG_W1(0x0001002cU), 0x6600U, \
+        SM_CFG_W1(0x00010040U), 0x00300000U, \
+        SM_CFG_W1(0x00010180U), 0x00300000U, \
+        SM_CFG_W1(0x000101a8U), 0x00003000U, \
+        SM_CFG_W1(0x000101d0U), 0x00003000U, \
+        SM_CFG_W1(0x00010240U), 0x00009000U, \
+        SM_CFG_W1(0x00010380U), 0x00009000U, \
+        SM_CFG_W1(0x000103a8U), 0x00000900U, \
+        SM_CFG_W1(0x000103d0U), 0x00000900U, \
+        SM_CFG_W1(0x00010440U), 0x33000333U, \
+        SM_CFG_W1(0x00010444U), 0x00033303U, \
+        SM_CFG_W1(0x00010450U), 0x30000000U, \
+        SM_CFG_W1(0x00010580U), 0x33000333U, \
+        SM_CFG_W1(0x00010584U), 0x00033303U, \
+        SM_CFG_W1(0x00010590U), 0x30000000U, \
+        SM_CFG_W1(0x000105a8U), 0x00030000U, \
+        SM_CFG_W1(0x000105d0U), 0x00030000U, \
+        SM_CFG_Z1(0x00010640U), \
+        SM_CFG_W1(0x00010644U), 0x99900000U, \
+        SM_CFG_W1(0x00010648U), 0x99999990U, \
+        SM_CFG_W1(0x0001064cU), 0x99999999U, \
+        SM_CFG_W1(0x00010650U), 0x09999999U, \
+        SM_CFG_Z1(0x00010780U), \
+        SM_CFG_W1(0x00010784U), 0x99900000U, \
+        SM_CFG_W1(0x00010788U), 0x99999990U, \
+        SM_CFG_W1(0x0001078cU), 0x99999999U, \
+        SM_CFG_W1(0x00010790U), 0x09999999U, \
+        SM_CFG_Z1(0x00010840U), \
+        SM_CFG_Z1(0x00010980U), \
+        SM_CFG_Z1(0x00010a40U), \
+        SM_CFG_Z1(0x00010b80U), \
+        SM_CFG_Z1(0x00010c40U), \
+        SM_CFG_Z1(0x00010d80U), \
+        SM_CFG_Z1(0x00010e40U), \
+        SM_CFG_Z1(0x00010f80U), \
+        SM_CFG_W1(0x00011040U), 0x00090000U, \
+        SM_CFG_W1(0x00011180U), 0x00090000U, \
+        SM_CFG_W1(0x00011240U), 0x33333333U, \
+        SM_CFG_W1(0x00011244U), 0x33333303U, \
+        SM_CFG_W1(0x00011248U), 0x33333330U, \
+        SM_CFG_W1(0x0001124cU), 0x33333333U, \
+        SM_CFG_W1(0x00011250U), 0x33333333U, \
+        SM_CFG_W1(0x00011380U), 0x33333333U, \
+        SM_CFG_W1(0x00011384U), 0x33333303U, \
+        SM_CFG_W1(0x00011388U), 0x33333330U, \
+        SM_CFG_W1(0x0001138cU), 0x33333333U, \
+        SM_CFG_W1(0x00011390U), 0x33333333U, \
+        SM_CFG_W1(0x000113a8U), 0x00033300U, \
+        SM_CFG_W1(0x000113d0U), 0x00033300U, \
+        SM_CFG_Z1(0x00011440U), \
+        SM_CFG_Z1(0x00011580U), \
+        SM_CFG_Z1(0x00011640U), \
+        SM_CFG_Z1(0x00011780U), \
+        SM_CFG_Z1(0x00011840U), \
+        SM_CFG_Z1(0x00011980U), \
+        SM_CFG_Z1(0x00011a40U), \
+        SM_CFG_Z1(0x00011b80U), \
+        SM_CFG_Z1(0x00011c40U), \
+        SM_CFG_Z1(0x00011d80U), \
+        SM_CFG_Z1(0x00011e40U), \
+        SM_CFG_Z1(0x00011f80U), \
+        SM_CFG_W1(0x00012024U), 0x6666U, \
+        SM_CFG_W1(0x00012028U), 0x7777U, \
+        SM_CFG_W1(0x0001202cU), 0x6600U, \
+        SM_CFG_W1(0x00012440U), 0x33333333U, \
+        SM_CFG_W1(0x00012444U), 0x33333333U, \
+        SM_CFG_W1(0x00012448U), 0x00000333U, \
+        SM_CFG_W1(0x00012580U), 0x33333333U, \
+        SM_CFG_W1(0x00012584U), 0x33333333U, \
+        SM_CFG_W1(0x00012588U), 0x00000333U, \
+        SM_CFG_W1(0x00012640U), 0x99999999U, \
+        SM_CFG_W1(0x00012644U), 0x99999999U, \
+        SM_CFG_W1(0x00012648U), 0x00000999U, \
+        SM_CFG_W1(0x00012780U), 0x99999999U, \
+        SM_CFG_W1(0x00012784U), 0x99999999U, \
+        SM_CFG_W1(0x00012788U), 0x00000999U, \
+        SM_CFG_W1(0x00013240U), 0x33333333U, \
+        SM_CFG_W1(0x00013244U), 0x33333333U, \
+        SM_CFG_W1(0x00013248U), 0x00000333U, \
+        SM_CFG_W1(0x00013380U), 0x33333333U, \
+        SM_CFG_W1(0x00013384U), 0x33333333U, \
+        SM_CFG_W1(0x00013388U), 0x00000333U, \
+        SM_CFG_W1(0x00014024U), 0x6666U, \
+        SM_CFG_W1(0x00014028U), 0x7777U, \
+        SM_CFG_W1(0x0001402cU), 0x7700U, \
+        SM_CFG_W1(0x00014030U), 0x6600U, \
+        SM_CFG_W1(0x00014040U), 0x99999999U, \
+        SM_CFG_W1(0x00014044U), 0x99999999U, \
+        SM_CFG_W1(0x00014048U), 0x00999999U, \
+        SM_CFG_W1(0x00014180U), 0x99999999U, \
+        SM_CFG_W1(0x00014184U), 0x99999999U, \
+        SM_CFG_W1(0x00014188U), 0x00999999U, \
+        SM_CFG_Z1(0x00014440U), \
+        SM_CFG_Z1(0x00014444U), \
+        SM_CFG_Z1(0x00014448U), \
+        SM_CFG_Z1(0x00014580U), \
+        SM_CFG_Z1(0x00014584U), \
+        SM_CFG_Z1(0x00014588U), \
+        SM_CFG_W1(0x00014640U), 0x33333333U, \
+        SM_CFG_W1(0x00014644U), 0x33333333U, \
+        SM_CFG_W1(0x00014648U), 0x00AAAAAAU, \
+        SM_CFG_W1(0x00014780U), 0x33333333U, \
+        SM_CFG_W1(0x00014784U), 0x33333333U, \
+        SM_CFG_W1(0x00014788U), 0x00AAAAAAU, \
+        SM_CFG_W1(0x000147a8U), 0x99999999U, \
+        SM_CFG_W1(0x000147acU), 0x00000009U, \
+        SM_CFG_W1(0x000147d0U), 0x99999999U, \
+        SM_CFG_W1(0x000147d4U), 0x00000009U, \
+        SM_CFG_Z1(0x00014840U), \
+        SM_CFG_Z1(0x00014844U), \
+        SM_CFG_Z1(0x00014848U), \
+        SM_CFG_Z1(0x00014980U), \
+        SM_CFG_Z1(0x00014984U), \
+        SM_CFG_Z1(0x00014988U), \
+        SM_CFG_Z1(0x00014a40U), \
+        SM_CFG_Z1(0x00014a44U), \
+        SM_CFG_Z1(0x00014a48U), \
+        SM_CFG_Z1(0x00014b80U), \
+        SM_CFG_Z1(0x00014b84U), \
+        SM_CFG_Z1(0x00014b88U), \
+        SM_CFG_Z1(0x00014c40U), \
+        SM_CFG_Z1(0x00014c44U), \
+        SM_CFG_Z1(0x00014c48U), \
+        SM_CFG_Z1(0x00014d80U), \
+        SM_CFG_Z1(0x00014d84U), \
+        SM_CFG_Z1(0x00014d88U), \
+        SM_CFG_Z1(0x00014e40U), \
+        SM_CFG_Z1(0x00014e44U), \
+        SM_CFG_Z1(0x00014e48U), \
+        SM_CFG_Z1(0x00014f80U), \
+        SM_CFG_Z1(0x00014f84U), \
+        SM_CFG_Z1(0x00014f88U), \
+        SM_CFG_W1(0x00015240U), 0x44444444U, \
+        SM_CFG_W1(0x00015244U), 0x44444444U, \
+        SM_CFG_W1(0x00015248U), 0x00444444U, \
+        SM_CFG_W1(0x00015380U), 0x44444444U, \
+        SM_CFG_W1(0x00015384U), 0x44444444U, \
+        SM_CFG_W1(0x00015388U), 0x00444444U, \
+        SM_CFG_W1(0x000153a8U), 0x44444444U, \
+        SM_CFG_W1(0x000153acU), 0x00000004U, \
+        SM_CFG_W1(0x000153d0U), 0x44444444U, \
+        SM_CFG_W1(0x000153d4U), 0x00000004U, \
+        SM_CFG_Z1(0x00015440U), \
+        SM_CFG_Z1(0x00015444U), \
+        SM_CFG_Z1(0x00015448U), \
+        SM_CFG_Z1(0x00015580U), \
+        SM_CFG_Z1(0x00015584U), \
+        SM_CFG_Z1(0x00015588U), \
+        SM_CFG_Z1(0x00015640U), \
+        SM_CFG_Z1(0x00015644U), \
+        SM_CFG_Z1(0x00015648U), \
+        SM_CFG_Z1(0x00015780U), \
+        SM_CFG_Z1(0x00015784U), \
+        SM_CFG_Z1(0x00015788U), \
+        SM_CFG_W1(0x00016024U), 0x6666U, \
+        SM_CFG_W1(0x00016028U), 0x7777U, \
+        SM_CFG_W1(0x0001602cU), 0x6600U, \
+        SM_CFG_W1(0x000161a8U), 0x00003000U, \
+        SM_CFG_W1(0x000161d0U), 0x00003000U, \
+        SM_CFG_W1(0x00016240U), 0x00000900U, \
+        SM_CFG_W1(0x00016380U), 0x00000900U, \
+        SM_CFG_W1(0x000163a8U), 0x00000900U, \
+        SM_CFG_W1(0x000163d0U), 0x00000900U, \
+        SM_CFG_W1(0x00016440U), 0x33300030U, \
+        SM_CFG_W1(0x00016444U), 0x00000033U, \
+        SM_CFG_W1(0x00016580U), 0x33300030U, \
+        SM_CFG_W1(0x00016584U), 0x00000033U, \
+        SM_CFG_W1(0x000165a8U), 0x33300000U, \
+        SM_CFG_W1(0x000165d0U), 0x33300000U, \
+        SM_CFG_W1(0x00016644U), 0x00000090U, \
+        SM_CFG_W1(0x00016784U), 0x00000090U, \
+        SM_CFG_W1(0x000167a8U), 0x00000090U, \
+        SM_CFG_W1(0x000167d0U), 0x00000090U, \
+        SM_CFG_W1(0x00017040U), 0x00000009U, \
+        SM_CFG_W1(0x00017180U), 0x00000009U, \
+        SM_CFG_W1(0x000171a8U), 0x00000009U, \
+        SM_CFG_W1(0x000171d0U), 0x00000009U, \
+        SM_CFG_W1(0x00017240U), 0x33300333U, \
+        SM_CFG_W1(0x00017244U), 0x00000033U, \
+        SM_CFG_W1(0x00017380U), 0x33300333U, \
+        SM_CFG_W1(0x00017384U), 0x00000033U, \
+        SM_CFG_W1(0x000173a8U), 0x33303333U, \
+        SM_CFG_W1(0x000173d0U), 0x33303333U, \
+        SM_CFG_W1(0x00018024U), 0x6666U, \
+        SM_CFG_W1(0x00018028U), 0x7777U, \
+        SM_CFG_W1(0x0001802cU), 0x6600U, \
+        SM_CFG_W1(0x00018440U), 0x33333333U, \
+        SM_CFG_W1(0x00018580U), 0x33333333U, \
+        SM_CFG_W1(0x00019240U), 0x33333333U, \
+        SM_CFG_W1(0x00019380U), 0x33333333U, \
+        SM_CFG_W1(0x0001a024U), 0x7777U, \
+        SM_CFG_W1(0x0001a028U), 0x7700U, \
+        SM_CFG_W1(0x0001a02cU), 0x6600U, \
+        SM_CFG_W1(0x0001a040U), 0x08000000U, \
+        SM_CFG_W1(0x0001a044U), 0x87FFFC11U, \
+        SM_CFG_Z1(0x0001a04cU), \
+        SM_CFG_Z1(0x0001a054U), \
+        SM_CFG_Z1(0x0001a05cU), \
+        SM_CFG_Z1(0x0001a244U), \
+        SM_CFG_Z1(0x0001a24cU), \
+        SM_CFG_Z1(0x0001a254U), \
+        SM_CFG_Z1(0x0001a25cU), \
+        SM_CFG_W1(0x0001a340U), 0x08800001U, \
+        SM_CFG_W1(0x0001a344U), 0x089FFC11U, \
+        SM_CFG_W1(0x0001a348U), 0x08A00002U, \
+        SM_CFG_W1(0x0001a34cU), 0x08DFFC01U, \
+        SM_CFG_W1(0x0001a350U), 0x08E00001U, \
+        SM_CFG_W1(0x0001a354U), 0x87FFFC11U, \
+        SM_CFG_Z1(0x0001a35cU), \
+        SM_CFG_W1(0x0001a440U), 0x08000001U, \
+        SM_CFG_W1(0x0001a444U), 0x089FFC11U, \
+        SM_CFG_Z1(0x0001a44cU), \
+        SM_CFG_Z1(0x0001a454U), \
+        SM_CFG_Z1(0x0001a45cU), \
+        SM_CFG_Z1(0x0001a544U), \
+        SM_CFG_Z1(0x0001a54cU), \
+        SM_CFG_Z1(0x0001a554U), \
+        SM_CFG_Z1(0x0001a55cU), \
+        SM_CFG_Z1(0x0001a644U), \
+        SM_CFG_Z1(0x0001a64cU), \
+        SM_CFG_Z1(0x0001a654U), \
+        SM_CFG_Z1(0x0001a65cU), \
+        SM_CFG_Z1(0x0001a744U), \
+        SM_CFG_Z1(0x0001a74cU), \
+        SM_CFG_Z1(0x0001a754U), \
+        SM_CFG_Z1(0x0001a75cU), \
+        SM_CFG_Z1(0x0001a844U), \
+        SM_CFG_Z1(0x0001a84cU), \
+        SM_CFG_Z1(0x0001a854U), \
+        SM_CFG_Z1(0x0001a85cU), \
+        SM_CFG_W1(0x0001a940U), 0x08000003U, \
+        SM_CFG_W1(0x0001a944U), 0x089FFC01U, \
+        SM_CFG_W1(0x0001a948U), 0x08000003U, \
+        SM_CFG_W1(0x0001a94cU), 0x87FFFC01U, \
+        SM_CFG_W1(0x0001a950U), 0x08800003U, \
+        SM_CFG_W1(0x0001a954U), 0x089FFC01U, \
+        SM_CFG_W1(0x0001a958U), 0x08A00003U, \
+        SM_CFG_W1(0x0001a95cU), 0x08DFFC01U, \
+        SM_CFG_W1(0x0001a960U), 0x08E00003U, \
+        SM_CFG_W1(0x0001a964U), 0x87FFFC01U, \
+        SM_CFG_Z1(0x0001aa44U), \
+        SM_CFG_Z1(0x0001aa4cU), \
+        SM_CFG_Z1(0x0001aa54U), \
+        SM_CFG_Z1(0x0001aa5cU), \
+        SM_CFG_Z1(0x0001ab44U), \
+        SM_CFG_Z1(0x0001ab4cU), \
+        SM_CFG_Z1(0x0001ab54U), \
+        SM_CFG_Z1(0x0001ab5cU), \
+        SM_CFG_Z1(0x0001ac44U), \
+        SM_CFG_Z1(0x0001ac4cU), \
+        SM_CFG_Z1(0x0001ac54U), \
+        SM_CFG_Z1(0x0001ac5cU), \
+        SM_CFG_Z1(0x00010020U), \
+        SM_CFG_Z1(0x00012020U), \
+        SM_CFG_Z1(0x00014020U), \
+        SM_CFG_Z1(0x00016020U), \
+        SM_CFG_Z1(0x00018020U), \
+        SM_CFG_W1(0x0001a020U), 0x6666U, \
+        SM_CFG_C1(0x00000000U), 0x0000C001U, \
+        SM_CFG_END \
+    }
+
+/*--------------------------------------------------------------------------*/
+/* TRDC V Config                                                            */
+/*--------------------------------------------------------------------------*/
+
+/*! Config for TRDC V */
+#define SM_TRDC_V_CONFIG \
+    { \
+        SM_CFG_W1(0x00000800U), 0xB0000053U, \
+        SM_CFG_W1(0x00000820U), 0xB0000053U, \
+        SM_CFG_W1(0x00000840U), 0xB0000053U, \
+        SM_CFG_W1(0x00000860U), 0xB0000053U, \
+        SM_CFG_W1(0x00000880U), 0xB0000053U, \
+        SM_CFG_W1(0x000008a0U), 0xB0000053U, \
+        SM_CFG_W1(0x000008c0U), 0xB0000053U, \
+        SM_CFG_W1(0x000008e0U), 0xB0000053U, \
+        SM_CFG_W1(0x00000900U), 0xB0000053U, \
+        SM_CFG_W1(0x00000920U), 0xB0000053U, \
+        SM_CFG_W1(0x00000940U), 0xB0000053U, \
+        SM_CFG_W1(0x00000960U), 0xB0000053U, \
+        SM_CFG_W1(0x00000980U), 0xB0000053U, \
+        SM_CFG_W1(0x000009a0U), 0xB0000053U, \
+        SM_CFG_W1(0x000009c0U), 0xB0000053U, \
+        SM_CFG_W1(0x000009e0U), 0xB0000053U, \
+        SM_CFG_W1(0x00010024U), 0x6666U, \
+        SM_CFG_W1(0x00010028U), 0x7777U, \
+        SM_CFG_W1(0x0001002cU), 0x6600U, \
+        SM_CFG_W1(0x00010040U), 0x00003000U, \
+        SM_CFG_W1(0x00010180U), 0x00003000U, \
+        SM_CFG_W1(0x00010240U), 0x00000900U, \
+        SM_CFG_W1(0x00010380U), 0x00000900U, \
+        SM_CFG_W1(0x00010440U), 0x00330000U, \
+        SM_CFG_W1(0x00010450U), 0x00000003U, \
+        SM_CFG_W1(0x00010580U), 0x00330000U, \
+        SM_CFG_W1(0x00010590U), 0x00000003U, \
+        SM_CFG_W1(0x00010640U), 0x00000090U, \
+        SM_CFG_W1(0x00010644U), 0x00099999U, \
+        SM_CFG_W1(0x00010648U), 0x99999999U, \
+        SM_CFG_W1(0x0001064cU), 0x00000099U, \
+        SM_CFG_W1(0x00010780U), 0x00000090U, \
+        SM_CFG_W1(0x00010784U), 0x00099999U, \
+        SM_CFG_W1(0x00010788U), 0x99999999U, \
+        SM_CFG_W1(0x0001078cU), 0x00000099U, \
+        SM_CFG_Z1(0x00010840U), \
+        SM_CFG_Z1(0x00010980U), \
+        SM_CFG_Z1(0x00010a40U), \
+        SM_CFG_Z1(0x00010b80U), \
+        SM_CFG_Z1(0x00010c40U), \
+        SM_CFG_Z1(0x00010d80U), \
+        SM_CFG_Z1(0x00010e40U), \
+        SM_CFG_Z1(0x00010f80U), \
+        SM_CFG_W1(0x00011040U), 0x00000009U, \
+        SM_CFG_W1(0x00011180U), 0x00000009U, \
+        SM_CFG_W1(0x00011240U), 0x00333333U, \
+        SM_CFG_W1(0x00011244U), 0x00033333U, \
+        SM_CFG_W1(0x00011248U), 0x33333333U, \
+        SM_CFG_W1(0x0001124cU), 0x00000033U, \
+        SM_CFG_W1(0x00011250U), 0x00000003U, \
+        SM_CFG_W1(0x00011380U), 0x00333333U, \
+        SM_CFG_W1(0x00011384U), 0x00033333U, \
+        SM_CFG_W1(0x00011388U), 0x33333333U, \
+        SM_CFG_W1(0x0001138cU), 0x00000033U, \
+        SM_CFG_W1(0x00011390U), 0x00000003U, \
+        SM_CFG_Z1(0x00011440U), \
+        SM_CFG_Z1(0x00011580U), \
+        SM_CFG_Z1(0x00011640U), \
+        SM_CFG_Z1(0x00011780U), \
+        SM_CFG_Z1(0x00011840U), \
+        SM_CFG_Z1(0x00011980U), \
+        SM_CFG_Z1(0x00011a40U), \
+        SM_CFG_Z1(0x00011b80U), \
+        SM_CFG_Z1(0x00011c40U), \
+        SM_CFG_Z1(0x00011d80U), \
+        SM_CFG_Z1(0x00011e40U), \
+        SM_CFG_Z1(0x00011f80U), \
+        SM_CFG_Z1(0x00010020U), \
+        SM_CFG_C1(0x00000000U), 0x0000C001U, \
+        SM_CFG_END \
+    }
+
+/*--------------------------------------------------------------------------*/
+/* TRDC W Config                                                            */
+/*--------------------------------------------------------------------------*/
+
+/*! Config for TRDC W */
+#define SM_TRDC_W_CONFIG \
+    { \
+        SM_CFG_W1(0x00000800U), 0x90000004U, \
+        SM_CFG_W1(0x00000820U), 0xB0000053U, \
+        SM_CFG_W1(0x00000840U), 0xB0000053U, \
+        SM_CFG_W1(0x00000860U), 0xB0000053U, \
+        SM_CFG_W1(0x00000880U), 0xB0000053U, \
+        SM_CFG_W1(0x000008a0U), 0xB0000053U, \
+        SM_CFG_W1(0x000008c0U), 0xB0000053U, \
+        SM_CFG_W1(0x000008e0U), 0xB0000053U, \
+        SM_CFG_W1(0x00000900U), 0xB0000053U, \
+        SM_CFG_W1(0x00000920U), 0xB0000053U, \
+        SM_CFG_W1(0x00000940U), 0xB0000053U, \
+        SM_CFG_W1(0x00000960U), 0xB0000053U, \
+        SM_CFG_W1(0x00000980U), 0xB0000053U, \
+        SM_CFG_W1(0x000009a0U), 0xB0000053U, \
+        SM_CFG_W1(0x000009c0U), 0xB0000053U, \
+        SM_CFG_W1(0x000009e0U), 0xB0000053U, \
+        SM_CFG_W1(0x00000a00U), 0xB0000053U, \
+        SM_CFG_W1(0x00000a20U), 0xB0000053U, \
+        SM_CFG_W1(0x00000a40U), 0xB0000053U, \
+        SM_CFG_W1(0x00000a60U), 0xB0000053U, \
+        SM_CFG_W1(0x00000a80U), 0xB0000053U, \
+        SM_CFG_W1(0x00000aa0U), 0xB0000053U, \
+        SM_CFG_W1(0x00000ac0U), 0xB0000053U, \
+        SM_CFG_W1(0x00000ae0U), 0xB0000053U, \
+        SM_CFG_W1(0x00000b00U), 0xB0000053U, \
+        SM_CFG_W1(0x00000b20U), 0xB0000053U, \
+        SM_CFG_W1(0x00000b40U), 0xB0000053U, \
+        SM_CFG_W1(0x00000b60U), 0xB0000053U, \
+        SM_CFG_W1(0x00000b80U), 0xB0000053U, \
+        SM_CFG_W1(0x00000ba0U), 0xB0000053U, \
+        SM_CFG_W1(0x00000bc0U), 0xB0000053U, \
+        SM_CFG_W1(0x00000be0U), 0xB0000053U, \
+        SM_CFG_W1(0x00000c00U), 0xB0000053U, \
+        SM_CFG_W1(0x00000c20U), 0xB0000053U, \
+        SM_CFG_W1(0x00000c40U), 0xB0000053U, \
+        SM_CFG_W1(0x00010024U), 0x6666U, \
+        SM_CFG_W1(0x00010028U), 0x7777U, \
+        SM_CFG_W1(0x0001002cU), 0x6600U, \
+        SM_CFG_Z1(0x00010060U), \
+        SM_CFG_W1(0x00010070U), 0x00003000U, \
+        SM_CFG_Z1(0x00010260U), \
+        SM_CFG_W1(0x00010270U), 0x00000090U, \
+        SM_CFG_W1(0x00010460U), 0x33000300U, \
+        SM_CFG_W1(0x00010478U), 0x33300000U, \
+        SM_CFG_W1(0x0001047cU), 0x00003333U, \
+        SM_CFG_W1(0x000105d0U), 0x33333333U, \
+        SM_CFG_W1(0x000105d4U), 0x33333333U, \
+        SM_CFG_W1(0x000105d8U), 0x00000003U, \
+        SM_CFG_W1(0x00010640U), 0x99999999U, \
+        SM_CFG_W1(0x00010644U), 0x99999999U, \
+        SM_CFG_W1(0x00010648U), 0x99999999U, \
+        SM_CFG_W1(0x0001064cU), 0x99999999U, \
+        SM_CFG_W1(0x00010650U), 0x99999999U, \
+        SM_CFG_W1(0x00010654U), 0x99999999U, \
+        SM_CFG_W1(0x00010658U), 0x99999999U, \
+        SM_CFG_W1(0x0001065cU), 0x99999999U, \
+        SM_CFG_W1(0x00010660U), 0x00909099U, \
+        SM_CFG_W1(0x00010664U), 0x99090990U, \
+        SM_CFG_W1(0x00010668U), 0x99999999U, \
+        SM_CFG_W1(0x0001066cU), 0x09999999U, \
+        SM_CFG_W1(0x00010670U), 0x99900009U, \
+        SM_CFG_W1(0x00010674U), 0x99999999U, \
+        SM_CFG_W1(0x00010678U), 0x00009999U, \
+        SM_CFG_W1(0x0001067cU), 0x00990000U, \
+        SM_CFG_W1(0x00010780U), 0x00000009U, \
+        SM_CFG_W1(0x000107a8U), 0x00000009U, \
+        SM_CFG_W1(0x00010860U), 0x00090000U, \
+        SM_CFG_W1(0x00010864U), 0x00909009U, \
+        SM_CFG_W1(0x00010868U), 0x90000000U, \
+        SM_CFG_W1(0x00010878U), 0x00090000U, \
+        SM_CFG_Z1(0x00010a60U), \
+        SM_CFG_Z1(0x00010c60U), \
+        SM_CFG_Z1(0x00010e60U), \
+        SM_CFG_Z1(0x00011060U), \
+        SM_CFG_W1(0x00011070U), 0x00000900U, \
+        SM_CFG_W1(0x00011240U), 0x33333333U, \
+        SM_CFG_W1(0x00011244U), 0x33333333U, \
+        SM_CFG_W1(0x00011248U), 0x33333333U, \
+        SM_CFG_W1(0x0001124cU), 0x33333333U, \
+        SM_CFG_W1(0x00011250U), 0x33333333U, \
+        SM_CFG_W1(0x00011254U), 0x33333333U, \
+        SM_CFG_W1(0x00011258U), 0x33333333U, \
+        SM_CFG_W1(0x0001125cU), 0x33333333U, \
+        SM_CFG_W1(0x00011260U), 0x33333333U, \
+        SM_CFG_W1(0x00011264U), 0x33333333U, \
+        SM_CFG_W1(0x00011268U), 0x33333333U, \
+        SM_CFG_W1(0x0001126cU), 0x03333333U, \
+        SM_CFG_W1(0x00011270U), 0x33303333U, \
+        SM_CFG_W1(0x00011274U), 0x33333333U, \
+        SM_CFG_W1(0x00011278U), 0x33333333U, \
+        SM_CFG_W1(0x0001127cU), 0x00333333U, \
+        SM_CFG_W1(0x00011380U), 0x00000003U, \
+        SM_CFG_W1(0x000113a8U), 0x00000003U, \
+        SM_CFG_W1(0x000113d0U), 0x33333333U, \
+        SM_CFG_W1(0x000113d4U), 0x33333333U, \
+        SM_CFG_W1(0x000113d8U), 0x00000003U, \
+        SM_CFG_Z1(0x00011460U), \
+        SM_CFG_Z1(0x00011660U), \
+        SM_CFG_Z1(0x00011860U), \
+        SM_CFG_Z1(0x00011a60U), \
+        SM_CFG_Z1(0x00011c60U), \
+        SM_CFG_Z1(0x00011e60U), \
+        SM_CFG_W1(0x00012024U), 0x6666U, \
+        SM_CFG_W1(0x00012028U), 0x7777U, \
+        SM_CFG_W1(0x0001202cU), 0x6600U, \
+        SM_CFG_Z1(0x00012040U), \
+        SM_CFG_W1(0x00012240U), 0x90000000U, \
+        SM_CFG_W1(0x00012440U), 0x00003330U, \
+        SM_CFG_W1(0x00012580U), 0x00000003U, \
+        SM_CFG_W1(0x000125a8U), 0x00000003U, \
+        SM_CFG_W1(0x00012640U), 0x09900000U, \
+        SM_CFG_W1(0x00012644U), 0x00009900U, \
+        SM_CFG_W1(0x000127d0U), 0x00000099U, \
+        SM_CFG_Z1(0x00012840U), \
+        SM_CFG_Z1(0x00012a40U), \
+        SM_CFG_Z1(0x00012c40U), \
+        SM_CFG_Z1(0x00012e40U), \
+        SM_CFG_Z1(0x00013040U), \
+        SM_CFG_W1(0x00013240U), 0x33303330U, \
+        SM_CFG_W1(0x00013244U), 0x00003300U, \
+        SM_CFG_W1(0x00013380U), 0x00000003U, \
+        SM_CFG_W1(0x000133a8U), 0x00000003U, \
+        SM_CFG_W1(0x000133d0U), 0x00000033U, \
+        SM_CFG_Z1(0x00013440U), \
+        SM_CFG_Z1(0x00013640U), \
+        SM_CFG_Z1(0x00013840U), \
+        SM_CFG_Z1(0x00013a40U), \
+        SM_CFG_Z1(0x00013c40U), \
+        SM_CFG_Z1(0x00013e40U), \
+        SM_CFG_W1(0x00014024U), 0x6666U, \
+        SM_CFG_W1(0x00014028U), 0x7777U, \
+        SM_CFG_W1(0x0001402cU), 0x6600U, \
+        SM_CFG_W1(0x00014640U), 0x00999909U, \
+        SM_CFG_W1(0x00014780U), 0x00999909U, \
+        SM_CFG_W1(0x00014840U), 0x00000090U, \
+        SM_CFG_W1(0x00014980U), 0x00000090U, \
+        SM_CFG_W1(0x00015240U), 0x00333333U, \
+        SM_CFG_W1(0x00015380U), 0x00333333U, \
+        SM_CFG_W1(0x00017024U), 0x6600U, \
+        SM_CFG_Z1(0x00017244U), \
+        SM_CFG_Z1(0x0001724cU), \
+        SM_CFG_Z1(0x00017254U), \
+        SM_CFG_Z1(0x0001725cU), \
+        SM_CFG_Z1(0x00017340U), \
+        SM_CFG_W1(0x00017344U), 0xFFFFC011U, \
+        SM_CFG_Z1(0x0001734cU), \
+        SM_CFG_Z1(0x00017354U), \
+        SM_CFG_Z1(0x0001735cU), \
+        SM_CFG_Z1(0x00017444U), \
+        SM_CFG_Z1(0x0001744cU), \
+        SM_CFG_Z1(0x00017454U), \
+        SM_CFG_Z1(0x0001745cU), \
+        SM_CFG_Z1(0x00017544U), \
+        SM_CFG_Z1(0x0001754cU), \
+        SM_CFG_Z1(0x00017554U), \
+        SM_CFG_Z1(0x0001755cU), \
+        SM_CFG_Z1(0x00017644U), \
+        SM_CFG_Z1(0x0001764cU), \
+        SM_CFG_Z1(0x00017654U), \
+        SM_CFG_Z1(0x0001765cU), \
+        SM_CFG_Z1(0x00017744U), \
+        SM_CFG_Z1(0x0001774cU), \
+        SM_CFG_Z1(0x00017754U), \
+        SM_CFG_Z1(0x0001775cU), \
+        SM_CFG_Z1(0x00017844U), \
+        SM_CFG_Z1(0x0001784cU), \
+        SM_CFG_Z1(0x00017854U), \
+        SM_CFG_Z1(0x0001785cU), \
+        SM_CFG_W1(0x00017940U), 0x00000001U, \
+        SM_CFG_W1(0x00017944U), 0xFFFFC001U, \
+        SM_CFG_Z1(0x0001794cU), \
+        SM_CFG_Z1(0x00017954U), \
+        SM_CFG_Z1(0x0001795cU), \
+        SM_CFG_Z1(0x00017a44U), \
+        SM_CFG_Z1(0x00017a4cU), \
+        SM_CFG_Z1(0x00017a54U), \
+        SM_CFG_Z1(0x00017a5cU), \
+        SM_CFG_Z1(0x00017b44U), \
+        SM_CFG_Z1(0x00017b4cU), \
+        SM_CFG_Z1(0x00017b54U), \
+        SM_CFG_Z1(0x00017b5cU), \
+        SM_CFG_Z1(0x00017c44U), \
+        SM_CFG_Z1(0x00017c4cU), \
+        SM_CFG_Z1(0x00017c54U), \
+        SM_CFG_Z1(0x00017c5cU), \
+        SM_CFG_W1(0x00018024U), 0x6666U, \
+        SM_CFG_W1(0x00018040U), 0x4A030000U, \
+        SM_CFG_W1(0x00018044U), 0x4A03C001U, \
+        SM_CFG_Z1(0x0001804cU), \
+        SM_CFG_Z1(0x00018054U), \
+        SM_CFG_Z1(0x0001805cU), \
+        SM_CFG_W1(0x00018140U), 0x4A020001U, \
+        SM_CFG_W1(0x00018144U), 0x4A02C011U, \
+        SM_CFG_Z1(0x0001814cU), \
+        SM_CFG_Z1(0x00018154U), \
+        SM_CFG_Z1(0x0001815cU), \
+        SM_CFG_W1(0x00018240U), 0x4A050000U, \
+        SM_CFG_W1(0x00018244U), 0x4A0AC001U, \
+        SM_CFG_Z1(0x0001824cU), \
+        SM_CFG_Z1(0x00018254U), \
+        SM_CFG_Z1(0x0001825cU), \
+        SM_CFG_Z1(0x00018344U), \
+        SM_CFG_Z1(0x0001834cU), \
+        SM_CFG_Z1(0x00018354U), \
+        SM_CFG_Z1(0x0001835cU), \
+        SM_CFG_W1(0x00018440U), 0x4A060001U, \
+        SM_CFG_W1(0x00018444U), 0x4A09C011U, \
+        SM_CFG_W1(0x00018448U), 0x20380001U, \
+        SM_CFG_W1(0x0001844cU), 0x2047C011U, \
+        SM_CFG_Z1(0x00018454U), \
+        SM_CFG_Z1(0x0001845cU), \
+        SM_CFG_Z1(0x00018544U), \
+        SM_CFG_Z1(0x0001854cU), \
+        SM_CFG_Z1(0x00018554U), \
+        SM_CFG_Z1(0x0001855cU), \
+        SM_CFG_Z1(0x00018644U), \
+        SM_CFG_Z1(0x0001864cU), \
+        SM_CFG_Z1(0x00018654U), \
+        SM_CFG_Z1(0x0001865cU), \
+        SM_CFG_Z1(0x00018744U), \
+        SM_CFG_Z1(0x0001874cU), \
+        SM_CFG_Z1(0x00018754U), \
+        SM_CFG_Z1(0x0001875cU), \
+        SM_CFG_Z1(0x00018844U), \
+        SM_CFG_Z1(0x0001884cU), \
+        SM_CFG_Z1(0x00018854U), \
+        SM_CFG_Z1(0x0001885cU), \
+        SM_CFG_W1(0x00018940U), 0x4A020000U, \
+        SM_CFG_W1(0x00018944U), 0x4A02C001U, \
+        SM_CFG_W1(0x00018948U), 0x4A030000U, \
+        SM_CFG_W1(0x0001894cU), 0x4A03C001U, \
+        SM_CFG_W1(0x00018950U), 0x4A050000U, \
+        SM_CFG_W1(0x00018954U), 0x4A0AC001U, \
+        SM_CFG_W1(0x00018958U), 0x4A060000U, \
+        SM_CFG_W1(0x0001895cU), 0x4A09C001U, \
+        SM_CFG_W1(0x00018960U), 0x20380000U, \
+        SM_CFG_W1(0x00018964U), 0x2047C001U, \
+        SM_CFG_Z1(0x00018a44U), \
+        SM_CFG_Z1(0x00018a4cU), \
+        SM_CFG_Z1(0x00018a54U), \
+        SM_CFG_Z1(0x00018a5cU), \
+        SM_CFG_Z1(0x00018b44U), \
+        SM_CFG_Z1(0x00018b4cU), \
+        SM_CFG_Z1(0x00018b54U), \
+        SM_CFG_Z1(0x00018b5cU), \
+        SM_CFG_Z1(0x00018c44U), \
+        SM_CFG_Z1(0x00018c4cU), \
+        SM_CFG_Z1(0x00018c54U), \
+        SM_CFG_Z1(0x00018c5cU), \
+        SM_CFG_Z1(0x00010020U), \
+        SM_CFG_Z1(0x00012020U), \
+        SM_CFG_Z1(0x00014020U), \
+        SM_CFG_W1(0x00017020U), 0x7777U, \
+        SM_CFG_W1(0x00018020U), 0x6600U, \
+        SM_CFG_C1(0x00000000U), 0x0000C001U, \
+        SM_CFG_END \
+    }
+
+#endif /* CONFIG_TRDC_H */
+
+/** @} */
+
diff --git a/configs/tdx-verdin-imx95/config_user.h b/configs/tdx-verdin-imx95/config_user.h
new file mode 100644
index 0000000..ddf2266
--- /dev/null
+++ b/configs/tdx-verdin-imx95/config_user.h
@@ -0,0 +1,230 @@
+/*
+** ###################################################################
+**
+** Copyright 2023-2024 NXP
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** o Redistributions of source code must retain the above copyright notice, this list
+**   of conditions and the following disclaimer.
+**
+** o Redistributions in binary form must reproduce the above copyright notice, this
+**   list of conditions and the following disclaimer in the documentation and/or
+**   other materials provided with the distribution.
+**
+** o Neither the name of the copyright holder nor the names of its
+**   contributors may be used to endorse or promote products derived from this
+**   software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+** ###################################################################
+*/
+
+/*==========================================================================*/
+/*!
+ * @addtogroup CONFIG_TDXVERDINIMX95
+ * @{
+ *
+ * @file
+ * @brief
+ *
+ * Header file containing configuration info for the manual user settings.
+ */
+/*==========================================================================*/
+
+#ifndef CONFIG_USER_H
+#define CONFIG_USER_H
+
+/* Includes */
+
+#include "config.h"
+
+/* Defines */
+
+
+/*--------------------------------------------------------------------------*/
+/* CAMERA Config                                                            */
+/*--------------------------------------------------------------------------*/
+
+/*! Data load config for the CAMERA mix */
+#define SM_CAMERA_CONFIG \
+    { \
+        SM_CFG_END \
+    }
+
+/*--------------------------------------------------------------------------*/
+/* A55P Config                                                              */
+/*--------------------------------------------------------------------------*/
+
+/*! Data load config for the A55P mix */
+#define SM_A55P_CONFIG \
+    { \
+        SM_CFG_END \
+    }
+
+/*--------------------------------------------------------------------------*/
+/* DDR Config                                                               */
+/*--------------------------------------------------------------------------*/
+
+/*! Data load config for the DDR mix */
+#define SM_DDR_CONFIG \
+    { \
+        SM_CFG_END \
+    }
+
+/*--------------------------------------------------------------------------*/
+/* DISPLAY Config                                                           */
+/*--------------------------------------------------------------------------*/
+
+/*! Data load config for the DISPLAY mix */
+#define SM_DISPLAY_CONFIG \
+    { \
+        SM_CFG_END \
+    }
+
+/*--------------------------------------------------------------------------*/
+/* GPU Config                                                               */
+/*--------------------------------------------------------------------------*/
+
+/*! Data load config for the GPU mix */
+#define SM_GPU_CONFIG \
+    { \
+        SM_CFG_END \
+    }
+
+/*--------------------------------------------------------------------------*/
+/* HSIO_TOP Config                                                          */
+/*--------------------------------------------------------------------------*/
+
+/*! Data load config for the HSIO_TOP mix */
+#define SM_HSIO_TOP_CONFIG \
+    { \
+        SM_CFG_END \
+    }
+
+/*--------------------------------------------------------------------------*/
+/* HSIO_WAON Config                                                         */
+/*--------------------------------------------------------------------------*/
+
+/*! Data load config for the HSIO_WAON mix */
+#define SM_HSIO_WAON_CONFIG \
+    { \
+        SM_CFG_END \
+    }
+
+/*--------------------------------------------------------------------------*/
+/* M7 Config                                                                */
+/*--------------------------------------------------------------------------*/
+
+/*! Data load config for the M7 mix */
+#define SM_M7_CONFIG \
+    { \
+        SM_CFG_END \
+    }
+
+/*--------------------------------------------------------------------------*/
+/* NETC Config                                                              */
+/*--------------------------------------------------------------------------*/
+
+/*! Data load config for the NETC mix */
+#define SM_NETC_CONFIG \
+    { \
+        SM_CFG_END \
+    }
+
+/*--------------------------------------------------------------------------*/
+/* NOC Config                                                               */
+/*--------------------------------------------------------------------------*/
+
+/*! Data load config for the NOC mix */
+#define SM_NOC_CONFIG \
+    { \
+        SM_CFG_END \
+    }
+
+/*--------------------------------------------------------------------------*/
+/* NPU Config                                                               */
+/*--------------------------------------------------------------------------*/
+
+/*! Data load config for the NPU mix */
+#define SM_NPU_CONFIG \
+    { \
+        SM_CFG_END \
+    }
+
+/*--------------------------------------------------------------------------*/
+/* VPU Config                                                               */
+/*--------------------------------------------------------------------------*/
+
+/*! Data load config for the VPU mix */
+#define SM_VPU_CONFIG \
+    { \
+        SM_CFG_END \
+    }
+
+/*--------------------------------------------------------------------------*/
+/* WKUP Config                                                              */
+/*--------------------------------------------------------------------------*/
+
+/*! Data load config for the WKUP mix */
+#define SM_WKUP_CONFIG \
+    { \
+        SM_CFG_END \
+    }
+
+/*--------------------------------------------------------------------------*/
+/* ANA Config                                                               */
+/*--------------------------------------------------------------------------*/
+
+/*! Data load config for the ANA mix */
+#define SM_ANA_CONFIG \
+    { \
+        SM_CFG_END \
+    }
+
+/*--------------------------------------------------------------------------*/
+/* AON Config                                                               */
+/*--------------------------------------------------------------------------*/
+
+/*! Data load config for the AON mix */
+#define SM_AON_CONFIG \
+    { \
+        SM_CFG_END \
+    }
+
+/*--------------------------------------------------------------------------*/
+/* BBSM Config                                                              */
+/*--------------------------------------------------------------------------*/
+
+/*! Data load config for the BBSM mix */
+#define SM_BBSM_CONFIG \
+    { \
+        SM_CFG_END \
+    }
+
+/*--------------------------------------------------------------------------*/
+/* CCMSRCGPC Config                                                         */
+/*--------------------------------------------------------------------------*/
+
+/*! Data load config for the CCMSRCGPC mix */
+#define SM_CCMSRCGPC_CONFIG \
+    { \
+        SM_CFG_END \
+    }
+
+#endif /* CONFIG_USER_H */
+
+/** @} */
+