diff options
Diffstat (limited to 'boards')
| -rwxr-xr-x | boards/tdx-verdin-imx95/board.c | 576 | ||||
| -rwxr-xr-x | boards/tdx-verdin-imx95/board.h | 164 | ||||
| -rwxr-xr-x | boards/tdx-verdin-imx95/pin_mux.c | 54 | ||||
| -rwxr-xr-x | boards/tdx-verdin-imx95/pin_mux.h | 44 | ||||
| -rwxr-xr-x | boards/tdx-verdin-imx95/sm/Makefile | 63 | ||||
| -rwxr-xr-x | boards/tdx-verdin-imx95/sm/brd_sm.c | 686 | ||||
| -rwxr-xr-x | boards/tdx-verdin-imx95/sm/brd_sm.dox | 55 | ||||
| -rwxr-xr-x | boards/tdx-verdin-imx95/sm/brd_sm.h | 96 | ||||
| -rwxr-xr-x | boards/tdx-verdin-imx95/sm/brd_sm_control.c | 155 | ||||
| -rwxr-xr-x | boards/tdx-verdin-imx95/sm/brd_sm_control.h | 172 | ||||
| -rwxr-xr-x | boards/tdx-verdin-imx95/sm/brd_sm_handlers.c | 215 | ||||
| -rwxr-xr-x | boards/tdx-verdin-imx95/sm/brd_sm_handlers.h | 88 | ||||
| -rwxr-xr-x | boards/tdx-verdin-imx95/sm/brd_sm_sensor.c | 367 | ||||
| -rwxr-xr-x | boards/tdx-verdin-imx95/sm/brd_sm_sensor.h | 210 | ||||
| -rwxr-xr-x | boards/tdx-verdin-imx95/sm/brd_sm_voltage.c | 517 | ||||
| -rwxr-xr-x | boards/tdx-verdin-imx95/sm/brd_sm_voltage.h | 213 |
16 files changed, 3675 insertions, 0 deletions
diff --git a/boards/tdx-verdin-imx95/board.c b/boards/tdx-verdin-imx95/board.c new file mode 100755 index 0000000..55bd498 --- /dev/null +++ b/boards/tdx-verdin-imx95/board.c @@ -0,0 +1,576 @@ +/* + * Copyright 2023-2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "sm.h" +#include "board.h" +#include "brd_sm_voltage.h" +#include "fsl_lpuart.h" +#include "fsl_lpi2c.h" +#include "fsl_ccm.h" +#include "fsl_clock.h" +#include "fsl_bbnsm.h" +#include "fsl_reset.h" +#include "fsl_sysctr.h" +#include "fsl_systick.h" +#include "fsl_wdog32.h" +#include "fsl_cache.h" +#include "fsl_iomuxc.h" +#include "fsl_fro.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* External board-level clock rates */ +#define BOARD_EXT_CLK_RATE 25000000UL /* 25MHz */ + +/* ADC clck rate */ +#define BOARD_ADC_CLK_RATE 80000000UL /* 80MHz */ + +/* SM SysTick parameters */ +#define BOARD_SYSTICK_CLKSRC 0U /* 0 = external ref */ +#define BOARD_SYSTICK_CLK_ROOT CLOCK_ROOT_M33SYSTICK /* Dedicated CCM root */ + +/* SM WDOG */ +#define BOARD_WDOG_BASE_PTR WDOG2 +#define BOARD_WDOG_IRQn WDOG2_IRQn +#define BOARD_WDOG_CLK_SRC kWDOG32_ClockSource1 /* lpo_clk @ 32K */ +#define BOARD_WDOG_TIMEOUT 0xFFFFU /* 65535 ticks @ 32K = 2 sec */ +#define BOARD_WDOG_SRMASK (1UL << RST_REASON_WDOG2) +#define BOARD_WDOG_ANY_INIT ~(BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG2_MASK) +#define BOARD_WDOG_ANY_MASK BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG2_MASK +#define BOARD_WDOG_IPG_DEBUG BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_WDOG2_MASK + +/* Board UART */ +#ifdef INC_LIBC +#define BOARD_UART BOARD_DEBUG_UART_INSTANCE +#else +#define BOARD_UART 0U +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ +static wdog32_config_t s_wdogConfig; + +/* Debug UART base pointer list */ +static LPUART_Type *const s_uartBases[] = LPUART_BASE_PTRS; + +/* Debug UART base pointer list */ +static IRQn_Type const s_uartIrqs[] = LPUART_RX_TX_IRQS; + +/* Debug UART clock list */ +static uint32_t const s_uartClks[] = +{ + 0U, + CLOCK_ROOT_LPUART1, + CLOCK_ROOT_LPUART2, + CLOCK_ROOT_LPUART3, + CLOCK_ROOT_LPUART4, + CLOCK_ROOT_LPUART5, + CLOCK_ROOT_LPUART6, + CLOCK_ROOT_LPUART7, + CLOCK_ROOT_LPUART8 +}; + +/* Debug UART peripheral LPI list */ +static uint32_t const s_uartPerLpi[] = +{ + 0U, + CPU_PER_LPI_IDX_LPUART1, + CPU_PER_LPI_IDX_LPUART2, + CPU_PER_LPI_IDX_LPUART3, + CPU_PER_LPI_IDX_LPUART4, + CPU_PER_LPI_IDX_LPUART5, + CPU_PER_LPI_IDX_LPUART6, + CPU_PER_LPI_IDX_LPUART7, + CPU_PER_LPI_IDX_LPUART8 +}; + +/* Debug UART configuration info */ +static board_uart_config_t const s_uartConfig = +{ + .base = s_uartBases[BOARD_UART], + .irq = s_uartIrqs[BOARD_UART], + .clockId = s_uartClks[BOARD_UART], + .perLpiId = s_uartPerLpi[BOARD_UART], + .baud = BOARD_DEBUG_UART_BAUDRATE, + .inst = BOARD_UART +}; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*--------------------------------------------------------------------------*/ +/* Configure CM33 MPU and XCACHE controller */ +/*--------------------------------------------------------------------------*/ +void BOARD_ConfigMPU(void) +{ + uint8_t attr; + + /* Disable code cache(ICache) and system cache(DCache) */ + XCACHE_DisableCache(LPCAC_PC); + XCACHE_DisableCache(LPCAC_PS); + + /* NOTE: All TCRAM is non-cacheable regardless of MPU setting. */ + + /* + * default cache policy(default memory access behavior) after enable + * mpu on cortex-m33(according to RM of cortex-m33): + * 0x00000000-0x1FFFFFFF Normal memory, Non-shareable, Write-Through, + * not Write Allocate + * 0x20000000-0x3FFFFFFF Normal memory, Non-shareable, Write-Back, + * Write Allocate + * 0x40000000-0x5FFFFFFF Device, Shareable + * 0x60000000-0x7FFFFFFF Normal memory, Non-shareable, Write-Back, + * Write Allocate + * 0x80000000-0x9FFFFFFF Normal memory, Non-shareable, Write-Through, + * not Write Allocate + * 0xA0000000-0xDFFFFFFF Device, Shareable + * 0xE0000000-0xE003FFFF Device, Shareable + * 0xE0040000-0xE0043FFF Device, Shareable + * 0xE0044000-0xE00EFFFF Device, Shareable + * 0xF0000000-0xFFFFFFFF Device, Shareable + */ + /* Disable MPU */ + ARM_MPU_Disable(); + + /* Attr0: Device-nGnRnE */ + // coverity[misra_c_2012_rule_14_3_violation:FALSE] + ARM_MPU_SetMemAttr(0U, ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, + ARM_MPU_ATTR_DEVICE)); + + /* Attr1: Normal memory, Outer non-cacheable, Inner non-cacheable */ + // coverity[misra_c_2012_rule_14_3_violation:FALSE] + ARM_MPU_SetMemAttr(1U, ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, + ARM_MPU_ATTR_NON_CACHEABLE)); + + /* Attr2: Normal memory, Inner write-through transient, read allocate. + * Inner write-through transient, read allocate + */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 0U, 1U, 0U); + ARM_MPU_SetMemAttr(2U, ARM_MPU_ATTR(attr, attr)); + + /* Attr3: Normal memory, Outer write-back transient, read/write allocate. + * Inner write-back transient, read/write + * allocate */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 1U, 1U, 1U); + ARM_MPU_SetMemAttr(3U, ARM_MPU_ATTR(attr, attr)); + + /* + * Change macro definitions as follows when choose cache policy + * as non-cacheable: + * #define DDR_NONCACHEABLE (1U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy + * as Write-Through: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (1U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy + * as Write-Back: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (1U) + */ +#define DDR_NONCACHEABLE (1U) +#define DDR_WRITE_THROUGH (0U) +#define DDR_WRITE_BACK (0U) +#if DDR_NONCACHEABLE + /* NOTE: DDR is used as shared memory for A/M core communication, + * set it to non-cacheable. */ + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, + * read/write, any privileged, executable. Attr 1 (non-cacheable). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000U, ARM_MPU_SH_OUTER, 0U, + 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFFU, 1U)); +#elif DDR_WRITE_THROUGH + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, + * any privileged, executable. Attr 2 + * (Normal memory, Inner write-through transient, read allocate. Inner + * write-through transient, read allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000U, ARM_MPU_SH_OUTER, 0U, + 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFFU, 2U)); +#elif DDR_WRITE_BACK + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, + * any privileged, executable. Attr 3 + * (Normal memory, Outer write-back transient, read/write allocate. Inner + * write-back transient, read/write allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000U, ARM_MPU_SH_OUTER, 0U, + 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFFU, 3U)); +#endif + +#define OCRAM_NONCACHEABLE (1U) +#define OCRAM_WRITE_THROUGH (0U) +#define OCRAM_WRITE_BACK (0U) +#if OCRAM_NONCACHEABLE + /* Region 1: [0x20480000, 0x2051FFFF](OCRAM), outer shareable, read/write, + * any privileged, executable. Attr 1 (non-cacheable). */ + ARM_MPU_SetRegion(1U, ARM_MPU_RBAR(0x20480000U, ARM_MPU_SH_OUTER, 0U, + 1U, 0U), ARM_MPU_RLAR(0x2051FFFFU, 1U)); +#elif OCRAM_WRITE_THROUGH + /* Region 1: [0x20480000, 0x2051FFFF](OCRAM), outer shareable, + * read/write, any privileged, executable. Attr 2 (Normal memory, Inner + * write-through transient, read allocate. Inner write-through transient, + * read allocate). */ + ARM_MPU_SetRegion(1U, ARM_MPU_RBAR(0x20480000U, ARM_MPU_SH_OUTER, 0U, + 1U, 0U), ARM_MPU_RLAR(0x2051FFFFU, 2U)); +#elif OCRAM_WRITE_BACK + /* Region 1: [0x20480000, 0x2051FFFF](OCRAM), outer shareable, + * read/write, any privileged, executable. Attr 3 (Normal memory, + * Outer write-back transient, read/write allocate. Inner write-back + * transient, read/write allocate). */ + ARM_MPU_SetRegion(1U, ARM_MPU_RBAR(0x20480000U, ARM_MPU_SH_OUTER, 0U, + 1U, 0U), ARM_MPU_RLAR(0x2051FFFFU, 3U)); +#endif + + /* Enable MPU(use default memory map when access the memory within + * region) */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + /* Enable ICache and DCache */ + XCACHE_EnableCache(LPCAC_PC); + XCACHE_EnableCache(LPCAC_PS); +} + +/*--------------------------------------------------------------------------*/ +/* Initialize clocking */ +/*--------------------------------------------------------------------------*/ +void BOARD_InitClocks(void) +{ + uint32_t fuseTrim = FSB->FUSE[FSB_FUSE_ANA_CFG4]; + + if (fuseTrim == 0U) + { + /* Enable the FRO clock with default value */ + (void)FRO_SetEnable(true); + } + else + { + /* Set the Trim value read from the fuses */ + bool status = FRO_SetTrim(fuseTrim); + + if (status) + { + /* Enable the FRO clock with default value */ + (void) FRO_SetEnable(true); + } + } + + /* Configure default EXT_CLK1 rate tied to XTAL_OUT/EXT_CLK pin */ + (void) CLOCK_SourceSetRate(CLOCK_SRC_EXT1, BOARD_EXT_CLK_RATE, 0U); + + /* Configure ADC clock */ + (void) CCM_RootSetParent(CLOCK_ROOT_ADC, CLOCK_SRC_SYSPLL1_PFD1_DIV2); + (void) CCM_RootSetRate(CLOCK_ROOT_ADC, BOARD_ADC_CLK_RATE, + CLOCK_ROUND_RULE_CEILING); +} + +/*--------------------------------------------------------------------------*/ +/* Return the debug UART info */ +/*--------------------------------------------------------------------------*/ +const board_uart_config_t *BOARD_GetDebugUart(void) +{ + return &s_uartConfig; +} + +/*--------------------------------------------------------------------------*/ +/* Initialize debug console */ +/*--------------------------------------------------------------------------*/ +void BOARD_InitDebugConsole(void) +{ + if (s_uartConfig.base != NULL) + { + uint64_t rate = CCM_RootGetRate(s_uartConfig.clockId); + + /* Configure debug UART */ + lpuart_config_t lpuart_config; + LPUART_GetDefaultConfig(&lpuart_config); + lpuart_config.baudRate_Bps = s_uartConfig.baud; + lpuart_config.rxFifoWatermark = ((uint8_t) + FSL_FEATURE_LPUART_FIFO_SIZEn(s_uartConfig.base)) - 1U; + lpuart_config.txFifoWatermark = ((uint8_t) + FSL_FEATURE_LPUART_FIFO_SIZEn(s_uartConfig.base)) - 1U; + lpuart_config.enableTx = true; + lpuart_config.enableRx = true; + (void) LPUART_Init(s_uartConfig.base, &lpuart_config, + (uint32_t) rate & 0xFFFFFFFFU); + } +} + +/*--------------------------------------------------------------------------*/ +/* Initialize IRQ handlers */ +/*--------------------------------------------------------------------------*/ +void BOARD_InitHandlers(void) +{ + /* Configure default priority of exceptions and IRQs */ + for (int32_t irq = ((int32_t) SVCall_IRQn); irq < ((int32_t) + NUMBER_OF_INT_VECTORS); irq++) + { + // coverity[misra_c_2012_rule_10_5_violation:FALSE] + NVIC_SetPriority((IRQn_Type) irq, IRQ_PRIO_NOPREEMPT_NORMAL); + } + + /* Configure SWI handler */ + NVIC_EnableIRQ(BOARD_SWI_IRQn); + + /* Enable BBNSM handler */ + NVIC_EnableIRQ(BBNSM_IRQn); + + /* Enable GPC SM handler */ + NVIC_SetPriority(GPC_SM_REQ_IRQn, IRQ_PRIO_NOPREEMPT_VERY_HIGH); + NVIC_EnableIRQ(GPC_SM_REQ_IRQn); + + /* Enable ELE Group IRQ handlers */ + NVIC_EnableIRQ(ELE_Group1_IRQn); + NVIC_EnableIRQ(ELE_Group2_IRQn); + NVIC_EnableIRQ(ELE_Group3_IRQn); + + /* Enable FCCU handler */ + NVIC_SetPriority(FCCU_INT0_IRQn, IRQ_PRIO_NOPREEMPT_CRITICAL); + NVIC_EnableIRQ(FCCU_INT0_IRQn); +} + +/*--------------------------------------------------------------------------*/ +/* Initialize timers */ +/*--------------------------------------------------------------------------*/ +void BOARD_InitTimers(void) +{ + /* Configure and enable the BBNSM RTC */ + bbnsm_rtc_config_t rtcConfig; + BBNSM_RTC_GetDefaultConfig(&rtcConfig); + BBNSM_RTC_Init(BBNSM, &rtcConfig); + + /* Configure and enable system counter */ + SYSCTR_Init(); + + /* Configure and enable M33 SysTick */ + uint64_t rate = CCM_RootGetRate(BOARD_SYSTICK_CLK_ROOT); + uint32_t reloadVal = (uint32_t) (rate & 0xFFFFFFFFU); + reloadVal = ((reloadVal * BOARD_TICK_PERIOD_MSEC) + 999U) / 1000U; + SYSTICK_Init(1U, BOARD_SYSTICK_CLKSRC, (uint32_t) (rate & 0xFFFFFFFFU), + reloadVal); + NVIC_EnableIRQ(SysTick_IRQn); + + /* Configure and enable the WDOG */ + WDOG32_GetDefaultConfig(&s_wdogConfig); + s_wdogConfig.clockSource = BOARD_WDOG_CLK_SRC; + s_wdogConfig.timeoutValue = BOARD_WDOG_TIMEOUT; + s_wdogConfig.enableInterrupt = true; + WDOG32_Init(BOARD_WDOG_BASE_PTR, &s_wdogConfig); + NVIC_SetPriority(BOARD_WDOG_IRQn, IRQ_PRIO_PREEMPT_CRITICAL); + + /* Configure to just non-FCCU SM watchdogs */ + BLK_CTRL_S_AONMIX->WDOG_ANY_MASK = BOARD_WDOG_ANY_INIT; + + /* Switch WDOG to COLD mode */ + BOARD_WdogModeSet(BOARD_WDOG_MODE_COLD); + + /* Halt SM WDOG on M33 debug entry */ + BLK_CTRL_NS_AONMIX->IPG_DEBUG_CM33 = (BOARD_WDOG_IPG_DEBUG); + + /* Halt CM7 WDOG on CM7 debug entry */ + BLK_CTRL_WAKEUPMIX->IPG_DEBUG_CM7 = + BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_WDOG5_MASK; +} + +/*--------------------------------------------------------------------------*/ +/* Set watchdog mode */ +/*--------------------------------------------------------------------------*/ +void BOARD_WdogModeSet(uint32_t mode) +{ + switch (mode) + { + case BOARD_WDOG_MODE_WARM: /* warm */ + /* Allow WDOG to generate internal warm reset */ + SRC_GEN->SRMASK &= (~BOARD_WDOG_SRMASK); + + /* Enable WDOG interrupt */ + NVIC_EnableIRQ(BOARD_WDOG_IRQn); + + /* Disable WDOG_ANY */ + BLK_CTRL_S_AONMIX->WDOG_ANY_MASK |= BOARD_WDOG_ANY_MASK; + + /* Drive WDOG_ANY from WDOG */ + IOMUXC_SetPinMux(IOMUXC_PAD_WDOG_ANY__WDOG_ANY, 0U); + break; + case BOARD_WDOG_MODE_COLD: /* cold */ + /* Allow WDOG to generate internal warm reset */ + SRC_GEN->SRMASK &= (~BOARD_WDOG_SRMASK); + + /* Enable WDOG interrupt */ + NVIC_EnableIRQ(BOARD_WDOG_IRQn); + + /* Enable WDOG_ANY */ + BLK_CTRL_S_AONMIX->WDOG_ANY_MASK &= ~BOARD_WDOG_ANY_MASK; + + /* Drive WDOG_ANY from WDOG */ + IOMUXC_SetPinMux(IOMUXC_PAD_WDOG_ANY__WDOG_ANY, 0U); + break; + case BOARD_WDOG_MODE_IRQ: /* irq */ + /* Enable WDOG interrupt */ + NVIC_EnableIRQ(BOARD_WDOG_IRQn); + + /* Disallow WDOG to generate internal warm reset */ + SRC_GEN->SRMASK |= BOARD_WDOG_SRMASK; + + /* Disable WDOG_ANY */ + BLK_CTRL_S_AONMIX->WDOG_ANY_MASK |= BOARD_WDOG_ANY_MASK; + + /* Drive WDOG_ANY from WDOG */ + IOMUXC_SetPinMux(IOMUXC_PAD_WDOG_ANY__WDOG_ANY, 0U); + break; + case BOARD_WDOG_MODE_OFF: /* off */ + s_wdogConfig.enableWdog32 = false; + WDOG32_Deinit(BOARD_WDOG_BASE_PTR); + break; + case BOARD_WDOG_MODE_TRIGGER: /* trigger */ + BOARD_WDOG_BASE_PTR->CNT = 0U; + break; + case BOARD_WDOG_MODE_FCCU: /* fccu */ + /* Drive WDOG_ANY from FCCU */ + IOMUXC_SetPinMux(IOMUXC_PAD_WDOG_ANY__FCCU_EOUT1, 0U); + + /* Disallow WDOG to generate internal warm reset */ + SRC_GEN->SRMASK |= BOARD_WDOG_SRMASK; + + /* Disable WDOG interrupt */ + NVIC_DisableIRQ(BOARD_WDOG_IRQn); + break; + default: + ; /* Intentional empty default */ + break; + } +} + +/*--------------------------------------------------------------------------*/ +/* Kick the watchdog timer */ +/*--------------------------------------------------------------------------*/ +void BOARD_WdogRefresh(void) +{ + WDOG32_Refresh(BOARD_WDOG_BASE_PTR); +} + +/*--------------------------------------------------------------------------*/ +/* Initialize serial bus for external devices */ +/*--------------------------------------------------------------------------*/ +void BOARD_InitSerialBus(void) +{ + static LPI2C_Type *const s_i2cBases[] = LPI2C_BASE_PTRS; + LPI2C_Type *base = s_i2cBases[BOARD_I2C_INSTANCE]; + lpi2c_master_config_t lpi2cConfig = {0}; + static uint32_t const s_i2cClks[] = + { + 0U, + CLOCK_ROOT_LPI2C1, + CLOCK_ROOT_LPI2C2 + }; + uint32_t clockId = s_i2cClks[BOARD_I2C_INSTANCE]; + + uint32_t rate = (uint32_t) CCM_RootGetRate(clockId); + + LPI2C_MasterGetDefaultConfig(&lpi2cConfig); + + lpi2cConfig.baudRate_Hz = BOARD_I2C_BAUDRATE; + lpi2cConfig.enableDoze = false; + + LPI2C_MasterInit(base, &lpi2cConfig, rate); +} + +/*--------------------------------------------------------------------------*/ +/* System sleep prepare */ +/*--------------------------------------------------------------------------*/ +void BOARD_SystemSleepPrepare(uint32_t sleepMode, uint32_t sleepFlags) +{ + BRD_SM_VoltageSuspend(true); + + /* Configure SM LPUART for wakeup */ + if (s_uartConfig.base != NULL) + { + /* Enable edge-detect IRQ */ + (void) LPUART_ClearStatusFlags(s_uartConfig.base, + (uint32_t)kLPUART_RxActiveEdgeFlag); + LPUART_EnableInterrupts(s_uartConfig.base, + (uint32_t)kLPUART_RxActiveEdgeInterruptEnable); + NVIC_EnableIRQ(s_uartConfig.irq); + + /* Configure LPI of SM LPUART */ + (void) CPU_PerLpiConfigSet(CPU_IDX_M33P, s_uartConfig.perLpiId, + CPU_PER_LPI_ON_RUN_WAIT_STOP); + } + + /* Configure LPI for GPIO1 */ + (void) CPU_PerLpiConfigSet(CPU_IDX_M33P, CPU_PER_LPI_IDX_GPIO1, + CPU_PER_LPI_ON_RUN_WAIT_STOP); +} + +/*--------------------------------------------------------------------------*/ +/* System sleep entry */ +/*--------------------------------------------------------------------------*/ +void BOARD_SystemSleepEnter(uint32_t sleepMode, uint32_t sleepFlags) +{ + /* Disable SysTick */ + uint32_t sysTickMask = SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; + SysTick->CTRL &= (~sysTickMask); + + /* Clear pending SysTick exception */ + SCB->ICSR = SCB_ICSR_PENDSTCLR_Msk; + + if (s_wdogConfig.enableWdog32) + { + /* Disable WDOG */ + WDOG32_Deinit(BOARD_WDOG_BASE_PTR); + + /* Waits for new configuration to take effect. */ + while (0U == ((BOARD_WDOG_BASE_PTR->CS) & WDOG_CS_RCS_MASK)) + { + ; /* Intentional empty while */ + } + } +} + +/*--------------------------------------------------------------------------*/ +/* System sleep exit */ +/*--------------------------------------------------------------------------*/ +void BOARD_SystemSleepExit(uint32_t sleepMode, uint32_t sleepFlags) +{ + if (s_wdogConfig.enableWdog32) + { + /* Enable WDOG */ + WDOG32_Init(BOARD_WDOG_BASE_PTR, &s_wdogConfig); + } + + /* Enable SysTick */ + uint32_t sysTickMask = SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; + SysTick->VAL = 0U; + SysTick->CTRL |= (sysTickMask); +} + +/*--------------------------------------------------------------------------*/ +/* System sleep unprepare */ +/*--------------------------------------------------------------------------*/ +void BOARD_SystemSleepUnprepare(uint32_t sleepMode, uint32_t sleepFlags) +{ + BRD_SM_VoltageRestore(); + + /* Service SM LPUART wakeup events */ + if (s_uartConfig.base != NULL) + { + (void) LPUART_ClearStatusFlags(s_uartConfig.base, + (uint32_t)kLPUART_RxActiveEdgeFlag); + LPUART_DisableInterrupts(s_uartConfig.base, + (uint32_t)kLPUART_RxActiveEdgeInterruptEnable); + + NVIC_DisableIRQ(s_uartConfig.irq); + NVIC_ClearPendingIRQ(s_uartConfig.irq); + } +} + diff --git a/boards/tdx-verdin-imx95/board.h b/boards/tdx-verdin-imx95/board.h new file mode 100755 index 0000000..3cddd2f --- /dev/null +++ b/boards/tdx-verdin-imx95/board.h @@ -0,0 +1,164 @@ +/* + * Copyright 2023-2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef BOARD_H +#define BOARD_H + +#include "fsl_common.h" +#include "config_board.h" +#include "dev_sm.h" + +/*! + * @addtogroup BRD_SM_TDXVERDINIMX95 + * @{ + * + * @file + * @brief + * + * Header file containing the board API. + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @name Board general parameters + */ +/** @{ */ +#define BOARD_TICK_PERIOD_MSEC 10U /*!< Tick period */ +#define BOARD_SWI_IRQn Reserved110_IRQn /*!< SWI IRQ */ +#define BOARD_HAS_WDOG /*!< Has a watchdog */ +#define BOARD_HAS_PMIC /*!< Has a PMIC */ +#define BOARD_PMIC_RESUME_TICKS ((20U * 32768U) / 10000U) /*!< 2ms in 32K ticks */ +/** @} */ + +/*! + * @name Board PF09 OTP voltages (uV) + */ +/** @{ */ +#define BOARD_VOLT_SOC 920000 /*!< SOC OTP */ +#define BOARD_VOLT_ARM 920000 /*!< ARM OTP */ +/** @} */ + +/*! + * @name Watchdog modes + */ +/** @{ */ +#define BOARD_WDOG_MODE_WARM 0U /*!< Wdog generate warm reset */ +#define BOARD_WDOG_MODE_COLD 1U /*!< Wdog generate cold reset */ +#define BOARD_WDOG_MODE_IRQ 2U /*!< Wdog generate IRQ only */ +#define BOARD_WDOG_MODE_OFF 3U /*!< Wdog disabled */ +#define BOARD_WDOG_MODE_TRIGGER 4U /*!< Trigger wdog */ +#define BOARD_WDOG_MODE_FCCU 5U /*!< Wdog generate FCCU fault */ +/** @} */ + +/******************************************************************************* + * Types + ******************************************************************************/ + +/*! + * Debug UART configuration info + */ +typedef struct +{ + LPUART_Type *const base; /*!< LPUART base pointer */ + IRQn_Type irq; /*!< Interrupt number */ + uint32_t clockId; /*!< Clock ID */ + uint32_t perLpiId; /*!< Peripheral LPI ID */ + uint32_t baud; /*!< Baud rate */ + uint8_t inst; /*!< Instance number */ +} board_uart_config_t; + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! Configure the M33 MPU */ +void BOARD_ConfigMPU(void); + +/*! Init hardware */ +void BOARD_InitHardware(void); + +/*! Init clocks */ +void BOARD_InitClocks(void); + +/*! + * Get a device clock debug UART info. + * + * This function returns the UART info for the UART used for SM + * debug. + * + * @return Returns the debug UART config info. + */ +const board_uart_config_t *BOARD_GetDebugUart(void); + +/*! Init the debug UART */ +void BOARD_InitDebugConsole(void); + +/*! Init interrupt handlers */ +void BOARD_InitHandlers(void); + +/*! Init timers */ +void BOARD_InitTimers(void); + +/*! Init serial buses */ +void BOARD_InitSerialBus(void); + +/*! + * Board-level prepare for system sleep entry + * + * @param sleepMode Sleep mode being entered. + * @param sleepFlags Sleep flag options. + */ +void BOARD_SystemSleepPrepare(uint32_t sleepMode, uint32_t sleepFlags); + +/*! + * Board-level system sleep entry + * + * @param sleepMode Sleep mode being entered. + * @param sleepFlags Sleep flag options. + */ +void BOARD_SystemSleepEnter(uint32_t sleepMode, uint32_t sleepFlags); + +/*! + * Board-level system sleep exit + * + * @param sleepMode Sleep mode being exited. + * @param sleepFlags Sleep flag options. + */ +void BOARD_SystemSleepExit(uint32_t sleepMode, uint32_t sleepFlags); + +/*! + * Board-level unprepare for system sleep entry + * + * @param sleepMode Sleep mode being entered. + * @param sleepFlags Sleep flag options. + */ +void BOARD_SystemSleepUnprepare(uint32_t sleepMode, uint32_t sleepFlags); + +/*! + * Set the watchdog mode + * + * @param mode Mode to set. + */ +void BOARD_WdogModeSet(uint32_t mode); + +/*! Service the watchdog */ +void BOARD_WdogRefresh(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/** @} */ + +#endif /* BOARD_H */ + diff --git a/boards/tdx-verdin-imx95/pin_mux.c b/boards/tdx-verdin-imx95/pin_mux.c new file mode 100755 index 0000000..797150c --- /dev/null +++ b/boards/tdx-verdin-imx95/pin_mux.c @@ -0,0 +1,54 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pin_mux.h" +#include "board.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) +{ +#if (BOARD_DEBUG_UART_INSTANCE == 1U) + /* Configure LPUART 1 */ + IOMUXC_SetPinMux(IOMUXC_PAD_UART1_RXD__LPUART1_RX, 0U); + IOMUXC_SetPinConfig(IOMUXC_PAD_UART1_RXD__LPUART1_RX, IOMUXC_PAD_PD(1U)); + + IOMUXC_SetPinMux(IOMUXC_PAD_UART1_TXD__LPUART1_TX, 0); + IOMUXC_SetPinConfig(IOMUXC_PAD_UART1_TXD__LPUART1_TX, IOMUXC_PAD_DSE(0xFU)); +#elif (BOARD_DEBUG_UART_INSTANCE == 2U) + /* Configure LPUART 2 */ + IOMUXC_SetPinMux(IOMUXC_PAD_UART2_RXD__LPUART2_RX, 0); + IOMUXC_SetPinConfig(IOMUXC_PAD_UART2_RXD__LPUART2_RX, IOMUXC_PAD_PD(1U)); + + IOMUXC_SetPinMux(IOMUXC_PAD_UART2_TXD__LPUART2_TX, 0); + IOMUXC_SetPinConfig(IOMUXC_PAD_UART2_TXD__LPUART2_TX, IOMUXC_PAD_DSE(0xFU)); +#endif + +#if (BOARD_I2C_INSTANCE == 1U) + /* Configure LPI2C 1 */ + IOMUXC_SetPinMux(IOMUXC_PAD_I2C1_SCL__LPI2C1_SCL, 1U); + IOMUXC_SetPinConfig(IOMUXC_PAD_I2C1_SCL__LPI2C1_SCL, IOMUXC_PAD_DSE(0xFU) + | IOMUXC_PAD_FSEL1(0x3U) | IOMUXC_PAD_PU(0x1U) | IOMUXC_PAD_OD(0x1U)); + + IOMUXC_SetPinMux(IOMUXC_PAD_I2C1_SDA__LPI2C1_SDA, 1U); + IOMUXC_SetPinConfig(IOMUXC_PAD_I2C1_SDA__LPI2C1_SDA, IOMUXC_PAD_DSE(0xFU) + | IOMUXC_PAD_FSEL1(0x3U) | IOMUXC_PAD_PU(0x1U) | IOMUXC_PAD_OD(0x1U)); +#elif (BOARD_I2C_INSTANCE == 2U) + /* Configure LPI2C 2 */ + IOMUXC_SetPinMux(IOMUXC_PAD_I2C2_SCL__LPI2C2_SCL, 1U); + IOMUXC_SetPinConfig(IOMUXC_PAD_I2C2_SCL__LPI2C2_SCL, IOMUXC_PAD_DSE(0xFU) + | IOMUXC_PAD_FSEL1(0x3U) | IOMUXC_PAD_PU(0x1U) | IOMUXC_PAD_OD(0x1U)); + + IOMUXC_SetPinMux(IOMUXC_PAD_I2C2_SDA__LPI2C2_SDA, 1U); + IOMUXC_SetPinConfig(IOMUXC_PAD_I2C2_SDA__LPI2C2_SDA, IOMUXC_PAD_DSE(0xFU) + | IOMUXC_PAD_FSEL1(0x3U) | IOMUXC_PAD_PU(0x1U) | IOMUXC_PAD_OD(0x1U)); +#endif +} + diff --git a/boards/tdx-verdin-imx95/pin_mux.h b/boards/tdx-verdin-imx95/pin_mux.h new file mode 100755 index 0000000..4b5940b --- /dev/null +++ b/boards/tdx-verdin-imx95/pin_mux.h @@ -0,0 +1,44 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PIN_MUX_H +#define PIN_MUX_H + +#include "fsl_iomuxc.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup BRD_SM_TDXVERDINIMX95 + * @file + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M33[cm33] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* PIN_MUX_H */ + diff --git a/boards/tdx-verdin-imx95/sm/Makefile b/boards/tdx-verdin-imx95/sm/Makefile new file mode 100755 index 0000000..9d7c28f --- /dev/null +++ b/boards/tdx-verdin-imx95/sm/Makefile @@ -0,0 +1,63 @@ +## ################################################################### +## +## Copyright 2023 NXP +## +## Redistribution and use in source and binary forms, with or without modification, +## are permitted provided that the following conditions are met: +## +## o Redistributions of source code must retain the above copyright notice, this list +## of conditions and the following disclaimer. +## +## o Redistributions in binary form must reproduce the above copyright notice, this +## list of conditions and the following disclaimer in the documentation and/or +## other materials provided with the distribution. +## +## o Neither the name of the copyright holder nor the names of its +## contributors may be used to endorse or promote products derived from this +## software without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +## WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +## ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +## (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +## ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +## (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +## SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +## +## +## ################################################################### + +BOARD ?= tdx-verdin-imx95 +BRD_SM_API_DIR = $(ROOT_DIR)/sm/brd +BOARDS_DIR = $(ROOT_DIR)/boards +BOARD_DIR = $(BOARDS_DIR)/$(BOARD) + +INCLUDE += \ + -I$(BRD_SM_API_DIR) \ + -I$(BOARDS_DIR) \ + -I$(BOARD_DIR) \ + -I$(BOARD_DIR)/sm \ + -I$(COMPONENTS_DIR)/pf09 \ + -I$(COMPONENTS_DIR)/pf53 + +VPATH += \ + $(BRD_SM_API_DIR) \ + $(BOARDS_DIR) \ + $(BOARD_DIR) \ + $(BOARD_DIR)/sm \ + $(COMPONENTS_DIR)/pf09 \ + $(COMPONENTS_DIR)/pf53 + +OBJS += \ + $(OUT)/board.o \ + $(OUT)/brd_sm.o \ + $(OUT)/brd_sm_handlers.o \ + $(OUT)/brd_sm_control.o \ + $(OUT)/brd_sm_sensor.o \ + $(OUT)/brd_sm_voltage.o \ + $(OUT)/fsl_pf09.o \ + $(OUT)/fsl_pf53.o + diff --git a/boards/tdx-verdin-imx95/sm/brd_sm.c b/boards/tdx-verdin-imx95/sm/brd_sm.c new file mode 100755 index 0000000..5d60d1e --- /dev/null +++ b/boards/tdx-verdin-imx95/sm/brd_sm.c @@ -0,0 +1,686 @@ +/* +** ################################################################### +** +** Copyright 2023-2024 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/* File containing the implementation of the SM abstraction for the board. */ +/*==========================================================================*/ + +/* Includes */ + +#include "sm.h" +#include "brd_sm.h" +#include "dev_sm.h" +#include "lmm.h" +#include "fsl_lpi2c.h" +#include "fsl_bbnsm.h" +#include "fsl_rgpio.h" +#include "fsl_iomuxc.h" + +/* Local defines */ + +#define BRD_SM_RST_REC_FIRST 4U /* First GPR for shutdown record */ +#define BRD_SM_RST_REC_NUM 4U /* Number of GPR for shutdown record */ + +/* Defines to encode the reason */ +#define BRD_SM_REC_REASON_MASK (0x000000FFU) +#define BRD_SM_REC_REASON_SHIFT (0U) +#define BRD_SM_REC_REASON(x) \ + (((uint32_t)(((uint32_t)(x)) << BRD_SM_REC_REASON_SHIFT)) & \ + BRD_SM_REC_REASON_MASK) + +/* Defines to encode the error ID */ +#define BRD_SM_REC_EID_MASK (0x007FFF00U) +#define BRD_SM_REC_EID_SHIFT (8U) +#define BRD_SM_REC_EID(x) \ + (((uint32_t)(((uint32_t)(x)) << BRD_SM_REC_EID_SHIFT)) & \ + BRD_SM_REC_EID_MASK) +#define BRD_SM_REC_EID_SIGN (0x00004000U) +#define BRD_SM_REC_EID_EXT (0xFFFF8000U) + +/* Defines to encode the valid flag for the errId */ +#define BRD_SM_REC_VERR_MASK (0x00800000U) +#define BRD_SM_REC_VERR_SHIFT (23U) +#define BRD_SM_REC_VERR(x) \ + (((uint32_t)(((uint32_t)(x)) << BRD_SM_REC_VERR_SHIFT)) & \ + BRD_SM_REC_VERR_MASK) + +/* Defines to encode the source/origin */ +#define BRD_SM_REC_SRC_MASK (0x0F000000U) +#define BRD_SM_REC_SRC_SHIFT (24U) +#define BRD_SM_REC_SRC(x) \ + (((uint32_t)(((uint32_t)(x)) << BRD_SM_REC_SRC_SHIFT)) & \ + BRD_SM_REC_SRC_MASK) + +/* Defines to encode the valid flag for the source */ +#define BRD_SM_REC_VSRC_MASK (0x10000000U) +#define BRD_SM_REC_VSRC_SHIFT (28U) +#define BRD_SM_REC_VSRC(x) \ + (((uint32_t)(((uint32_t)(x)) << BRD_SM_REC_VSRC_SHIFT)) & \ + BRD_SM_REC_VSRC_MASK) + +/* Defines to encode the extended info length */ +#define BRD_SM_REC_LEN_MASK (0x60000000U) +#define BRD_SM_REC_LEN_SHIFT (29U) +#define BRD_SM_REC_LEN(x) \ + (((uint32_t)(((uint32_t)(x)) << BRD_SM_REC_LEN_SHIFT)) & \ + BRD_SM_REC_LEN_MASK) + +/* Defines to encode the valid */ +#define BRD_SM_REC_VLD_MASK (0x80000000U) +#define BRD_SM_REC_VLD_SHIFT (31U) +#define BRD_SM_REC_VLD(x) \ + (((uint32_t)(((uint32_t)(x)) << BRD_SM_REC_VLD_SHIFT)) & \ + BRD_SM_REC_VLD_MASK) + +/* Performance parameters */ +#define BOARD_PERF_LEVEL DEV_SM_PERF_LVL_ODV /* Target perf level */ +#define BOARD_PERF_VDROP 20000 /* Perf voltage drop */ +#if BOARD_VOLT_SOC >= ES_ODV_UV_VDD_SOC +#define BOARD_BOOT_LEVEL DEV_SM_PERF_LVL_ODV /* Boot perf overdrive */ +#elif BOARD_VOLT_SOC >= ES_NOM_UV_VDD_SOC +#define BOARD_BOOT_LEVEL DEV_SM_PERF_LVL_NOM /* Boot perf nominal */ +#else +#define BOARD_BOOT_LEVEL DEV_SM_PERF_LVL_LOW /* Boot perf low */ +#endif + +/* Defines to encode the GPIO1 access protection */ +#define GPIO_PCNS_I2C_GP_CK RGPIO_PCNS_NSE2_MASK +#define GPIO_PCNS_I2C_GP_DAT RGPIO_PCNS_NSE3_MASK +#define GPIO_PCNS_PMIC_RTC_IRQ_N RGPIO_PCNS_NSE10_MASK +#define GPIO_PCNS_EC_MCU_INT RGPIO_PCNS_NSE11_MASK +#define GPIO_PCNS_CTRL_IO_EXP_INT_B RGPIO_PCNS_NSE14_MASK + +#define GPIO_PCNP_I2C_GP_CK RGPIO_PCNP_NSE2_MASK +#define GPIO_PCNP_I2C_GP_DAT RGPIO_PCNP_NSE3_MASK +#define GPIO_PCNP_PMIC_RTC_IRQ_N RGPIO_PCNP_NPE10_MASK +#define GPIO_PCNP_EC_MCU_INT RGPIO_PCNP_NPE11_MASK +#define GPIO_PCNP_CTRL_IO_EXP_INT_B RGPIO_PCNP_NPE14_MASK + +/* Local types */ + +/* Local variables */ + +/* Local functions */ + +static int32_t BRD_SM_InitComplete(uint32_t mSel); + +/*--------------------------------------------------------------------------*/ +/* Init board */ +/*--------------------------------------------------------------------------*/ +// coverity[misra_c_2012_directive_4_6_violation:FALSE] +int32_t BRD_SM_Init(int argc, const char * const argv[], uint32_t *mSel) +{ + int32_t status; + uint64_t addr; + uint32_t ms; + uint32_t flags; + + /* Init board hardware */ + BOARD_InitHardware(); + + /* Get the boot mode select */ + if (DEV_SM_RomBootCpuGet(DEV_SM_CPU_M33P, &addr, &ms, &flags) + == SM_ERR_SUCCESS) + { + *mSel = ms; + } + + /* Initialize devices connected to serial buses (PMIC, IOExp, etc) */ + status = BRD_SM_SerialDevicesInit(); + + if (status == SM_ERR_SUCCESS) + { + /* Init the device */ + status = DEV_SM_Init(BOARD_BOOT_LEVEL, BOARD_PERF_LEVEL); + } + + if (status == SM_ERR_SUCCESS) + { + /* Complete board init after device init */ + status = BRD_SM_InitComplete(*mSel); + } + + if (status == SM_ERR_SUCCESS) + { + /* Disallow ANA TMPSNS to generate internal warm reset */ + SRC_GEN->SRMASK |= BIT32(RST_REASON_TEMPSENSE); + + /* Switch WDOG to FCCU mode */ + BOARD_WdogModeSet(BOARD_WDOG_MODE_FCCU); + } + + /* Configure non secure non privileged access to + * GPIO1 registers and interrupts + */ + GPIO1->PCNS = ( GPIO_PCNS_I2C_GP_CK | + GPIO_PCNS_I2C_GP_DAT | + GPIO_PCNS_PMIC_RTC_IRQ_N | + GPIO_PCNS_EC_MCU_INT | + GPIO_PCNS_CTRL_IO_EXP_INT_B); + GPIO1->ICNS = 1; + GPIO1->PCNP = ( GPIO_PCNS_I2C_GP_CK | + GPIO_PCNS_I2C_GP_DAT | + GPIO_PCNP_PMIC_RTC_IRQ_N | + GPIO_PCNP_EC_MCU_INT | + GPIO_PCNP_CTRL_IO_EXP_INT_B); + GPIO1->ICNP = 1; + + /* TODO: Remove when A0 support dropped */ + /* Configure ISO controls based on feature fuses */ + uint32_t ipIsoMask = 0U; + + /* Deassert PCIe ISO if corresponding module is enabled */ + uint32_t fuseHwCfg2 = FSB->FUSE[FSB_FUSE_HW_CFG2]; + + /* PCIe1 is tied to HSIO ISO[0] */ + if ((fuseHwCfg2 & FSB_FUSE_HW_CFG2_PCIE1_DISABLE_MASK) == 0U) + { + ipIsoMask |= SRC_XSPR_SLICE_SW_CTRL_ISO_CTRL_0_MASK; + } + + /* PCIe2 is tied to HSIO ISO[1] */ + if ((fuseHwCfg2 & FSB_FUSE_HW_CFG2_PCIE2_DISABLE_MASK) == 0U) + { + ipIsoMask |= SRC_XSPR_SLICE_SW_CTRL_ISO_CTRL_1_MASK; + } + + /* Apply ISO mask */ + if (ipIsoMask != 0U) + { + SRC_XSPR_HSIOMIX_TOP->SLICE_SW_CTRL &= (~ipIsoMask); + } + + /* Return status */ + return status; +} + +/*--------------------------------------------------------------------------*/ +/* Exit function */ +/*--------------------------------------------------------------------------*/ +void BRD_SM_Exit(int32_t status, uint32_t pc) +{ +#if defined(MONITOR) || defined(RUN_TEST) + printf("exit %d, 0x%08X\n", status, pc); + + /* Disable watchdog */ + BOARD_WdogModeSet(BOARD_WDOG_MODE_OFF); +#else + SM_SYSTEMERROR(status, pc); + // coverity[misra_c_2012_rule_2_2_violation:FALSE] + SystemExit(); +#endif + + /* Hang */ + // coverity[infinite_loop:FALSE] + while (true) + { + ; /* Intentional empty while */ + } +} + +/*--------------------------------------------------------------------------*/ +/* Board timer tick */ +/*--------------------------------------------------------------------------*/ +void BRD_SM_TimerTick(uint32_t msec) +{ + /* Kick the dog */ + BOARD_WdogRefresh(); +} + +/*--------------------------------------------------------------------------*/ +/* Custom monitor function */ +/*--------------------------------------------------------------------------*/ +int32_t BRD_SM_Custom(int32_t argc, const char * const argv[]) +{ + return SM_ERR_SUCCESS; +} + +/*--------------------------------------------------------------------------*/ +/* Get fault reaction */ +/*--------------------------------------------------------------------------*/ +int32_t BRD_SM_FaultReactionGet(dev_sm_rst_rec_t resetRec, + // coverity[misra_c_2012_rule_8_13_violation:FALSE] + uint32_t *reaction, uint32_t *lm) +{ + int32_t status = SM_ERR_SUCCESS; + + /* Print reaction */ + switch (*reaction) + { + case LMM_REACT_SYS_RESET: + case LMM_REACT_SYS_SHUTDOWN: + ; /* Intentional empty as will print elsewhere */ + break; + case LMM_REACT_GRP_RESET: + printf("\nReset group %u", *lm); + BRD_SM_ResetRecordPrint(",", resetRec); + break; + case LMM_REACT_GRP_SHUTDOWN: + printf("\nShutdown group %u", *lm); + BRD_SM_ResetRecordPrint(",", resetRec); + break; + case LMM_REACT_LM_RESET: + printf("\nReset LM %u", *lm); + BRD_SM_ResetRecordPrint(",", resetRec); + break; + case LMM_REACT_LM_SHUTDOWN: + printf("\nShutdown LM %u", *lm); + BRD_SM_ResetRecordPrint(",", resetRec); + break; + case LMM_REACT_BOARD: + printf("\nBoard %u", *lm); + BRD_SM_ResetRecordPrint(",", resetRec); + break; + case LMM_REACT_FUSA: + printf("\nFuSa %u", *lm); + BRD_SM_ResetRecordPrint(",", resetRec); + break; + case LMM_REACT_NONE: + ; /* Intentional empty case */ + break; + default: + status = SM_ERR_INVALID_PARAMETERS; + break; + } + + /* Return status */ + return status; +} + +/*--------------------------------------------------------------------------*/ +/* Custom fault handler */ +/*--------------------------------------------------------------------------*/ +int32_t BRD_SM_CustomFault(dev_sm_rst_rec_t resetRec, uint32_t lm) +{ + /* Return status */ + return SM_ERR_SUCCESS; +} + +/*--------------------------------------------------------------------------*/ +/* Print reset record */ +/*--------------------------------------------------------------------------*/ +void BRD_SM_ResetRecordPrint(string name, dev_sm_rst_rec_t resetRec) +{ + if (resetRec.valid) + { + int32_t status; + string reasonNameAddr; + + /* Get name */ + status = LMM_SystemReasonNameGet(0U, resetRec.reason, + &reasonNameAddr, NULL); + + /* Print reason */ + printf("%s reason=", name); + if (status == SM_ERR_SUCCESS) + { + printf("%s", reasonNameAddr); + } + else + { + printf("%u", resetRec.reason); + } + if (resetRec.validErr) + { + printf(", errId=%d", (int32_t) resetRec.errId); + } + if (resetRec.validOrigin) + { + printf(", srcLm=%u", resetRec.origin); + } + printf("\n"); + + /* Print extended info */ + for (uint32_t ex = 0U; ex < resetRec.extLen; ex++) + { + printf(" 0x%08X\n", resetRec.extInfo[ex]); + } + } +} + +/*--------------------------------------------------------------------------*/ +/* Load and clear persistent shutdown record of previous boot */ +/*--------------------------------------------------------------------------*/ +void BRD_SM_ShutdownRecordLoad(dev_sm_rst_rec_t *shutdownRec) +{ +#if BRD_SM_RST_REC_NUM > 0 + uint32_t hdr = 0U; + uint32_t *ePtr = &(shutdownRec->extInfo[0]); + + /* Read and clear header */ + (void) BBNSM_GprGetValue(BBNSM, BRD_SM_RST_REC_FIRST, &hdr); + (void) BBNSM_GprSetValue(BBNSM, BRD_SM_RST_REC_FIRST, 0U); + + /* Valid? */ + if (((hdr & BRD_SM_REC_VLD_MASK ) >> BRD_SM_REC_VLD_SHIFT) != 0U) + { + shutdownRec->valid = true; + + /* Parse header */ + shutdownRec->reason = (hdr & BRD_SM_REC_REASON_MASK ) >> + BRD_SM_REC_REASON_SHIFT; + shutdownRec->errId = (hdr & BRD_SM_REC_EID_MASK ) >> + BRD_SM_REC_EID_SHIFT; + shutdownRec->validErr = ((hdr & BRD_SM_REC_VERR_MASK ) != 0U); + shutdownRec->origin = (hdr & BRD_SM_REC_SRC_MASK ) >> + BRD_SM_REC_SRC_SHIFT; + shutdownRec->validOrigin = ((hdr & BRD_SM_REC_VSRC_MASK ) != 0U); + shutdownRec->extLen = (hdr & BRD_SM_REC_LEN_MASK ) >> + BRD_SM_REC_LEN_SHIFT; + + /* Sign extend */ + if ((shutdownRec->errId & BRD_SM_REC_EID_SIGN) != 0U) + { + shutdownRec->errId |= BRD_SM_REC_EID_EXT; + } + + shutdownRec->extLen = MIN(shutdownRec->extLen, DEV_SM_NUM_EXT_INFO); + } + + /* Copy out extended info */ + for (uint8_t idx = 1U; idx < BRD_SM_RST_REC_NUM; idx++) + { + if (idx <= shutdownRec->extLen) + { + (void) BBNSM_GprGetValue(BBNSM, idx + BRD_SM_RST_REC_FIRST, + ePtr); + ePtr++; + } + else + { + break; + } + } +#endif + + /* PMIC reset? */ + if ((g_pmicFaultFlags & ~PF09_XRESET_FLG) != 0U) + { + shutdownRec->valid = true; + shutdownRec->reset = true; + shutdownRec->reason = DEV_SM_REASON_PMIC; + shutdownRec->extLen = 1U; + shutdownRec->extInfo[0] = g_pmicFaultFlags; + } +} + +/*--------------------------------------------------------------------------*/ +/* Save shutdown record to persistent storage */ +/*--------------------------------------------------------------------------*/ +void BRD_SM_ShutdownRecordSave(dev_sm_rst_rec_t shutdownRec) +{ +#if BRD_SM_RST_REC_NUM > 0 + uint32_t hdr; + const uint32_t *ePtr = &(shutdownRec.extInfo[0]); + + /* Store extended info */ + for (uint8_t idx = 1U; idx < BRD_SM_RST_REC_NUM; idx++) + { + if (idx <= shutdownRec.extLen) + { + (void) BBNSM_GprSetValue(BBNSM, idx + BRD_SM_RST_REC_FIRST, + *ePtr); + ePtr++; + } + else + { + break; + } + } + + /* Create header */ + hdr = BRD_SM_REC_REASON(shutdownRec.reason) + | BRD_SM_REC_EID(shutdownRec.errId) + | BRD_SM_REC_VERR(shutdownRec.validErr ? 1U : 0U) + | BRD_SM_REC_SRC(shutdownRec.origin) + | BRD_SM_REC_VSRC(shutdownRec.validOrigin ? 1U : 0U) + | BRD_SM_REC_LEN(shutdownRec.extLen) + | BRD_SM_REC_VLD(shutdownRec.valid ? 1U : 0U); + + /* Save header */ + (void) BBNSM_GprSetValue(BBNSM, BRD_SM_RST_REC_FIRST, hdr); +#endif + + /* Print shutdown record */ + if (shutdownRec.reset) + { + BRD_SM_ResetRecordPrint("\nReset request:", shutdownRec); + } + else + { + BRD_SM_ResetRecordPrint("\nShutdown request:", shutdownRec); + } +} + +/*--------------------------------------------------------------------------*/ +/* Reset board */ +/*--------------------------------------------------------------------------*/ +int32_t BRD_SM_SystemReset(void) +{ + int32_t status = SM_ERR_SUCCESS; + rgpio_pin_config_t gpioConfig = + { + kRGPIO_DigitalOutput, + 0U + }; + + /* Drive WDOG_ANY to reset PMIC */ + RGPIO_PinInit(GPIO1, 15U, &gpioConfig); + IOMUXC_SetPinMux(IOMUXC_PAD_WDOG_ANY__GPIO1_IO_BIT15, 0U); + + /* Wait for PMIC to react */ + SystemTimeDelay(1000U); + + /* Fall back to warm reset of the device */ + status = DEV_SM_SystemReset(); + + /* Return status */ + return status; +} + +/*--------------------------------------------------------------------------*/ +/* Get PMIC info */ +/*--------------------------------------------------------------------------*/ +int32_t BRD_SM_PmicInfoGet(uint32_t idx, uint8_t *devAddr, uint8_t **info, + uint8_t *len) +{ + int32_t status = SM_ERR_SUCCESS; + + /* Call PMIC driver to get info */ + switch (idx) + { + case 0U: + *devAddr = g_pf09Dev.devAddr; + if (!PF09_PmicInfoGet(&g_pf09Dev, info, len)) + { + status = SM_ERR_HARDWARE_ERROR; + } + break; + case 1U: + *devAddr = g_pf5301Dev.devAddr; + if (!PF53_PmicInfoGet(&g_pf5301Dev, info, len)) + { + status = SM_ERR_HARDWARE_ERROR; + } + break; + case 2U: + *devAddr = g_pf5302Dev.devAddr; + if (!PF53_PmicInfoGet(&g_pf5302Dev, info, len)) + { + status = SM_ERR_HARDWARE_ERROR; + } + break; + default: + status = SM_ERR_NOT_FOUND; + break; + } + + /* Return status */ + return status; +} + +/*--------------------------------------------------------------------------*/ +/* PMIC register write */ +/*--------------------------------------------------------------------------*/ +int32_t BRD_SM_PmicWrite(uint8_t devAddr, uint8_t regAddr, uint8_t val, + uint8_t mask) +{ + int32_t status = SM_ERR_SUCCESS; + + /* Call PF09 driver write data */ + if (devAddr == g_pf09Dev.devAddr) + { + if (!PF09_PmicWrite(&g_pf09Dev, regAddr, val, mask)) + { + status = SM_ERR_HARDWARE_ERROR; + } + } + /* Call PF5301 driver write data */ + else if (devAddr == g_pf5301Dev.devAddr) + { + if (!PF53_PmicWrite(&g_pf5301Dev, regAddr, val, mask)) + { + status = SM_ERR_HARDWARE_ERROR; + } + } + /* Call PF5302 driver write data */ + else if (devAddr == g_pf5302Dev.devAddr) + { + if (!PF53_PmicWrite(&g_pf5302Dev, regAddr, val, mask)) + { + status = SM_ERR_HARDWARE_ERROR; + } + } + /* Invalid device address */ + else + { + status = SM_ERR_NOT_FOUND; + } + + /* Return status */ + return status; +} + +/*--------------------------------------------------------------------------*/ +/* PMIC register read */ +/*--------------------------------------------------------------------------*/ +int32_t BRD_SM_PmicRead(uint8_t devAddr, uint8_t regAddr, uint8_t *val) +{ + int32_t status = SM_ERR_SUCCESS; + + /* Call PF09 driver read data */ + if (devAddr == g_pf09Dev.devAddr) + { + if (!PF09_PmicRead(&g_pf09Dev, regAddr, val)) + { + status = SM_ERR_HARDWARE_ERROR; + } + } + /* Call PF5301 driver read data */ + else if (devAddr == g_pf5301Dev.devAddr) + { + if (!PF53_PmicRead(&g_pf5301Dev, regAddr, val)) + { + status = SM_ERR_HARDWARE_ERROR; + } + } + /* Call PF5302 driver read data */ + else if (devAddr == g_pf5302Dev.devAddr) + { + if (!PF53_PmicRead(&g_pf5302Dev, regAddr, val)) + { + status = SM_ERR_HARDWARE_ERROR; + } + } + /* Invalid device address */ + else + { + status = SM_ERR_NOT_FOUND; + } + + /* Return status */ + return status; +} + +/*--------------------------------------------------------------------------*/ +/* Set mode of specified SoC supply */ +/*--------------------------------------------------------------------------*/ +int32_t BRD_SM_SupplyModeSet(uint32_t domain, uint8_t voltMode) +{ + /* Set voltage mode */ + return BRD_SM_VoltageModeSet(domain, voltMode); +} + +/*--------------------------------------------------------------------------*/ +/* Get mode of specified SoC supply */ +/*--------------------------------------------------------------------------*/ +int32_t BRD_SM_SupplyModeGet(uint32_t domain, uint8_t *voltMode) +{ + /* Get voltage mode */ + return BRD_SM_VoltageModeGet(domain, voltMode); +} + +/*--------------------------------------------------------------------------*/ +/* Set voltage of specified SoC supply */ +/*--------------------------------------------------------------------------*/ +int32_t BRD_SM_SupplyLevelSet(uint32_t domain, uint32_t microVolt) +{ + /* Set voltage level */ + return BRD_SM_VoltageLevelSet(domain, ((int32_t) microVolt) + + BOARD_PERF_VDROP); +} + +/*--------------------------------------------------------------------------*/ +/* Get voltage of specified SoC supply */ +/*--------------------------------------------------------------------------*/ +int32_t BRD_SM_SupplyLevelGet(uint32_t domain, uint32_t *microVolt) +{ + /* Get voltage level */ + return BRD_SM_VoltageLevelGet(domain, (int32_t*) microVolt); +} + +/*==========================================================================*/ + +/*--------------------------------------------------------------------------*/ +/* Complete init after DEV_SM init */ +/*--------------------------------------------------------------------------*/ +static int32_t BRD_SM_InitComplete(uint32_t mSel) +{ + /* Safe to call DEV_SM functions to init hardware. For example, to + enabled a power domain, configure a clock SSC, clock rate, or pin. + Not safe to call LMM functions! */ + + return SM_ERR_SUCCESS; +} + diff --git a/boards/tdx-verdin-imx95/sm/brd_sm.dox b/boards/tdx-verdin-imx95/sm/brd_sm.dox new file mode 100755 index 0000000..2101f47 --- /dev/null +++ b/boards/tdx-verdin-imx95/sm/brd_sm.dox @@ -0,0 +1,55 @@ +/* +** ################################################################### +** +** Copyright 2023 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*! + * @addtogroup BRD_SM + * @{ + */ + +/*! + +@defgroup BRD_SM_TDXVERDINIMX95 BOARD_TDXVERDINIMX95: Toradex Verdin iMX95 SM Implementation + +@brief Module for the Toradex Verdin iMX95 for the SM. + +Board Module +============ + +This port supports i.MX95 on Toradex Verdin iMX95. See +the @ref PORT_MX95_EVK section for more information. + +*/ + +/** @} */ + diff --git a/boards/tdx-verdin-imx95/sm/brd_sm.h b/boards/tdx-verdin-imx95/sm/brd_sm.h new file mode 100755 index 0000000..5a22d61 --- /dev/null +++ b/boards/tdx-verdin-imx95/sm/brd_sm.h @@ -0,0 +1,96 @@ +/* +** ################################################################### +** +** Copyright 2023-2024 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +#ifndef BRD_SM_H +#define BRD_SM_H + +/*==========================================================================*/ +/*! + * @addtogroup BRD_SM_TDXVERDINIMX95 + * @{ + * + * @file + * @brief + * + * Header file containing the API for the SM abstraction of the board. + */ +/*==========================================================================*/ + +/* Includes */ + +#include "sm.h" +#include "brd_sm_handlers.h" +#include "brd_sm_control.h" +#include "brd_sm_sensor.h" +#include "brd_sm_voltage.h" +#include "board.h" +#include "brd_sm_api.h" + +/* Defines */ + +/*! Board name string */ +#define BRD_SM_NAME "Toradex Verdin iMX95" + +/*! Board attributes */ +#define BRD_SM_ATTR 0x0 + +/*! + * @name Board redirection defines + * @{ + */ +#define SM_SYSTEMRESET BRD_SM_SystemReset /*!< Reset */ +/** @} */ + +/* Types */ + +/* External variables */ + +/* Functions */ + +/*! + * Reset the system. + * + * Redirect to just spin. + * + * @return Returns the status (::SM_ERR_SUCCESS = success). + * + * Return errors (see @ref STATUS "SM error codes"): + * - ::SM_ERR_SUCCESS + */ +int32_t BRD_SM_SystemReset(void); + +/** @} */ + +#endif /* BRD_SM_H */ + diff --git a/boards/tdx-verdin-imx95/sm/brd_sm_control.c b/boards/tdx-verdin-imx95/sm/brd_sm_control.c new file mode 100755 index 0000000..dabb349 --- /dev/null +++ b/boards/tdx-verdin-imx95/sm/brd_sm_control.c @@ -0,0 +1,155 @@ +/* +** ################################################################### +** +** Copyright 2023-2024 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/* File containing the implementation of the board controls. */ +/*==========================================================================*/ + +/* Includes */ + +#include "sm.h" +#include "brd_sm.h" +#include "lmm.h" + +/* Local defines */ + +/* Local types */ + +/* Local variables */ + +/*--------------------------------------------------------------------------*/ +/* Set a control value */ +/*--------------------------------------------------------------------------*/ +int32_t BRD_SM_ControlSet(uint32_t ctrlId, uint32_t numVal, + const uint32_t *val) +{ + int32_t status = SM_ERR_SUCCESS; + + /* Check to see if ctrlId is within bounds*/ + if (ctrlId < SM_NUM_CTRL) + { + /* Check if device or board */ + if (ctrlId < DEV_SM_NUM_CTRL) + { + status = DEV_SM_ControlSet(ctrlId, numVal, val); + } + else if (ctrlId == BRD_SM_CTRL_TEST) + { + /* Test response to an reported SM error */ + SM_Error(SM_ERR_GENERIC_ERROR); + } + else + { + status = SM_ERR_NOT_SUPPORTED; + } + } + else + { + status = SM_ERR_NOT_FOUND; + } + + /* Return status */ + return status; +} + +/*--------------------------------------------------------------------------*/ +/* Get a control value */ +/*--------------------------------------------------------------------------*/ +int32_t BRD_SM_ControlGet(uint32_t ctrlId, uint32_t *numRtn, uint32_t *rtn) +{ + if (ctrlId < DEV_SM_NUM_CTRL) + return DEV_SM_ControlGet(ctrlId, numRtn, rtn); + + return SM_ERR_NOT_FOUND; +} + +/*--------------------------------------------------------------------------*/ +/* Set an extended control value */ +/*--------------------------------------------------------------------------*/ +int32_t BRD_SM_ControlExtSet(uint32_t ctrlId, uint32_t addr, + uint32_t numVal, const uint32_t *val) +{ + int32_t status = SM_ERR_SUCCESS; + + /* Check to see if ctrlId is within bounds*/ + if (ctrlId < SM_NUM_CTRL) + { + /* Check if device or board */ + if (ctrlId < DEV_SM_NUM_CTRL) + { + status = DEV_SM_ControlExtSet(ctrlId, addr, numVal, val); + } + else + { + status = SM_ERR_NOT_SUPPORTED; + } + } + else + { + status = SM_ERR_NOT_FOUND; + } + + /* Return status */ + return status; +} + +/*--------------------------------------------------------------------------*/ +/* Get an extended control value */ +/*--------------------------------------------------------------------------*/ +int32_t BRD_SM_ControlExtGet(uint32_t ctrlId, uint32_t addr, + uint32_t numRtn, uint32_t *rtn) +{ + int32_t status = SM_ERR_SUCCESS; + + /* Check to see if ctrlId is within bounds*/ + if (ctrlId < SM_NUM_CTRL) + { + /* Check if device or board */ + if (ctrlId < DEV_SM_NUM_CTRL) + { + status = DEV_SM_ControlExtGet(ctrlId, addr, numRtn, rtn); + } + else + { + status = SM_ERR_NOT_SUPPORTED; + } + } + else + { + status = SM_ERR_NOT_FOUND; + } + + /* Return status */ + return status; +} diff --git a/boards/tdx-verdin-imx95/sm/brd_sm_control.h b/boards/tdx-verdin-imx95/sm/brd_sm_control.h new file mode 100755 index 0000000..fcb3390 --- /dev/null +++ b/boards/tdx-verdin-imx95/sm/brd_sm_control.h @@ -0,0 +1,172 @@ +/* +** ################################################################### +** +** Copyright 2023-2024 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @addtogroup BRD_SM_TDXVERDINIMX95 + * @{ + * + * @file + * @brief + * + * Header file containing the SM API for the board controls. + */ +/*==========================================================================*/ + +#ifndef BRD_SM_CONTROL_H +#define BRD_SM_CONTROL_H + +/* Includes */ + +#include "sm.h" +#include "dev_sm.h" + +/* Defines */ + +/*! + * @name Board redirection defines + * @{ + */ +#define SM_CONTROLSET BRD_SM_ControlSet /*!< Control set */ +#define SM_CONTROLGET BRD_SM_ControlGet /*!< Control get */ +#define SM_CONTROLEXTSET BRD_SM_ControlExtSet /*!< Extended control set */ +#define SM_CONTROLEXTGET BRD_SM_ControlExtGet /*!< Extended control get */ +#define SM_CONTROLFLAGSSET DEV_SM_ControlFlagsSet /*!< Control flags */ +/** @} */ + +/*! Number of board controls */ +#define BRD_SM_NUM_CTRL 1UL + +/*! Total number of controls */ +#define SM_NUM_CTRL (DEV_SM_NUM_CTRL + BRD_SM_NUM_CTRL) + +/*! + * @name BRD_SM control domain indexes + */ +/** @{ */ +#define BRD_SM_CTRL_TEST (DEV_SM_NUM_CTRL + 0U) /*!< Test */ +/** @} */ + +/* Types */ + +/* Functions */ + +/*! + * @name Board control functions + * @{ + */ + +/*! + * Set a board control value. + * + * @param[in] ctrlId Index of control to write + * @param[in] numVal Number of array elements + * @param[in] val Pointer to array of values to set + * + * This function allows a caller to write an array of values for + * a control. + * + * @return Returns the status (::SM_ERR_SUCCESS = success). + * + * Return errors (see @ref STATUS "SM error codes"): + * - ::SM_ERR_NOT_FOUND: if ctrlId is not valid. + */ +int32_t BRD_SM_ControlSet(uint32_t ctrlId, uint32_t numVal, + const uint32_t *val); + +/*! + * Get a board control value. + * + * @param[in] ctrlId Index of control to read + * @param[out] numRtn Return pointer to number of array elements + * @param[out] rtn Pointer to array to store return + * + * This function allows a caller to read an array of values for + * a control. + * + * @return Returns the status (::SM_ERR_SUCCESS = success). + * + * Return errors (see @ref STATUS "SM error codes"): + * - ::SM_ERR_NOT_FOUND: if ctrlId is not valid. + */ +int32_t BRD_SM_ControlGet(uint32_t ctrlId, uint32_t *numRtn, uint32_t *rtn); + +/*! + * Set an extended board control value. + * + * @param[in] ctrlId Index of control to write + * @param[in] addr Address of write + * @param[in] numVal Number of array elements + * @param[in] val Pointer to array of values to set + * + * This function allows a caller to write an array of values for + * a control. Extra parameters allow this write to be more complex + * such as to an I2C. + * + * @return Returns the status (::SM_ERR_SUCCESS = success). + * + * Return errors (see @ref STATUS "SM error codes"): + * - ::SM_ERR_NOT_FOUND: if ctrlId is not valid. + * - ::SM_ERR_INVALID_PARAMETERS: if addr or numVal are not valid. + */ +int32_t BRD_SM_ControlExtSet(uint32_t ctrlId, uint32_t addr, + uint32_t numVal, const uint32_t *val); + +/*! + * Get an extended board control value. + * + * @param[in] ctrlId Index of control to read + * @param[in] addr Address of read + * @param[in] numRtn Number of array elements + * @param[out] rtn Pointer to array to store return + * + * This function allows a caller to read an array of values for + * a control. Extra parameters allow this read to be more complex + * such as from an I2C. + * + * @return Returns the status (::SM_ERR_SUCCESS = success). + * + * Return errors (see @ref STATUS "SM error codes"): + * - ::SM_ERR_NOT_FOUND: if ctrlId is not valid. + * - ::SM_ERR_INVALID_PARAMETERS: if addr or numRtn are not valid. + */ +int32_t BRD_SM_ControlExtGet(uint32_t ctrlId, uint32_t addr, + uint32_t numRtn, uint32_t *rtn); + +/** @} */ + +#endif /* BRD_SM_CONTROL_H */ + +/** @} */ + diff --git a/boards/tdx-verdin-imx95/sm/brd_sm_handlers.c b/boards/tdx-verdin-imx95/sm/brd_sm_handlers.c new file mode 100755 index 0000000..0840103 --- /dev/null +++ b/boards/tdx-verdin-imx95/sm/brd_sm_handlers.c @@ -0,0 +1,215 @@ +/* +** ################################################################### +** +** Copyright 2023-2024 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/* File containing the implementation of the handlers for the board. */ +/*==========================================================================*/ + +/* Includes */ + +#include "sm.h" +#include "brd_sm.h" +#include "dev_sm.h" +#include "fsl_lpi2c.h" +#include "fsl_rgpio.h" + +/* Local defines */ + +/* I2C device addresses */ +#define BOARD_PF09_DEV_ADDR 0x08U +#define BOARD_PF5301_DEV_ADDR 0x2AU +#define BOARD_PF5302_DEV_ADDR 0x29U + +/* Local types */ + +/* Local variables */ + +/* Global variables */ + +PF09_Type g_pf09Dev; +PF53_Type g_pf5301Dev; +PF53_Type g_pf5302Dev; + +uint32_t g_pmicFaultFlags = 0U; + +/* Local functions */ + +static void BRD_SM_Pf09Handler(void); + +/*--------------------------------------------------------------------------*/ +/* Init serial devices */ +/*--------------------------------------------------------------------------*/ +int32_t BRD_SM_SerialDevicesInit(void) +{ + int32_t status = SM_ERR_SUCCESS; + LPI2C_Type *const s_i2cBases[] = LPI2C_BASE_PTRS; + + /* Fill in PF09 PMIC handle */ + g_pf09Dev.i2cBase = s_i2cBases[BOARD_I2C_INSTANCE]; + g_pf09Dev.devAddr = BOARD_PF09_DEV_ADDR; + g_pf09Dev.crcEn = true; + + /* Inialize PF09 PMIC */ + if (!PF09_Init(&g_pf09Dev)) + { + status = SM_ERR_HARDWARE_ERROR; + } + + /* Disable voltage monitor 1 */ + if (status == SM_ERR_SUCCESS) + { + if (!PF09_MonitorEnable(&g_pf09Dev, PF09_VMON1, false)) + { + status = SM_ERR_HARDWARE_ERROR; + } + } + + /* Disable voltage monitor 2 */ + if (status == SM_ERR_SUCCESS) + { + if (!PF09_MonitorEnable(&g_pf09Dev, PF09_VMON2, false)) + { + status = SM_ERR_HARDWARE_ERROR; + } + } + + /* Disable the PWRUP interrupt */ + if (status == SM_ERR_SUCCESS) + { + const uint8_t mask[PF09_MASK_LEN] = + { + [PF09_MASK_IDX_STATUS1] = 0x08U + }; + + if (!PF09_IntEnable(&g_pf09Dev, mask, PF09_MASK_LEN, false)) + { + status = SM_ERR_HARDWARE_ERROR; + } + } + + /* Change the LDO3 sequence */ + if (status == SM_ERR_SUCCESS) + { + if (!PF09_PmicWrite(&g_pf09Dev, 0x4AU, 0x1EU, 0xFFU)) + { + status = SM_ERR_HARDWARE_ERROR; + } + } + + /* Set the LDO3 OV bypass */ + if (status == SM_ERR_SUCCESS) + { + if (!PF09_PmicWrite(&g_pf09Dev, 0x7FU, 0xFCU, 0xFFU)) + { + status = SM_ERR_HARDWARE_ERROR; + } + } + + /* Set the OV debounce to 50us due to errata ER011/12 */ + if (status == SM_ERR_SUCCESS) + { + if (!PF09_PmicWrite(&g_pf09Dev, 0x37U, 0x94U, 0xFFU)) + { + status = SM_ERR_HARDWARE_ERROR; + } + } + + /* Save and clear any fault flags */ + if (status == SM_ERR_SUCCESS) + { + if (!PF09_FaultFlags(&g_pf09Dev, &g_pmicFaultFlags, true)) + { + status = SM_ERR_HARDWARE_ERROR; + } + } + + /* Handle any already pending PF09 interrupts */ + if (status == SM_ERR_SUCCESS) + { + BRD_SM_Pf09Handler(); + } + + if (status == SM_ERR_SUCCESS) + { + /* Fill in PF5301 PMIC handle */ + g_pf5301Dev.i2cBase = s_i2cBases[BOARD_I2C_INSTANCE]; + g_pf5301Dev.devAddr = BOARD_PF5301_DEV_ADDR; + + /* Inialize PF0901 PMIC */ + if (!PF53_Init(&g_pf5301Dev)) + { + status = SM_ERR_HARDWARE_ERROR; + } + + } + + if (status == SM_ERR_SUCCESS) + { + /* Fill in PF5302 PMIC handle */ + g_pf5302Dev.i2cBase = s_i2cBases[BOARD_I2C_INSTANCE]; + g_pf5302Dev.devAddr = BOARD_PF5302_DEV_ADDR; + + /* Inialize PF0901 PMIC */ + if (!PF53_Init(&g_pf5302Dev)) + { + status = SM_ERR_HARDWARE_ERROR; + } + } + + /* Return status */ + return status; +} + +/*==========================================================================*/ + +/*--------------------------------------------------------------------------*/ +/* PF09 handler */ +/*--------------------------------------------------------------------------*/ +static void BRD_SM_Pf09Handler(void) +{ + uint8_t stat[PF09_MASK_LEN] = { 0 }; + + /* Read status of interrupts */ + (void) PF09_IntStatus(&g_pf09Dev, stat, PF09_MASK_LEN); + + /* Clear pending */ + (void) PF09_IntClear(&g_pf09Dev, stat, PF09_MASK_LEN); + + /* Handle pending temp interrupts */ + if ((stat[PF09_MASK_IDX_STATUS2] & 0x0FU) != 0U) + { + BRD_SM_SensorHandler(); + } +} + diff --git a/boards/tdx-verdin-imx95/sm/brd_sm_handlers.h b/boards/tdx-verdin-imx95/sm/brd_sm_handlers.h new file mode 100755 index 0000000..937525c --- /dev/null +++ b/boards/tdx-verdin-imx95/sm/brd_sm_handlers.h @@ -0,0 +1,88 @@ +/* +** ################################################################### +** +** Copyright 2023-2024 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +#ifndef BRD_SM_HANDLERS_H +#define BRD_SM_HANDLERS_H + +/*==========================================================================*/ +/*! + * @addtogroup BRD_SM_TDXVERDINIMX95 + * @{ + * + * @file + * @brief + * + * Header file containing the implementation of interrupt handlers for the + * board. + */ +/*==========================================================================*/ + +/* Includes */ + +#include "sm.h" +#include "dev_sm.h" +#include "fsl_pf09.h" +#include "fsl_pf53.h" + +/* Defines */ + +/* Types */ + +/* External variables */ + +/*! Handle to access PF09 */ +extern PF09_Type g_pf09Dev; + +/*! Handle to access PF5301 */ +extern PF53_Type g_pf5301Dev; + +/*! Handle to access PF5302 */ +extern PF53_Type g_pf5302Dev; + +/*! Fault flags from the PMICs */ +extern uint32_t g_pmicFaultFlags; + +/* Functions */ + +/*! + * Init serial devices. + * + * @return Returns the status (::SM_ERR_SUCCESS = success). + */ +int32_t BRD_SM_SerialDevicesInit(void); + +/** @} */ + +#endif /* BRD_SM_HANDLERS_H */ + diff --git a/boards/tdx-verdin-imx95/sm/brd_sm_sensor.c b/boards/tdx-verdin-imx95/sm/brd_sm_sensor.c new file mode 100755 index 0000000..c6cf6bb --- /dev/null +++ b/boards/tdx-verdin-imx95/sm/brd_sm_sensor.c @@ -0,0 +1,367 @@ +/* +** ################################################################### +** +** Copyright 2023-2024 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/* File containing the implementation of the board sensors. */ +/*==========================================================================*/ + +/* Includes */ + +#include "sm.h" +#include "brd_sm.h" +#include "lmm.h" + +/* Local defines */ + +/* Local types */ + +/* Local variables */ + +static bool sensorEnb[BRD_SM_NUM_SENSOR]; + +/*--------------------------------------------------------------------------*/ +/* Return sensor name */ +/*--------------------------------------------------------------------------*/ +int32_t BRD_SM_SensorNameGet(uint32_t sensorId, string *sensorNameAddr, + int32_t *len) +{ + int32_t status = SM_ERR_SUCCESS; + static int32_t s_maxLen = 0; + + static string const s_name[BRD_SM_NUM_SENSOR] = + { + "temp_pf09", + "temp_pf53_soc", + "temp_pf53_arm" + }; + + /* Get max string width */ + DEV_SM_MaxStringGet(len, &s_maxLen, s_name, BRD_SM_NUM_SENSOR); + + /* Check to see if sensorId is within bounds*/ + if (sensorId < SM_NUM_SENSOR) + { + /* Check if device or board */ + if (sensorId < DEV_SM_NUM_SENSOR) + { + status = DEV_SM_SensorNameGet(sensorId, sensorNameAddr, len); + } + else + { + uint32_t brdSensorId = sensorId - DEV_SM_NUM_SENSOR; + + /* Return pointer to name */ + *sensorNameAddr = s_name[brdSensorId]; + } + } + else + { + status = SM_ERR_NOT_FOUND; + } + + /* Return status */ + return status; +} + +/*--------------------------------------------------------------------------*/ +/* Return sensor description */ +/*--------------------------------------------------------------------------*/ +int32_t BRD_SM_SensorDescribe(uint32_t sensorId, + dev_sm_sensor_desc_t *desc) +{ + int32_t status = SM_ERR_SUCCESS; + + /* Check to see if sensorId is within bounds*/ + if (sensorId < SM_NUM_SENSOR) + { + /* Check if device or board */ + if (sensorId < DEV_SM_NUM_SENSOR) + { + status = DEV_SM_SensorDescribe(sensorId, desc); + } + else + { + desc->sensorType = 2U; + desc->sensorExponent = 0; + desc->numTripPoints = 0U; + desc->timestampSupport = false; + desc->timestampExponent = 0; + + /* PF09? */ + if (sensorId == BRD_SM_SENSOR_TEMP_PF09) + { + desc->numTripPoints = 1U; + } + } + } + else + { + status = SM_ERR_NOT_FOUND; + } + + /* Return status */ + return status; +} + +/*--------------------------------------------------------------------------*/ +/* Get sensor reading */ +/*--------------------------------------------------------------------------*/ +int32_t BRD_SM_SensorReadingGet(uint32_t sensorId, int64_t *sensorValue, + uint64_t *sensorTimestamp) +{ + int32_t status = SM_ERR_SUCCESS; + + /* Check to see if sensorId is within bounds*/ + if (sensorId < SM_NUM_SENSOR) + { + /* Check if device or board */ + if (sensorId < DEV_SM_NUM_SENSOR) + { + status = DEV_SM_SensorReadingGet(sensorId, sensorValue, + sensorTimestamp); + } + else + { + uint32_t brdSensorId = sensorId - DEV_SM_NUM_SENSOR; + + /* Check if enabled */ + if (sensorEnb[brdSensorId]) + { + int32_t temp; + bool rc = false; + + /* Read sensor */ + switch (sensorId) + { + case BRD_SM_SENSOR_TEMP_PF09: + rc = PF09_TempGet(&g_pf09Dev, &temp); + break; + case BRD_SM_SENSOR_TEMP_PF5301: + rc = PF53_TempGet(&g_pf5301Dev, &temp); + break; + default: + rc = PF53_TempGet(&g_pf5302Dev, &temp); + break; + } + + if (rc) + { + *sensorValue = (int64_t) temp; + *sensorTimestamp = 0ULL; + } + else + { + status = SM_ERR_HARDWARE_ERROR; + } + } + else + { + status = SM_ERR_NOT_SUPPORTED; + } + } + } + else + { + status = SM_ERR_NOT_FOUND; + } + + /* Return status */ + return status; +} + +/*--------------------------------------------------------------------------*/ +/* Set sensor trippoint */ +/*--------------------------------------------------------------------------*/ +int32_t BRD_SM_SensorTripPointSet(uint32_t sensorId, uint8_t tripPoint, + int64_t value, uint8_t eventControl) +{ + int32_t status = SM_ERR_SUCCESS; + + /* Check to see if sensorId is within bounds*/ + if (sensorId < SM_NUM_SENSOR) + { + /* Check if device or board */ + if (sensorId < DEV_SM_NUM_SENSOR) + { + status = DEV_SM_SensorTripPointSet(sensorId, tripPoint, + value, eventControl); + } + else + { + uint32_t brdSensorId = sensorId - DEV_SM_NUM_SENSOR; + + /* Check if enabled */ + if ((sensorId == BRD_SM_SENSOR_TEMP_PF09) + && sensorEnb[brdSensorId]) + { + /* Check trip point */ + if (tripPoint == 0U) + { + if (eventControl == DEV_SM_SENSOR_TP_NONE) + { + if (!PF09_TempAlarmSet(&g_pf09Dev, 500)) + { + status = SM_ERR_HARDWARE_ERROR; + } + } + else if (eventControl == DEV_SM_SENSOR_TP_RISING) + { + int32_t temp = (int32_t) value; + + if (!PF09_TempAlarmSet(&g_pf09Dev, temp)) + { + status = SM_ERR_HARDWARE_ERROR; + } + } + else + { + status = SM_ERR_INVALID_PARAMETERS; + } + } + else + { + status = SM_ERR_INVALID_PARAMETERS; + } + } + else + { + status = SM_ERR_NOT_SUPPORTED; + } + } + } + else + { + status = SM_ERR_NOT_FOUND; + } + + /* Return status */ + return status; +} + +/*--------------------------------------------------------------------------*/ +/* Enable/disable sensor */ +/*--------------------------------------------------------------------------*/ +int32_t BRD_SM_SensorEnable(uint32_t sensorId, bool enable, + bool timestampReporting) +{ + int32_t status = SM_ERR_SUCCESS; + + /* Check to see if sensorId is within bounds*/ + if (sensorId < SM_NUM_SENSOR) + { + /* Check if device or board */ + if (sensorId < DEV_SM_NUM_SENSOR) + { + status = DEV_SM_SensorEnable(sensorId, enable, + timestampReporting); + } + else + { + uint32_t brdSensorId = sensorId - DEV_SM_NUM_SENSOR; + + /* Timestamp not supported */ + if (timestampReporting) + { + status = SM_ERR_NOT_SUPPORTED; + } + else + { + /* Record sensor enable */ + sensorEnb[brdSensorId] = enable; + + /* Disable alarm */ + if ((sensorId == BRD_SM_SENSOR_TEMP_PF09) + && !sensorEnb[brdSensorId]) + { + if (!PF09_TempAlarmSet(&g_pf09Dev, 500)) + { + status = SM_ERR_HARDWARE_ERROR; + } + } + } + } + } + else + { + status = SM_ERR_NOT_FOUND; + } + + /* Return status */ + return status; +} + +/*--------------------------------------------------------------------------*/ +/* Return sensor enable status */ +/*--------------------------------------------------------------------------*/ +int32_t BRD_SM_SensorIsEnabled(uint32_t sensorId, bool *enabled, + bool *timestampReporting) +{ + int32_t status = SM_ERR_SUCCESS; + + /* Check to see if sensorId is within bounds*/ + if (sensorId < SM_NUM_SENSOR) + { + uint32_t brdSensorId = sensorId - DEV_SM_NUM_SENSOR; + + /* Check if device or board */ + if (sensorId < DEV_SM_NUM_SENSOR) + { + status = DEV_SM_SensorIsEnabled(sensorId, enabled, + timestampReporting); + } + else + { + /* Return sensor enable */ + *enabled = sensorEnb[brdSensorId]; + *timestampReporting = false; + } + } + else + { + status = SM_ERR_NOT_FOUND; + } + + /* Return status */ + return status; +} + +/*--------------------------------------------------------------------------*/ +/* PMIC sensor handler */ +/*--------------------------------------------------------------------------*/ +void BRD_SM_SensorHandler(void) +{ + /* Send sensor event */ + LMM_SensorEvent(BRD_SM_SENSOR_TEMP_PF09, 0U, 1U); +} + diff --git a/boards/tdx-verdin-imx95/sm/brd_sm_sensor.h b/boards/tdx-verdin-imx95/sm/brd_sm_sensor.h new file mode 100755 index 0000000..7afd460 --- /dev/null +++ b/boards/tdx-verdin-imx95/sm/brd_sm_sensor.h @@ -0,0 +1,210 @@ +/* +** ################################################################### +** +** Copyright 2023 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @addtogroup BRD_SM_TDXVERDINIMX95 + * @{ + * + * @file + * @brief + * + * Header file containing the SM API for the board sensors. + */ +/*==========================================================================*/ + +#ifndef BRD_SM_SENSOR_H +#define BRD_SM_SENSOR_H + +/* Includes */ + +#include "sm.h" +#include "dev_sm.h" + +/* Defines */ + +/*! + * @name Board redirection defines + * @{ + */ +#define SM_SENSORNAMEGET BRD_SM_SensorNameGet /*!< Sensor name */ +#define SM_SENSORDESCRIBE BRD_SM_SensorDescribe /*!< Sensor describe */ +#define SM_SENSORREADINGGET BRD_SM_SensorReadingGet /*!< Sensor read */ +#define SM_SENSORTRIPPOINTSET BRD_SM_SensorTripPointSet /*!< Sensor trip point */ +#define SM_SENSORENABLE BRD_SM_SensorEnable /*!< Sensor enable */ +#define SM_SENSORISENABLED BRD_SM_SensorIsEnabled /*!< Sensor status */ +/** @} */ + +/*! Number of board sensors */ +#define BRD_SM_NUM_SENSOR 3UL + +/*! Total number of sensors */ +#define SM_NUM_SENSOR (DEV_SM_NUM_SENSOR + BRD_SM_NUM_SENSOR) + +/*! + * @name BRD_SM sensor domain indexes + */ +/** @{ */ +#define BRD_SM_SENSOR_TEMP_PF09 (DEV_SM_NUM_SENSOR + 0U) /*!< PF09 temp sensor */ +#define BRD_SM_SENSOR_TEMP_PF5302 (DEV_SM_NUM_SENSOR + 1U) /*!< PF5302 temp sensor */ +#define BRD_SM_SENSOR_TEMP_PF5301 (DEV_SM_NUM_SENSOR + 2U) /*!< PF5301 temp sensor */ +/** @} */ + +/* Types */ + +/* Functions */ + +/*! + * @name Board sensor functions + * @{ + */ + +/*! + * Get a board sensor name. + * + * @param[in] sensorId Sensor name to get + * @param[out] sensorNameAddr Return pointer to name + * @param[out] len Return max length of all sensor names + * + * This function allows the caller to get the name of a sensor. + * + * @return Returns the status (::SM_ERR_SUCCESS = success). + * + * Return errors (see @ref STATUS "SM error codes"): + * - ::SM_ERR_NOT_FOUND: if \a sensorId is invalid. + */ +int32_t BRD_SM_SensorNameGet(uint32_t sensorId, string *sensorNameAddr, + int32_t *len); + +/*! + * Get a board sensor description. + * + * @param[in] sensorId Sensor description to get + * @param[out] desc Return pointer to the description + * + * This function allows the caller to get the description of a sensor. + * + * @return Returns the status (::SM_ERR_SUCCESS = success). + * + * Return errors (see @ref STATUS "SM error codes"): + * - ::SM_ERR_NOT_FOUND: if \a sensorId is invalid. + */ +int32_t BRD_SM_SensorDescribe(uint32_t sensorId, + dev_sm_sensor_desc_t *desc); + +/*! + * Read a board sensor. + * + * @param[in] sensorId Sensor to read + * @param[out] sensorValue Return pointer to sensor value + * @param[out] sensorTimestamp Return pointer to timestamp + * + * This function allows the caller to read the value of a sensor. + * + * @return Returns the status (::SM_ERR_SUCCESS = success). + * + * Return errors (see @ref STATUS "SM error codes"): + * - ::SM_ERR_NOT_FOUND: if \a sensorId is invalid. + */ +int32_t BRD_SM_SensorReadingGet(uint32_t sensorId, int64_t *sensorValue, + uint64_t *sensorTimestamp); + +/*! + * Configure a trip point for a board sensor. + * + * @param[in] sensorId Sensor to configure TP + * @param[in] tripPoint Trip point ID + * @param[in] value Value to trip at + * @param[in] eventControl Event control (notifications) + * + * This function allows the caller to configure one of the trip + * points for a sensor. The caller can also configure which crossing + * direction will generate a notification. + * + * @return Returns the status (::SM_ERR_SUCCESS = success). + * + * Return errors (see @ref STATUS "SM error codes"): + * - ::SM_ERR_NOT_FOUND: if \a sensorId is invalid. + */ +int32_t BRD_SM_SensorTripPointSet(uint32_t sensorId, uint8_t tripPoint, + int64_t value, uint8_t eventControl); + +/*! + * Enable/disable a board sensor. + * + * @param[in] sensorId Sensor to enable/disable + * @param[in] enable True to enable + * @param[in] timestampReporting True to enable timestamp reporting + * + * This function allows the caller to enable/disable a sensor. + * + * @return Returns the status (::SM_ERR_SUCCESS = success). + * + * Return errors (see @ref STATUS "SM error codes"): + * - ::SM_ERR_NOT_FOUND: if \a sensorId is invalid. + */ +int32_t BRD_SM_SensorEnable(uint32_t sensorId, bool enable, + bool timestampReporting); + +/*! + * Get enable/disable state of a board sensor. + * + * @param[in] sensorId Sensor to get state + * @param[out] enabled Return pointer to enable + * @param[out] timestampReporting Return pointer to reporting + * + * This function allows the caller to get the enable/disable + * state of a sensor. + * + * @return Returns the status (::SM_ERR_SUCCESS = success). + * + * Return errors (see @ref STATUS "SM error codes"): + * - ::SM_ERR_NOT_FOUND: if \a sensorId is invalid. + */ +int32_t BRD_SM_SensorIsEnabled(uint32_t sensorId, bool *enabled, + bool *timestampReporting); + +/*! + * Sensor interrupt handler. + * + * Called by PF09 interrupt handler. + */ +void BRD_SM_SensorHandler(void); + +/** @} */ + +#endif /* BRD_SM_SENSOR_H */ + +/** @} */ + diff --git a/boards/tdx-verdin-imx95/sm/brd_sm_voltage.c b/boards/tdx-verdin-imx95/sm/brd_sm_voltage.c new file mode 100755 index 0000000..df36e54 --- /dev/null +++ b/boards/tdx-verdin-imx95/sm/brd_sm_voltage.c @@ -0,0 +1,517 @@ +/* +** ################################################################### +** +** Copyright 2023-2024 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/* File containing the implementation of the board voltages. */ +/*==========================================================================*/ + +/* Includes */ + +#include "sm.h" +#include "brd_sm.h" + +/* Local defines */ + +/* Local types */ + +/* Local variables */ + +static int32_t s_levelSoc = BOARD_VOLT_SOC; +static int32_t s_levelArm = BOARD_VOLT_ARM; +static uint32_t s_modeArm = DEV_SM_VOLT_MODE_ON; +static uint32_t s_modeArmSave = DEV_SM_VOLT_MODE_ON; + +/*--------------------------------------------------------------------------*/ +/* Return voltage name */ +/*--------------------------------------------------------------------------*/ +int32_t BRD_SM_VoltageNameGet(uint32_t domainId, string *voltNameAddr, + int32_t *len) +{ + int32_t status = SM_ERR_SUCCESS; + static int32_t s_maxLen = 0; + + static string const s_name[BRD_SM_NUM_VOLT] = + { + "vdd_gpio_3p3", + "vdd_ana_0p8", + "vdd_gpio_1p8", + "vddq_ddr", + "vdd2_ddr", + "sd_card", + "nvcc_sd2" + }; + + /* Get max string width */ + DEV_SM_MaxStringGet(len, &s_maxLen, s_name, BRD_SM_NUM_VOLT); + + /* Check to see if domain is within bounds*/ + if (domainId < SM_NUM_VOLT) + { + /* Check if device or board */ + if (domainId < DEV_SM_NUM_VOLT) + { + status = DEV_SM_VoltageNameGet(domainId, voltNameAddr, len); + } + else + { + /* Return pointer to name */ + *voltNameAddr = s_name[domainId - DEV_SM_NUM_VOLT]; + } + } + else + { + status = SM_ERR_NOT_FOUND; + } + + /* Return status */ + return status; +} + +/*--------------------------------------------------------------------------*/ +/* Return supported voltage range */ +/*--------------------------------------------------------------------------*/ +int32_t BRD_SM_VoltageDescribe(uint32_t domainId, + dev_sm_voltage_range_t *range) +{ + int32_t status = SM_ERR_HARDWARE_ERROR; + bool rc = false; + PF09_RegInfo info; + + /* Get voltage range/info */ + switch (domainId) + { + case DEV_SM_VOLT_SOC: + status = DEV_SM_VoltageDescribe(domainId, range); + break; + case DEV_SM_VOLT_ARM: + status = DEV_SM_VoltageDescribe(domainId, range); + break; + case BRD_SM_VOLT_VDD_GPIO_3P3: + rc = PF09_RegulatorInfoGet(PF09_REG_SW1, &info); + break; + case BRD_SM_VOLT_VDD_ANA_0P8: + rc = PF09_RegulatorInfoGet(PF09_REG_SW2, &info); + break; + case BRD_SM_VOLT_VDD_GPIO_1P8: + rc = PF09_RegulatorInfoGet(PF09_REG_SW3, &info); + break; + case BRD_SM_VOLT_VDDQ_DDR: + rc = PF09_RegulatorInfoGet(PF09_REG_SW4, &info); + break; + case BRD_SM_VOLT_VDD2_DDR: + rc = PF09_RegulatorInfoGet(PF09_REG_SW5, &info); + break; + case BRD_SM_VOLT_SD_CARD: + rc = PF09_RegulatorInfoGet(PF09_REG_LDO1, &info); + break; + case BRD_SM_VOLT_NVCC_SD2: + rc = PF09_RegulatorInfoGet(PF09_REG_LDO2, &info); + break; + default: + status = SM_ERR_NOT_FOUND; + break; + } + + /* Return results */ + if ((status != SM_ERR_SUCCESS) && rc) + { + range->highestVolt = (int32_t) info.maxV; + range->lowestVolt = (int32_t) info.minV; + range->stepSize= (int32_t) info.stepV; + status = SM_ERR_SUCCESS; + } + + /* Return status */ + return status; +} + +/*--------------------------------------------------------------------------*/ +/* Set voltage mode */ +/*--------------------------------------------------------------------------*/ +int32_t BRD_SM_VoltageModeSet(uint32_t domainId, uint8_t voltMode) +{ + int32_t status = SM_ERR_SUCCESS; + bool enable = (voltMode == DEV_SM_VOLT_MODE_ON); + uint8_t mode = ((voltMode == DEV_SM_VOLT_MODE_OFF) + ? PF09_SW_MODE_OFF : PF09_SW_MODE_PWM); + bool rc; + + /* Set mode */ + switch (domainId) + { + case DEV_SM_VOLT_SOC: + mode = ((voltMode == DEV_SM_VOLT_MODE_OFF) + ? PF53_SW_MODE_OFF : PF53_SW_MODE_PWM); + rc = PF53_SwModeSet(&g_pf5302Dev, PF53_REG_SW1, PF53_STATE_VRUN, + mode); + break; + case DEV_SM_VOLT_ARM: + rc = PF09_GpioCtrlSet(&g_pf09Dev, PF09_GPIO4, PF53_STATE_VRUN, + enable); + if (enable && rc) + { + /* Wait for PF53 power up and ramp */ + SystemTimeDelay(1000U); + + if (s_levelArm != BOARD_VOLT_ARM) + { + /* Restore voltage as enable resets the PF53 */ + status = BRD_SM_VoltageLevelSet(domainId, s_levelArm); + } + } + if (rc) + { + s_modeArm = voltMode; + } + break; + case BRD_SM_VOLT_VDD_GPIO_3P3: + rc = PF09_SwModeSet(&g_pf09Dev, PF09_REG_SW1, PF09_STATE_VRUN, + mode); + break; + case BRD_SM_VOLT_VDD_ANA_0P8: + rc = PF09_SwModeSet(&g_pf09Dev, PF09_REG_SW2, PF09_STATE_VRUN, + mode); + break; + case BRD_SM_VOLT_VDD_GPIO_1P8: + rc = PF09_SwModeSet(&g_pf09Dev, PF09_REG_SW3, PF09_STATE_VRUN, + mode); + break; + case BRD_SM_VOLT_VDDQ_DDR: + rc = PF09_SwModeSet(&g_pf09Dev, PF09_REG_SW4, PF09_STATE_VRUN, + mode); + break; + case BRD_SM_VOLT_VDD2_DDR: + rc = PF09_SwModeSet(&g_pf09Dev, PF09_REG_SW5, PF09_STATE_VRUN, + mode); + break; + case BRD_SM_VOLT_SD_CARD: + rc = PF09_LdoEnable(&g_pf09Dev, PF09_REG_LDO1, PF09_STATE_VRUN, + enable); + break; + case BRD_SM_VOLT_NVCC_SD2: + rc = PF09_LdoEnable(&g_pf09Dev, PF09_REG_LDO2, PF09_STATE_VRUN, + enable); + break; + default: + status = SM_ERR_NOT_FOUND; + break; + } + + /* Translate error */ + if ((status == SM_ERR_SUCCESS) && !rc) + { + status = SM_ERR_HARDWARE_ERROR; + } + + /* Return status */ + return status; +} + +/*--------------------------------------------------------------------------*/ +/* Get voltage mode */ +/*--------------------------------------------------------------------------*/ +int32_t BRD_SM_VoltageModeGet(uint32_t domainId, uint8_t *voltMode) +{ + int32_t status = SM_ERR_SUCCESS; + bool enable; + uint8_t mode; + bool rc; + + /* Get mode */ + switch (domainId) + { + case DEV_SM_VOLT_SOC: + rc = PF53_SwModeGet(&g_pf5302Dev, PF53_REG_SW1, PF53_STATE_VRUN, + &mode); + enable = (mode != PF53_SW_MODE_OFF); + break; + case DEV_SM_VOLT_ARM: + rc = PF09_GpioCtrlGet(&g_pf09Dev, PF09_GPIO4, PF53_STATE_VRUN, + &enable); + break; + case BRD_SM_VOLT_VDD_GPIO_3P3: + rc = PF09_SwModeGet(&g_pf09Dev, PF09_REG_SW1, PF09_STATE_VRUN, + &mode); + enable = (mode != PF09_SW_MODE_OFF); + break; + case BRD_SM_VOLT_VDD_ANA_0P8: + rc = PF09_SwModeGet(&g_pf09Dev, PF09_REG_SW2, PF09_STATE_VRUN, + &mode); + enable = (mode != PF09_SW_MODE_OFF); + break; + case BRD_SM_VOLT_VDD_GPIO_1P8: + rc = PF09_SwModeGet(&g_pf09Dev, PF09_REG_SW3, PF09_STATE_VRUN, + &mode); + enable = (mode != PF09_SW_MODE_OFF); + break; + case BRD_SM_VOLT_VDDQ_DDR: + rc = PF09_SwModeGet(&g_pf09Dev, PF09_REG_SW4, PF09_STATE_VRUN, + &mode); + enable = (mode != PF09_SW_MODE_OFF); + break; + case BRD_SM_VOLT_VDD2_DDR: + rc = PF09_SwModeGet(&g_pf09Dev, PF09_REG_SW5, PF09_STATE_VRUN, + &mode); + enable = (mode != PF09_SW_MODE_OFF); + break; + case BRD_SM_VOLT_SD_CARD: + rc = PF09_LdoIsEnabled(&g_pf09Dev, PF09_REG_LDO1, PF09_STATE_VRUN, + &enable); + break; + case BRD_SM_VOLT_NVCC_SD2: + rc = PF09_LdoIsEnabled(&g_pf09Dev, PF09_REG_LDO2, PF09_STATE_VRUN, + &enable); + break; + default: + status = SM_ERR_NOT_FOUND; + break; + } + + /* Return result */ + if ((status == SM_ERR_SUCCESS) && rc) + { + *voltMode = enable ? DEV_SM_VOLT_MODE_ON : DEV_SM_VOLT_MODE_OFF; + } + + /* Translate error */ + if ((status == SM_ERR_SUCCESS) && !rc) + { + status = SM_ERR_HARDWARE_ERROR; + } + + /* Return status */ + return status; +} + +/*--------------------------------------------------------------------------*/ +/* Set voltage level */ +/*--------------------------------------------------------------------------*/ +int32_t BRD_SM_VoltageLevelSet(uint32_t domainId, int32_t voltageLevel) +{ + int32_t status = SM_ERR_SUCCESS; + bool rc; + uint32_t level = (uint32_t) voltageLevel; + + /* Set level */ + switch (domainId) + { + case DEV_SM_VOLT_SOC: + rc = PF53_VoltageSet(&g_pf5302Dev, PF53_REG_SW1, PF53_STATE_VRUN, + level); + + if (rc) + { + /* Save level to restore */ + s_levelSoc = (int32_t) level; + } + break; + case DEV_SM_VOLT_ARM: + (void) PF53_VoltageSet(&g_pf5301Dev, PF53_REG_SW1, PF53_STATE_VRUN, + level); + + /* Save level to restore */ + s_levelArm = (int32_t) level; + rc = true; + break; + case BRD_SM_VOLT_VDD_GPIO_3P3: + rc = PF09_VoltageSet(&g_pf09Dev, PF09_REG_SW1, PF09_STATE_VRUN, + level); + break; + case BRD_SM_VOLT_VDD_ANA_0P8: + rc = PF09_VoltageSet(&g_pf09Dev, PF09_REG_SW2, PF09_STATE_VRUN, + level); + break; + case BRD_SM_VOLT_VDD_GPIO_1P8: + rc = PF09_VoltageSet(&g_pf09Dev, PF09_REG_SW3, PF09_STATE_VRUN, + level); + break; + case BRD_SM_VOLT_VDDQ_DDR: + rc = PF09_VoltageSet(&g_pf09Dev, PF09_REG_SW4, PF09_STATE_VRUN, + level); + break; + case BRD_SM_VOLT_VDD2_DDR: + rc = PF09_VoltageSet(&g_pf09Dev, PF09_REG_SW5, PF09_STATE_VRUN, + level); + break; + case BRD_SM_VOLT_SD_CARD: + rc = PF09_VoltageSet(&g_pf09Dev, PF09_REG_LDO1, PF09_STATE_VRUN, + level); + break; + case BRD_SM_VOLT_NVCC_SD2: + rc = PF09_VoltageSet(&g_pf09Dev, PF09_REG_LDO2, PF09_STATE_VRUN, + level); + break; + default: + status = SM_ERR_NOT_FOUND; + break; + } + + /* Translate error */ + if ((status == SM_ERR_SUCCESS) && !rc) + { + status = SM_ERR_HARDWARE_ERROR; + } + + /* Return status */ + return status; +} + +/*--------------------------------------------------------------------------*/ +/* Get voltage level */ +/*--------------------------------------------------------------------------*/ +int32_t BRD_SM_VoltageLevelGet(uint32_t domainId, int32_t *voltageLevel) +{ + int32_t status = SM_ERR_SUCCESS; + bool rc; + uint32_t level; + + /* Get level */ + switch (domainId) + { + case DEV_SM_VOLT_SOC: + rc = PF53_VoltageGet(&g_pf5302Dev, PF53_REG_SW1, PF53_STATE_VRUN, + &level); + break; + case DEV_SM_VOLT_ARM: + rc = PF53_VoltageGet(&g_pf5301Dev, PF53_REG_SW1, PF53_STATE_VRUN, + &level); + if (rc) + { + /* Save level to restore */ + s_levelArm = (int32_t) level; + } + else + { + /* Return saved level */ + level = (uint32_t) s_levelArm; + rc = true; + } + break; + case BRD_SM_VOLT_VDD_GPIO_3P3: + rc = PF09_VoltageGet(&g_pf09Dev, PF09_REG_SW1, PF09_STATE_VRUN, + &level); + break; + case BRD_SM_VOLT_VDD_ANA_0P8: + rc = PF09_VoltageGet(&g_pf09Dev, PF09_REG_SW2, PF09_STATE_VRUN, + &level); + break; + case BRD_SM_VOLT_VDD_GPIO_1P8: + rc = PF09_VoltageGet(&g_pf09Dev, PF09_REG_SW3, PF09_STATE_VRUN, + &level); + break; + case BRD_SM_VOLT_VDDQ_DDR: + rc = PF09_VoltageGet(&g_pf09Dev, PF09_REG_SW4, PF09_STATE_VRUN, + &level); + break; + case BRD_SM_VOLT_VDD2_DDR: + rc = PF09_VoltageGet(&g_pf09Dev, PF09_REG_SW5, PF09_STATE_VRUN, + &level); + break; + case BRD_SM_VOLT_SD_CARD: + rc = PF09_VoltageGet(&g_pf09Dev, PF09_REG_LDO1, PF09_STATE_VRUN, + &level); + break; + case BRD_SM_VOLT_NVCC_SD2: + rc = PF09_VoltageGet(&g_pf09Dev, PF09_REG_LDO2, PF09_STATE_VRUN, + &level); + break; + default: + status = SM_ERR_NOT_FOUND; + break; + } + + /* Return result */ + if ((status == SM_ERR_SUCCESS) && rc) + { + *voltageLevel = (int32_t) level; + } + + /* Translate error */ + if ((status == SM_ERR_SUCCESS) && !rc) + { + status = SM_ERR_HARDWARE_ERROR; + } + + /* Return status */ + return status; +} + +/*--------------------------------------------------------------------------*/ +/* Suspend SoC voltages */ +/*--------------------------------------------------------------------------*/ +void BRD_SM_VoltageSuspend(bool offArm) +{ + /* Turn off VDD_ARM */ + if (offArm && (s_modeArm != DEV_SM_VOLT_MODE_OFF)) + { + /* Save VDD_ARM mode */ + s_modeArmSave = s_modeArm; + + (void) BRD_SM_VoltageModeSet(DEV_SM_VOLT_ARM, DEV_SM_VOLT_MODE_OFF); + } +} + +/*--------------------------------------------------------------------------*/ +/* Restore SoC voltages */ +/*--------------------------------------------------------------------------*/ +void BRD_SM_VoltageRestore(void) +{ + /* Restore VDD_SOC level */ + if (s_levelSoc != BOARD_VOLT_SOC) + { + /* Restore voltage as enable resets the PF53 */ + (void) BRD_SM_VoltageLevelSet(DEV_SM_VOLT_SOC, s_levelSoc); + } + + /* Restore VDD_ARM mode */ + if (s_modeArm != s_modeArmSave) + { + if (PF09_GpioCtrlSet(&g_pf09Dev, PF09_GPIO4, PF53_STATE_VRUN, + true)) + { + /* Wait for PF53 power up and ramp */ + SystemTimeDelay(1000U); + + s_modeArm = DEV_SM_VOLT_MODE_ON; + } + } + + /* Restore VDD_ARM level */ + if (s_levelArm != BOARD_VOLT_ARM) + { + /* Restore voltage as enable resets the PF53 */ + (void) BRD_SM_VoltageLevelSet(DEV_SM_VOLT_ARM, s_levelArm); + } +} + diff --git a/boards/tdx-verdin-imx95/sm/brd_sm_voltage.h b/boards/tdx-verdin-imx95/sm/brd_sm_voltage.h new file mode 100755 index 0000000..1734b6f --- /dev/null +++ b/boards/tdx-verdin-imx95/sm/brd_sm_voltage.h @@ -0,0 +1,213 @@ +/* +** ################################################################### +** +** Copyright 2023-2024 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @addtogroup BRD_SM_TDXVERDINIMX95 + * @{ + * + * @file + * @brief + * + * Header file containing the SM API for the board voltages. + */ +/*==========================================================================*/ + +#ifndef BRD_SM_VOLTAGE_H +#define BRD_SM_VOLTAGE_H + +/* Includes */ + +#include "sm.h" +#include "dev_sm.h" + +/* Defines */ + +/*! + * @name Board redirection defines + * @{ + */ +#define SM_VOLTAGENAMEGET BRD_SM_VoltageNameGet /*!< Voltage name */ +#define SM_VOLTAGEDESCRIBE BRD_SM_VoltageDescribe /*!< Voltage describe */ +#define SM_VOLTAGEMODESET BRD_SM_VoltageModeSet /*!< Set voltage mode */ +#define SM_VOLTAGEMODEGET BRD_SM_VoltageModeGet /*!< Get coltage mode */ +#define SM_VOLTAGELEVELSET BRD_SM_VoltageLevelSet /*!< Set voltage level */ +#define SM_VOLTAGELEVELGET BRD_SM_VoltageLevelGet /*!< Get voltage level */ +/** @} */ + +/*! Number of board voltages */ +#define BRD_SM_NUM_VOLT 7UL + +/*! Total number of sensors */ +#define SM_NUM_VOLT (DEV_SM_NUM_VOLT + BRD_SM_NUM_VOLT) + +/*! + * @name BRD_SM voltage domains + */ +/** @{ */ +#define BRD_SM_VOLT_VDD_GPIO_3P3 (DEV_SM_NUM_VOLT + 0U) /*!< VDD GPIO 3.3v */ +#define BRD_SM_VOLT_VDD_ANA_0P8 (DEV_SM_NUM_VOLT + 1U) /*!< VDD ANA 0.8v */ +#define BRD_SM_VOLT_VDD_GPIO_1P8 (DEV_SM_NUM_VOLT + 2U) /*!< VDD GPIO 1.8v */ +#define BRD_SM_VOLT_VDDQ_DDR (DEV_SM_NUM_VOLT + 3U) /*!< DDR VDDQ */ +#define BRD_SM_VOLT_VDD2_DDR (DEV_SM_NUM_VOLT + 4U) /*!< DDR VDD2 */ +#define BRD_SM_VOLT_SD_CARD (DEV_SM_NUM_VOLT + 5U) /*!< SD1 */ +#define BRD_SM_VOLT_NVCC_SD2 (DEV_SM_NUM_VOLT + 6U) /*!< SD2 */ +/** @} */ + +/* Types */ + +/* Functions */ + +/*! + * Get a board voltage domain name. + * + * @param[in] domainId Domain name to get + * @param[out] voltNameAddr Return pointer to name + * @param[out] len Return max length of all domain names + * + * This function allows the caller to get the name of a voltage domain. + * + * @return Returns the status (::SM_ERR_SUCCESS = success). + * + * Return errors (see @ref STATUS "SM error codes"): + * - ::SM_ERR_NOT_FOUND: if \a domainId is invalid. + */ +int32_t BRD_SM_VoltageNameGet(uint32_t domainId, string *voltNameAddr, + int32_t *len); + +/*! + * Get a board voltage domain description. + * + * @param[in] domainId Voltage description to get + * @param[out] range Pointer to return range + * + * This function allows the caller to get the voltage range for + * a voltage. The range contains the high, low, and step voltage + * in microvolts (uV). + * + * @return Returns the status (::SM_ERR_SUCCESS = success). + * + * Return errors (see @ref STATUS "SM error codes"): + * - ::SM_ERR_NOT_FOUND: if \a domainId is invalid. + */ +int32_t BRD_SM_VoltageDescribe(uint32_t domainId, + dev_sm_voltage_range_t *range); + +/*! + * Set a board voltage mode. + * + * @param[in] domainId Identifier for the voltage domain + * @param[in] voltMode Voltage mode to set + * + * This function allows the caller to set the current mode of + * a voltage domain. + * + * @return Returns the status (::SM_ERR_SUCCESS = success). + * + * Return errors (see @ref STATUS "SM error codes"): + * - ::SM_ERR_NOT_FOUND: if \a domainId is invalid. + */ +int32_t BRD_SM_VoltageModeSet(uint32_t domainId, uint8_t voltMode); + +/*! + * Get a board voltage mode. + * + * @param[in] domainId Identifier for the voltage domain + * @param[out] voltMode Pointer to return the voltage mode + * + * This function allows the caller to request the current mode of + * a voltage domain. + * + * @return Returns the status (::SM_ERR_SUCCESS = success). + * + * Return errors (see @ref STATUS "SM error codes"): + * - ::SM_ERR_NOT_FOUND: if \a domainId is invalid. + */ +int32_t BRD_SM_VoltageModeGet(uint32_t domainId, uint8_t *voltMode); + +/*! + * Set a board voltage level. + * + * @param[in] domainId Identifier for the voltage domain + * @param[in] voltageLevel Voltage level to set + * + * This function allows the caller to set the current level of + * a voltage domain. + * + * @return Returns the status (::SM_ERR_SUCCESS = success). + * + * Return errors (see @ref STATUS "SM error codes"): + * - ::SM_ERR_NOT_FOUND: if \a domainId is invalid. + * - ::SM_ERR_INVALID_PARAMETERS: if \a voltageLevel is negative. + * - other from BRD_SM_SupplyLevelSet() + */ +int32_t BRD_SM_VoltageLevelSet(uint32_t domainId, int32_t voltageLevel); + +/*! + * Get a board voltage level. + * + * @param[in] domainId Identifier for the voltage domain + * @param[out] voltageLevel Pointer to return the voltage level + * + * This function allows the caller to request the current level of + * a voltage domain. + * + * @return Returns the status (::SM_ERR_SUCCESS = success). + * + * Return errors (see @ref STATUS "SM error codes"): + * - ::SM_ERR_NOT_FOUND: if \a domainId is invalid. + * - other from BRD_SM_SupplyLevelGet() + */ +int32_t BRD_SM_VoltageLevelGet(uint32_t domainId, int32_t *voltageLevel); + +/*! + * Suspend voltage modes/levels. + * + * @param[in] offArm Turn off VDD_ARM if on + * + * This function saves and disabled the ARM voltage. + */ +void BRD_SM_VoltageSuspend(bool offArm); + +/*! + * Restore voltage modes/levels. + * + * This function writes the last set voltage levels back to the PMICs. + */ +void BRD_SM_VoltageRestore(void); + +#endif /* BRD_SM_VOLTAGE_H */ + +/** @} */ + |