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authorLaurent Pinchart <laurent.pinchart@ideasonboard.com>2021-02-15 05:27:41 +0100
committerMauro Carvalho Chehab <mchehab+huawei@kernel.org>2021-03-11 11:59:53 +0100
commit1cb3ff130f4d97dec2d1bee968a87f5d6e24dd60 (patch)
treeeb6b85fa16eb38ce79217777b825432d2455aad4
parent4fe5bb0b666ee53cf0faa778422cc2997d8d091a (diff)
media: imx: imx7_mipi_csis: Print shadow registers in mipi_csis_dump_regs()
Print the value of the ISP shadow registers in mipi_csis_dump_regs() as this can help debugging. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Rui Miguel Silva <rmfrfs@gmail.com> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
-rw-r--r--drivers/staging/media/imx/imx7-mipi-csis.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/staging/media/imx/imx7-mipi-csis.c b/drivers/staging/media/imx/imx7-mipi-csis.c
index b1cdc2403a45..bd587e550d99 100644
--- a/drivers/staging/media/imx/imx7-mipi-csis.c
+++ b/drivers/staging/media/imx/imx7-mipi-csis.c
@@ -188,6 +188,11 @@
#define MIPI_CSIS_ISP_SYNC_VSYNC_SINTV_OFFSET 12
#define MIPI_CSIS_ISP_SYNC_VSYNC_EINTV_OFFSET 0
+/* ISP shadow registers */
+#define MIPI_CSIS_SDW_CONFIG_CH(n) (0x80 + (n) * 0x10)
+#define MIPI_CSIS_SDW_RESOL_CH(n) (0x84 + (n) * 0x10)
+#define MIPI_CSIS_SDW_SYNC_CH(n) (0x88 + (n) * 0x10)
+
/* Debug control register */
#define MIPI_CSIS_DBG_CTRL 0xc0
@@ -411,6 +416,8 @@ static int mipi_csis_dump_regs(struct csi_state *state)
{ MIPI_CSIS_DPHY_SCTRL_H, "DPHY_SCTRL_H" },
{ MIPI_CSIS_ISP_CONFIG_CH(0), "ISP_CONFIG_CH0" },
{ MIPI_CSIS_ISP_RESOL_CH(0), "ISP_RESOL_CH0" },
+ { MIPI_CSIS_SDW_CONFIG_CH(0), "SDW_CONFIG_CH0" },
+ { MIPI_CSIS_SDW_RESOL_CH(0), "SDW_RESOL_CH0" },
{ MIPI_CSIS_DBG_CTRL, "DBG_CTRL" },
};