diff options
| author | Russell King (Oracle) <rmk+kernel@armlinux.org.uk> | 2026-01-08 17:36:09 +0000 |
|---|---|---|
| committer | Jakub Kicinski <kuba@kernel.org> | 2026-01-12 18:02:10 -0800 |
| commit | 1fd3b573713a91bc65cb90b919f17786fe7f147a (patch) | |
| tree | c7317e9d009539287d560ab0255a75d9a213a3ee | |
| parent | 5c024716f52bb8b683ff7c85c574a49644a1f299 (diff) | |
net: stmmac: dwmac4: remove duplicated definitions
dwmac4.h duplicates some of the debug register definitions. Remove
the second copy.
Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Link: https://patch.msgid.link/E1vdtvd-00000002GtJ-0qFI@rmk-PC.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
| -rw-r--r-- | drivers/net/ethernet/stmicro/stmmac/dwmac4.h | 29 |
1 files changed, 0 insertions, 29 deletions
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h index 3cb733781e1e..fa27639895ce 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h @@ -485,35 +485,6 @@ static inline u32 mtl_low_credx_base_addr(const struct dwmac4_addrs *addrs, /* To dump the core regs excluding the Address Registers */ #define GMAC_REG_NUM 132 -/* MTL debug */ -#define MTL_DEBUG_TXSTSFSTS BIT(5) -#define MTL_DEBUG_TXFSTS BIT(4) -#define MTL_DEBUG_TWCSTS BIT(3) - -/* MTL debug: Tx FIFO Read Controller Status */ -#define MTL_DEBUG_TRCSTS_MASK GENMASK(2, 1) -#define MTL_DEBUG_TRCSTS_SHIFT 1 -#define MTL_DEBUG_TRCSTS_IDLE 0 -#define MTL_DEBUG_TRCSTS_READ 1 -#define MTL_DEBUG_TRCSTS_TXW 2 -#define MTL_DEBUG_TRCSTS_WRITE 3 -#define MTL_DEBUG_TXPAUSED BIT(0) - -/* MAC debug: GMII or MII Transmit Protocol Engine Status */ -#define MTL_DEBUG_RXFSTS_MASK GENMASK(5, 4) -#define MTL_DEBUG_RXFSTS_SHIFT 4 -#define MTL_DEBUG_RXFSTS_EMPTY 0 -#define MTL_DEBUG_RXFSTS_BT 1 -#define MTL_DEBUG_RXFSTS_AT 2 -#define MTL_DEBUG_RXFSTS_FULL 3 -#define MTL_DEBUG_RRCSTS_MASK GENMASK(2, 1) -#define MTL_DEBUG_RRCSTS_SHIFT 1 -#define MTL_DEBUG_RRCSTS_IDLE 0 -#define MTL_DEBUG_RRCSTS_RDATA 1 -#define MTL_DEBUG_RRCSTS_RSTAT 2 -#define MTL_DEBUG_RRCSTS_FLUSH 3 -#define MTL_DEBUG_RWCSTS BIT(0) - /* SGMII/RGMII status register */ #define GMAC_PHYIF_CTRLSTATUS_TC BIT(0) #define GMAC_PHYIF_CTRLSTATUS_LUD BIT(1) |