diff options
| author | Kaz Fukuoka <kfukuoka@nvidia.com> | 2013-03-06 15:12:36 -0800 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 13:02:19 -0700 |
| commit | 2187a33fcec30b8ae89d0660cd1a0a87e045ecba (patch) | |
| tree | 41d4756372822224722d33a66ad8a3d51b22eaf2 | |
| parent | c837b092f9a8debc6d26586ae213d51b6ca7d42d (diff) | |
ARM: tegra14: clock: Update PLL settings
bug 1239762
Change-Id: Ia2407b2d0155aa4c90a9eb0d309def1b1acdeb15
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/206839
Reviewed-by: Harshada Kale <hkale@nvidia.com>
Tested-by: Harshada Kale <hkale@nvidia.com>
| -rw-r--r-- | arch/arm/mach-tegra/tegra14_clocks.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/arch/arm/mach-tegra/tegra14_clocks.c b/arch/arm/mach-tegra/tegra14_clocks.c index ac3bc336b0e8..d0c82ace326f 100644 --- a/arch/arm/mach-tegra/tegra14_clocks.c +++ b/arch/arm/mach-tegra/tegra14_clocks.c @@ -253,9 +253,9 @@ ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT)) #define PLLCX_MISC_DIV_LOW_RANGE \ - ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | (0x2 << PLLCX_MISC_FILT_DIV_SHIFT)) -#define PLLCX_MISC_DIV_HIGH_RANGE \ ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | (0x1 << PLLCX_MISC_FILT_DIV_SHIFT)) +#define PLLCX_MISC_DIV_HIGH_RANGE \ + ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | (0x2 << PLLCX_MISC_FILT_DIV_SHIFT)) #define PLLCX_MISC_DEFAULT_VALUE ((0x0 << PLLCX_MISC_VCO_GAIN_SHIFT) | \ PLLCX_MISC_KOEF_LOW_RANGE | \ @@ -1971,7 +1971,9 @@ static void tegra14_pll_clk_disable(struct clk *c) static u8 get_pll_cpcon(struct clk *c, u16 n) { if (c->flags & PLLD) { - if (n >= 600) + if (n >= 1000) + return 15; + else if (n >= 600) return 12; else if (n >= 300) return 8; @@ -2307,7 +2309,7 @@ static void pllcx_update_dynamic_koef(struct clk *c, unsigned long input_rate, n_threshold = 55; break; case 19200000: - n_threshold = 48; + n_threshold = 43; break; default: pr_err("%s: Unexpected reference rate %lu\n", |