diff options
| author | Heiko Stuebner <heiko@sntech.de> | 2025-07-07 18:49:03 +0200 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2025-08-22 23:20:58 +0200 |
| commit | 21bc1a7fcea4635a49f6b2eff3e4c661e80e8f43 (patch) | |
| tree | c59bb652c88adb3cb6bb46ee7e9e31129f94fc0b | |
| parent | 0e3f3d7c7ae3dec5ff52325915e3efcbce652a82 (diff) | |
arm64: dts: rockchip: add mipi-dcphy to rk3576
Add the MIPI-DC-phy node to the RK3576, that will be used by the one
DSI2 controller and hopefully in some future also for camera input.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20250707164906.1445288-11-heiko@sntech.de
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3576.dtsi | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi index f28c5a3e4f4c..0536aa8c3cb7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -966,6 +966,12 @@ reg = <0x0 0x26032000 0x0 0x100>; }; + mipidcphy_grf: syscon@26034000 { + compatible = "rockchip,rk3576-dcphy-grf", "syscon"; + reg = <0x0 0x26034000 0x0 0x2000>; + clocks = <&cru PCLK_PMUPHY_ROOT>; + }; + vo1_grf: syscon@26036000 { compatible = "rockchip,rk3576-vo1-grf", "syscon"; reg = <0x0 0x26036000 0x0 0x100>; @@ -2563,6 +2569,22 @@ status = "disabled"; }; + mipidcphy: phy@2b020000 { + compatible = "rockchip,rk3576-mipi-dcphy"; + reg = <0x0 0x2b020000 0x0 0x10000>; + clocks = <&cru PCLK_MIPI_DCPHY>, + <&cru CLK_PHY_REF_SRC>; + clock-names = "pclk", "ref"; + resets = <&cru SRST_M_MIPI_DCPHY>, + <&cru SRST_P_MIPI_DCPHY>, + <&cru SRST_P_DCPHY_GRF>, + <&cru SRST_S_MIPI_DCPHY>; + reset-names = "m_phy", "apb", "grf", "s_phy"; + rockchip,grf = <&mipidcphy_grf>; + #phy-cells = <1>; + status = "disabled"; + }; + combphy0_ps: phy@2b050000 { compatible = "rockchip,rk3576-naneng-combphy"; reg = <0x0 0x2b050000 0x0 0x100>; |