diff options
| author | Dave Airlie <airlied@redhat.com> | 2026-10-12 08:49:48 +1000 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2026-10-12 08:49:49 +1000 |
| commit | 22739ca2a80c9c2bbeace4075249efdc950d3ac1 (patch) | |
| tree | 8fc4b478f2a6f6adc749f178b25c92901a8fbe59 | |
| parent | 8e2d7e8d7580e57c4b68646909e52622d2ba9ba2 (diff) | |
| parent | d024361c631b3f020a26c07d683e5103404b0fbf (diff) | |
Merge tag 'drm-msm-next-2026-10-11' of https://gitlab.freedesktop.org/drm/msm into drm-next
Changes for v7.4
CI:
- Dropped sc7180 trogdor lazor from the CI
Core:
- Fixed msm_ioremap for resources without a name
- Changed msm.separate_gpu_kms to default to auto selection
GPU:
- Enable CLX (Current Limit eXtension) for gen8 to avoid
exceeding limits on CX/GX rails
- New GPUs: a830 (Pakala), a845 (Maili), a850 (Hawi),
x2-85 (Mahua)
- Fix VBIF halt mask on a306, which was preventing runpm
suspend
- Enable THP support for GEM buffers
- Add modparam to disable waiting on fences in shrinker
- Drop use of drm_prime_sg_to_page_array()
- a5xx: don't read the GPMU registers on GPUs without a GPMU
- a2xx/a3xx/a5xx: hangcheck progress detection
- a6xx: gmuwrapper runpm fix
- Calculate reported GMEM size based on active slices
- Split a6xx/a7xx/a8xx catalog
DP:
- Picked up some preparation patches for the MST support
- Fixed reported status of the link training
DPU:
- Fixed CRTC bandwidth computation
- Fixed DSC programming
- Fixed encoder disablement path
DSI:
- Fixed VM leak in error path
- Indention fix
MDP5:
- Added MSM8952 configuration
- Dropped incorrect cursor pipe on MSM8976/56
HDMI:
- Small fixes
Notes:
- Merged qcom-drivers-for-7.4 to pick up UBWC_7_0 support
(needed for Hawi/Maili) which in turn depended on
qcom-arm64-for-7.4
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Rob Clark <rob.clark@oss.qualcomm.com>
Link: https://patch.msgid.link/CACSVV02V-FOzGj71G0ZL7khkYEKWFW4q4biOZR8B8vyWy20PdQ@mail.gmail.com
190 files changed, 24780 insertions, 2894 deletions
diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 5be89c584026..2a90af67ca74 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -212,6 +212,7 @@ properties: - qcom,kryo465 - qcom,kryo468 - qcom,kryo470 + - qcom,kryo475 - qcom,kryo485 - qcom,kryo560 - qcom,kryo570 diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml index f3f3feac4ce2..335a8e1a5a9e 100644 --- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml @@ -32,6 +32,7 @@ properties: - qcom,glymur-ctcu - qcom,kaanapali-ctcu - qcom,qcs8300-ctcu + - qcom,shikra-ctcu - qcom,sm8750-ctcu - qcom,x1e80100-ctcu - const: qcom,sa8775p-ctcu diff --git a/Documentation/devicetree/bindings/arm/qcom-soc.yaml b/Documentation/devicetree/bindings/arm/qcom-soc.yaml index e7160b63d814..179aadc86a9f 100644 --- a/Documentation/devicetree/bindings/arm/qcom-soc.yaml +++ b/Documentation/devicetree/bindings/arm/qcom-soc.yaml @@ -30,7 +30,7 @@ select: contains: oneOf: - pattern: "^qcom,.*(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sar|sc|sd[amx]|sm|x1[ep])[0-9]+.*$" - - pattern: "^qcom,.*(eliza|kaanapali|glymur|hawi|mahua|maili|milos|nord|shikra).*$" + - pattern: "^qcom,.*(eliza|kaanapali|kuno|glymur|hawi|mahua|maili|milos|nord|shikra).*$" required: - compatible @@ -42,7 +42,7 @@ properties: - pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1[ep])[0-9]+(pro)?-.*$" - pattern: "^qcom,sar[0-9]+[a-z]?-.*$" - pattern: "^qcom,(sa|sc)8[0-9]+[a-z][a-z]?-.*$" - - pattern: "^qcom,(eliza|kaanapali|glymur|hawi|mahua|maili|milos|nord|shikra)-.+$" + - pattern: "^qcom,(eliza|kaanapali|kuno|glymur|hawi|mahua|maili|milos|nord|shikra)-.+$" # Legacy namings - variations of existing patterns/compatibles are OK, # but do not add completely new entries to these: diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index ff8a35df7862..5c0414d4af9b 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -86,7 +86,10 @@ properties: - items: - enum: + - asus,zenbook-a14-ux3407na - asus,zenbook-a16-ux3607oa + - hp,elitebook-x-g2q + - lenovo,yoga-slim7x-gen11 - qcom,glymur-crd - const: qcom,glymur @@ -177,6 +180,11 @@ properties: - items: - enum: + - qcom,kuno-idp + - const: qcom,kuno + + - items: + - enum: - qcom,mahua-crd - const: qcom,mahua @@ -402,6 +410,12 @@ properties: - xiaomi,sagit - const: qcom,msm8998 + - items: + - enum: + - qcom,iq10-rrd + - qcom,sa8797p-ride + - const: qcom,nord + - description: Qualcomm Technologies, Inc. Robotics RB1 items: - enum: @@ -433,6 +447,7 @@ properties: - items: - enum: - arduino,monza + - qcom,monaco-ac-evk - qcom,monaco-evk - qcom,qcs8300-ride - const: qcom,qcs8300 diff --git a/Documentation/devicetree/bindings/clock/qcom,milos-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,milos-camcc.yaml index 707b25d2c11e..0655cea72524 100644 --- a/Documentation/devicetree/bindings/clock/qcom,milos-camcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,milos-camcc.yaml @@ -8,16 +8,23 @@ title: Qualcomm Camera Clock & Reset Controller on Milos maintainers: - Luca Weiss <luca.weiss@fairphone.com> + - Taniya Das <taniya.das@oss.qualcomm.com> description: | Qualcomm camera clock control module provides the clocks, resets and power domains on Milos. - See also: include/dt-bindings/clock/qcom,milos-camcc.h + See also: + include/dt-bindings/clock/qcom,eliza-cambistmclkcc.h + include/dt-bindings/clock/qcom,eliza-camcc.h + include/dt-bindings/clock/qcom,milos-camcc.h properties: compatible: - const: qcom,milos-camcc + enum: + - qcom,eliza-cambistmclkcc + - qcom,eliza-camcc + - qcom,milos-camcc clocks: items: @@ -29,12 +36,33 @@ properties: items: - description: Interconnect path to enable the MultiMedia NoC + power-domains: + items: + - description: CX power domain + - description: MX power domain + + required-opps: + items: + - description: CX performance point + - description: MX performance point + required: - compatible - clocks + - power-domains + - required-opps allOf: - $ref: qcom,gcc.yaml# + - if: + not: + properties: + compatible: + contains: + const: qcom,eliza-cambistmclkcc + then: + required: + - '#power-domain-cells' unevaluatedProperties: false @@ -43,6 +71,7 @@ examples: #include <dt-bindings/clock/qcom,milos-gcc.h> #include <dt-bindings/interconnect/qcom,icc.h> #include <dt-bindings/interconnect/qcom,milos-rpmh.h> + #include <dt-bindings/power/qcom,rpmhpd.h> clock-controller@adb0000 { compatible = "qcom,milos-camcc"; reg = <0x0adb0000 0x40000>; @@ -51,6 +80,12 @@ examples: <&gcc GCC_CAMERA_AHB_CLK>; interconnects = <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS &mmss_noc SLAVE_MNOC_HF_MEM_NOC QCOM_ICC_TAG_ALWAYS>; + + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MX>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; diff --git a/Documentation/devicetree/bindings/clock/qcom,milos-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,milos-videocc.yaml index 14c31efe1308..08898f1d74e4 100644 --- a/Documentation/devicetree/bindings/clock/qcom,milos-videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,milos-videocc.yaml @@ -8,16 +8,21 @@ title: Qualcomm Video Clock & Reset Controller on Milos maintainers: - Luca Weiss <luca.weiss@fairphone.com> + - Taniya Das <taniya.das@oss.qualcomm.com> description: | Qualcomm video clock control module provides the clocks, resets and power domains on Milos. - See also: include/dt-bindings/clock/qcom,milos-videocc.h + See also: + include/dt-bindings/clock/qcom,eliza-videocc.h + include/dt-bindings/clock/qcom,milos-videocc.h properties: compatible: - const: qcom,milos-videocc + enum: + - qcom,eliza-videocc + - qcom,milos-videocc clocks: items: @@ -26,9 +31,22 @@ properties: - description: Sleep clock source - description: Video AHB clock from GCC + power-domains: + items: + - description: CX power domain + - description: MX power domain + + required-opps: + items: + - description: CX performance point + - description: MX performance point + required: - compatible - clocks + - power-domains + - required-opps + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# @@ -38,6 +56,7 @@ unevaluatedProperties: false examples: - | #include <dt-bindings/clock/qcom,milos-gcc.h> + #include <dt-bindings/power/qcom,rpmhpd.h> clock-controller@aaf0000 { compatible = "qcom,milos-videocc"; reg = <0x0aaf0000 0x10000>; @@ -45,6 +64,12 @@ examples: <&bi_tcxo_ao_div2>, <&sleep_clk>, <&gcc GCC_VIDEO_AHB_CLK>; + + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MX>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml index 2a2d37c59442..7eca456211e4 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml @@ -15,6 +15,7 @@ description: | domains on Qualcomm SoCs. See also: + include/dt-bindings/clock/qcom,eliza-gpucc.h include/dt-bindings/clock/qcom,glymur-gpucc.h include/dt-bindings/clock/qcom,kaanapali-gpucc.h include/dt-bindings/clock/qcom,milos-gpucc.h @@ -32,6 +33,7 @@ description: | properties: compatible: enum: + - qcom,eliza-gpucc - qcom,glymur-gpucc - qcom,kaanapali-gpucc - qcom,milos-gpucc @@ -75,6 +77,7 @@ allOf: compatible: contains: enum: + - qcom,eliza-gpucc - qcom,sm8750-gpucc then: required: diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Documentation/devicetree/bindings/display/msm/gmu.yaml index 9e459f12ce3f..07f0e547b43c 100644 --- a/Documentation/devicetree/bindings/display/msm/gmu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml @@ -305,7 +305,9 @@ allOf: properties: compatible: contains: - const: qcom,adreno-gmu-810.0 + enum: + - qcom,adreno-gmu-810.0 + - qcom,adreno-gmu-830.1 then: properties: reg: @@ -363,7 +365,9 @@ allOf: properties: compatible: contains: - const: qcom,adreno-gmu-x285.1 + enum: + - qcom,adreno-gmu-x285.0 + - qcom,adreno-gmu-x290.1 then: properties: reg: diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml index e5efe2d35ddc..c30de7feb447 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -414,6 +414,7 @@ allOf: contains: enum: - qcom,adreno-44010000 + - qcom,adreno-44050001 - qcom,adreno-44050a01 - qcom,adreno-44070001 then: @@ -451,7 +452,9 @@ allOf: - qcom,adreno-43050c01 - qcom,adreno-43051401 - qcom,adreno-44010000 + - qcom,adreno-44050001 - qcom,adreno-44050a01 + - qcom,adreno-44060000 - qcom,adreno-44070001 then: # Starting with A6xx, the clocks are usually defined in the GMU node diff --git a/Documentation/devicetree/bindings/display/msm/hdmi.yaml b/Documentation/devicetree/bindings/display/msm/hdmi.yaml index dfec6c3480f3..02d27ccad024 100644 --- a/Documentation/devicetree/bindings/display/msm/hdmi.yaml +++ b/Documentation/devicetree/bindings/display/msm/hdmi.yaml @@ -113,7 +113,7 @@ allOf: - const: core - const: master_iface - const: slave_iface - core-vcc-supplies: false + core-vcc-supply: false - if: properties: @@ -136,7 +136,7 @@ allOf: - const: core - const: alt_iface - const: extp - hdmi-mux-supplies: false + hdmi-mux-supply: false - if: properties: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml b/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml index 2735c78b0b67..2f0a32a3f586 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml @@ -26,6 +26,7 @@ properties: - qcom,msm8916-mdp5 - qcom,msm8917-mdp5 - qcom,msm8937-mdp5 + - qcom,msm8952-mdp5 - qcom,msm8953-mdp5 - qcom,msm8974-mdp5 - qcom,msm8976-mdp5 diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml index 037d4ad8f718..ecee5aef65a7 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -37,6 +37,7 @@ properties: - qcom,scm-ipq9574 - qcom,scm-ipq9650 - qcom,scm-kaanapali + - qcom,scm-kuno - qcom,scm-maili - qcom,scm-mdm9607 - qcom,scm-milos diff --git a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml index 21b4e04727de..f6969910bded 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml @@ -50,6 +50,7 @@ properties: - enum: - qcom,eliza-llcc-bwmon - qcom,hawi-llcc-bwmon + - qcom,milos-cpu-bwmon - qcom,qcs615-llcc-bwmon - qcom,qcs8300-llcc-bwmon - qcom,sa8775p-llcc-bwmon diff --git a/Documentation/devicetree/bindings/mmc/qcom,sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/qcom,sdhci-msm.yaml index b3fcc1673c10..5aa6b3a29ece 100644 --- a/Documentation/devicetree/bindings/mmc/qcom,sdhci-msm.yaml +++ b/Documentation/devicetree/bindings/mmc/qcom,sdhci-msm.yaml @@ -38,6 +38,7 @@ properties: - items: - enum: - qcom,eliza-sdhci + - qcom,glymur-sdhci - qcom,hawi-sdhci - qcom,ipq5018-sdhci - qcom,ipq5210-sdhci diff --git a/Documentation/devicetree/bindings/net/bluetooth/qcom,wcn6750-bt.yaml b/Documentation/devicetree/bindings/net/bluetooth/qcom,wcn6750-bt.yaml index 8606a45ac9b9..79522409d709 100644 --- a/Documentation/devicetree/bindings/net/bluetooth/qcom,wcn6750-bt.yaml +++ b/Documentation/devicetree/bindings/net/bluetooth/qcom,wcn6750-bt.yaml @@ -12,8 +12,14 @@ maintainers: properties: compatible: - enum: - - qcom,wcn6750-bt + oneOf: + - items: + - enum: + - qcom,wcn6755-bt + - const: qcom,wcn6750-bt + + - enum: + - qcom,wcn6750-bt enable-gpios: maxItems: 1 diff --git a/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml b/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml index d4aa56e2f823..929a3d60aaef 100644 --- a/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml +++ b/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml @@ -16,11 +16,17 @@ description: | properties: compatible: - enum: - - qcom,ipq8074-wifi - - qcom,ipq6018-wifi - - qcom,wcn6750-wifi - - qcom,ipq5018-wifi + oneOf: + - items: + - enum: + - qcom,wcn6755-wifi + - const: qcom,wcn6750-wifi + + - enum: + - qcom,ipq8074-wifi + - qcom,ipq6018-wifi + - qcom,wcn6750-wifi + - qcom,ipq5018-wifi reg: maxItems: 1 diff --git a/MAINTAINERS b/MAINTAINERS index 5e20f9d0dddb..66b5d688c789 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3432,6 +3432,7 @@ F: include/linux/soc/qcom/ ARM/QUALCOMM SUPPORT M: Bjorn Andersson <andersson@kernel.org> M: Konrad Dybcio <konradybcio@kernel.org> +R: Abel Vesa <abelvesa@kernel.org> L: linux-arm-msm@vger.kernel.org S: Maintained C: irc://irc.oftc.net/linux-msm diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 1c86e7e98f55..efd7bc724ee1 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -16,8 +16,11 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8096sg-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb dtb-$(CONFIG_ARCH_QCOM) += eliza-cqs-evk.dtb dtb-$(CONFIG_ARCH_QCOM) += eliza-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM) += glymur-asus-zenbook-a14-ux3407na.dtb dtb-$(CONFIG_ARCH_QCOM) += glymur-asus-zenbook-a16-ux3607oa.dtb dtb-$(CONFIG_ARCH_QCOM) += glymur-crd.dtb +dtb-$(CONFIG_ARCH_QCOM) += glymur-hp-elitebook-x-g2q.dtb +dtb-$(CONFIG_ARCH_QCOM) += glymur-lenovo-yoga-slim7x.dtb dtb-$(CONFIG_ARCH_QCOM) += hamoa-iot-evk.dtb hamoa-iot-evk-el2-dtbs := hamoa-iot-evk.dtb x1-el2.dtbo @@ -61,6 +64,7 @@ dtb-$(CONFIG_ARCH_QCOM) += mahua-crd.dtb dtb-$(CONFIG_ARCH_QCOM) += milos-fairphone-fp6.dtb dtb-$(CONFIG_ARCH_QCOM) += milos-nothing-asteroids.dtb dtb-$(CONFIG_ARCH_QCOM) += monaco-arduino-monza.dtb +dtb-$(CONFIG_ARCH_QCOM) += monaco-ac-evk.dtb dtb-$(CONFIG_ARCH_QCOM) += monaco-evk.dtb monaco-evk-camera-imx577-dtbs := monaco-evk.dtb monaco-evk-camera-imx577.dtbo @@ -68,6 +72,9 @@ dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-camera-imx577.dtb monaco-evk-el2-dtbs := monaco-evk.dtb monaco-el2.dtbo +monaco-ac-evk-ifp-mezzanine-dtbs := monaco-ac-evk.dtb monaco-evk-ifp-mezzanine.dtbo +dtb-$(CONFIG_ARCH_QCOM) += monaco-ac-evk-ifp-mezzanine.dtb + dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-el2.dtb monaco-evk-ifp-mezzanine-dtbs := monaco-evk.dtb monaco-evk-ifp-mezzanine.dtbo dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-ifp-mezzanine.dtb @@ -160,6 +167,8 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-lilac.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-maple.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-poplar.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-xiaomi-sagit.dtb +dtb-$(CONFIG_ARCH_QCOM) += nord-ride.dtb +dtb-$(CONFIG_ARCH_QCOM) += nord-rrd.dtb dtb-$(CONFIG_ARCH_QCOM) += purwa-iot-evk.dtb purwa-iot-evk-el2-dtbs := purwa-iot-evk.dtb x1-el2.dtbo @@ -186,6 +195,21 @@ dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-industrial-mezzanine.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-vision-mezzanine.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs6490-thundercomm-minipc-g1iot.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs6490-thundercomm-rubikpi3.dtb + +qcs6490-thundercomm-rubikpi3-cam1-imx219-dtbs := \ + qcs6490-thundercomm-rubikpi3.dtb \ + qcs6490-thundercomm-rubikpi3-cam1-imx219.dtbo +qcs6490-thundercomm-rubikpi3-cam2-imx219-dtbs := \ + qcs6490-thundercomm-rubikpi3.dtb \ + qcs6490-thundercomm-rubikpi3-cam2-imx219.dtbo +qcs6490-thundercomm-rubikpi3-dual-imx219-dtbs := \ + qcs6490-thundercomm-rubikpi3.dtb \ + qcs6490-thundercomm-rubikpi3-cam1-imx219.dtbo \ + qcs6490-thundercomm-rubikpi3-cam2-imx219.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += qcs6490-thundercomm-rubikpi3-cam1-imx219.dtb +dtb-$(CONFIG_ARCH_QCOM) += qcs6490-thundercomm-rubikpi3-cam2-imx219.dtb +dtb-$(CONFIG_ARCH_QCOM) += qcs6490-thundercomm-rubikpi3-dual-imx219.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs6490-vicharak-axon-mini.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs8300-ride.dtb @@ -421,6 +445,9 @@ dtb-$(CONFIG_ARCH_QCOM) += talos-evk-camera-imx577.dtb talos-evk-lvds-auo,g133han01-dtbs := \ talos-evk.dtb talos-evk-lvds-auo,g133han01.dtbo dtb-$(CONFIG_ARCH_QCOM) += talos-evk-lvds-auo,g133han01.dtb +talos-evk-rpi-display-2-5in-dtbs := \ + talos-evk.dtb talos-evk-rpi-display-2-5in.dtbo +dtb-$(CONFIG_ARCH_QCOM) += talos-evk-rpi-display-2-5in.dtb x1e001de-devkit-el2-dtbs := x1e001de-devkit.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1e001de-devkit.dtb x1e001de-devkit-el2.dtb x1e78100-lenovo-thinkpad-t14s-el2-dtbs := x1e78100-lenovo-thinkpad-t14s.dtb x1-el2.dtbo diff --git a/arch/arm64/boot/dts/qcom/agatti.dtsi b/arch/arm64/boot/dts/qcom/agatti.dtsi index 590bd2432d85..e7fed60a59d9 100644 --- a/arch/arm64/boot/dts/qcom/agatti.dtsi +++ b/arch/arm64/boot/dts/qcom/agatti.dtsi @@ -1572,12 +1572,15 @@ }; }; - usb: usb@4ef8800 { - compatible = "qcom,qcm2290-dwc3", "qcom,dwc3"; - reg = <0x0 0x04ef8800 0x0 0x400>; - interrupts-extended = <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, + usb: usb@4e00000 { + compatible = "qcom,qcm2290-dwc3", "qcom,snps-dwc3"; + reg = <0x0 0x04e00000 0x0 0xfc100>; + + interrupts-extended = <&intc GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, <&mpm 12 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hs_phy_irq", + interrupt-names = "dwc_usb3", + "hs_phy_irq", "ss_phy_irq"; clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, @@ -1595,7 +1598,8 @@ assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, <&gcc GCC_USB30_PRIM_MASTER_CLK>; - assigned-clock-rates = <19200000>, <133333333>; + assigned-clock-rates = <19200000>, + <133333333>; resets = <&gcc GCC_USB30_PRIM_BCR>; power-domains = <&gcc GCC_USB30_PRIM_GDSC>; @@ -1606,48 +1610,42 @@ &config_noc SLAVE_USB3 RPM_ALWAYS_TAG>; interconnect-names = "usb-ddr", "apps-usb"; - wakeup-source; - #address-cells = <2>; - #size-cells = <2>; - ranges; + iommus = <&apps_smmu 0x120 0x0>; - status = "disabled"; + phys = <&usb_hsphy>, + <&usb_qmpphy>; + phy-names = "usb2-phy", + "usb3-phy"; - usb_dwc3: usb@4e00000 { - compatible = "snps,dwc3"; - reg = <0x0 0x04e00000 0x0 0xcd00>; - interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; - phys = <&usb_hsphy>, <&usb_qmpphy>; - phy-names = "usb2-phy", "usb3-phy"; - iommus = <&apps_smmu 0x120 0x0>; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - snps,has-lpm-erratum; - snps,hird-threshold = /bits/ 8 <0x10>; - snps,usb3_lpm_capable; - snps,parkmode-disable-ss-quirk; - maximum-speed = "super-speed"; - dr_mode = "otg"; - usb-role-switch; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,parkmode-disable-ss-quirk; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,has-lpm-erratum; + snps,usb3_lpm_capable; - ports { - #address-cells = <1>; - #size-cells = <0>; + usb-role-switch; + wakeup-source; - port@0 { - reg = <0>; + status = "disabled"; - usb_dwc3_hs: endpoint { - }; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_dwc3_hs: endpoint { }; + }; - port@1 { - reg = <1>; + port@1 { + reg = <1>; - usb_dwc3_ss: endpoint { - remote-endpoint = <&usb_qmpphy_usb_ss_in>; - }; + usb_dwc3_ss: endpoint { + remote-endpoint = <&usb_qmpphy_usb_ss_in>; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/eliza-cqs-som.dtsi b/arch/arm64/boot/dts/qcom/eliza-cqs-som.dtsi index 5ef6c51618bf..03f9192324c7 100644 --- a/arch/arm64/boot/dts/qcom/eliza-cqs-som.dtsi +++ b/arch/arm64/boot/dts/qcom/eliza-cqs-som.dtsi @@ -374,6 +374,14 @@ vdd3-supply = <&vreg_l17b>; }; +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/eliza/gen71700_zap.mbn"; +}; + &remoteproc_adsp { firmware-name = "qcom/eliza/adsp.mbn", "qcom/eliza/adsp_dtb.mbn"; @@ -381,6 +389,13 @@ status = "okay"; }; +&remoteproc_cdsp { + firmware-name = "qcom/eliza/cdsp.mbn", + "qcom/eliza/cdsp_dtb.mbn"; + + status = "okay"; +}; + &sdhc_1 { vmmc-supply = <&vreg_l12b>; vqmmc-supply = <&vreg_l1d>; diff --git a/arch/arm64/boot/dts/qcom/eliza-evk.dtsi b/arch/arm64/boot/dts/qcom/eliza-evk.dtsi index 2fc945658300..6c5cc47a183e 100644 --- a/arch/arm64/boot/dts/qcom/eliza-evk.dtsi +++ b/arch/arm64/boot/dts/qcom/eliza-evk.dtsi @@ -12,6 +12,19 @@ stdout-path = "serial0:115200n8"; }; + gpio-keys { + compatible = "gpio-keys"; + + key-volume-up { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + gpios = <&pm7550_gpios 6 GPIO_ACTIVE_LOW>; + debounce-interval = <10>; + linux,can-disable; + wakeup-source; + }; + }; + pmic-glink { compatible = "qcom,eliza-pmic-glink", "qcom,sm8550-pmic-glink", @@ -49,6 +62,121 @@ }; }; }; + + vreg_0p9: regulator-0v9 { + compatible = "regulator-fixed"; + regulator-name = "VREG_0P9"; + + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + }; + + vreg_1p8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "VREG_1P8"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vreg_pcie_m_3p3: regulator-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "vreg_3p3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio_expander1 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + connector-0 { + compatible = "pcie-m2-e-connector"; + vpcie3v3-supply = <&vreg_pcie_m_3p3>; + w-disable1-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; + w-disable2-gpios = <&pm8550vs_g_gpios 4 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&m2_w_disable1>, <&m2_w_disable2>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + m2_e_pcie_ep: endpoint@0 { + reg = <0>; + remote-endpoint = <&pcieport0_ep>; + }; + }; + + port@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + m2_e_uart_ep: endpoint@0 { + reg = <0>; + remote-endpoint = <&uart5_ep>; + }; + }; + }; + }; +}; + +&i2c4 { + pinctrl-0 = <&qup_i2c4_data_clk>; + pinctrl-names = "default"; + + clock-frequency = <400000>; + + status = "okay"; + + gpio_expander1: gpio@3c { + compatible = "ti,tca9538"; + #gpio-cells = <2>; + gpio-controller; + reg = <0x3c>; + }; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l1k>; + vdda-pll-supply = <&vreg_l3k>; + + status = "okay"; +}; + +&pcie0_port0 { + wake-gpios = <&tlmm 114 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 78 GPIO_ACTIVE_LOW>; + + port { + pcieport0_ep: endpoint { + remote-endpoint = <&m2_e_pcie_ep>; + }; + }; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; }; &pm7550ba_eusb2_repeater { @@ -77,6 +205,91 @@ }; }; +&pcie1 { + iommu-map = <0x0 &apps_smmu 0x1400 0x0 0x1>, + <0x100 &apps_smmu 0x1401 0x0 0x1>, + <0x208 &apps_smmu 0x1402 0x0 0x1>, + <0x210 &apps_smmu 0x1403 0x0 0x1>, + <0x218 &apps_smmu 0x1404 0x0 0x1>, + <0x300 &apps_smmu 0x1405 0x0 0x1>, + <0x400 &apps_smmu 0x1406 0x0 0x1>, + <0x500 &apps_smmu 0x1407 0x0 0x1>, + <0x501 &apps_smmu 0x1408 0x0 0x1>; + + status = "okay"; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l1k>; + vdda-pll-supply = <&vreg_l3k>; + + status = "okay"; +}; + +&pcie1_port0 { + wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; + /* Same GPIO is used for both PERST# and resx-gpio */ + + tc9563: pcie@0,0 { + compatible = "pci1179,0623"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x2 0xff>; + + vddc-supply = <&vreg_0p9>; + vdd18-supply = <&vreg_1p8>; + vdd09-supply = <&vreg_0p9>; + vddio1-supply = <&vreg_1p8>; + vddio2-supply = <&vreg_1p8>; + vddio18-supply = <&vreg_1p8>; + + i2c-parent = <&i2c4 0x77>; + + resx-gpios = <&tlmm 54 GPIO_ACTIVE_LOW>; + + pcie@1,0 { + reg = <0x20800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x3 0xff>; + }; + + pcie@2,0 { + reg = <0x21000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x4 0xff>; + }; + + pcie@3,0 { + reg = <0x21800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + bus-range = <0x5 0xff>; + + ethernet@0,0 { + reg = <0x50000 0x0 0x0 0x0 0x0>; + }; + + ethernet@0,1 { + reg = <0x50100 0x0 0x0 0x0 0x0>; + }; + }; + }; +}; + &uart13 { compatible = "qcom,geni-debug-uart"; @@ -110,3 +323,33 @@ status = "okay"; }; + +&uart5 { + status = "okay"; + + port { + uart5_ep: endpoint { + remote-endpoint = <&m2_e_uart_ep>; + }; + }; +}; + +&pm8550vs_g_gpios { + m2_w_disable2: m2-w-disable2-state { + pins = "gpio4"; + function = "normal"; + input-disable; + output-enable; + bias-disable; + power-source = <2>; + }; +}; + +&tlmm { + m2_w_disable1: m2-w-disable1-state { + pins = "gpio35"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/eliza-mtp.dts b/arch/arm64/boot/dts/qcom/eliza-mtp.dts index 868ae6c34830..ee05192adcfb 100644 --- a/arch/arm64/boot/dts/qcom/eliza-mtp.dts +++ b/arch/arm64/boot/dts/qcom/eliza-mtp.dts @@ -422,6 +422,14 @@ }; }; +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/eliza/gen71700_zap.mbn"; +}; + &mdss { status = "okay"; }; @@ -484,6 +492,26 @@ status = "okay"; }; +&remoteproc_cdsp { + firmware-name = "qcom/eliza/cdsp.mbn", + "qcom/eliza/cdsp_dtb.mbn"; + + status = "okay"; +}; + +&sdhc_2 { + vmmc-supply = <&vreg_l13b>; + vqmmc-supply = <&vreg_l23b>; + + cd-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&sdc2_default>, <&sd_cd>; + pinctrl-1 = <&sdc2_sleep>, <&sd_cd>; + pinctrl-names = "default", "sleep"; + + status = "okay"; +}; + &spi8 { status = "okay"; @@ -534,6 +562,12 @@ bias-pull-down; }; + sd_cd: sd-cd-state { + pins = "gpio58"; + function = "gpio"; + bias-pull-up; + }; + ts_irq: ts-irq-state { pins = "gpio13"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi index 66ea4aaafd73..a8042291bd07 100644 --- a/arch/arm64/boot/dts/qcom/eliza.dtsi +++ b/arch/arm64/boot/dts/qcom/eliza.dtsi @@ -4,9 +4,13 @@ */ #include <dt-bindings/clock/qcom,dsi-phy-28nm.h> +#include <dt-bindings/clock/qcom,eliza-cambistmclkcc.h> +#include <dt-bindings/clock/qcom,eliza-camcc.h> #include <dt-bindings/clock/qcom,eliza-dispcc.h> #include <dt-bindings/clock/qcom,eliza-gcc.h> +#include <dt-bindings/clock/qcom,eliza-gpucc.h> #include <dt-bindings/clock/qcom,eliza-tcsr.h> +#include <dt-bindings/clock/qcom,eliza-videocc.h> #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/dma/qcom-gpi.h> #include <dt-bindings/gpio/gpio.h> @@ -20,6 +24,7 @@ #include <dt-bindings/soc/qcom,gpr.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> +#include <dt-bindings/thermal/thermal.h> / { interrupt-parent = <&intc>; @@ -636,6 +641,30 @@ }; }; + smp2p-cdsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + smp2p_cdsp_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_cdsp_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + soc: soc@0 { compatible = "simple-bus"; @@ -650,12 +679,12 @@ clocks = <&bi_tcxo_div2>, <&sleep_clk>, - <0>, - <0>, + <&pcie0_phy>, + <&pcie1_phy>, <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>, - <0>; + <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; power-domains = <&rpmhpd RPMHPD_CX>; @@ -1787,6 +1816,23 @@ #interconnect-cells = <2>; }; + cambistmclkcc: clock-controller@1760000 { + compatible = "qcom,eliza-cambistmclkcc"; + reg = <0x0 0x01760000 0x0 0x6000>; + + clocks = <&bi_tcxo_div2>, + <&sleep_clk>, + <&gcc GCC_CAM_BIST_MCLK_AHB_CLK>; + + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MX>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + + #clock-cells = <1>; + #reset-cells = <1>; + }; + mmss_noc: interconnect@1780000 { compatible = "qcom,eliza-mmss-noc"; reg = <0x0 0x01780000 0x0 0x7d800>; @@ -1794,6 +1840,369 @@ #interconnect-cells = <2>; }; + pcie0: pcie@1c00000 { + device_type = "pci"; + compatible = "qcom,eliza-pcie", "qcom,pcie-sm8550"; + reg = <0x0 0x01c00000 0x0 0x3000>, + <0x0 0x40000000 0x0 0xf1d>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x1000>, + <0x0 0x40100000 0x0 0x100000>, + <0x0 0x01c03000 0x0 0x1000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x3d00000>; + + interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 537 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 540 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, + <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ddrss_sf_tbu", + "noc_aggr", + "cnoc_sf_axi"; + + resets = <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; + reset-names = "pci", + "link_down"; + + interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "pcie-mem", + "cpu-pcie"; + + power-domains = <&gcc GCC_PCIE_0_GDSC>; + + operating-points-v2 = <&pcie0_opp_table>; + + iommu-map = <0x0 &apps_smmu 0x1480 0x0 0x1>, + <0x100 &apps_smmu 0x1481 0x0 0x1>; + + interrupt-map = <0 0 0 1 &intc 0 0 0 564 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 565 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 566 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 567 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + #interrupt-cells = <1>; + + linux,pci-domain = <0>; + bus-range = <0x0 0xff>; + + dma-coherent; + + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + status = "disabled"; + + pcie0_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* 2.5 GT/s x1 */ + opp-2500000-1 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <250000 1>; + opp-level = <1>; + }; + + /* 5 GT/s x1 */ + opp-5000000-2 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + opp-level = <2>; + }; + + /* 8 GT/s x1 */ + opp-8000000-3 { + opp-hz = /bits/ 64 <8000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <984500 1>; + opp-level = <3>; + }; + + }; + + pcie0_port0: pcie@0 { + compatible = "pciclass,0604"; + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + phys = <&pcie0_phy>; + }; + }; + + pcie0_phy: phy@1c06000 { + compatible = "qcom,eliza-qmp-gen3x1-pcie-phy"; + reg = <0x0 0x01c06000 0x0 0x2000>; + + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&tcsr TCSR_PCIE_0_CLKREF_EN>, + <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_PIPE_DIV2_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; + + assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + resets = <&gcc GCC_PCIE_0_PHY_BCR>, + <&gcc GCC_PCIE_0_NOCSR_COM_PHY_BCR>; + reset-names = "phy", + "phy_nocsr"; + + power-domains = <&gcc GCC_PCIE_0_PHY_GDSC>; + + #clock-cells = <0>; + clock-output-names = "pcie0_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + + pcie1: pcie@1c08000 { + device_type = "pci"; + compatible = "qcom,eliza-pcie", "qcom,pcie-sm8550"; + reg = <0x0 0x01c08000 0x0 0x3000>, + <0x0 0x44000000 0x0 0xf1d>, + <0x0 0x44000f20 0x0 0xa8>, + <0x0 0x44001000 0x0 0x1000>, + <0x0 0x44100000 0x0 0x100000>, + <0x0 0x01c0b000 0x0 0x1000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x44200000 0x0 0x100000>, + <0x02000000 0x0 0x44300000 0x0 0x44300000 0x0 0x3d00000>, + <0x43000000 0x4 0x00000000 0x4 0x00000000 0x3 0x00000000>; + + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + clocks = <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, + <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ddrss_sf_tbu", + "noc_aggr", + "cnoc_sf_axi"; + + resets = <&gcc GCC_PCIE_1_BCR>, + <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; + reset-names = "pci", + "link_down"; + + interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_main SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "pcie-mem", + "cpu-pcie"; + + power-domains = <&gcc GCC_PCIE_1_GDSC>; + + operating-points-v2 = <&pcie1_opp_table>; + + iommu-map = <0x0 &apps_smmu 0x1400 0x0 0x1>, + <0x100 &apps_smmu 0x1401 0x0 0x1>; + + interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + #interrupt-cells = <1>; + + linux,pci-domain = <1>; + bus-range = <0x0 0xff>; + + dma-coherent; + + pinctrl-0 = <&pcie1_default_state>; + pinctrl-names = "default"; + + status = "disabled"; + + pcie1_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* 2.5 GT/s x1 */ + opp-2500000-1 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <250000 1>; + opp-level = <1>; + }; + + /* 2.5 GT/s x2 */ + opp-5000000-1 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + opp-level = <1>; + }; + + /* 5 GT/s x1 */ + opp-5000000-2 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + opp-level = <2>; + }; + + /* 5 GT/s x2 */ + opp-10000000-2 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1000000 1>; + opp-level = <2>; + }; + + /* 8 GT/s x1 */ + opp-8000000-3 { + opp-hz = /bits/ 64 <8000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <984500 1>; + opp-level = <3>; + }; + + /* 8 GT/s x2 */ + opp-16000000-3 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1969000 1>; + opp-level = <3>; + }; + + }; + + pcie1_port0: pcie@0 { + compatible = "pciclass,0604"; + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + phys = <&pcie1_phy>; + }; + }; + + pcie1_phy: phy@1c0e000 { + compatible = "qcom,eliza-qmp-gen3x2-pcie-phy"; + reg = <0x0 0x01c0e000 0x0 0x2000>; + + clocks = <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&tcsr TCSR_PCIE_1_CLKREF_EN>, + <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK>, + <&gcc GCC_PCIE_1_PIPE_DIV2_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; + + assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + resets = <&gcc GCC_PCIE_1_PHY_BCR>, + <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>; + reset-names = "phy", + "phy_nocsr"; + + power-domains = <&gcc GCC_PCIE_1_PHY_GDSC>; + + #clock-cells = <0>; + clock-output-names = "pcie1_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + ufs_mem_phy: phy@1d80000 { compatible = "qcom,eliza-qmp-ufs-phy", "qcom,sm8650-qmp-ufs-phy"; @@ -2893,6 +3302,98 @@ }; }; + adreno_smmu: iommu@3da0000 { + compatible = "qcom,eliza-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x03da0000 0x0 0x40000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + clock-names = "hlos"; + power-domains = <&gpucc GPU_CC_CX_GDSC>; + dma-coherent; + }; + + gpucc: clock-controller@3d90000 { + compatible = "qcom,eliza-gpucc"; + reg = <0x0 0x03d90000 0x0 0xa000>; + + clocks = <&bi_tcxo_div2>, + <&gcc GCC_GPU_GPLL0_CPH_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CPH_CLK_SRC>; + + power-domains = <&rpmhpd RPMHPD_MX>, + <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + videocc: clock-controller@aaf0000 { + compatible = "qcom,eliza-videocc"; + reg = <0x0 0xaaf0000 0x0 0x10000>; + + clocks = <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>, + <&gcc GCC_VIDEO_AHB_CLK>; + + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MX>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + camcc: clock-controller@ade0000 { + compatible = "qcom,eliza-camcc"; + reg = <0x0 0x0ade0000 0x0 0x20000>; + + clocks = <&bi_tcxo_div2>, + <&sleep_clk>, + <&gcc GCC_CAMERA_AHB_CLK>; + + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MX>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + dispcc: clock-controller@af00000 { compatible = "qcom,eliza-dispcc"; reg = <0x0 0x0af00000 0x0 0x20000>; @@ -3079,6 +3580,52 @@ gpio-ranges = <&tlmm 0 0 184>; wakeup-parent = <&pdc>; + pcie0_default_state: pcie0-default-state { + perst-pins { + pins = "gpio78"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + clkreq-pins { + pins = "gpio80"; + function = "pcie0_clk_req_n"; + drive-strength = <2>; + bias-pull-up; + }; + + wake-pins { + pins = "gpio114"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie1_default_state: pcie1-default-state { + perst-pins { + pins = "gpio54"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + clkreq-pins { + pins = "gpio52"; + function = "pcie1_clk_req_n"; + drive-strength = <2>; + bias-pull-up; + }; + + wake-pins { + pins = "gpio53"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + qup_i2c0_data_clk: qup-i2c0-data-clk-state { pins = "gpio28", "gpio29"; function = "qup1_se0"; @@ -3975,6 +4522,209 @@ qcom,bcm-voters = <&apps_bcm_voter>; #interconnect-cells = <2>; }; + + remoteproc_cdsp: remoteproc@32300000 { + compatible = "qcom,eliza-cdsp-pas"; + reg = <0x0 0x32300000 0x0 0x10000>; + + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MX>, + <&rpmhpd RPMHPD_NSP>; + power-domain-names = "cx", + "mx", + "nsp"; + + interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>, <&global_sync_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_cdsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "cdsp"; + qcom,remote-pid = <5>; + }; + }; + + gpu: gpu@3d00000 { + compatible = "qcom,adreno-43020100", "qcom,adreno"; + reg = <0x0 0x03d00000 0x0 0x40000>, + <0x0 0x03d9e000 0x0 0x1000>, + <0x0 0x03d61000 0x0 0x800>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; + + iommus = <&adreno_smmu 0x0 0x0>; + + operating-points-v2 = <&gpu_opp_table>; + qcom,gmu = <&gmu>; + #cooling-cells = <2>; + interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "gfx-mem"; + + status = "disabled"; + + gpu_zap_shader: zap-shader { + memory-region = <&gpu_micro_code_mem>; + }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2-adreno", + "operating-points-v2"; + + opp-259000000 { + opp-hz = /bits/ 64 <259000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; + opp-peak-kBps = <781250>; + qcom,opp-acd-level = <0xc82f5ffd>; + }; + + opp-345000000 { + opp-hz = /bits/ 64 <345000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + opp-peak-kBps = <2136718>; + qcom,opp-acd-level = <0xc82f5ffd>; + }; + + opp-515000000 { + opp-hz = /bits/ 64 <515000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + opp-peak-kBps = <5285156>; + qcom,opp-acd-level = <0xc02d5ffd>; + }; + + opp-645000000 { + opp-hz = /bits/ 64 <645000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + opp-peak-kBps = <6074218>; + qcom,opp-acd-level = <0x882f5ffd>; + }; + + opp-724000000 { + opp-hz = /bits/ 64 <724000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; + opp-peak-kBps = <6671875>; + qcom,opp-acd-level = <0xa82d5ffd>; + }; + + opp-796000000 { + opp-hz = /bits/ 64 <796000000>; + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; + opp-peak-kBps = <10687500>; + qcom,opp-acd-level = <0x882d5ffd>; + }; + + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; + opp-peak-kBps = <10687500>; + qcom,opp-acd-level = <0x882d5ffd>; + }; + + opp-975000000 { + opp-hz = /bits/ 64 <975000000>; + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; + opp-peak-kBps = <12449218>; + qcom,opp-acd-level = <0x882c5ffd>; + }; + + opp-1075000000 { + opp-hz = /bits/ 64 <1075000000>; + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; + opp-peak-kBps = <16500000>; + qcom,opp-acd-level = <0xa82a5ffd>; + }; + + opp-1150000000 { + opp-hz = /bits/ 64 <1150000000>; + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L2>; + opp-peak-kBps = <16500000>; + qcom,opp-acd-level = <0xa8295ffd>; + }; + }; + }; + + gmu: gmu@3d6a000 { + compatible = "qcom,adreno-gmu-722.0", "qcom,adreno-gmu"; + reg = <0x0 0x03d6a000 0x0 0x35000>, + <0x0 0x03d50000 0x0 0x10000>, + <0x0 0x0b290000 0x0 0x10000>; + reg-names = "gmu", "rscc", "gmu_pdc"; + + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hfi", "gmu"; + + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_GEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_DEMET_CLK>; + clock-names = "ahb", + "gmu", + "cxo", + "axi", + "memnoc", + "hub", + "demet"; + + power-domains = <&gpucc GPU_CC_CX_GDSC>, + <&gpucc GPU_CC_GX_GDSC>; + power-domain-names = "cx", + "gx"; + + iommus = <&adreno_smmu 0x5 0x0>; + qcom,qmp = <&aoss_qmp>; + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-220000000 { + opp-hz = /bits/ 64 <220000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + }; + + opp-550000000 { + opp-hz = /bits/ 64 <550000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + }; + }; + }; }; thermal-zones { @@ -4284,7 +5034,7 @@ thermal-sensors = <&tsens1 8>; trips { - gpu-alert { + gpuss0_alert0: gpu-alert { temperature = <95000>; hysteresis = <1000>; type = "passive"; @@ -4302,6 +5052,13 @@ type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&gpuss0_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; gpuss1-thermal { @@ -4310,7 +5067,7 @@ thermal-sensors = <&tsens1 9>; trips { - gpu-alert { + gpuss1_alert0: gpu-alert { temperature = <95000>; hysteresis = <1000>; type = "passive"; @@ -4328,6 +5085,13 @@ type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&gpuss1_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; modem0-thermal { diff --git a/arch/arm64/boot/dts/qcom/glymur-asus-zenbook-a14-ux3407na.dts b/arch/arm64/boot/dts/qcom/glymur-asus-zenbook-a14-ux3407na.dts new file mode 100644 index 000000000000..e96e65a0c5b4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/glymur-asus-zenbook-a14-ux3407na.dts @@ -0,0 +1,1140 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +/dts-v1/; + +#include "glymur.dtsi" + +#include "pmcx0102.dtsi" +#include "pmh0101.dtsi" +#include "pmh0110-glymur.dtsi" +#include "pmh0104-glymur.dtsi" +#include "pmk8850.dtsi" +#include "smb2370.dtsi" + +#include <dt-bindings/input/gpio-keys.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> + +/ { + compatible = "asus,zenbook-a14-ux3407na", "qcom,glymur"; + model = "ASUS Zenbook A14 (UX3407NA)"; + + aliases { + i2c0 = &i2c0; + i2c5 = &i2c5; + i2c8 = &i2c8; + i2c10 = &i2c10; + i2c19 = &i2c19; + serial0 = &uart14; + }; + + clocks { + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <38400000>; + #clock-cells = <0>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&hall_int_n_default>; + pinctrl-names = "default"; + + switch-lid { + label = "lid"; + gpios = <&tlmm 92 GPIO_ACTIVE_LOW>; + linux,input-type = <EV_SW>; + linux,code = <SW_LID>; + wakeup-source; + wakeup-event-action = <EV_ACT_DEASSERTED>; + }; + }; + + hdmi-bridge { + compatible = "parade,ps185hdm"; + + pinctrl-0 = <&usb2_dp_hot_plug_detect>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_bridge_in: endpoint { + remote-endpoint = <&usb_2_qmpphy_out_dp>; + }; + }; + + port@1 { + reg = <1>; + + hdmi_bridge_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&hdmi_bridge_out>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + pinctrl-0 = <&cam_indicator_en>, + <&keyboard_cam_led>, + <&keyboard_mic_led>; + pinctrl-names = "default"; + + keyboard-camera-led { + function = LED_FUNCTION_INDICATOR; + color = <LED_COLOR_ID_ORANGE>; + gpios = <&tlmm 120 GPIO_ACTIVE_HIGH>; + default-state = "off"; + panic-indicator; + }; + + keyboard-mic-led { + function = LED_FUNCTION_MICMUTE; + color = <LED_COLOR_ID_ORANGE>; + gpios = <&tlmm 98 GPIO_ACTIVE_LOW>; + default-state = "off"; + panic-indicator; + }; + + privacy-led { + function = LED_FUNCTION_INDICATOR; + color = <LED_COLOR_ID_WHITE>; + gpios = <&tlmm 111 GPIO_ACTIVE_HIGH>; + default-state = "off"; + panic-indicator; + }; + }; + + pmic-glink { + compatible = "qcom,glymur-pmic-glink", + "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + + /* Left side display-adjacent port */ + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&usb_0_qmpphy_out>; + }; + }; + }; + }; + + /* Left side user-adjacent port */ + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in1: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in1: endpoint { + remote-endpoint = <&usb_1_qmpphy_out>; + }; + }; + }; + }; + }; + + vreg_edp: regulator-edp { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_pwr_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_misc_3p3: regulator-misc-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_MISC_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmh0110_f_e0_gpios 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&misc_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_nvme: regulator-nvme { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmh0101_gpios 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&nvme_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 94 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wcn_sw_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + reserved-memory { + linux,cma { + compatible = "shared-dma-pool"; + size = <0x0 0x10000000>; + reusable; + linux,cma-default; + }; + }; + + sound { + compatible = "qcom,glymur-sndcard"; + model = "GLYMUR-ASUS-Zenbook-A14-UX3407NA"; + + audio-routing = "SpkrLeft IN", "WSA WSA_SPK1 OUT", + "SpkrRight IN", "WSA WSA_SPK2 OUT", + "VA DMIC0", "vdd-micb", + "VA DMIC1", "vdd-micb"; + + va-dai-link { + link-name = "VA Capture"; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + codec { + sound-dai = <&left_speaker>, <&right_speaker>, + <&swr0 0>, <&lpass_wsamacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + wlan-connector { + compatible = "pcie-m2-e-connector"; + vpcie3v3-supply = <&vreg_wcn_3p3>; + vpcie1v8-supply = <&vreg_l15b0>; + + w-disable1-gpios = <&tlmm 117 GPIO_ACTIVE_LOW>; + w-disable2-gpios = <&tlmm 116 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&wcn_wlan_bt_en>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + m2_e_pcie_ep: endpoint@0 { + reg = <0>; + remote-endpoint = <&pcie4_port0_ep>; + }; + }; + + port@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + m2_e_uart_ep: endpoint@0 { + reg = <0>; + remote-endpoint = <&uart14_ep>; + }; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pmh0101-rpmh-regulators"; + qcom,pmic-id = "B_E0"; + + vreg_l1b0: ldo1 { + regulator-name = "vreg_l1b0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7b0: ldo7 { + regulator-name = "vreg_l7b0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8b0: ldo8 { + regulator-name = "vreg_l8b0"; + regulator-min-microvolt = <3304000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l15b0: ldo15 { + regulator-name = "vreg_l15b0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + /* Provides reference voltage for many undescribed components */ + regulator-always-on; + }; + + vreg_l18b0: ldo18 { + regulator-name = "vreg_l18b0"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + + /* + * This is also reference voltage for &pcie3b wake and + * reset signals. + */ + regulator-always-on; + }; + }; + + regulators-1 { + compatible = "qcom,pmcx0102-rpmh-regulators"; + qcom,pmic-id = "C_E1"; + + vreg_l1c1: ldo1 { + regulator-name = "vreg_l1c1"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2c1: ldo2 { + regulator-name = "vreg_l2c1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3c1: ldo3 { + regulator-name = "vreg_l3c1"; + regulator-min-microvolt = <936000>; + regulator-max-microvolt = <936000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4c1: ldo4 { + regulator-name = "vreg_l4c1"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-2 { + compatible = "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id = "F_E0"; + + vreg_l2f0: ldo2 { + regulator-name = "vreg_l2f0"; + regulator-min-microvolt = <936000>; + regulator-max-microvolt = <936000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3f0: ldo3 { + regulator-name = "vreg_l3f0"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-3 { + compatible = "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id = "F_E1"; + + vreg_l1f1: ldo1 { + regulator-name = "vreg_l1f1"; + regulator-min-microvolt = <904000>; + regulator-max-microvolt = <904000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2f1: ldo2 { + regulator-name = "vreg_l2f1"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4f1: ldo4 { + regulator-name = "vreg_l4f1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-4 { + compatible = "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id = "H_E0"; + + vreg_l1h0: ldo1 { + regulator-name = "vreg_l1h0"; + regulator-min-microvolt = <936000>; + regulator-max-microvolt = <936000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2h0: ldo2 { + regulator-name = "vreg_l2h0"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4h0: ldo4 { + regulator-name = "vreg_l4h0"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; +}; + +&gpu { + status = "okay"; +}; + +&gmu { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + + status = "okay"; + + touchpad@15 { + compatible = "hid-over-i2c"; + reg = <0x15>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l15b0>; + + pinctrl-0 = <&tpad_default>; + pinctrl-names = "default"; + + wakeup-source; + }; +}; + +&i2c5 { + clock-frequency = <400000>; + + status = "okay"; + + ptn3222_1: redriver@43 { + compatible = "nxp,ptn3222"; + reg = <0x43>; + + reset-gpios = <&tlmm 184 GPIO_ACTIVE_LOW>; + + vdd3v3-supply = <&vreg_l8b0>; + vdd1v8-supply = <&vreg_l15b0>; + + #phy-cells = <0>; + }; + + ptn3222_0: redriver@4f { + compatible = "nxp,ptn3222"; + reg = <0x4f>; + + reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>; + + vdd3v3-supply = <&vreg_l8b0>; + vdd1v8-supply = <&vreg_l15b0>; + + #phy-cells = <0>; + }; +}; + +&i2c8 { + clock-frequency = <400000>; + + status = "okay"; + + touchscreen@15 { + compatible = "hid-over-i2c"; + reg = <0x15>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&ts_default>; + pinctrl-names = "default"; + + wakeup-source; + }; +}; + +&i2c10 { + clock-frequency = <400000>; + + status = "okay"; + + hid@17 { + compatible = "hid-over-i2c"; + reg = <0x17>; + interrupts-extended = <&tlmm 43 IRQ_TYPE_LEVEL_LOW>; + hid-descr-addr = <0x1>; + wakeup-source; + + pinctrl-0 = <&hid_app_default>; + pinctrl-names = "default"; + }; +}; + +&i2c19 { + clock-frequency = <400000>; + + status = "okay"; + + keyboard@15 { + compatible = "hid-over-i2c"; + reg = <0x15>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>; + + wakeup-source; + + pinctrl-0 = <&kybd_default>; + pinctrl-names = "default"; + }; +}; + +&lpass_vamacro { + vdd-micb-supply = <&vreg_l1b0>; + + pinctrl-0 = <&dmic01_default>; + pinctrl-names = "default"; + + qcom,dmic-sample-rate = <2400000>; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp1 { + status = "okay"; +}; + +&mdss_dp1_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp2 { + status = "okay"; +}; + +&mdss_dp2_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp3 { + /delete-property/ #sound-dai-cells; + + pinctrl-0 = <&edp0_hpd_default>; + pinctrl-names = "default"; + + status = "okay"; + + aux-bus { + panel { + compatible = "samsung,atna40ct06", "samsung,atna33xc20"; + enable-gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>; + power-supply = <&vreg_edp>; + + pinctrl-0 = <&edp_bl_en>; + pinctrl-names = "default"; + + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + }; +}; + +&mdss_dp3_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&edp_panel_in>; +}; + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l2f1>; + vdda-pll-supply = <&vreg_l4f1>; + + status = "okay"; +}; + +&pcie3_phy { + vdda-phy-supply = <&vreg_l3c1>; + vdda-pll-supply = <&vreg_l2c1>; + + vdda-refgen0p9-supply = <&vreg_l1c1>; + vdda-refgen1p2-supply = <&vreg_l4f1>; + + status = "okay"; +}; + +&pcie3b { + vddpe-3v3-supply = <&vreg_nvme>; + + pinctrl-0 = <&pcie3b_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie3b_port0 { + reset-gpios = <&tlmm 155 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 157 GPIO_ACTIVE_LOW>; +}; + +&pcie4 { + pinctrl-0 = <&pcie4_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l1c1>; + vdda-pll-supply = <&vreg_l4f1>; + + status = "okay"; +}; + +&pcie4_port0 { + reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; +}; + +&pcie4_port0_ep { + remote-endpoint = <&m2_e_pcie_ep>; +}; + +&pmh0101_gpios { + nvme_reg_en: nvme-reg-en-state { + pins = "gpio14"; + function = "normal"; + bias-disable; + }; +}; + +&pmh0110_f_e0_gpios { + misc_3p3_reg_en: misc-3p3-reg-en-state { + pins = "gpio6"; + function = "normal"; + bias-disable; + input-disable; + output-enable; + drive-push-pull; + power-source = <1>; /* 1.8 V */ + qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; + }; +}; + +&pmk8850_rtc { + qcom,no-alarm; +}; + +&remoteproc_adsp { + firmware-name = "qcom/glymur/ASUSTeK/UX3407NA/qcadsp8480.mbn", + "qcom/glymur/ASUSTeK/UX3407NA/adsp_dtbs.elf"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/glymur/ASUSTeK/UX3407NA/qccdsp8480.mbn", + "qcom/glymur/ASUSTeK/UX3407NA/cdsp_dtbs.elf"; + + status = "okay"; +}; + +&remoteproc_soccp { + status = "okay"; +}; + +&smb2370_j_e2_eusb2_repeater { + vdd18-supply = <&vreg_l15b0>; + vdd3-supply = <&vreg_l7b0>; +}; + +&smb2370_k_e2_eusb2_repeater { + vdd18-supply = <&vreg_l15b0>; + vdd3-supply = <&vreg_l7b0>; +}; + +&swr0 { + status = "okay"; + + /* WSA8845, left */ + left_speaker: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrLeft"; + vdd-1p8-supply = <&vreg_l15b0>; + vdd-io-supply = <&vreg_l18b0>; + qcom,port-mapping = <1 2 3 7 12 14>; + }; + + /* WSA8845, right */ + right_speaker: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrRight"; + vdd-1p8-supply = <&vreg_l15b0>; + vdd-io-supply = <&vreg_l18b0>; + qcom,port-mapping = <4 5 6 7 13 15>; + }; +}; + +&tcsr { + vdda-qrefrpt0-0p9-supply = <&vreg_l2f1>; + vdda-qrefrpt1-0p9-supply = <&vreg_l2f1>; + vdda-qrefrpt2-0p9-supply = <&vreg_l2f1>; + vdda-qrefrpt3-0p9-supply = <&vreg_l2h0>; + vdda-qrefrpt4-0p9-supply = <&vreg_l2h0>; + vdda-qrefrx0-0p9-supply = <&vreg_l2f1>; + vdda-qrefrx1-0p9-supply = <&vreg_l2f1>; + vdda-qrefrx2-0p9-supply = <&vreg_l2f1>; + vdda-qrefrx4-0p9-supply = <&vreg_l2h0>; + vdda-qrefrx5-0p9-supply = <&vreg_l3f0>; + vdda-qreftx0-0p9-supply = <&vreg_l3f0>; + vdda-qreftx0-1p2-supply = <&vreg_l4h0>; + vdda-qreftx1-0p9-supply = <&vreg_l1f1>; + vdda-refgen3-0p9-supply = <&vreg_l2f0>; + vdda-refgen3-1p2-supply = <&vreg_l4h0>; + vdda-refgen4-0p9-supply = <&vreg_l1f1>; + vdda-refgen4-1p2-supply = <&vreg_l4f1>; +}; + +&tlmm { + gpio-reserved-ranges = <4 4>, /* EC Secure */ + <10 2>, /* OOB UART */ + <44 4>, /* TPM */ + <65 1>, /* EC reset */ + <90 2>; /* TPM */ + + tpad_default: tpad-default-state { + pins = "gpio3"; + function = "gpio"; + bias-disable; + }; + + edp_bl_en: edp-bl-en-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + hid_app_default: hid-app-default-state { + pins = "gpio43"; + function = "gpio"; + bias-disable; + }; + + ts_default: ts-default-state { + reset-n-pins { + pins = "gpio48"; + function = "gpio"; + bias-disable; + }; + + int-pins { + pins = "gpio51"; + function = "gpio"; + bias-disable; + }; + }; + + kybd_default: kybd-default-state { + pins = "gpio67"; + function = "gpio"; + bias-disable; + }; + + edp_pwr_en: edp-pwr-en-state { + pins = "gpio70"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + hall_int_n_default: hall-int-n-state { + pins = "gpio92"; + function = "gpio"; + bias-disable; + }; + + wcn_sw_en: wcn-sw-en-state { + pins = "gpio94"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + keyboard_mic_led: keyboard-mic-led-state { + pins = "gpio98"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + cam_indicator_en: cam-indicator-en-state { + pins = "gpio111"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wcn_wlan_bt_en: wcn-wlan-bt-en-state { + pins = "gpio116", "gpio117"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + edp0_hpd_default: edp0-hpd-default-state { + pins = "gpio119"; + function = "edp0_hot"; + bias-disable; + }; + + keyboard_cam_led: keyboard-cam-led-state { + pins = "gpio120"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb2_dp_hot_plug_detect: usb2-dp-hot-plug-detect-state { + pins = "gpio126"; + function = "usb2_dp"; + bias-disable; + }; + + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins = "gpio147"; + function = "pcie4_clk_req_n"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio146"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio148"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie3b_default: pcie3b-default-state { + clkreq-n-pins { + pins = "gpio156"; + function = "pcie3b_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio155"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio157"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; +}; + +&uart14 { + status = "okay"; + + port { + uart14_ep: endpoint { + remote-endpoint = <&m2_e_uart_ep>; + }; + }; +}; + +&uart21 { + status = "disabled"; +}; + +&usb_0 { + status = "okay"; +}; + +&usb_0_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_0_hsphy { + vdd-supply = <&vreg_l3f0>; + vdda12-supply = <&vreg_l4h0>; + + phys = <&smb2370_j_e2_eusb2_repeater>; + + status = "okay"; +}; + +&usb_0_qmpphy { + vdda-phy-supply = <&vreg_l3f0>; + vdda-pll-supply = <&vreg_l4h0>; + refgen-supply = <&vreg_l2f0>; + + status = "okay"; +}; + +&usb_0_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in>; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in1>; +}; + +&usb_1_hsphy { + vdd-supply = <&vreg_l3f0>; + vdda12-supply = <&vreg_l4h0>; + + phys = <&smb2370_k_e2_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply = <&vreg_l1h0>; + vdda-pll-supply = <&vreg_l4h0>; + refgen-supply = <&vreg_l2f0>; + + status = "okay"; +}; + +&usb_1_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in1>; +}; + +&usb_2_qmpphy { + vdda-phy-supply = <&vreg_l4c1>; + vdda-pll-supply = <&vreg_l4f1>; + refgen-supply = <&vreg_l4f1>; + + /delete-property/ mode-switch; + /delete-property/ orientation-switch; + + status = "okay"; + + ports { + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + /delete-node/ endpoint; + + usb_2_qmpphy_out_dp: endpoint@0 { + reg = <0>; + + data-lanes = <3 2 1 0>; + remote-endpoint = <&hdmi_bridge_in>; + }; + }; + }; +}; + +&usb_mp { + status = "okay"; +}; + +&usb_mp_hsphy0 { + vdd-supply = <&vreg_l2h0>; + vdda12-supply = <&vreg_l4h0>; + + phys = <&ptn3222_0>; + + status = "okay"; +}; + +&usb_mp_hsphy1 { + vdd-supply = <&vreg_l2h0>; + vdda12-supply = <&vreg_l4h0>; + + phys = <&ptn3222_1>; + + status = "okay"; +}; + +&usb_mp_qmpphy0 { + vdda-phy-supply = <&vreg_l2h0>; + vdda-pll-supply = <&vreg_l4h0>; + refgen-supply = <&vreg_l4f1>; + + status = "okay"; +}; + +&usb_mp_qmpphy1 { + vdda-phy-supply = <&vreg_l2h0>; + vdda-pll-supply = <&vreg_l4h0>; + refgen-supply = <&vreg_l4f1>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/glymur-asus-zenbook-a16-ux3607oa.dts b/arch/arm64/boot/dts/qcom/glymur-asus-zenbook-a16-ux3607oa.dts index 939e1a927a79..40433dc2d6cf 100644 --- a/arch/arm64/boot/dts/qcom/glymur-asus-zenbook-a16-ux3607oa.dts +++ b/arch/arm64/boot/dts/qcom/glymur-asus-zenbook-a16-ux3607oa.dts @@ -737,7 +737,7 @@ pinctrl-0 = <&dmic01_default>; pinctrl-names = "default"; - qcom,dmic-sample-rate = <4800000>; + qcom,dmic-sample-rate = <2400000>; }; &mdss { diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts index 44766a73b0d1..b8e3fedcdea8 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts @@ -29,6 +29,14 @@ link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; +&pcie3_phy { + vdda-phy-supply = <&vreg_l3c_e1_0p89>; + vdda-pll-supply = <&vreg_l2c_e1_1p14>; + + vdda-refgen0p9-supply = <&vreg_l1c_e1_0p82>; + vdda-refgen1p2-supply = <&vreg_l4f_e1_1p08>; +}; + &tcsr { vdda-qrefrpt0-0p9-supply = <&vreg_l2f_e1_0p83>; vdda-qrefrpt1-0p9-supply = <&vreg_l2f_e1_0p83>; diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi index e27c697e3170..ccdc322157e0 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi @@ -373,7 +373,7 @@ vreg_l2b_e0_2p9: ldo2 { regulator-name = "vreg_l2b_e0_2p9"; - regulator-min-microvolt = <2904000>; + regulator-min-microvolt = <1804000>; regulator-max-microvolt = <2904000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; @@ -392,10 +392,10 @@ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; - vreg_l9b_e0_2p7: ldo9 { - regulator-name = "vreg_l9b_e0_2p7"; - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2704000>; + vreg_l9b_e0_2p9: ldo9 { + regulator-name = "vreg_l9b_e0_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; @@ -963,7 +963,8 @@ &tlmm { gpio-reserved-ranges = <4 4>, /* EC TZ Secure I3C */ <10 2>, /* OOB UART */ - <44 4>; /* Security SPI (TPM) */ + <44 4>, /* Security SPI (TPM) */ + <65 1>; /* EC reset */ edp_bl_en: edp-bl-en-state { pins = "gpio18"; diff --git a/arch/arm64/boot/dts/qcom/glymur-hp-elitebook-x-g2q.dts b/arch/arm64/boot/dts/qcom/glymur-hp-elitebook-x-g2q.dts new file mode 100644 index 000000000000..096d40e49210 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/glymur-hp-elitebook-x-g2q.dts @@ -0,0 +1,940 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +/dts-v1/; + +#include "glymur.dtsi" + +#include "pmcx0102.dtsi" +#include "pmh0101.dtsi" +#include "pmh0110-glymur.dtsi" +#include "pmh0104-glymur.dtsi" +#include "pmk8850.dtsi" +#include "smb2370.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/gpio-keys.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> + +/ { + model = "HP EliteBook X G2q 14 AI"; + compatible = "hp,elitebook-x-g2q", "qcom,glymur"; + + aliases { + i2c0 = &i2c0; + i2c8 = &i2c8; + + serial0 = &uart21; + serial1 = &uart14; + }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <38400000>; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&lid_default>; + pinctrl-names = "default"; + + switch-lid { + label = "lid"; + gpios = <&tlmm 92 GPIO_ACTIVE_LOW>; + linux,input-type = <EV_SW>; + linux,code = <SW_LID>; + wakeup-source; + wakeup-event-action = <EV_ACT_DEASSERTED>; + }; + }; + + pmic-glink { + compatible = "qcom,glymur-pmic-glink", + "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + + /* Left side port */ + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&usb_0_qmpphy_out>; + }; + }; + }; + }; + + /* Right side port */ + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in1: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in1: endpoint { + remote-endpoint = <&usb_1_qmpphy_out>; + }; + }; + }; + }; + }; + + vreg_edp_3p3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_nvme: regulator-nvme { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmh0101_gpios 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&nvme_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_wcn_0p95: regulator-wcn-0p95 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_0P95"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 94 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wcn_sw_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + sound { + compatible = "qcom,glymur-sndcard"; + model = "GLYMUR-HP-EliteBook-X-G2q"; + + audio-routing = "WooferLeft IN", "WSA WSA_SPK1 OUT", + "TweeterLeft IN", "WSA WSA_SPK2 OUT", + "WooferRight IN", "WSA2 WSA_SPK1 OUT", + "TweeterRight IN", "WSA2 WSA_SPK2 OUT", + "VA DMIC0", "vdd-micb", + "VA DMIC1", "vdd-micb"; + + va-dai-link { + link-name = "VA Capture"; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + codec { + sound-dai = <&left_woofer>, <&left_tweeter>, + <&swr0 0>, <&lpass_wsamacro 0>, + <&right_woofer>, <&right_tweeter>, + <&swr3 0>, <&lpass_wsa2macro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + vdd-supply = <&vreg_wcn_0p95>; + vddio-supply = <&vreg_l15b_e0_1p8>; + vddaon-supply = <&vreg_l15b_e0_1p8>; + vdddig-supply = <&vreg_l15b_e0_1p8>; + vddrfa1p2-supply = <&vreg_l15b_e0_1p8>; + vddrfa1p8-supply = <&vreg_l15b_e0_1p8>; + + wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; + bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&wcn_wlan_bt_en>; + pinctrl-names = "default"; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pmh0101-rpmh-regulators"; + qcom,pmic-id = "B_E0"; + + vreg_l1b_e0_1p8: ldo1 { + regulator-name = "vreg_l1b_e0_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7b_e0_3p1: ldo7 { + regulator-name = "vreg_l7b_e0_3p1"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l15b_e0_1p8: ldo15 { + regulator-name = "vreg_l15b_e0_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l18b_e0_1p2: ldo18 { + regulator-name = "vreg_l18b_e0_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-1 { + compatible = "qcom,pmcx0102-rpmh-regulators"; + qcom,pmic-id = "C_E1"; + + vreg_l1c_e1_0p91: ldo1 { + regulator-name = "vreg_l1c_e1_0p91"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-2 { + compatible = "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id = "F_E0"; + + vreg_l2f_e0_0p94: ldo2 { + regulator-name = "vreg_l2f_e0_0p94"; + regulator-min-microvolt = <936000>; + regulator-max-microvolt = <936000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3f_e0_0p91: ldo3 { + regulator-name = "vreg_l3f_e0_0p91"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-3 { + compatible = "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id = "F_E1"; + + vreg_l1f_e1_0p88: ldo1 { + regulator-name = "vreg_l1f_e1_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2f_e1_0p88: ldo2 { + regulator-name = "vreg_l2f_e1_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4f_e1_1p2: ldo4 { + regulator-name = "vreg_l4f_e1_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-4 { + compatible = "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id = "H_E0"; + + vreg_l1h_e0_0p94: ldo1 { + regulator-name = "vreg_l1h_e0_0p94"; + regulator-min-microvolt = <936000>; + regulator-max-microvolt = <936000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2h_e0_0p88: ldo2 { + regulator-name = "vreg_l2h_e0_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4h_e0_1p2: ldo4 { + regulator-name = "vreg_l4h_e0_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; +}; + +&gmu { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + + status = "okay"; + + touchpad@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + + hid-descr-addr = <0x20>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&tpad_default>; + pinctrl-names = "default"; + + wakeup-source; + }; + + keyboard@3a { + compatible = "hid-over-i2c"; + reg = <0x3a>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&kybd_default>; + pinctrl-names = "default"; + + wakeup-source; + }; +}; + +&i2c8 { + clock-frequency = <400000>; + + status = "okay"; + + touchscreen@10 { + compatible = "hid-over-i2c"; + reg = <0x10>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>; + + post-power-on-delay-ms = <200>; + + pinctrl-0 = <&ts0_default>; + pinctrl-names = "default"; + }; +}; + +&lpass_vamacro { + vdd-micb-supply = <&vreg_l1b_e0_1p8>; + + pinctrl-0 = <&dmic01_default>; + pinctrl-names = "default"; + + qcom,dmic-sample-rate = <4800000>; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp1 { + status = "okay"; +}; + +&mdss_dp1_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp3 { + /delete-property/ #sound-dai-cells; + + status = "okay"; + + aux-bus { + panel { + compatible = "samsung,atna33xc20"; + enable-gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>; + power-supply = <&vreg_edp_3p3>; + + pinctrl-0 = <&edp_bl_en>; + pinctrl-names = "default"; + + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + }; +}; + +&mdss_dp3_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&edp_panel_in>; +}; + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l2f_e1_0p88>; + vdda-pll-supply = <&vreg_l4f_e1_1p2>; + + status = "okay"; +}; + +&pcie4 { + pinctrl-0 = <&pcie4_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l1c_e1_0p91>; + vdda-pll-supply = <&vreg_l4f_e1_1p2>; + + status = "okay"; +}; + +&pcie4_port0 { + reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; +}; + +&pcie5 { + vddpe-3v3-supply = <&vreg_nvme>; + + pinctrl-0 = <&pcie5_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie5_phy { + vdda-phy-supply = <&vreg_l2f_e0_0p94>; + vdda-pll-supply = <&vreg_l4h_e0_1p2>; + + status = "okay"; +}; + +&pcie5_port0 { + reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&pmh0101_gpios { + nvme_reg_en: nvme-reg-en-state { + pins = "gpio14"; + function = "normal"; + bias-disable; + }; +}; + +&pmk8850_rtc { + qcom,no-alarm; + qcom,uefi-rtc-info; +}; + +&remoteproc_adsp { + firmware-name = "qcom/glymur/hp/elitebook-x-g2q/qcadsp8480.mbn", + "qcom/glymur/hp/elitebook-x-g2q/adsp_dtbs.elf"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/glymur/hp/elitebook-x-g2q/qccdsp8480.mbn", + "qcom/glymur/hp/elitebook-x-g2q/cdsp_dtbs.elf"; + + status = "okay"; +}; + +&remoteproc_soccp { + firmware-name = "qcom/glymur/hp/elitebook-x-g2q/soccp.mbn", + "qcom/glymur/hp/elitebook-x-g2q/soccp_dtb.mbn"; +}; + +&smb2370_j_e2_eusb2_repeater { + vdd18-supply = <&vreg_l15b_e0_1p8>; + vdd3-supply = <&vreg_l7b_e0_3p1>; +}; + +&smb2370_k_e2_eusb2_repeater { + vdd18-supply = <&vreg_l15b_e0_1p8>; + vdd3-supply = <&vreg_l7b_e0_3p1>; +}; + +&swr0 { + status = "okay"; + + /* WSA8845, left woofer */ + left_woofer: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "WooferLeft"; + vdd-1p8-supply = <&vreg_l15b_e0_1p8>; + vdd-io-supply = <&vreg_l18b_e0_1p2>; + qcom,port-mapping = <1 2 3 7 12 14>; + }; + + /* WSA8845, left tweeter */ + left_tweeter: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "TweeterLeft"; + vdd-1p8-supply = <&vreg_l15b_e0_1p8>; + vdd-io-supply = <&vreg_l18b_e0_1p2>; + qcom,port-mapping = <4 5 6 7 13 15>; + }; +}; + +&swr3 { + status = "okay"; + + /* WSA8845, right woofer */ + right_woofer: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "WooferRight"; + vdd-1p8-supply = <&vreg_l15b_e0_1p8>; + vdd-io-supply = <&vreg_l18b_e0_1p2>; + qcom,port-mapping = <1 2 3 7 12 14>; + }; + + /* WSA8845, right tweeter */ + right_tweeter: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "TweeterRight"; + vdd-1p8-supply = <&vreg_l15b_e0_1p8>; + vdd-io-supply = <&vreg_l18b_e0_1p2>; + qcom,port-mapping = <4 5 6 7 13 15>; + }; +}; + +&tcsr { + vdda-qrefrpt0-0p9-supply = <&vreg_l2f_e1_0p88>; + vdda-qrefrpt1-0p9-supply = <&vreg_l2f_e1_0p88>; + vdda-qrefrpt2-0p9-supply = <&vreg_l2f_e1_0p88>; + vdda-qrefrpt3-0p9-supply = <&vreg_l2h_e0_0p88>; + vdda-qrefrpt4-0p9-supply = <&vreg_l2h_e0_0p88>; + vdda-qrefrx0-0p9-supply = <&vreg_l2f_e1_0p88>; + vdda-qrefrx1-0p9-supply = <&vreg_l2f_e1_0p88>; + vdda-qrefrx2-0p9-supply = <&vreg_l2f_e1_0p88>; + vdda-qrefrx4-0p9-supply = <&vreg_l2h_e0_0p88>; + vdda-qrefrx5-0p9-supply = <&vreg_l3f_e0_0p91>; + vdda-qreftx0-0p9-supply = <&vreg_l3f_e0_0p91>; + vdda-qreftx0-1p2-supply = <&vreg_l4h_e0_1p2>; + vdda-qreftx1-0p9-supply = <&vreg_l1f_e1_0p88>; + vdda-refgen3-0p9-supply = <&vreg_l2f_e0_0p94>; + vdda-refgen3-1p2-supply = <&vreg_l4h_e0_1p2>; + vdda-refgen4-0p9-supply = <&vreg_l1f_e1_0p88>; + vdda-refgen4-1p2-supply = <&vreg_l4f_e1_1p2>; +}; + +&tlmm { + gpio-reserved-ranges = <4 4>, /* EC TZ Secure I3C */ + <10 2>, /* OOB UART */ + <44 4>, /* Security SPI (TPM) */ + <65 1>; /* EC reset */ + + tpad_default: tpad-default-state { + pins = "gpio3"; + function = "gpio"; + bias-disable; + }; + + edp_bl_en: edp-bl-en-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + ts0_default: ts0-default-state { + pins = "gpio51"; + function = "gpio"; + bias-disable; + }; + + kybd_default: kybd-default-state { + pins = "gpio67"; + function = "gpio"; + bias-disable; + }; + + edp_reg_en: edp-reg-en-state { + pins = "gpio70"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + lid_default: lid-default-state { + pins = "gpio92"; + function = "gpio"; + bias-disable; + }; + + wcn_sw_en: wcn-sw-en-state { + pins = "gpio94"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wcn_wlan_bt_en: wcn-wlan-bt-en-state { + pins = "gpio116", "gpio117"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins = "gpio147"; + function = "pcie4_clk_req_n"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio146"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio148"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie5_default: pcie5-default-state { + clkreq-n-pins { + pins = "gpio153"; + function = "pcie5_clk_req_n"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio152"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio154"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; +}; + +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + max-speed = <3200000>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + }; +}; + +&usb_0 { + status = "okay"; +}; + +&usb_0_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_0_hsphy { + vdd-supply = <&vreg_l3f_e0_0p91>; + vdda12-supply = <&vreg_l4h_e0_1p2>; + + phys = <&smb2370_j_e2_eusb2_repeater>; + + status = "okay"; +}; + +&usb_0_qmpphy { + vdda-phy-supply = <&vreg_l3f_e0_0p91>; + vdda-pll-supply = <&vreg_l4h_e0_1p2>; + refgen-supply = <&vreg_l2f_e0_0p94>; + + status = "okay"; +}; + +&usb_0_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in>; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in1>; +}; + +&usb_1_hsphy { + vdd-supply = <&vreg_l3f_e0_0p91>; + vdda12-supply = <&vreg_l4h_e0_1p2>; + + phys = <&smb2370_k_e2_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply = <&vreg_l1h_e0_0p94>; + vdda-pll-supply = <&vreg_l4h_e0_1p2>; + refgen-supply = <&vreg_l2f_e0_0p94>; + + status = "okay"; +}; + +&usb_1_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in1>; +}; + +/* Internal USB2 host for the Elan fingerprint reader (usb 04f3:0ca8). */ +&usb_hs { + dr_mode = "host"; + + status = "okay"; +}; + +&usb_hs_phy { + vdd-supply = <&vreg_l2h_e0_0p88>; + vdda12-supply = <&vreg_l4h_e0_1p2>; + + status = "okay"; +}; + +/* Multiport host: port 0 = chassis USB-A, port 1 = internal USB HID. */ +&usb_mp { + status = "okay"; +}; + +&usb_mp_hsphy0 { + vdd-supply = <&vreg_l2h_e0_0p88>; + vdda12-supply = <&vreg_l4h_e0_1p2>; + + status = "okay"; +}; + +&usb_mp_hsphy1 { + vdd-supply = <&vreg_l2h_e0_0p88>; + vdda12-supply = <&vreg_l4h_e0_1p2>; + + status = "okay"; +}; + +&usb_mp_qmpphy0 { + vdda-phy-supply = <&vreg_l2h_e0_0p88>; + vdda-pll-supply = <&vreg_l4h_e0_1p2>; + refgen-supply = <&vreg_l4f_e1_1p2>; + + status = "okay"; +}; + +&usb_mp_qmpphy1 { + vdda-phy-supply = <&vreg_l2h_e0_0p88>; + vdda-pll-supply = <&vreg_l4h_e0_1p2>; + refgen-supply = <&vreg_l4f_e1_1p2>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/glymur-lenovo-yoga-slim7x.dts b/arch/arm64/boot/dts/qcom/glymur-lenovo-yoga-slim7x.dts new file mode 100644 index 000000000000..769f195c99d9 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/glymur-lenovo-yoga-slim7x.dts @@ -0,0 +1,1221 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +/dts-v1/; + +#include "glymur.dtsi" + +#include "pmcx0102.dtsi" /* SPMI0: SID-2/3 SPMI1: SID-2/3 */ +#include "pmh0101.dtsi" /* SPMI0: SID-1 */ +#include "pmh0110-glymur.dtsi" /* SPMI0: SID-5/7 SPMI1: SID-5 */ +#include "pmh0104-glymur.dtsi" /* SPMI0: SID-8/9 SPMI1: SID-11 */ +#include "pmk8850.dtsi" /* SPMI0: SID-0 */ +#include "smb2370.dtsi" /* SPMI2: SID-9/10/11 */ + +#include <dt-bindings/input/gpio-keys.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> + +/ { + model = "Lenovo Yoga Slim 7x Gen 11"; + compatible = "lenovo,yoga-slim7x-gen11", "qcom,glymur"; + + aliases { + serial0 = &uart21; + serial1 = &uart14; + i2c0 = &i2c0; + i2c5 = &i2c5; + i2c8 = &i2c8; + i2c9 = &i2c9; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <38400000>; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&hall_int_n_default>, <&cam_privacy_default>; + pinctrl-names = "default"; + + switch-lid { + label = "lid"; + gpios = <&tlmm 92 GPIO_ACTIVE_LOW>; + linux,input-type = <EV_SW>; + linux,code = <SW_LID>; + wakeup-source; + wakeup-event-action = <EV_ACT_DEASSERTED>; + }; + + switch-camera-privacy { + label = "Camera privacy switch"; + gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; + linux,input-type = <EV_SW>; + linux,code = <SW_CAMERA_LENS_COVER>; + }; + }; + + leds { + compatible = "gpio-leds"; + + pinctrl-0 = <&cam_indicator_en>; + pinctrl-names = "default"; + + privacy_led: privacy-led { + function = LED_FUNCTION_INDICATOR; + color = <LED_COLOR_ID_WHITE>; + gpios = <&tlmm 111 GPIO_ACTIVE_HIGH>; + default-state = "off"; + panic-indicator; + }; + }; + + pmic-glink { + compatible = "qcom,glymur-pmic-glink", + "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + + /* Left side display-adjacent port */ + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&usb_0_qmpphy_out>; + }; + }; + }; + }; + + /* Left side user-adjacent port */ + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in1: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in1: endpoint { + remote-endpoint = <&usb_1_qmpphy_out>; + }; + }; + }; + }; + + /* Right side port */ + connector@2 { + compatible = "usb-c-connector"; + reg = <2>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in2: endpoint { + remote-endpoint = <&usb_2_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in2: endpoint { + remote-endpoint = <&usb_2_qmpphy_out>; + }; + }; + }; + }; + }; + + vreg_edp_3p3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_misc_3p3: regulator-misc-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_MISC_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmh0110_f_e0_gpios 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&misc_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_nvme: regulator-nvme { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmh0101_gpios 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&nvme_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_wcn_0p95: regulator-wcn-0p95 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_0P95"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 94 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wcn_sw_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_wwan: regulator-wwan { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WWAN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 246 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wwan_reg_en>; + pinctrl-names = "default"; + }; + + sound { + compatible = "qcom,glymur-sndcard"; + model = "GLYMUR-LENOVO-Yoga-Slim7x"; + audio-routing = "WooferLeft IN", "WSA WSA_SPK1 OUT", + "TweeterLeft IN", "WSA WSA_SPK2 OUT", + "WooferRight IN", "WSA2 WSA_SPK1 OUT", + "TweeterRight IN", "WSA2 WSA_SPK2 OUT", + "VA DMIC0", "vdd-micb", + "VA DMIC1", "vdd-micb", + "VA DMIC2", "vdd-micb", + "VA DMIC3", "vdd-micb"; + + va-dai-link { + link-name = "VA Capture"; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + codec { + sound-dai = <&left_woofer>, <&left_tweeter>, + <&swr0 0>, <&lpass_wsamacro 0>, + <&right_woofer>, <&right_tweeter>, + <&swr3 0>, <&lpass_wsa2macro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + vdd-supply = <&vreg_wcn_0p95>; + vddio-supply = <&vreg_l15b_e0>; + vddaon-supply = <&vreg_l15b_e0>; + vdddig-supply = <&vreg_l15b_e0>; + vddrfa1p2-supply = <&vreg_l15b_e0>; + vddrfa1p8-supply = <&vreg_l15b_e0>; + + wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; + bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&wcn_wlan_bt_en>; + pinctrl-names = "default"; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pmh0101-rpmh-regulators"; + qcom,pmic-id = "B_E0"; + + vreg_l1b_e0: ldo1 { + regulator-name = "vreg_l1b_e0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7b_e0: ldo7 { + regulator-name = "vreg_l7b_e0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8b_e0: ldo8 { + regulator-name = "vreg_l8b_e0"; + regulator-min-microvolt = <3304000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l9b_e0: ldo9 { + regulator-name = "vreg_l9b_e0"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l10b_e0: ldo10 { + regulator-name = "vreg_l10b_e0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l11b_e0: ldo11 { + regulator-name = "vreg_l11b_e0"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l12b_e0: ldo12 { + regulator-name = "vreg_l12b_e0"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l15b_e0: ldo15 { + regulator-name = "vreg_l15b_e0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l17b_e0: ldo17 { + regulator-name = "vreg_l17b_e0"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l18b_e0: ldo18 { + regulator-name = "vreg_l18b_e0"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-1 { + compatible = "qcom,pmcx0102-rpmh-regulators"; + qcom,pmic-id = "C_E1"; + + vreg_l1c_e1: ldo1 { + regulator-name = "vreg_l1c_e1"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2c_e1: ldo2 { + regulator-name = "vreg_l2c_e1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3c_e1: ldo3 { + regulator-name = "vreg_l3c_e1"; + regulator-min-microvolt = <936000>; + regulator-max-microvolt = <936000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4c_e1: ldo4 { + regulator-name = "vreg_l4c_e1"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-2 { + compatible = "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id = "F_E0"; + + vreg_s7f_e0: smps7 { + regulator-name = "vreg_s7f_e0"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s8f_e0: smps8 { + regulator-name = "vreg_s8f_e0"; + regulator-min-microvolt = <952000>; + regulator-max-microvolt = <952000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2f_e0: ldo2 { + regulator-name = "vreg_l2f_e0"; + regulator-min-microvolt = <936000>; + regulator-max-microvolt = <936000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3f_e0: ldo3 { + regulator-name = "vreg_l3f_e0"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-3 { + compatible = "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id = "F_E1"; + + vreg_l1f_e1: ldo1 { + regulator-name = "vreg_l1f_e1"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <904000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2f_e1: ldo2 { + regulator-name = "vreg_l2f_e1"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4f_e1: ldo4 { + regulator-name = "vreg_l4f_e1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-4 { + compatible = "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id = "H_E0"; + + vreg_l1h_e0: ldo1 { + regulator-name = "vreg_l1h_e0"; + regulator-min-microvolt = <936000>; + regulator-max-microvolt = <936000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2h_e0: ldo2 { + regulator-name = "vreg_l2h_e0"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3h_e0: ldo3 { + regulator-name = "vreg_l3h_e0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4h_e0: ldo4 { + regulator-name = "vreg_l4h_e0"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; +}; + +&gpu { + status = "okay"; +}; + +&gmu { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + + status = "okay"; + + touchpad@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + + hid-descr-addr = <0x20>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l15b_e0>; + + pinctrl-0 = <&tpad_default>; + pinctrl-names = "default"; + + wakeup-source; + }; + + keyboard@3a { + compatible = "hid-over-i2c"; + reg = <0x3a>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l15b_e0>; + + pinctrl-0 = <&kybd_default>; + pinctrl-names = "default"; + + wakeup-source; + }; + + /* Something @ 0x5b */ +}; + +&i2c5 { + clock-frequency = <400000>; + + status = "okay"; +}; + +&i2c8 { + clock-frequency = <400000>; + + status = "okay"; + + touchscreen@14 { + compatible = "hid-over-i2c"; + reg = <0x14>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>; + + post-power-on-delay-ms = <200>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l15b_e0>; + + pinctrl-0 = <&ts0_default>; + pinctrl-names = "default"; + }; +}; + +&i2c9 { + clock-frequency = <400000>; + + status = "okay"; + + /* EC @ 0x70, irq = TLMM 66 */ +}; + +&lpass_vamacro { + pinctrl-0 = <&dmic01_default>, <&dmic23_default>; + pinctrl-names = "default"; + qcom,dmic-sample-rate = <4800000>; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp1 { + status = "okay"; +}; + +&mdss_dp1_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp2 { + status = "okay"; +}; + +&mdss_dp2_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp3 { + /delete-property/ #sound-dai-cells; + + status = "okay"; + + aux-bus { + panel { + compatible = "samsung,atna40hq08", "samsung,atna33xc20"; + enable-gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>; + power-supply = <&vreg_edp_3p3>; + + pinctrl-0 = <&edp_bl_en>; + pinctrl-names = "default"; + + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + }; +}; + +&mdss_dp3_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&edp_panel_in>; +}; + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l2f_e1>; + vdda-pll-supply = <&vreg_l4f_e1>; + + status = "okay"; +}; + +&pcie4 { + pinctrl-0 = <&pcie4_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l1c_e1>; + vdda-pll-supply = <&vreg_l4f_e1>; + + status = "okay"; +}; + +&pcie4_port0 { + reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; +}; + +&pcie5 { + vddpe-3v3-supply = <&vreg_nvme>; + + pinctrl-0 = <&pcie5_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie5_phy { + vdda-phy-supply = <&vreg_l2f_e0>; + vdda-pll-supply = <&vreg_l4h_e0>; + + status = "okay"; +}; + +&pcie5_port0 { + reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; +}; + +&pcie6 { + vddpe-3v3-supply = <&vreg_wwan>; + + pinctrl-0 = <&pcie6_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie6_phy { + vdda-phy-supply = <&vreg_l1c_e1>; + vdda-pll-supply = <&vreg_l4f_e1>; + + status = "okay"; +}; + +&pcie6_port0 { + reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; +}; + +&pmh0101_gpios { + nvme_reg_en: nvme-reg-en-state { + pins = "gpio14"; + function = "normal"; + bias-disable; + }; +}; + +&pmh0110_f_e0_gpios { + misc_3p3_reg_en: misc-3p3-reg-en-state { + pins = "gpio6"; + function = "normal"; + bias-disable; + input-disable; + output-enable; + drive-push-pull; + power-source = <1>; /* 1.8 V */ + qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; + }; +}; + +&pmh0110_f_e1_gpios { + nvme_sec_reg_en: nvme-reg-en-state { + pins = "gpio14"; + function = "normal"; + bias-disable; + }; +}; + +&pmk8850_rtc { + qcom,no-alarm; +}; + +&remoteproc_adsp { + firmware-name = "qcom/glymur/LENOVO/83QR/qcadsp8480.mbn", + "qcom/glymur/LENOVO/83QR/adsp_dtbs.elf"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/glymur/LENOVO/83QR/qccdsp8480.mbn", + "qcom/glymur/LENOVO/83QR/cdsp_dtbs.elf"; + + status = "okay"; +}; + +&remoteproc_soccp { + status = "okay"; +}; + +&smb2370_j_e2_eusb2_repeater { + vdd18-supply = <&vreg_l15b_e0>; + vdd3-supply = <&vreg_l7b_e0>; +}; + +&smb2370_k_e2_eusb2_repeater { + vdd18-supply = <&vreg_l15b_e0>; + vdd3-supply = <&vreg_l7b_e0>; +}; + +&smb2370_l_e2_eusb2_repeater { + vdd18-supply = <&vreg_l15b_e0>; + vdd3-supply = <&vreg_l7b_e0>; + + status = "okay"; +}; + +&swr0 { + status = "okay"; + + /* WSA8845, Left Woofer */ + left_woofer: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "WooferLeft"; + vdd-1p8-supply = <&vreg_l15b_e0>; + vdd-io-supply = <&vreg_l18b_e0>; + qcom,port-mapping = <1 2 3 7 12 14>; + }; + + /* WSA8845, Left Tweeter */ + left_tweeter: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "TweeterLeft"; + vdd-1p8-supply = <&vreg_l15b_e0>; + vdd-io-supply = <&vreg_l18b_e0>; + qcom,port-mapping = <4 5 6 7 13 15>; + }; +}; + +&swr3 { + status = "okay"; + + /* WSA8845, Right Woofer */ + right_woofer: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "WooferRight"; + vdd-1p8-supply = <&vreg_l15b_e0>; + vdd-io-supply = <&vreg_l18b_e0>; + qcom,port-mapping = <1 2 3 7 12 14>; + }; + + /* WSA8845, Right Tweeter */ + right_tweeter: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "TweeterRight"; + vdd-1p8-supply = <&vreg_l15b_e0>; + vdd-io-supply = <&vreg_l18b_e0>; + qcom,port-mapping = <4 5 6 7 13 15>; + }; +}; + +&tcsr { + vdda-qrefrpt0-0p9-supply = <&vreg_l2f_e1>; + vdda-qrefrpt1-0p9-supply = <&vreg_l2f_e1>; + vdda-qrefrpt2-0p9-supply = <&vreg_l2f_e1>; + vdda-qrefrpt3-0p9-supply = <&vreg_l2h_e0>; + vdda-qrefrpt4-0p9-supply = <&vreg_l2h_e0>; + vdda-qrefrx0-0p9-supply = <&vreg_l2f_e1>; + vdda-qrefrx1-0p9-supply = <&vreg_l2f_e1>; + vdda-qrefrx2-0p9-supply = <&vreg_l2f_e1>; + vdda-qrefrx4-0p9-supply = <&vreg_l2h_e0>; + vdda-qrefrx5-0p9-supply = <&vreg_l3f_e0>; + vdda-qreftx0-0p9-supply = <&vreg_l3f_e0>; + vdda-qreftx0-1p2-supply = <&vreg_l4h_e0>; + vdda-qreftx1-0p9-supply = <&vreg_l1f_e1>; + vdda-refgen3-0p9-supply = <&vreg_l2f_e0>; + vdda-refgen3-1p2-supply = <&vreg_l4h_e0>; + vdda-refgen4-0p9-supply = <&vreg_l1f_e1>; + vdda-refgen4-1p2-supply = <&vreg_l4f_e1>; +}; + +&tlmm { + gpio-reserved-ranges = <4 4>, /* EC TZ Secure I3C */ + <10 2>, /* OOB UART */ + <44 4>, /* Security SPI (TPM) */ + <65 1>; /* EC reset (need to unplug the battery if asserted) */ + + tpad_default: tpad-default-state { + pins = "gpio3"; + function = "gpio"; + bias-disable; + }; + + edp_bl_en: edp-bl-en-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + ts0_default: ts0-default-state { + int-n-pins { + pins = "gpio51"; + function = "gpio"; + bias-disable; + }; + + reset-n-pins { + pins = "gpio48"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + }; + + ec_int_n_default: ec-int-n-state { + pins = "gpio66"; + function = "gpio"; + bias-disable; + }; + + kybd_default: kybd-default-state { + pins = "gpio67"; + function = "gpio"; + bias-disable; + }; + + edp_reg_en: edp-reg-en-state { + pins = "gpio70"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + hall_int_n_default: hall-int-n-state { + pins = "gpio92"; + function = "gpio"; + bias-disable; + }; + + wcn_sw_en: wcn-sw-en-state { + pins = "gpio94"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + cam_privacy_default: cam-privacy-default-state { + pins = "gpio99"; + function = "gpio"; + bias-pull-up; + }; + + cam_indicator_en: cam-indicator-en-state { + pins = "gpio111"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wcn_wlan_bt_en: wcn-wlan-bt-en-state { + pins = "gpio116", "gpio117"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins = "gpio147"; + function = "pcie4_clk_req_n"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio146"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio148"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie5_default: pcie5-default-state { + clkreq-n-pins { + pins = "gpio153"; + function = "pcie5_clk_req_n"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio152"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio154"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie6_default: pcie6-default-state { + clkreq-n-pins { + pins = "gpio150"; + function = "pcie6_clk_req_n"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio149"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio151"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + wwan_reg_en: wwan-reg-en-state { + pins = "gpio246"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + max-speed = <3200000>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + }; +}; + +&usb_0 { + status = "okay"; +}; + +&usb_0_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_0_hsphy { + vdd-supply = <&vreg_l3f_e0>; + vdda12-supply = <&vreg_l4h_e0>; + + phys = <&smb2370_j_e2_eusb2_repeater>; + + status = "okay"; +}; + +&usb_0_qmpphy { + vdda-phy-supply = <&vreg_l4h_e0>; + vdda-pll-supply = <&vreg_l3f_e0>; + refgen-supply = <&vreg_l2f_e0>; + + status = "okay"; +}; + +&usb_0_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in>; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in1>; +}; + +&usb_1_hsphy { + vdd-supply = <&vreg_l3f_e0>; + vdda12-supply = <&vreg_l4h_e0>; + + phys = <&smb2370_k_e2_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply = <&vreg_l4h_e0>; + vdda-pll-supply = <&vreg_l1h_e0>; + refgen-supply = <&vreg_l2f_e0>; + + status = "okay"; +}; + +&usb_1_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in1>; +}; + +&usb_2 { + status = "okay"; +}; + +&usb_2_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in2>; +}; + +&usb_2_hsphy { + vdd-supply = <&vreg_l4c_e1>; + vdda12-supply = <&vreg_l4f_e1>; + + phys = <&smb2370_l_e2_eusb2_repeater>; + + status = "okay"; +}; + +&usb_2_qmpphy { + vdda-phy-supply = <&vreg_l4f_e1>; + vdda-pll-supply = <&vreg_l4c_e1>; + refgen-supply = <&vreg_l1c_e1>; + + status = "okay"; +}; + +&usb_2_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in2>; +}; diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index f04058d2e089..de7c395d9c35 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -21,7 +21,6 @@ #include <dt-bindings/mailbox/qcom-ipcc.h> #include <dt-bindings/phy/phy-qcom-qmp.h> #include <dt-bindings/power/qcom,rpmhpd.h> -#include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include <dt-bindings/soc/qcom,gpr.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> @@ -801,8 +800,8 @@ <0>, /* USB 2 Phy PCIE PIPEGMUX */ <0>, /* USB 2 Phy PIPEGMUX */ <0>, /* USB 2 Phy SYS PCIE PIPEGMUX */ - <0>, /* PCIe 3a */ - <0>, /* PCIe 3b */ + <&pcie3_phy 0>, /* PCIe 3a pipe */ + <&pcie3_phy 1>, /* PCIe 3b pipe */ <&pcie4_phy>, /* PCIe 4 */ <&pcie5_phy>, /* PCIe 5 */ <&pcie6_phy>, /* PCIe 6 */ @@ -2374,6 +2373,62 @@ }; }; + pcie3_phy: phy@f00000 { + compatible = "qcom,glymur-qmp-gen5x8-pcie-phy"; + reg = <0x0 0x00f00000 0x0 0x10000>, + <0x0 0x00f10000 0x0 0x10000>; + reg-names = "port_a", + "port_b"; + + clocks = <&gcc GCC_PCIE_PHY_3A_AUX_CLK>, + <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, + <&tcsr TCSR_PCIE_3_CLKREF_EN>, + <&gcc GCC_PCIE_3A_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_3A_PIPE_CLK>, + <&gcc GCC_PCIE_PHY_3B_AUX_CLK>, + <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, + <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_3B_PIPE_CLK>, + <&gcc GCC_PCIE_3B_PIPE_DIV2_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "phy_b_aux", + "cfg_ahb_b", + "rchng_b", + "pipe_b", + "pipediv2_b"; + + resets = <&gcc GCC_PCIE_3A_PHY_BCR>, + <&gcc GCC_PCIE_3A_NOCSR_COM_PHY_BCR>, + <&gcc GCC_PCIE_3B_PHY_BCR>, + <&gcc GCC_PCIE_3B_NOCSR_COM_PHY_BCR>; + reset-names = "port_a", + "port_a_nocsr", + "port_b", + "port_b_nocsr"; + + assigned-clocks = <&gcc GCC_PCIE_3A_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>, <100000000>; + + power-domains = <&gcc GCC_PCIE_3A_PHY_GDSC>, + <&gcc GCC_PCIE_3B_PHY_GDSC>; + power-domain-names = "port_a", "port_b"; + + qcom,link-mode = <&tcsr 0x5000>; + + #clock-cells = <1>; + clock-output-names = "pcie3a_pipe_clk", + "pcie3b_pipe_clk"; + + #phy-cells = <1>; + + status = "disabled"; + }; + usb_hs_phy: phy@fa0000 { compatible = "qcom,glymur-m31-eusb2-phy", "qcom,sm8750-m31-eusb2-phy"; @@ -3755,6 +3810,8 @@ reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; + phys = <&pcie3_phy 1>; + #address-cells = <3>; #size-cells = <2>; ranges; @@ -3766,6 +3823,280 @@ }; }; + pcie3a: pcie@1c10000 { + device_type = "pci"; + compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; + reg = <0x0 0x01c10000 0x0 0x3000>, + <0x0 0x70000000 0x0 0xf20>, + <0x0 0x70000f40 0x0 0xa8>, + <0x0 0x70001000 0x0 0x4000>, + <0x0 0x70100000 0x0 0x100000>, + <0x0 0x01c13000 0x0 0x1000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x70200000 0x0 0x100000>, + <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x3d00000>, + <0x03000000 0x7 0x00000000 0x7 0x00000000 0x0 0x40000000>, + <0x43000000 0x70 0x00000000 0x70 0x00000000 0x10 0x00000000>; + + bus-range = <0x00 0xff>; + + dma-coherent; + + linux,pci-domain = <3>; + + operating-points-v2 = <&pcie3a_opp_table>; + + msi-map = <0x0 &gic_its 0xb0000 0x10000>; + iommu-map = <0x0 &pcie_smmu 0x30000 0x10000>; + + interrupts = <GIC_SPI 948 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 949 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 942 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 851 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_3A_AUX_CLK>, + <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, + <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_3A_SLV_AXI_CLK>, + <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_3A_WEST_SF_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "noc_aggr"; + + assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>; + assigned-clock-rates = <19200000>; + + interconnects = <&pcie_west_anoc MASTER_PCIE_3A QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &pcie_west_slv_noc SLAVE_PCIE_3A QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "pcie-mem", + "cpu-pcie"; + + resets = <&gcc GCC_PCIE_3A_BCR>, + <&gcc GCC_PCIE_3A_LINK_DOWN_BCR>; + reset-names = "pci", + "link_down"; + + power-domains = <&gcc GCC_PCIE_3A_GDSC>; + + eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555 + 0x5555 0x5555 0x5555 0x5555>; + eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55>; + eq-presets-32gts = /bits/ 8 <0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55>; + + status = "disabled"; + + pcie3a_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000-1 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <250000 1>; + opp-level = <1>; + }; + + /* GEN 1 x2 */ + opp-5000000-1 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + opp-level = <1>; + }; + + /* GEN 1 x4 */ + opp-10000000-1 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1000000 1>; + opp-level = <1>; + }; + + /* GEN 1 x8 */ + opp-20000000-1 { + opp-hz = /bits/ 64 <20000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <2000000 1>; + opp-level = <1>; + }; + + /* GEN 2 x1 */ + opp-5000000-2 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + opp-level = <2>; + }; + + /* GEN 2 x2 */ + opp-10000000-2 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1000000 1>; + opp-level = <2>; + }; + + /* GEN 2 x4 */ + opp-20000000-2 { + opp-hz = /bits/ 64 <20000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <2000000 1>; + opp-level = <2>; + }; + + /* GEN 2 x8 */ + opp-40000000-2 { + opp-hz = /bits/ 64 <40000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <4000000 1>; + opp-level = <2>; + }; + + /* GEN 3 x1 */ + opp-8000000-3 { + opp-hz = /bits/ 64 <8000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <984500 1>; + opp-level = <3>; + }; + + /* GEN 3 x2 */ + opp-16000000-3 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1969000 1>; + opp-level = <3>; + }; + + /* GEN 3 x4 */ + opp-32000000-3 { + opp-hz = /bits/ 64 <32000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <3938000 1>; + opp-level = <3>; + }; + + /* GEN 3 x8 */ + opp-64000000-3 { + opp-hz = /bits/ 64 <64000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <7876000 1>; + opp-level = <3>; + }; + + /* GEN 4 x1 */ + opp-16000000-4 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <1969000 1>; + opp-level = <4>; + }; + + /* GEN 4 x2 */ + opp-32000000-4 { + opp-hz = /bits/ 64 <32000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <3938000 1>; + opp-level = <4>; + }; + + /* GEN 4 x4 */ + opp-64000000-4 { + opp-hz = /bits/ 64 <64000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <7876000 1>; + opp-level = <4>; + }; + + /* GEN 4 x8 */ + opp-128000000-4 { + opp-hz = /bits/ 64 <128000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <15753000 1>; + opp-level = <4>; + }; + + /* GEN 5 x1 */ + opp-32000000-5 { + opp-hz = /bits/ 64 <32000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <3938000 1>; + opp-level = <5>; + }; + + /* GEN 5 x2 */ + opp-64000000-5 { + opp-hz = /bits/ 64 <64000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <7876000 1>; + opp-level = <5>; + }; + + /* GEN 5 x4 */ + opp-128000000-5 { + opp-hz = /bits/ 64 <128000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <15753000 1>; + opp-level = <5>; + }; + + /* GEN 5 x8 */ + opp-256000000-5 { + opp-hz = /bits/ 64 <256000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <31506000 1>; + opp-level = <5>; + }; + }; + + pcie3a_port0: pcie@0 { + device_type = "pci"; + compatible = "pciclass,0604"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + phys = <&pcie3_phy 0>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; + rng: rng@10c3000 { compatible = "qcom,glymur-trng", "qcom,trng"; reg = <0x0 0x010c3000 0x0 0x1000>; @@ -4572,6 +4903,10 @@ "noc_aggr_north", "noc_aggr_south"; + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + interrupts-extended = <&intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, <&pdc 90 IRQ_TYPE_EDGE_BOTH>, @@ -4584,9 +4919,18 @@ "ss_phy_irq"; power-domains = <&gcc GCC_USB30_PRIM_GDSC>; + required-opps = <&rpmhpd_opp_nom>; resets = <&gcc GCC_USB30_PRIM_BCR>; iommus = <&apps_smmu 0x1420 0x0>; + + interconnects = <&aggre4_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "usb-ddr", + "apps-usb"; + phys = <&usb_0_hsphy>, <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", @@ -4605,6 +4949,8 @@ usb-role-switch; wakeup-source; + dma-coherent; + status = "disabled"; ports { @@ -4647,6 +4993,10 @@ "noc_aggr_north", "noc_aggr_south"; + assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + interrupts-extended = <&intc GIC_SPI 875 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, <&pdc 88 IRQ_TYPE_EDGE_BOTH>, @@ -4660,9 +5010,17 @@ resets = <&gcc GCC_USB30_SEC_BCR>; power-domains = <&gcc GCC_USB30_SEC_GDSC>; + required-opps = <&rpmhpd_opp_nom>; iommus = <&apps_smmu 0x1460 0x0>; + interconnects = <&aggre4_noc MASTER_USB3_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_USB3_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "usb-ddr", + "apps-usb"; + phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", @@ -4681,6 +5039,8 @@ usb-role-switch; wakeup-source; + dma-coherent; + status = "disabled"; ports { @@ -4723,6 +5083,10 @@ "noc_aggr_north", "noc_aggr_south"; + assigned-clocks = <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_TERT_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + interrupts-extended = <&intc GIC_SPI 871 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, <&pdc 89 IRQ_TYPE_EDGE_BOTH>, @@ -4736,9 +5100,17 @@ resets = <&gcc GCC_USB30_TERT_BCR>; power-domains = <&gcc GCC_USB30_TERT_GDSC>; + required-opps = <&rpmhpd_opp_nom>; iommus = <&apps_smmu 0x420 0x0>; + interconnects = <&aggre2_noc MASTER_USB3_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_USB3_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "usb-ddr", + "apps-usb"; + phys = <&usb_2_hsphy>, <&usb_2_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", @@ -4757,6 +5129,8 @@ usb-role-switch; wakeup-source; + dma-coherent; + status = "disabled"; ports { @@ -4847,6 +5221,8 @@ usb-role-switch; wakeup-source; + dma-coherent; + status = "disabled"; }; @@ -4869,6 +5245,10 @@ "noc_aggr_north", "noc_aggr_south"; + assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_MP_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + interrupts-extended = <&intc GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, @@ -4894,9 +5274,17 @@ resets = <&gcc GCC_USB30_MP_BCR>; power-domains = <&gcc GCC_USB30_MP_GDSC>; + required-opps = <&rpmhpd_opp_nom>; iommus = <&apps_smmu 0xda0 0x0>; + interconnects = <&aggre3_noc MASTER_USB3_MP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_USB3_MP QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "usb-ddr", + "apps-usb"; + phys = <&usb_mp_hsphy0>, <&usb_mp_qmpphy0>, <&usb_mp_hsphy1>, @@ -4919,6 +5307,8 @@ dr_mode = "host"; wakeup-source; + dma-coherent; + status = "disabled"; }; diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts index 9fa86bb6438e..776bded3a312 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts @@ -479,32 +479,6 @@ regulator-boot-on; }; - /* - * TODO: These two regulators are actually part of the removable M.2 - * card and not the EVK mainboard. Need to describe this differently. - * Functionally it works correctly, because all we need to do is to - * turn on the actual 3.3V supply above. - */ - vreg_wcn_0p95: regulator-wcn-0p95 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_WCN_0P95"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <950000>; - - vin-supply = <&vreg_wcn_3p3>; - }; - - vreg_wcn_1p9: regulator-wcn-1p9 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_WCN_1P9"; - regulator-min-microvolt = <1900000>; - regulator-max-microvolt = <1900000>; - - vin-supply = <&vreg_wcn_3p3>; - }; - vreg_wcn_3p3: regulator-wcn-3p3 { compatible = "regulator-fixed"; @@ -677,64 +651,44 @@ }; }; - wcn7850-pmu { - compatible = "qcom,wcn7850-pmu"; - - vdd-supply = <&vreg_wcn_0p95>; - vddio-supply = <&vreg_l15b_1p8>; - vddaon-supply = <&vreg_wcn_0p95>; - vdddig-supply = <&vreg_wcn_0p95>; - vddrfa1p2-supply = <&vreg_wcn_1p9>; - vddrfa1p8-supply = <&vreg_wcn_1p9>; + wifi-bt-connector { + compatible = "pcie-m2-e-connector"; + vpcie3v3-supply = <&vreg_wcn_3p3>; - bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; - wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; + w-disable1-gpios = <&tlmm 117 GPIO_ACTIVE_LOW>; + w-disable2-gpios = <&tlmm 116 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&wcn_bt_en>, <&wcn_wlan_en>; + pinctrl-0 = <&wcn_wlan_en>, <&wcn_bt_en>; pinctrl-names = "default"; - regulators { - vreg_pmu_rfa_cmn: ldo0 { - regulator-name = "vreg_pmu_rfa_cmn"; - }; - - vreg_pmu_aon_0p59: ldo1 { - regulator-name = "vreg_pmu_aon_0p59"; - }; - - vreg_pmu_wlcx_0p8: ldo2 { - regulator-name = "vreg_pmu_wlcx_0p8"; - }; - - vreg_pmu_wlmx_0p85: ldo3 { - regulator-name = "vreg_pmu_wlmx_0p85"; - }; - - vreg_pmu_btcmx_0p85: ldo4 { - regulator-name = "vreg_pmu_btcmx_0p85"; - }; - - vreg_pmu_rfa_0p8: ldo5 { - regulator-name = "vreg_pmu_rfa_0p8"; - }; + ports { + #address-cells = <1>; + #size-cells = <0>; - vreg_pmu_rfa_1p2: ldo6 { - regulator-name = "vreg_pmu_rfa_1p2"; - }; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; - vreg_pmu_rfa_1p8: ldo7 { - regulator-name = "vreg_pmu_rfa_1p8"; + m2_e_pcie_ep: endpoint@0 { + reg = <0>; + remote-endpoint = <&pcie4_port0_ep>; + }; }; - vreg_pmu_pcie_0p9: ldo8 { - regulator-name = "vreg_pmu_pcie_0p9"; - }; + port@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; - vreg_pmu_pcie_1p8: ldo9 { - regulator-name = "vreg_pmu_pcie_1p8"; + m2_e_uart_ep: endpoint@0 { + reg = <0>; + remote-endpoint = <&uart14_ep>; + }; }; }; }; + }; &i2c1 { @@ -1024,21 +978,10 @@ &pcie4_port0 { reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; +}; - wifi@0 { - compatible = "pci17cb,1107"; - reg = <0x10000 0x0 0x0 0x0 0x0>; - - vddaon-supply = <&vreg_pmu_aon_0p59>; - vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; - vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; - vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; - vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; - vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; - vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; - vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; - vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; - }; +&pcie4_port0_ep { + remote-endpoint = <&m2_e_pcie_ep>; }; &pcie5 { @@ -1530,19 +1473,10 @@ &uart14 { status = "okay"; +}; - bluetooth { - compatible = "qcom,wcn7850-bt"; - max-speed = <3200000>; - - vddaon-supply = <&vreg_pmu_aon_0p59>; - vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; - vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; - vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; - vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; - vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; - vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; - }; +&uart14_ep { + remote-endpoint = <&m2_e_uart_ep>; }; &uart21 { diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi index bc70fe5db96f..f139f3adb933 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi @@ -478,6 +478,27 @@ status = "okay"; }; +&tcsr { + vdda-qrefrpt0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrpt1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrpt4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qrefrx0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrx1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrx4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qreftx0-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx0-1p2-supply = <&vreg_l2j_1p2>; + vdda-qreftx1-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx1-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen0-0p9-supply = <&vreg_l3i_0p8>; + vdda-refgen0-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen2-0p9-supply = <&vreg_l3j_0p8>; + vdda-refgen2-1p2-supply = <&vreg_l2j_1p2>; +}; + &tlmm { gpio-reserved-ranges = <34 2>; /* TPM LP & INT */ diff --git a/arch/arm64/boot/dts/qcom/hamoa-lenovo-ideacentre-mini-01q8x10.dts b/arch/arm64/boot/dts/qcom/hamoa-lenovo-ideacentre-mini-01q8x10.dts index 284825008389..75ce8b0c94d2 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-lenovo-ideacentre-mini-01q8x10.dts +++ b/arch/arm64/boot/dts/qcom/hamoa-lenovo-ideacentre-mini-01q8x10.dts @@ -902,6 +902,27 @@ }; }; +&tcsr { + vdda-qrefrpt0-0p9-supply = <&vreg_l3c>; + vdda-qrefrpt1-0p9-supply = <&vreg_l3i>; + vdda-qrefrpt2-0p9-supply = <&vreg_l3i>; + vdda-qrefrpt3-0p9-supply = <&vreg_l3j>; + vdda-qrefrpt4-0p9-supply = <&vreg_l1d>; + vdda-qrefrx0-0p9-supply = <&vreg_l3c>; + vdda-qrefrx1-0p9-supply = <&vreg_l3i>; + vdda-qrefrx2-0p9-supply = <&vreg_l3i>; + vdda-qrefrx3-0p9-supply = <&vreg_l3j>; + vdda-qrefrx4-0p9-supply = <&vreg_l1d>; + vdda-qreftx0-0p9-supply = <&vreg_l3j>; + vdda-qreftx0-1p2-supply = <&vreg_l2j>; + vdda-qreftx1-0p9-supply = <&vreg_l3j>; + vdda-qreftx1-1p2-supply = <&vreg_l3e>; + vdda-refgen0-0p9-supply = <&vreg_l3i>; + vdda-refgen0-1p2-supply = <&vreg_l3e>; + vdda-refgen2-0p9-supply = <&vreg_l3j>; + vdda-refgen2-1p2-supply = <&vreg_l2j>; +}; + &tlmm { gpio-reserved-ranges = <44 4>, /* SPI11 (TPM) */ <76 4>, /* SPI19 (TZ Protected) */ diff --git a/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi b/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi index 17d754d57e18..7fad4a9b92fa 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi @@ -288,6 +288,7 @@ #address-cells = <1>; #size-cells = <0>; #io-channel-cells = <1>; + #thermal-sensor-cells = <1>; pinctrl-0 = <&sys_therm_0_gpio3>, <&sys_therm_1_gpio4>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index 8a96ea1bdb9c..4e35254cdd11 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -19,7 +19,6 @@ #include <dt-bindings/mailbox/qcom-ipcc.h> #include <dt-bindings/phy/phy-qcom-qmp.h> #include <dt-bindings/power/qcom,rpmhpd.h> -#include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/soc/qcom,gpr.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> @@ -2033,6 +2032,11 @@ pinctrl-names = "default"; status = "disabled"; + + port { + uart14_ep: endpoint { + }; + }; }; i2c15: i2c@a9c000 { @@ -2833,11 +2837,13 @@ clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, - <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&gcc GCC_USB4_0_PHY_P2RR2P_PIPE_CLK>; clock-names = "aux", "ref", "com_aux", - "usb3_pipe"; + "usb3_pipe", + "p2rr2p_pipe"; power-domains = <&gcc GCC_USB_0_PHY_GDSC>; @@ -2904,11 +2910,13 @@ clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, <&tcsr TCSR_USB4_1_CLKREF_EN>, <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, - <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; + <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>, + <&gcc GCC_USB4_1_PHY_P2RR2P_PIPE_CLK>; clock-names = "aux", "ref", "com_aux", - "usb3_pipe"; + "usb3_pipe", + "p2rr2p_pipe"; power-domains = <&gcc GCC_USB_1_PHY_GDSC>; @@ -2975,11 +2983,13 @@ clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>, <&tcsr TCSR_USB4_2_CLKREF_EN>, <&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>, - <&gcc GCC_USB3_TERT_PHY_PIPE_CLK>; + <&gcc GCC_USB3_TERT_PHY_PIPE_CLK>, + <&gcc GCC_USB4_2_PHY_P2RR2P_PIPE_CLK>; clock-names = "aux", "ref", "com_aux", - "usb3_pipe"; + "usb3_pipe", + "p2rr2p_pipe"; power-domains = <&gcc GCC_USB_2_PHY_GDSC>; @@ -3082,6 +3092,7 @@ qcom,bcm-voters = <&apps_bcm_voter>; #interconnect-cells = <2>; + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; }; aggre2_noc: interconnect@1700000 { @@ -3118,6 +3129,8 @@ qcom,bcm-voters = <&apps_bcm_voter>; #interconnect-cells = <2>; + clocks = <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>; }; usb_south_anoc: interconnect@1770000 { @@ -3127,6 +3140,12 @@ qcom,bcm-voters = <&apps_bcm_voter>; #interconnect-cells = <2>; + clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>, + <&gcc GCC_AGGRE_USB4_0_AXI_CLK>, + <&gcc GCC_AGGRE_USB4_1_AXI_CLK>, + <&gcc GCC_AGGRE_USB4_2_AXI_CLK>; }; mmss_noc: interconnect@1780000 { @@ -3784,6 +3803,7 @@ status = "disabled"; pcie4_port0: pcie@0 { + compatible = "pciclass,0604"; device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -3793,6 +3813,11 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + port { + pcie4_port0_ep: endpoint { + }; + }; }; }; @@ -3984,7 +4009,6 @@ reg = <0 0x01fc0000 0 0x30000>; clocks = <&rpmhcc RPMH_CXO_CLK>; #clock-cells = <1>; - #reset-cells = <1>; }; gpu: gpu@3d00000 { diff --git a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts index 33eef92b19b1..34d4a0886356 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts +++ b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts @@ -30,6 +30,16 @@ status = "okay"; }; +&mdio1 { + clock-frequency = <6250000>; + + status = "okay"; + + ethernet-phy@1c { + reg = <0x1c>; + }; +}; + &pcie0 { pinctrl-0 = <&pcie0_default>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi index 4fc627b47fe7..fe1ed240de59 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -222,8 +222,7 @@ clocks = <&gcc GCC_MDIO0_AHB_CLK>; clock-names = "gcc_mdio_ahb_clk"; - - status = "disabled"; + clock-frequency = <6250000>; ge_phy: ethernet-phy@7 { compatible = "ethernet-phy-id004d.d0c0"; @@ -241,6 +240,8 @@ reg = <0x00090000 0x64>; #address-cells = <1>; #size-cells = <0>; + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; clocks = <&gcc GCC_MDIO1_AHB_CLK>; clock-names = "gcc_mdio_ahb_clk"; @@ -421,6 +422,22 @@ interrupt-controller; #interrupt-cells = <2>; + mdio_pins: mdio-state { + mdc-pins { + pins = "gpio36"; + function = "mdc"; + drive-strength = <8>; + bias-pull-up; + }; + + mdio-pins { + pins = "gpio37"; + function = "mdio"; + drive-strength = <8>; + bias-pull-up; + }; + }; + uart1_pins: uart1-state { pins = "gpio31", "gpio32", "gpio33", "gpio34"; function = "blsp1_uart1"; diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi index f2da3706d5c8..347815e5983e 100644 --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi @@ -5852,142 +5852,124 @@ gpio-ranges = <&tlmm 0 0 175>; wakeup-parent = <&pdc>; - cam_mclk3_default: cam-mclk3-default-state { - pins = "gpio67"; - function = "cam_mclk"; - drive-strength = <2>; - bias-disable; + qup_i2c0_data_clk: qup-i2c0-data-clk-state { + pins = "gpio0", "gpio1"; + function = "qup00"; }; - cci0_default: cci0-default-state { - pins = "gpio69", "gpio70"; - function = "cci_i2c"; - drive-strength = <2>; - bias-pull-up; + qup_spi0_data_clk: qup-spi0-data-clk-state { + pins = "gpio0", "gpio1", "gpio2"; + function = "qup00"; }; - cci0_sleep: cci0-sleep-state { - pins = "gpio69", "gpio70"; - function = "cci_i2c"; - drive-strength = <2>; - bias-pull-down; + qup_uart0_cts: qup-uart0-cts-state { + pins = "gpio0"; + function = "qup00"; }; - cci1_default: cci1-default-state { - pins = "gpio71", "gpio72"; - function = "cci_i2c"; - drive-strength = <2>; - bias-pull-up; + qup_uart0_rts: qup-uart0-rts-state { + pins = "gpio1"; + function = "qup00"; }; - cci1_sleep: cci1-sleep-state { - pins = "gpio71", "gpio72"; - function = "cci_i2c"; - drive-strength = <2>; - bias-pull-down; + qup_uart0_tx: qup-uart0-tx-state { + pins = "gpio2"; + function = "qup00"; }; - cci2_default: cci2-default-state { - pins = "gpio73", "gpio74"; - function = "cci_i2c"; - drive-strength = <2>; - bias-pull-up; + qup_spi0_cs: qup-spi0-cs-state { + pins = "gpio3"; + function = "qup00"; }; - cci2_sleep: cci2-sleep-state { - pins = "gpio73", "gpio74"; - function = "cci_i2c"; - drive-strength = <2>; - bias-pull-down; + qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { + pins = "gpio3"; + function = "gpio"; }; - cci3_default: cci3-default-state { - pins = "gpio75", "gpio76"; - function = "cci_i2c"; - drive-strength = <2>; - bias-pull-up; + qup_uart0_rx: qup-uart0-rx-state { + pins = "gpio3"; + function = "qup00"; }; - cci3_sleep: cci3-sleep-state { - pins = "gpio75", "gpio76"; - function = "cci_i2c"; - drive-strength = <2>; - bias-pull-down; + qup_i2c1_data_clk: qup-i2c1-data-clk-state { + pins = "gpio4", "gpio5"; + function = "qup01"; }; - dp_hot_plug_det: dp-hot-plug-det-state { - pins = "gpio47"; - function = "dp_hot"; + qup_spi1_data_clk: qup-spi1-data-clk-state { + pins = "gpio4", "gpio5", "gpio6"; + function = "qup01"; }; - edp_hot_plug_det: edp-hot-plug-det-state { - pins = "gpio60"; - function = "edp_hot"; + qup_uart1_cts: qup-uart1-cts-state { + pins = "gpio4"; + function = "qup01"; }; - mi2s0_data0: mi2s0-data0-state { - pins = "gpio98"; - function = "mi2s0_data0"; + qup_uart1_rts: qup-uart1-rts-state { + pins = "gpio5"; + function = "qup01"; }; - mi2s0_data1: mi2s0-data1-state { - pins = "gpio99"; - function = "mi2s0_data1"; + qup_uart1_tx: qup-uart1-tx-state { + pins = "gpio6"; + function = "qup01"; }; - mi2s0_mclk: mi2s0-mclk-state { - pins = "gpio96"; - function = "pri_mi2s"; + qup_spi1_cs: qup-spi1-cs-state { + pins = "gpio7"; + function = "qup01"; }; - mi2s0_sclk: mi2s0-sclk-state { - pins = "gpio97"; - function = "mi2s0_sck"; + qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { + pins = "gpio7"; + function = "gpio"; }; - mi2s0_ws: mi2s0-ws-state { - pins = "gpio100"; - function = "mi2s0_ws"; + qup_uart1_rx: qup-uart1-rx-state { + pins = "gpio7"; + function = "qup01"; }; - mi2s1_data0: mi2s1-data0-state { - pins = "gpio107"; - function = "mi2s1_data0"; + qup_i2c2_data_clk: qup-i2c2-data-clk-state { + pins = "gpio8", "gpio9"; + function = "qup02"; }; - mi2s1_sclk: mi2s1-sclk-state { - pins = "gpio106"; - function = "mi2s1_sck"; + qup_spi2_data_clk: qup-spi2-data-clk-state { + pins = "gpio8", "gpio9", "gpio10"; + function = "qup02"; }; - mi2s1_ws: mi2s1-ws-state { - pins = "gpio108"; - function = "mi2s1_ws"; + qup_uart2_cts: qup-uart2-cts-state { + pins = "gpio8"; + function = "qup02"; }; - pcie0_clkreq_n: pcie0-clkreq-n-state { - pins = "gpio88"; - function = "pcie0_clkreqn"; + qup_uart2_rts: qup-uart2-rts-state { + pins = "gpio9"; + function = "qup02"; }; - pcie1_clkreq_n: pcie1-clkreq-n-state { - pins = "gpio79"; - function = "pcie1_clkreqn"; + qup_uart2_tx: qup-uart2-tx-state { + pins = "gpio10"; + function = "qup02"; }; - qspi_clk: qspi-clk-state { - pins = "gpio14"; - function = "qspi_clk"; + qup_spi2_cs: qup-spi2-cs-state { + pins = "gpio11"; + function = "qup02"; }; - qspi_cs0: qspi-cs0-state { - pins = "gpio15"; - function = "qspi_cs"; + qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { + pins = "gpio11"; + function = "gpio"; }; - qspi_cs1: qspi-cs1-state { - pins = "gpio19"; - function = "qspi_cs"; + qup_uart2_rx: qup-uart2-rx-state { + pins = "gpio11"; + function = "qup02"; }; qspi_data0: qspi-data0-state { @@ -5995,159 +5977,94 @@ function = "qspi_data"; }; - qspi_data1: qspi-data1-state { - pins = "gpio13"; - function = "qspi_data"; - }; - - qspi_data23: qspi-data23-state { - pins = "gpio16", "gpio17"; - function = "qspi_data"; - }; - - qup_i2c0_data_clk: qup-i2c0-data-clk-state { - pins = "gpio0", "gpio1"; - function = "qup00"; - }; - - qup_i2c1_data_clk: qup-i2c1-data-clk-state { - pins = "gpio4", "gpio5"; - function = "qup01"; - }; - - qup_i2c2_data_clk: qup-i2c2-data-clk-state { - pins = "gpio8", "gpio9"; - function = "qup02"; - }; - qup_i2c3_data_clk: qup-i2c3-data-clk-state { pins = "gpio12", "gpio13"; function = "qup03"; }; - qup_i2c4_data_clk: qup-i2c4-data-clk-state { - pins = "gpio16", "gpio17"; - function = "qup04"; - }; - - qup_i2c5_data_clk: qup-i2c5-data-clk-state { - pins = "gpio20", "gpio21"; - function = "qup05"; - }; - - qup_i2c6_data_clk: qup-i2c6-data-clk-state { - pins = "gpio24", "gpio25"; - function = "qup06"; - }; - - qup_i2c7_data_clk: qup-i2c7-data-clk-state { - pins = "gpio28", "gpio29"; - function = "qup07"; - }; - - qup_i2c8_data_clk: qup-i2c8-data-clk-state { - pins = "gpio32", "gpio33"; - function = "qup10"; - }; - - qup_i2c9_data_clk: qup-i2c9-data-clk-state { - pins = "gpio36", "gpio37"; - function = "qup11"; - }; - - qup_i2c10_data_clk: qup-i2c10-data-clk-state { - pins = "gpio40", "gpio41"; - function = "qup12"; + qup_spi3_data_clk: qup-spi3-data-clk-state { + pins = "gpio12", "gpio13", "gpio14"; + function = "qup03"; }; - qup_i2c11_data_clk: qup-i2c11-data-clk-state { - pins = "gpio44", "gpio45"; - function = "qup13"; + qup_uart3_cts: qup-uart3-cts-state { + pins = "gpio12"; + function = "qup03"; }; - qup_i2c12_data_clk: qup-i2c12-data-clk-state { - pins = "gpio48", "gpio49"; - function = "qup14"; + qspi_data1: qspi-data1-state { + pins = "gpio13"; + function = "qspi_data"; }; - qup_i2c13_data_clk: qup-i2c13-data-clk-state { - pins = "gpio52", "gpio53"; - function = "qup15"; + qup_uart3_rts: qup-uart3-rts-state { + pins = "gpio13"; + function = "qup03"; }; - qup_i2c14_data_clk: qup-i2c14-data-clk-state { - pins = "gpio56", "gpio57"; - function = "qup16"; + qspi_clk: qspi-clk-state { + pins = "gpio14"; + function = "qspi_clk"; }; - qup_i2c15_data_clk: qup-i2c15-data-clk-state { - pins = "gpio60", "gpio61"; - function = "qup17"; + qup_uart3_tx: qup-uart3-tx-state { + pins = "gpio14"; + function = "qup03"; }; - qup_spi0_data_clk: qup-spi0-data-clk-state { - pins = "gpio0", "gpio1", "gpio2"; - function = "qup00"; + qspi_cs0: qspi-cs0-state { + pins = "gpio15"; + function = "qspi_cs"; }; - qup_spi0_cs: qup-spi0-cs-state { - pins = "gpio3"; - function = "qup00"; + qup_spi3_cs: qup-spi3-cs-state { + pins = "gpio15"; + function = "qup03"; }; - qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { - pins = "gpio3"; + qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { + pins = "gpio15"; function = "gpio"; }; - qup_spi1_data_clk: qup-spi1-data-clk-state { - pins = "gpio4", "gpio5", "gpio6"; - function = "qup01"; - }; - - qup_spi1_cs: qup-spi1-cs-state { - pins = "gpio7"; - function = "qup01"; - }; - - qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { - pins = "gpio7"; - function = "gpio"; + qup_uart3_rx: qup-uart3-rx-state { + pins = "gpio15"; + function = "qup03"; }; - qup_spi2_data_clk: qup-spi2-data-clk-state { - pins = "gpio8", "gpio9", "gpio10"; - function = "qup02"; + qspi_data23: qspi-data23-state { + pins = "gpio16", "gpio17"; + function = "qspi_data"; }; - qup_spi2_cs: qup-spi2-cs-state { - pins = "gpio11"; - function = "qup02"; + qup_i2c4_data_clk: qup-i2c4-data-clk-state { + pins = "gpio16", "gpio17"; + function = "qup04"; }; - qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { - pins = "gpio11"; - function = "gpio"; + qup_spi4_data_clk: qup-spi4-data-clk-state { + pins = "gpio16", "gpio17", "gpio18"; + function = "qup04"; }; - qup_spi3_data_clk: qup-spi3-data-clk-state { - pins = "gpio12", "gpio13", "gpio14"; - function = "qup03"; + qup_uart4_cts: qup-uart4-cts-state { + pins = "gpio16"; + function = "qup04"; }; - qup_spi3_cs: qup-spi3-cs-state { - pins = "gpio15"; - function = "qup03"; + qup_uart4_rts: qup-uart4-rts-state { + pins = "gpio17"; + function = "qup04"; }; - qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { - pins = "gpio15"; - function = "gpio"; + qup_uart4_tx: qup-uart4-tx-state { + pins = "gpio18"; + function = "qup04"; }; - qup_spi4_data_clk: qup-spi4-data-clk-state { - pins = "gpio16", "gpio17", "gpio18"; - function = "qup04"; + qspi_cs1: qspi-cs1-state { + pins = "gpio19"; + function = "qspi_cs"; }; qup_spi4_cs: qup-spi4-cs-state { @@ -6160,11 +6077,26 @@ function = "gpio"; }; + qup_uart4_rx: qup-uart4-rx-state { + pins = "gpio19"; + function = "qup04"; + }; + + qup_i2c5_data_clk: qup-i2c5-data-clk-state { + pins = "gpio20", "gpio21"; + function = "qup05"; + }; + qup_spi5_data_clk: qup-spi5-data-clk-state { pins = "gpio20", "gpio21", "gpio22"; function = "qup05"; }; + qup_uart5_tx: qup-uart5-tx-state { + pins = "gpio22"; + function = "qup05"; + }; + qup_spi5_cs: qup-spi5-cs-state { pins = "gpio23"; function = "qup05"; @@ -6175,11 +6107,36 @@ function = "gpio"; }; + qup_uart5_rx: qup-uart5-rx-state { + pins = "gpio23"; + function = "qup05"; + }; + + qup_i2c6_data_clk: qup-i2c6-data-clk-state { + pins = "gpio24", "gpio25"; + function = "qup06"; + }; + qup_spi6_data_clk: qup-spi6-data-clk-state { pins = "gpio24", "gpio25", "gpio26"; function = "qup06"; }; + qup_uart6_cts: qup-uart6-cts-state { + pins = "gpio24"; + function = "qup06"; + }; + + qup_uart6_rts: qup-uart6-rts-state { + pins = "gpio25"; + function = "qup06"; + }; + + qup_uart6_tx: qup-uart6-tx-state { + pins = "gpio26"; + function = "qup06"; + }; + qup_spi6_cs: qup-spi6-cs-state { pins = "gpio27"; function = "qup06"; @@ -6190,11 +6147,36 @@ function = "gpio"; }; + qup_uart6_rx: qup-uart6-rx-state { + pins = "gpio27"; + function = "qup06"; + }; + + qup_i2c7_data_clk: qup-i2c7-data-clk-state { + pins = "gpio28", "gpio29"; + function = "qup07"; + }; + qup_spi7_data_clk: qup-spi7-data-clk-state { pins = "gpio28", "gpio29", "gpio30"; function = "qup07"; }; + qup_uart7_cts: qup-uart7-cts-state { + pins = "gpio28"; + function = "qup07"; + }; + + qup_uart7_rts: qup-uart7-rts-state { + pins = "gpio29"; + function = "qup07"; + }; + + qup_uart7_tx: qup-uart7-tx-state { + pins = "gpio30"; + function = "qup07"; + }; + qup_spi7_cs: qup-spi7-cs-state { pins = "gpio31"; function = "qup07"; @@ -6205,11 +6187,36 @@ function = "gpio"; }; + qup_uart7_rx: qup-uart7-rx-state { + pins = "gpio31"; + function = "qup07"; + }; + + qup_i2c8_data_clk: qup-i2c8-data-clk-state { + pins = "gpio32", "gpio33"; + function = "qup10"; + }; + qup_spi8_data_clk: qup-spi8-data-clk-state { pins = "gpio32", "gpio33", "gpio34"; function = "qup10"; }; + qup_uart8_cts: qup-uart8-cts-state { + pins = "gpio32"; + function = "qup10"; + }; + + qup_uart8_rts: qup-uart8-rts-state { + pins = "gpio33"; + function = "qup10"; + }; + + qup_uart8_tx: qup-uart8-tx-state { + pins = "gpio34"; + function = "qup10"; + }; + qup_spi8_cs: qup-spi8-cs-state { pins = "gpio35"; function = "qup10"; @@ -6220,419 +6227,447 @@ function = "gpio"; }; + qup_uart8_rx: qup-uart8-rx-state { + pins = "gpio35"; + function = "qup10"; + }; + + qup_i2c9_data_clk: qup-i2c9-data-clk-state { + pins = "gpio36", "gpio37"; + function = "qup11"; + }; + qup_spi9_data_clk: qup-spi9-data-clk-state { pins = "gpio36", "gpio37", "gpio38"; function = "qup11"; }; - qup_spi9_cs: qup-spi9-cs-state { - pins = "gpio39"; + qup_uart9_cts: qup-uart9-cts-state { + pins = "gpio36"; function = "qup11"; }; - qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { - pins = "gpio39"; - function = "gpio"; + qup_uart9_rts: qup-uart9-rts-state { + pins = "gpio37"; + function = "qup11"; }; - qup_spi10_data_clk: qup-spi10-data-clk-state { - pins = "gpio40", "gpio41", "gpio42"; - function = "qup12"; + qup_uart9_tx: qup-uart9-tx-state { + pins = "gpio38"; + function = "qup11"; }; - qup_spi10_cs: qup-spi10-cs-state { - pins = "gpio43"; - function = "qup12"; + qup_spi9_cs: qup-spi9-cs-state { + pins = "gpio39"; + function = "qup11"; }; - qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { - pins = "gpio43"; + qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { + pins = "gpio39"; function = "gpio"; }; - qup_spi11_data_clk: qup-spi11-data-clk-state { - pins = "gpio44", "gpio45", "gpio46"; - function = "qup13"; - }; - - qup_spi11_cs: qup-spi11-cs-state { - pins = "gpio47"; - function = "qup13"; + qup_uart9_rx: qup-uart9-rx-state { + pins = "gpio39"; + function = "qup11"; }; - qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { - pins = "gpio47"; - function = "gpio"; + qup_i2c10_data_clk: qup-i2c10-data-clk-state { + pins = "gpio40", "gpio41"; + function = "qup12"; }; - qup_spi12_data_clk: qup-spi12-data-clk-state { - pins = "gpio48", "gpio49", "gpio50"; - function = "qup14"; + qup_spi10_data_clk: qup-spi10-data-clk-state { + pins = "gpio40", "gpio41", "gpio42"; + function = "qup12"; }; - qup_spi12_cs: qup-spi12-cs-state { - pins = "gpio51"; - function = "qup14"; + qup_uart10_cts: qup-uart10-cts-state { + pins = "gpio40"; + function = "qup12"; }; - qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { - pins = "gpio51"; - function = "gpio"; + qup_uart10_rts: qup-uart10-rts-state { + pins = "gpio41"; + function = "qup12"; }; - qup_spi13_data_clk: qup-spi13-data-clk-state { - pins = "gpio52", "gpio53", "gpio54"; - function = "qup15"; + qup_uart10_tx: qup-uart10-tx-state { + pins = "gpio42"; + function = "qup12"; }; - qup_spi13_cs: qup-spi13-cs-state { - pins = "gpio55"; - function = "qup15"; + qup_spi10_cs: qup-spi10-cs-state { + pins = "gpio43"; + function = "qup12"; }; - qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { - pins = "gpio55"; + qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { + pins = "gpio43"; function = "gpio"; }; - qup_spi14_data_clk: qup-spi14-data-clk-state { - pins = "gpio56", "gpio57", "gpio58"; - function = "qup16"; - }; - - qup_spi14_cs: qup-spi14-cs-state { - pins = "gpio59"; - function = "qup16"; + qup_uart10_rx: qup-uart10-rx-state { + pins = "gpio43"; + function = "qup12"; }; - qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { - pins = "gpio59"; - function = "gpio"; + qup_i2c11_data_clk: qup-i2c11-data-clk-state { + pins = "gpio44", "gpio45"; + function = "qup13"; }; - qup_spi15_data_clk: qup-spi15-data-clk-state { - pins = "gpio60", "gpio61", "gpio62"; - function = "qup17"; + qup_spi11_data_clk: qup-spi11-data-clk-state { + pins = "gpio44", "gpio45", "gpio46"; + function = "qup13"; }; - qup_spi15_cs: qup-spi15-cs-state { - pins = "gpio63"; - function = "qup17"; + qup_uart11_cts: qup-uart11-cts-state { + pins = "gpio44"; + function = "qup13"; }; - qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { - pins = "gpio63"; - function = "gpio"; + qup_uart11_rts: qup-uart11-rts-state { + pins = "gpio45"; + function = "qup13"; }; - qup_uart0_cts: qup-uart0-cts-state { - pins = "gpio0"; - function = "qup00"; + qup_uart11_tx: qup-uart11-tx-state { + pins = "gpio46"; + function = "qup13"; }; - qup_uart0_rts: qup-uart0-rts-state { - pins = "gpio1"; - function = "qup00"; + dp_hot_plug_det: dp-hot-plug-det-state { + pins = "gpio47"; + function = "dp_hot"; }; - qup_uart0_tx: qup-uart0-tx-state { - pins = "gpio2"; - function = "qup00"; + qup_spi11_cs: qup-spi11-cs-state { + pins = "gpio47"; + function = "qup13"; }; - qup_uart0_rx: qup-uart0-rx-state { - pins = "gpio3"; - function = "qup00"; + qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { + pins = "gpio47"; + function = "gpio"; }; - qup_uart1_cts: qup-uart1-cts-state { - pins = "gpio4"; - function = "qup01"; + qup_uart11_rx: qup-uart11-rx-state { + pins = "gpio47"; + function = "qup13"; }; - qup_uart1_rts: qup-uart1-rts-state { - pins = "gpio5"; - function = "qup01"; + qup_i2c12_data_clk: qup-i2c12-data-clk-state { + pins = "gpio48", "gpio49"; + function = "qup14"; }; - qup_uart1_tx: qup-uart1-tx-state { - pins = "gpio6"; - function = "qup01"; + qup_spi12_data_clk: qup-spi12-data-clk-state { + pins = "gpio48", "gpio49", "gpio50"; + function = "qup14"; }; - qup_uart1_rx: qup-uart1-rx-state { - pins = "gpio7"; - function = "qup01"; + qup_uart12_cts: qup-uart12-cts-state { + pins = "gpio48"; + function = "qup14"; }; - qup_uart2_cts: qup-uart2-cts-state { - pins = "gpio8"; - function = "qup02"; + qup_uart12_rts: qup-uart12-rts-state { + pins = "gpio49"; + function = "qup14"; }; - qup_uart2_rts: qup-uart2-rts-state { - pins = "gpio9"; - function = "qup02"; + qup_uart12_tx: qup-uart12-tx-state { + pins = "gpio50"; + function = "qup14"; }; - qup_uart2_tx: qup-uart2-tx-state { - pins = "gpio10"; - function = "qup02"; + qup_spi12_cs: qup-spi12-cs-state { + pins = "gpio51"; + function = "qup14"; }; - qup_uart2_rx: qup-uart2-rx-state { - pins = "gpio11"; - function = "qup02"; + qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { + pins = "gpio51"; + function = "gpio"; }; - qup_uart3_cts: qup-uart3-cts-state { - pins = "gpio12"; - function = "qup03"; + qup_uart12_rx: qup-uart12-rx-state { + pins = "gpio51"; + function = "qup14"; }; - qup_uart3_rts: qup-uart3-rts-state { - pins = "gpio13"; - function = "qup03"; + qup_i2c13_data_clk: qup-i2c13-data-clk-state { + pins = "gpio52", "gpio53"; + function = "qup15"; }; - qup_uart3_tx: qup-uart3-tx-state { - pins = "gpio14"; - function = "qup03"; + qup_spi13_data_clk: qup-spi13-data-clk-state { + pins = "gpio52", "gpio53", "gpio54"; + function = "qup15"; }; - qup_uart3_rx: qup-uart3-rx-state { - pins = "gpio15"; - function = "qup03"; + qup_uart13_cts: qup-uart13-cts-state { + pins = "gpio52"; + function = "qup15"; }; - qup_uart4_cts: qup-uart4-cts-state { - pins = "gpio16"; - function = "qup04"; + qup_uart13_rts: qup-uart13-rts-state { + pins = "gpio53"; + function = "qup15"; }; - qup_uart4_rts: qup-uart4-rts-state { - pins = "gpio17"; - function = "qup04"; + qup_uart13_tx: qup-uart13-tx-state { + pins = "gpio54"; + function = "qup15"; }; - qup_uart4_tx: qup-uart4-tx-state { - pins = "gpio18"; - function = "qup04"; + qup_spi13_cs: qup-spi13-cs-state { + pins = "gpio55"; + function = "qup15"; }; - qup_uart4_rx: qup-uart4-rx-state { - pins = "gpio19"; - function = "qup04"; + qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { + pins = "gpio55"; + function = "gpio"; }; - qup_uart5_tx: qup-uart5-tx-state { - pins = "gpio22"; - function = "qup05"; + qup_uart13_rx: qup-uart13-rx-state { + pins = "gpio55"; + function = "qup15"; }; - qup_uart5_rx: qup-uart5-rx-state { - pins = "gpio23"; - function = "qup05"; + qup_i2c14_data_clk: qup-i2c14-data-clk-state { + pins = "gpio56", "gpio57"; + function = "qup16"; }; - qup_uart6_cts: qup-uart6-cts-state { - pins = "gpio24"; - function = "qup06"; + qup_spi14_data_clk: qup-spi14-data-clk-state { + pins = "gpio56", "gpio57", "gpio58"; + function = "qup16"; }; - qup_uart6_rts: qup-uart6-rts-state { - pins = "gpio25"; - function = "qup06"; + qup_uart14_cts: qup-uart14-cts-state { + pins = "gpio56"; + function = "qup16"; }; - qup_uart6_tx: qup-uart6-tx-state { - pins = "gpio26"; - function = "qup06"; + qup_uart14_rts: qup-uart14-rts-state { + pins = "gpio57"; + function = "qup16"; }; - qup_uart6_rx: qup-uart6-rx-state { - pins = "gpio27"; - function = "qup06"; + qup_uart14_tx: qup-uart14-tx-state { + pins = "gpio58"; + function = "qup16"; }; - qup_uart7_cts: qup-uart7-cts-state { - pins = "gpio28"; - function = "qup07"; + qup_spi14_cs: qup-spi14-cs-state { + pins = "gpio59"; + function = "qup16"; }; - qup_uart7_rts: qup-uart7-rts-state { - pins = "gpio29"; - function = "qup07"; + qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { + pins = "gpio59"; + function = "gpio"; }; - qup_uart7_tx: qup-uart7-tx-state { - pins = "gpio30"; - function = "qup07"; + qup_uart14_rx: qup-uart14-rx-state { + pins = "gpio59"; + function = "qup16"; }; - qup_uart7_rx: qup-uart7-rx-state { - pins = "gpio31"; - function = "qup07"; + edp_hot_plug_det: edp-hot-plug-det-state { + pins = "gpio60"; + function = "edp_hot"; }; - qup_uart8_cts: qup-uart8-cts-state { - pins = "gpio32"; - function = "qup10"; + qup_i2c15_data_clk: qup-i2c15-data-clk-state { + pins = "gpio60", "gpio61"; + function = "qup17"; }; - qup_uart8_rts: qup-uart8-rts-state { - pins = "gpio33"; - function = "qup10"; + qup_spi15_data_clk: qup-spi15-data-clk-state { + pins = "gpio60", "gpio61", "gpio62"; + function = "qup17"; }; - qup_uart8_tx: qup-uart8-tx-state { - pins = "gpio34"; - function = "qup10"; + qup_uart15_cts: qup-uart15-cts-state { + pins = "gpio60"; + function = "qup17"; }; - qup_uart8_rx: qup-uart8-rx-state { - pins = "gpio35"; - function = "qup10"; + qup_uart15_rts: qup-uart15-rts-state { + pins = "gpio61"; + function = "qup17"; }; - qup_uart9_cts: qup-uart9-cts-state { - pins = "gpio36"; - function = "qup11"; + qup_uart15_tx: qup-uart15-tx-state { + pins = "gpio62"; + function = "qup17"; }; - qup_uart9_rts: qup-uart9-rts-state { - pins = "gpio37"; - function = "qup11"; + qup_spi15_cs: qup-spi15-cs-state { + pins = "gpio63"; + function = "qup17"; }; - qup_uart9_tx: qup-uart9-tx-state { - pins = "gpio38"; - function = "qup11"; + qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { + pins = "gpio63"; + function = "gpio"; }; - qup_uart9_rx: qup-uart9-rx-state { - pins = "gpio39"; - function = "qup11"; + qup_uart15_rx: qup-uart15-rx-state { + pins = "gpio63"; + function = "qup17"; }; - qup_uart10_cts: qup-uart10-cts-state { - pins = "gpio40"; - function = "qup12"; + cam_mclk0_default: cam-mclk0-default-state { + pins = "gpio64"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; }; - qup_uart10_rts: qup-uart10-rts-state { - pins = "gpio41"; - function = "qup12"; + cam_mclk1_default: cam-mclk1-default-state { + pins = "gpio65"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; }; - qup_uart10_tx: qup-uart10-tx-state { - pins = "gpio42"; - function = "qup12"; + cam_mclk2_default: cam-mclk2-default-state { + pins = "gpio66"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; }; - qup_uart10_rx: qup-uart10-rx-state { - pins = "gpio43"; - function = "qup12"; + cam_mclk3_default: cam-mclk3-default-state { + pins = "gpio67"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; }; - qup_uart11_cts: qup-uart11-cts-state { - pins = "gpio44"; - function = "qup13"; + cam_mclk4_default: cam-mclk4-default-state { + pins = "gpio68"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; }; - qup_uart11_rts: qup-uart11-rts-state { - pins = "gpio45"; - function = "qup13"; + cci0_default: cci0-default-state { + pins = "gpio69", "gpio70"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; }; - qup_uart11_tx: qup-uart11-tx-state { - pins = "gpio46"; - function = "qup13"; + cci0_sleep: cci0-sleep-state { + pins = "gpio69", "gpio70"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; }; - qup_uart11_rx: qup-uart11-rx-state { - pins = "gpio47"; - function = "qup13"; + cci1_default: cci1-default-state { + pins = "gpio71", "gpio72"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; }; - qup_uart12_cts: qup-uart12-cts-state { - pins = "gpio48"; - function = "qup14"; + cci1_sleep: cci1-sleep-state { + pins = "gpio71", "gpio72"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; }; - qup_uart12_rts: qup-uart12-rts-state { - pins = "gpio49"; - function = "qup14"; + cci2_default: cci2-default-state { + pins = "gpio73", "gpio74"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; }; - qup_uart12_tx: qup-uart12-tx-state { - pins = "gpio50"; - function = "qup14"; + cci2_sleep: cci2-sleep-state { + pins = "gpio73", "gpio74"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; }; - qup_uart12_rx: qup-uart12-rx-state { - pins = "gpio51"; - function = "qup14"; + cci3_default: cci3-default-state { + pins = "gpio75", "gpio76"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; }; - qup_uart13_cts: qup-uart13-cts-state { - pins = "gpio52"; - function = "qup15"; + cci3_sleep: cci3-sleep-state { + pins = "gpio75", "gpio76"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; }; - qup_uart13_rts: qup-uart13-rts-state { - pins = "gpio53"; - function = "qup15"; + pcie1_clkreq_n: pcie1-clkreq-n-state { + pins = "gpio79"; + function = "pcie1_clkreqn"; }; - qup_uart13_tx: qup-uart13-tx-state { - pins = "gpio54"; - function = "qup15"; + pcie0_clkreq_n: pcie0-clkreq-n-state { + pins = "gpio88"; + function = "pcie0_clkreqn"; }; - qup_uart13_rx: qup-uart13-rx-state { - pins = "gpio55"; - function = "qup15"; + cam_mclk5_default: cam-mclk5-default-state { + pins = "gpio93"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; }; - qup_uart14_cts: qup-uart14-cts-state { - pins = "gpio56"; - function = "qup16"; + mi2s0_mclk: mi2s0-mclk-state { + pins = "gpio96"; + function = "pri_mi2s"; }; - qup_uart14_rts: qup-uart14-rts-state { - pins = "gpio57"; - function = "qup16"; + mi2s0_sclk: mi2s0-sclk-state { + pins = "gpio97"; + function = "mi2s0_sck"; }; - qup_uart14_tx: qup-uart14-tx-state { - pins = "gpio58"; - function = "qup16"; + mi2s0_data0: mi2s0-data0-state { + pins = "gpio98"; + function = "mi2s0_data0"; }; - qup_uart14_rx: qup-uart14-rx-state { - pins = "gpio59"; - function = "qup16"; + mi2s0_data1: mi2s0-data1-state { + pins = "gpio99"; + function = "mi2s0_data1"; }; - qup_uart15_cts: qup-uart15-cts-state { - pins = "gpio60"; - function = "qup17"; + mi2s0_ws: mi2s0-ws-state { + pins = "gpio100"; + function = "mi2s0_ws"; }; - qup_uart15_rts: qup-uart15-rts-state { - pins = "gpio61"; - function = "qup17"; + mi2s1_sclk: mi2s1-sclk-state { + pins = "gpio106"; + function = "mi2s1_sck"; }; - qup_uart15_tx: qup-uart15-tx-state { - pins = "gpio62"; - function = "qup17"; + mi2s1_data0: mi2s1-data0-state { + pins = "gpio107"; + function = "mi2s1_data0"; }; - qup_uart15_rx: qup-uart15-rx-state { - pins = "gpio63"; - function = "qup17"; + mi2s1_ws: mi2s1-ws-state { + pins = "gpio108"; + function = "mi2s1_ws"; }; sdc1_clk: sdc1-clk-state { diff --git a/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso b/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso index 6cfa0bc1440e..e42314c64857 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso @@ -271,20 +271,12 @@ ranges; bus-range = <0x5 0xff>; - pcie@0,0 { + dev@0,0 { reg = <0x50000 0x0 0x0 0x0 0x0>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges; }; - pcie@0,1 { + dev@0,1 { reg = <0x50100 0x0 0x0 0x0 0x0>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/lemans-pmics.dtsi b/arch/arm64/boot/dts/qcom/lemans-pmics.dtsi index 500f715931aa..4c853053be85 100644 --- a/arch/arm64/boot/dts/qcom/lemans-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans-pmics.dtsi @@ -88,6 +88,58 @@ }; }; }; + + pm8775-mbg0-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pmm8654au_0_mbg_temp>; + + trips { + trip0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + pm8775-mbg1-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pmm8654au_1_mbg_temp>; + + trips { + trip0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + pm8775-mbg2-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pmm8654au_2_mbg_temp>; + + trips { + trip0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + pm8775-mbg3-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pmm8654au_3_mbg_temp>; + + trips { + trip0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; }; reboot-mode { @@ -189,6 +241,22 @@ }; }; + pmm8654au_sail_0: pmic@1 { + compatible = "qcom,pmm8654au", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmm8654au_0_mbg_temp: temperature-sensor@d700 { + compatible = "qcom,pm8775-mbg-tm"; + reg = <0xd700>; + io-channels = <&pmm8654au_0_adc ADC5_GEN3_DIE_TEMP(0)>; + io-channel-names = "thermal"; + interrupts-extended = <&spmi_bus 0x1 0xd7 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <0>; + }; + }; + pmm8654au_1: pmic@2 { compatible = "qcom,pmm8654au", "qcom,spmi-pmic"; reg = <0x2 SPMI_USID>; @@ -236,6 +304,22 @@ }; }; + pmm8654au_sail_1: pmic@3 { + compatible = "qcom,pmm8654au", "qcom,spmi-pmic"; + reg = <0x3 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmm8654au_1_mbg_temp: temperature-sensor@d700 { + compatible = "qcom,pm8775-mbg-tm"; + reg = <0xd700>; + io-channels = <&pmm8654au_1_adc ADC5_GEN3_DIE_TEMP(2)>; + io-channel-names = "thermal"; + interrupts-extended = <&spmi_bus 0x3 0xd7 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <0>; + }; + }; + pmm8654au_2: pmic@4 { compatible = "qcom,pmm8654au", "qcom,spmi-pmic"; reg = <0x4 SPMI_USID>; @@ -283,6 +367,22 @@ }; }; + pmm8654au_sail_2: pmic@5 { + compatible = "qcom,pmm8654au", "qcom,spmi-pmic"; + reg = <0x5 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmm8654au_2_mbg_temp: temperature-sensor@d700 { + compatible = "qcom,pm8775-mbg-tm"; + reg = <0xd700>; + io-channels = <&pmm8654au_2_adc ADC5_GEN3_DIE_TEMP(4)>; + io-channel-names = "thermal"; + interrupts-extended = <&spmi_bus 0x5 0xd7 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <0>; + }; + }; + pmm8654au_3: pmic@6 { compatible = "qcom,pmm8654au", "qcom,spmi-pmic"; reg = <0x6 SPMI_USID>; @@ -329,4 +429,20 @@ #interrupt-cells = <2>; }; }; + + pmm8654au_sail_3: pmic@7 { + compatible = "qcom,pmm8654au", "qcom,spmi-pmic"; + reg = <0x7 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmm8654au_3_mbg_temp: temperature-sensor@d700 { + compatible = "qcom,pm8775-mbg-tm"; + reg = <0xd700>; + io-channels = <&pmm8654au_3_adc ADC5_GEN3_DIE_TEMP(6)>; + io-channel-names = "thermal"; + interrupts-extended = <&spmi_bus 0x7 0xd7 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <0>; + }; + }; }; diff --git a/arch/arm64/boot/dts/qcom/mahua-crd.dts b/arch/arm64/boot/dts/qcom/mahua-crd.dts index fa5229064b10..17e40f2a6259 100644 --- a/arch/arm64/boot/dts/qcom/mahua-crd.dts +++ b/arch/arm64/boot/dts/qcom/mahua-crd.dts @@ -20,6 +20,11 @@ compatible = "qcom,mahua-crd", "qcom,mahua"; }; +&pcie3b_phy { + vdda-phy-supply = <&vreg_l3c_e1_0p89>; + vdda-pll-supply = <&vreg_l2c_e1_1p14>; +}; + &tcsr { vdda-qrefrpt0-0p9-supply = <&vreg_l2f_e1_0p83>; vdda-qrefrpt1-0p9-supply = <&vreg_l2f_e1_0p83>; diff --git a/arch/arm64/boot/dts/qcom/mahua.dtsi b/arch/arm64/boot/dts/qcom/mahua.dtsi index e6c059708912..a59c5ed7b48e 100644 --- a/arch/arm64/boot/dts/qcom/mahua.dtsi +++ b/arch/arm64/boot/dts/qcom/mahua.dtsi @@ -22,6 +22,8 @@ /delete-node/ &cpu_pd16; /delete-node/ &cpu_pd17; /delete-node/ &cti_wpss; +/delete-node/ &pcie3_phy; +/delete-node/ &pcie3a; /delete-node/ &thermal_aoss_6; /delete-node/ &thermal_aoss_7; /delete-node/ &thermal_cpu_2_0_0; @@ -79,6 +81,52 @@ compatible = "qcom,mahua-cnoc-cfg"; }; +&gcc { + clocks = <&rpmhcc RPMH_CXO_CLK>, /* Board XO source */ + <&rpmhcc RPMH_CXO_CLK_A>, /* Board XO_A source */ + <&sleep_clk>, /* Sleep */ + <0>, /* USB 0 Phy DP0 GMUX */ + <0>, /* USB 0 Phy DP1 GMUX */ + <0>, /* USB 0 Phy PCIE PIPEGMUX */ + <0>, /* USB 0 Phy PIPEGMUX */ + <0>, /* USB 0 Phy SYS PCIE PIPEGMUX */ + <0>, /* USB 1 Phy DP0 GMUX 2 */ + <0>, /* USB 1 Phy DP1 GMUX 2 */ + <0>, /* USB 1 Phy PCIE PIPEGMUX */ + <0>, /* USB 1 Phy PIPEGMUX */ + <0>, /* USB 1 Phy SYS PCIE PIPEGMUX */ + <0>, /* USB 2 Phy DP0 GMUX 2 */ + <0>, /* USB 2 Phy DP1 GMUX 2 */ + <0>, /* USB 2 Phy PCIE PIPEGMUX */ + <0>, /* USB 2 Phy PIPEGMUX */ + <0>, /* USB 2 Phy SYS PCIE PIPEGMUX */ + <0>, /* PCIe 3a pipe */ + <&pcie3b_phy>, /* PCIe 3b pipe */ + <&pcie4_phy>, /* PCIe 4 */ + <&pcie5_phy>, /* PCIe 5 */ + <&pcie6_phy>, /* PCIe 6 */ + <0>, /* QUSB4 0 PHY RX 0 */ + <0>, /* QUSB4 0 PHY RX 1 */ + <0>, /* QUSB4 1 PHY RX 0 */ + <0>, /* QUSB4 1 PHY RX 1 */ + <0>, /* QUSB4 2 PHY RX 0 */ + <0>, /* QUSB4 2 PHY RX 1 */ + <0>, /* UFS PHY RX Symbol 0 */ + <0>, /* UFS PHY RX Symbol 1 */ + <0>, /* UFS PHY TX Symbol 0 */ + <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, + <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, + <&usb_2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, + <&usb_mp_qmpphy0>, /* USB3 UNI PHY pipe 0 */ + <&usb_mp_qmpphy1>, /* USB3 UNI PHY pipe 1 */ + <0>, /* USB4 PHY 0 pcie pipe */ + <0>, /* USB4 PHY 0 Max pipe */ + <0>, /* USB4 PHY 1 pcie pipe */ + <0>, /* USB4 PHY 1 Max pipe */ + <0>, /* USB4 PHY 2 pcie */ + <0>; /* USB4 PHY 2 Max */ +}; + &hsc_noc { compatible = "qcom,mahua-hscnoc"; }; @@ -115,6 +163,10 @@ compatible = "qcom,mahua-oobm-ss-noc", "qcom,glymur-oobm-ss-noc"; }; +&pcie3b_port0 { + phys = <&pcie3b_phy>; +}; + &pcie5_phy { clocks = <&gcc GCC_PCIE_PHY_5_AUX_CLK>, <&gcc GCC_PCIE_5_CFG_AHB_CLK>, @@ -143,6 +195,43 @@ compatible = "qcom,mahua-pcie-west-slv-noc"; }; +&soc { + pcie3b_phy: phy@1b90000 { + compatible = "qcom,glymur-qmp-gen5x4-pcie-phy"; + reg = <0x0 0x01b90000 0x0 0x10000>; + + clocks = <&gcc GCC_PCIE_PHY_3B_AUX_CLK>, + <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, + <&tcsr TCSR_PCIE_3_CLKREF_EN>, + <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_3B_PIPE_CLK>, + <&gcc GCC_PCIE_3B_PIPE_DIV2_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; + + resets = <&gcc GCC_PCIE_3B_PHY_BCR>, + <&gcc GCC_PCIE_3B_NOCSR_COM_PHY_BCR>; + reset-names = "phy", + "phy_nocsr"; + + assigned-clocks = <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + power-domains = <&gcc GCC_PCIE_3B_PHY_GDSC>; + + #clock-cells = <0>; + clock-output-names = "pcie3b_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; +}; + &system_noc { compatible = "qcom,mahua-system-noc", "qcom,glymur-system-noc"; }; diff --git a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts index bb3b67e2fd01..acdcd3fa85dc 100644 --- a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts +++ b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts @@ -24,6 +24,7 @@ aliases { serial0 = &uart5; + serial1 = &uart11; }; gpio-keys { @@ -225,6 +226,67 @@ }; }; }; + + wcn6750-pmu { + compatible = "qcom,wcn6755-pmu", "qcom,wcn6750-pmu"; + + vddaon-supply = <&vreg_s3b>; + vddasd-supply = <&vreg_l7b>; + vddpmu-supply = <&vreg_s3b>; + vddrfa0p8-supply = <&vreg_s3b>; + vddrfa1p2-supply = <&vreg_s2b>; + vddrfa1p7-supply = <&vreg_s1b>; + vddrfa2p2-supply = <&vreg_s1j>; + + bt-enable-gpios = <&tlmm 53 GPIO_ACTIVE_HIGH>; + + clocks = <&rpmhcc RPMH_RF_CLK1>; + + pinctrl-0 = <&bluetooth_enable_default>, <&pmk8550_sleep_clk_default>; + pinctrl-names = "default"; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p7: ldo7 { + regulator-name = "vreg_pmu_rfa_1p7"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; }; &apps_rsc { @@ -723,6 +785,17 @@ qcom,tune-usb2-preem = /bits/ 8 <0x6>; }; +&pmk8550_gpios { + pmk8550_sleep_clk_default: sleep-clk-default-state { + pins = "gpio5"; + function = "func1"; + input-disable; + output-enable; + bias-disable; + power-source = <0>; + }; +}; + &pmr735b_gpios { s1j_enable_default: s1j-enable-default-state { pins = "gpio1"; @@ -771,6 +844,39 @@ status = "okay"; }; +&qup_uart11_cts { + /* + * Configure a bias-bus-hold on CTS to lower power + * usage when Bluetooth is turned off. Bus hold will + * maintain a low power state regardless of whether + * the Bluetooth module drives the pin in either + * direction or leaves the pin fully unpowered. + */ + bias-bus-hold; +}; + +&qup_uart11_rts { + /* We'll drive RTS, so no pull */ + drive-strength = <2>; + bias-disable; +}; + +&qup_uart11_rx { + /* + * Configure a pull-up on RX. This is needed to avoid + * garbage data when the TX pin of the Bluetooth module is + * in tri-state (module powered off or not driving the + * signal yet). + */ + bias-pull-up; +}; + +&qup_uart11_tx { + /* We'll drive TX, so no pull */ + drive-strength = <2>; + bias-disable; +}; + &qupv3_id_0 { status = "okay"; }; @@ -834,6 +940,59 @@ <13 1>, /* NC */ <63 2>; /* WLAN UART */ + qup_uart11_sleep_cts: qup-uart11-sleep-cts-state { + pins = "gpio48"; + function = "gpio"; + /* + * Configure a bias-bus-hold on CTS to lower power + * usage when Bluetooth is turned off. Bus hold will + * maintain a low power state regardless of whether + * the Bluetooth module drives the pin in either + * direction or leaves the pin fully unpowered. + */ + bias-bus-hold; + }; + + qup_uart11_sleep_rts: qup-uart11-sleep-rts-state { + pins = "gpio49"; + function = "gpio"; + /* + * Configure pull-down on RTS. As RTS is active low + * signal, pull it low to indicate the BT SoC that it + * can wakeup the system anytime from suspend state by + * pulling RX low (by sending wakeup bytes). + */ + bias-pull-down; + }; + + qup_uart11_sleep_tx: qup-uart11-sleep-tx-state { + pins = "gpio50"; + function = "gpio"; + /* + * Configure pull-up on TX when it isn't actively driven + * to prevent BT SoC from receiving garbage during sleep. + */ + bias-pull-up; + }; + + qup_uart11_sleep_rx: qup-uart11-sleep-rx-state { + pins = "gpio51"; + function = "gpio"; + /* + * Configure a pull-up on RX. This is needed to avoid + * garbage data when the TX pin of the Bluetooth module + * is floating which may cause spurious wakeups. + */ + bias-pull-up; + }; + + bluetooth_enable_default: bluetooth-enable-default-state { + pins = "gpio53"; + function = "gpio"; + output-low; + bias-disable; + }; + sdc2_card_det_n: sdc2-card-det-state { pins = "gpio65"; function = "gpio"; @@ -874,6 +1033,32 @@ status = "okay"; }; +&uart11 { + /delete-property/ interrupts; + interrupts-extended = <&intc GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>, + <&tlmm 51 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-1 = <&qup_uart11_sleep_cts>, + <&qup_uart11_sleep_rts>, + <&qup_uart11_sleep_tx>, + <&qup_uart11_sleep_rx>; + pinctrl-names = "default", + "sleep"; + + status = "okay"; + + bluetooth { + compatible = "qcom,wcn6755-bt", "qcom,wcn6750-bt"; + + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddbtcmx-supply = <&vreg_pmu_btcmx_0p85>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + }; +}; + &ufs_mem_hc { reset-gpios = <&tlmm 167 GPIO_ACTIVE_LOW>; @@ -913,3 +1098,9 @@ status = "okay"; }; + +&wifi { + qcom,calibration-variant = "Fairphone_Gen_6"; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi index aad8bf678916..268e0a3fc84c 100644 --- a/arch/arm64/boot/dts/qcom/milos.dtsi +++ b/arch/arm64/boot/dts/qcom/milos.dtsi @@ -18,7 +18,6 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/mailbox/qcom-ipcc.h> #include <dt-bindings/power/qcom,rpmhpd.h> -#include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/soc/qcom,gpr.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> @@ -1949,6 +1948,11 @@ <&sleep_clk>, <&gcc GCC_VIDEO_AHB_CLK>; + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MX>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; @@ -2031,6 +2035,11 @@ interconnects = <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS &mmss_noc SLAVE_MNOC_HF_MEM_NOC QCOM_ICC_TAG_ALWAYS>; + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MX>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; @@ -2340,7 +2349,6 @@ qcom,ee = <0>; qcom,channel = <0>; - qcom,bus-id = <0>; interrupt-controller; #interrupt-cells = <4>; @@ -2413,19 +2421,27 @@ }; qup_uart11_cts_rts: qup-uart11-cts-rts-state { - /* CTS, RTS */ - pins = "gpio48", "gpio49"; - function = "qup1_se4"; - drive-strength = <2>; - bias-pull-down; + qup_uart11_cts: cts-pins { + pins = "gpio48"; + function = "qup1_se4"; + }; + + qup_uart11_rts: rts-pins { + pins = "gpio49"; + function = "qup1_se4"; + }; }; qup_uart11_default: qup-uart11-default-state { - /* TX, RX */ - pins = "gpio50", "gpio51"; - function = "qup1_se4"; - drive-strength = <2>; - bias-pull-up; + qup_uart11_tx: tx-pins { + pins = "gpio50"; + function = "qup1_se4"; + }; + + qup_uart11_rx: rx-pins { + pins = "gpio51"; + function = "qup1_se4"; + }; }; sdc2_default: sdc2-default-state { @@ -2764,6 +2780,52 @@ }; }; + wifi: wifi@17110040 { + compatible = "qcom,wcn6755-wifi", "qcom,wcn6750-wifi"; + reg = <0x0 0x17110040 0x0 0x0>; + + iommus = <&apps_smmu 0x1400 0x1>; + + interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 769 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 770 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 771 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 772 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 773 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 774 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 775 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 776 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 777 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 778 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 779 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 780 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 781 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 782 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 783 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 784 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 785 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 786 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 787 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 788 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 789 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 790 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 791 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 792 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 793 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 794 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 795 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 796 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 797 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 798 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 799 IRQ_TYPE_EDGE_RISING 0>; + + qcom,rproc = <&remoteproc_wpss>; + qcom,smem-states = <&smp2p_wlan_out 0>; + qcom,smem-state-names = "wlan-smp2p-out"; + + status = "disabled"; + }; + timer@17420000 { compatible = "arm,armv7-timer-mem"; reg = <0x0 0x17420000 0x0 0x1000>; diff --git a/arch/arm64/boot/dts/qcom/monaco-ac-evk.dts b/arch/arm64/boot/dts/qcom/monaco-ac-evk.dts new file mode 100644 index 000000000000..6f3c3ffefe34 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/monaco-ac-evk.dts @@ -0,0 +1,938 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/sound/qcom,q6afe.h> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> + +#include "monaco.dtsi" +#include "monaco-pmics.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Monaco-ac EVK"; + compatible = "qcom,monaco-evk", "qcom,qcs8300"; + + aliases { + ethernet0 = ðernet0; + i2c1 = &i2c1; + serial0 = &uart7; + serial2 = &uart6; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + connector-2 { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + label = "micro-USB"; + type = "micro"; + + id-gpios = <&pmm8620au_0_gpios 9 GPIO_ACTIVE_HIGH>; + vbus-gpios = <&expander6 7 GPIO_ACTIVE_HIGH>; + vbus-supply = <&usb2_vbus>; + + pinctrl-0 = <&usb2_id>; + pinctrl-names = "default"; + + port { + usb2_con_hs_ep: endpoint { + remote-endpoint = <&usb_2_dwc3_hs>; + }; + }; + }; + + dmic: audio-codec-0 { + compatible = "dmic-codec"; + #sound-dai-cells = <0>; + num-channels = <1>; + }; + + max98357a: audio-codec-1 { + compatible = "maxim,max98357a"; + #sound-dai-cells = <0>; + }; + + dp-connector-0 { + compatible = "dp-connector"; + label = "DP0"; + type = "mini"; + + port { + dp0_connector_in: endpoint { + remote-endpoint = <<8713sx_dp0_out>; + }; + }; + }; + + dp-connector-1 { + compatible = "dp-connector"; + label = "DP1"; + type = "mini"; + + port { + dp1_connector_in: endpoint { + remote-endpoint = <<8713sx_dp1_out>; + }; + }; + }; + + usb2_vbus: regulator-usb2-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb2_vbus"; + gpio = <&pmm8650au_1_gpios 7 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + }; + + sound { + compatible = "qcom,qcs8275-sndcard"; + model = "MONACO-EVK"; + + pinctrl-0 = <&hs0_mi2s_active>, <&mi2s1_active>; + pinctrl-names = "default"; + + hs0-mi2s-playback-dai-link { + link-name = "HS0 MI2S Playback"; + + codec { + sound-dai = <&max98357a>; + }; + + cpu { + sound-dai = <&q6apmbedai PRIMARY_MI2S_RX>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + sec-mi2s-capture-dai-link { + link-name = "Secondary MI2S Capture"; + + codec { + sound-dai = <&dmic>; + }; + + cpu { + sound-dai = <&q6apmbedai SECONDARY_MI2S_TX>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + vreg_cam0_2p8: vreg-cam0-2p8 { + compatible = "regulator-fixed"; + regulator-name = "vreg_cam0_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + startup-delay-us = <10000>; + + gpio = <&tlmm 73 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&cam0_avdd_2v8_en_default>; + pinctrl-names = "default"; + }; + + vreg_cam1_2p8: vreg-cam1-2p8 { + compatible = "regulator-fixed"; + regulator-name = "vreg_cam1_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + startup-delay-us = <10000>; + + gpio = <&tlmm 74 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&cam1_avdd_2v8_en_default>; + pinctrl-names = "default"; + }; + + vreg_cam2_2p8: vreg-cam2-2p8 { + compatible = "regulator-fixed"; + regulator-name = "vreg_cam2_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + startup-delay-us = <10000>; + + gpio = <&tlmm 75 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&cam2_avdd_2v8_en_default>; + pinctrl-names = "default"; + }; + + /* This comes from a PMIC handled within the SAIL domain */ + vreg_s2s: vreg-s2s { + compatible = "regulator-fixed"; + regulator-name = "vreg_s2s"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id = "a"; + + vreg_l3a: ldo3 { + regulator-name = "vreg_l3a"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4a: ldo4 { + regulator-name = "vreg_l4a"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5a: ldo5 { + regulator-name = "vreg_l5a"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6a: ldo6 { + regulator-name = "vreg_l6a"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7a: ldo7 { + regulator-name = "vreg_l7a"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8a: ldo8 { + regulator-name = "vreg_l8a"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l9a: ldo9 { + regulator-name = "vreg_l9a"; + regulator-min-microvolt = <2970000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; + }; + vreg_s4a: smps4 { + regulator-name = "vreg_s4a"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s9a: smps9 { + regulator-name = "vreg_s9a"; + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-1 { + compatible = "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id = "c"; + + vreg_s5c: smps5 { + regulator-name = "vreg_s5c"; + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1104000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1c: ldo1 { + regulator-name = "vreg_l1c"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <512000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2c: ldo2 { + regulator-name = "vreg_l2c"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <904000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4c: ldo4 { + regulator-name = "vreg_l4c"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7c: ldo7 { + regulator-name = "vreg_l7c"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8c: ldo8 { + regulator-name = "vreg_l8c"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l9c: ldo9 { + regulator-name = "vreg_l9c"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; + }; + }; +}; + +ðernet0 { + phy-mode = "2500base-x"; + phy-handle = <&hsgmii_phy0>; + + pinctrl-0 = <ðernet0_default>; + pinctrl-names = "default"; + + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + nvmem-cells = <&mac_addr0>; + nvmem-cell-names = "mac-address"; + + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + hsgmii_phy0: ethernet-phy@1c { + compatible = "ethernet-phy-id004d.d101"; + reg = <0x1c>; + reset-gpios = <&tlmm 31 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <70000>; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x3>; + snps,priority = <0xc>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <4>; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + }; +}; + +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/qcs8300/a623_zap.mbn"; +}; + +&i2c0 { + status = "okay"; + + bridge@4f { + compatible = "lontium,lt8713sx"; + reg = <0x4f>; + reset-gpios = <&expander5 6 GPIO_ACTIVE_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lt8713sx_dp_in: endpoint { + remote-endpoint = <&mdss_dp0_out>; + }; + }; + + port@1 { + reg = <1>; + + lt8713sx_dp0_out: endpoint { + remote-endpoint = <&dp0_connector_in>; + }; + }; + + port@2 { + reg = <2>; + + lt8713sx_dp1_out: endpoint { + remote-endpoint = <&dp1_connector_in>; + }; + }; + }; + }; +}; + +&i2c1 { + pinctrl-0 = <&qup_i2c1_default>; + pinctrl-names = "default"; + + status = "okay"; + + fan_controller: fan@18 { + compatible = "ti,amc6821"; + reg = <0x18>; + #pwm-cells = <2>; + + fan { + pwms = <&fan_controller 40000 PWM_POLARITY_INVERTED>; + }; + }; + + eeprom0: eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + pagesize = <64>; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + mac_addr0: mac-addr@0 { + reg = <0x0 0x6>; + }; + }; + }; +}; + +&i2c15 { + pinctrl-0 = <&qup_i2c15_default>; + pinctrl-names = "default"; + + status = "okay"; + + expander0: gpio@38 { + compatible = "ti,tca9538"; + reg = <0x38>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + interrupts-extended = <&tlmm 56 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&expander0_int>; + pinctrl-names = "default"; + }; + + expander1: gpio@39 { + compatible = "ti,tca9538"; + reg = <0x39>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + interrupts-extended = <&tlmm 16 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&expander1_int>; + pinctrl-names = "default"; + }; + + expander2: gpio@3a { + compatible = "ti,tca9538"; + reg = <0x3a>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + interrupts-extended = <&tlmm 95 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&expander2_int>; + pinctrl-names = "default"; + }; + + expander3: gpio@3b { + compatible = "ti,tca9538"; + reg = <0x3b>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + interrupts-extended = <&tlmm 24 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&expander3_int>; + pinctrl-names = "default"; + }; + + expander4: gpio@3c { + compatible = "ti,tca9538"; + reg = <0x3c>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + interrupts-extended = <&tlmm 96 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&expander4_int>; + pinctrl-names = "default"; + }; + + expander5: gpio@3d { + compatible = "ti,tca9538"; + reg = <0x3d>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&expander5_int>; + pinctrl-names = "default"; + }; + + expander6: gpio@3e { + compatible = "ti,tca9538"; + reg = <0x3e>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + interrupts-extended = <&tlmm 52 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&expander6_int>; + pinctrl-names = "default"; + }; +}; + +&iris { + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + pinctrl-0 = <&dp_hot_plug_det>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&mdss_dp0_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + remote-endpoint = <<8713sx_dp_in>; +}; + +&mdss_dp0_phy { + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l4a>; + + status = "okay"; +}; + +&pcie0 { + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l6a>; + vdda-pll-supply = <&vreg_l5a>; + + status = "okay"; +}; + +&pcie1 { + pinctrl-0 = <&pcie1_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l6a>; + vdda-pll-supply = <&vreg_l5a>; + + status = "okay"; +}; + +&pcieport0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>; +}; + +&pcieport1 { + reset-gpios = <&tlmm 23 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>; +}; + +&pmm8620au_0_gpios { + usb2_id: usb2-id-state { + pins = "gpio9"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0>; + }; +}; + +&qup_i2c0_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qupv3_id_0 { + firmware-name = "qcom/qcs8300/qupv3fw.elf"; + status = "okay"; +}; + +&qupv3_id_1 { + firmware-name = "qcom/qcs8300/qupv3fw.elf"; + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/qcs8300/adsp.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/qcs8300/cdsp0.mbn"; + + status = "okay"; +}; + +&remoteproc_gpdsp { + firmware-name = "qcom/qcs8300/gpdsp0.mbn"; + + status = "okay"; +}; + +&sdhc_1 { + vmmc-supply = <&vreg_l8a>; + vqmmc-supply = <&vreg_s2s>; + + no-sd; + no-sdio; + non-removable; + + status = "okay"; +}; + +&serdes0 { + phy-supply = <&vreg_l4a>; + + status = "okay"; +}; + +&spi10 { + status = "okay"; + + tpm@0 { + compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi"; + reg = <0>; + spi-max-frequency = <20000000>; + }; +}; + +&tlmm { + pcie0_default_state: pcie0-default-state { + wake-pins { + pins = "gpio0"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + clkreq-pins { + pins = "gpio1"; + function = "pcie0_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-pins { + pins = "gpio2"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + ethernet0_default: ethernet0-default-state { + ethernet0_mdc: ethernet0-mdc-pins { + pins = "gpio5"; + function = "emac0_mdc"; + drive-strength = <16>; + bias-pull-up; + }; + + ethernet0_mdio: ethernet0-mdio-pins { + pins = "gpio6"; + function = "emac0_mdio"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + expander5_int: expander5-int-state { + pins = "gpio3"; + function = "gpio"; + bias-pull-up; + }; + + expander1_int: expander1-int-state { + pins = "gpio16"; + function = "gpio"; + bias-pull-up; + }; + + qup_i2c1_default: qup-i2c1-state { + pins = "gpio19", "gpio20"; + function = "qup0_se1"; + drive-strength = <2>; + bias-pull-up; + }; + + pcie1_default_state: pcie1-default-state { + wake-pins { + pins = "gpio21"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + clkreq-pins { + pins = "gpio22"; + function = "pcie1_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-pins { + pins = "gpio23"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + expander3_int: expander3-int-state { + pins = "gpio24"; + function = "gpio"; + bias-pull-up; + }; + + expander6_int: expander6-int-state { + pins = "gpio52"; + function = "gpio"; + bias-pull-up; + }; + + expander0_int: expander0-int-state { + pins = "gpio56"; + function = "gpio"; + bias-pull-up; + }; + + cam0_avdd_2v8_en_default: cam0-avdd-2v8-en-state { + pins = "gpio73"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + cam1_avdd_2v8_en_default: cam1-avdd-2v8-en-state { + pins = "gpio74"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + cam2_avdd_2v8_en_default: cam2-avdd-2v8-en-state { + pins = "gpio75"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + qup_i2c15_default: qup-i2c15-state { + pins = "gpio91", "gpio92"; + function = "qup1_se7"; + drive-strength = <2>; + bias-pull-up; + }; + + expander2_int: expander2-int-state { + pins = "gpio95"; + function = "gpio"; + bias-pull-up; + }; + + expander4_int: expander4-int-state { + pins = "gpio96"; + function = "gpio"; + bias-pull-up; + }; +}; + +&uart6 { + status = "okay"; +}; + +&uart7 { + status = "okay"; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>; + vcc-supply = <&vreg_l8a>; + vcc-max-microamp = <1100000>; + vccq-supply = <&vreg_l4c>; + vccq-max-microamp = <1200000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l4a>; + vdda-pll-supply = <&vreg_l5a>; + + status = "okay"; +}; + +&usb_1 { + dr_mode = "peripheral"; + + status = "okay"; +}; + +&usb_1_hsphy { + vdda-pll-supply = <&vreg_l7a>; + vdda18-supply = <&vreg_l7c>; + vdda33-supply = <&vreg_l9a>; + + status = "okay"; +}; + +&usb_qmpphy { + vdda-phy-supply = <&vreg_l7a>; + vdda-pll-supply = <&vreg_l5a>; + + status = "okay"; +}; + +&usb_2 { + status = "okay"; +}; + +&usb_2_dwc3_hs { + remote-endpoint = <&usb2_con_hs_ep>; +}; + +&usb_2_hsphy { + vdda-pll-supply = <&vreg_l7a>; + vdda18-supply = <&vreg_l7c>; + vdda33-supply = <&vreg_l9a>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso b/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso index ca5bf0fe5ec6..4f727ff6ecb6 100644 --- a/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso @@ -117,20 +117,12 @@ ranges; bus-range = <0x5 0xff>; - pcie@0,0 { + dev@0,0 { reg = <0x50000 0x0 0x0 0x0 0x0>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges; }; - pcie@0,1 { + dev@0,1 { reg = <0x50100 0x0 0x0 0x0 0x0>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/monaco-pmics.dtsi b/arch/arm64/boot/dts/qcom/monaco-pmics.dtsi index 6e096b9b7546..361f5163b6d9 100644 --- a/arch/arm64/boot/dts/qcom/monaco-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco-pmics.dtsi @@ -7,6 +7,36 @@ #include <dt-bindings/spmi/spmi.h> #include "qcom-adc5-gen3.h" +/ { + thermal-zones { + pm8775-mbg0-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pmm8620au_0_mbg_temp>; + + trips { + trip0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + pm8775-mbg1-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pmm8620au_1_mbg_temp>; + + trips { + trip0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + }; +}; + &spmi_bus { pmm8620au_0: pmic@0 { compatible = "qcom,pmm8654au", "qcom,spmi-pmic"; @@ -53,6 +83,22 @@ }; }; + pmm8620au_sail_0: pmic@1 { + compatible = "qcom,pmm8654au", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmm8620au_0_mbg_temp: temperature-sensor@d700 { + compatible = "qcom,pm8775-mbg-tm"; + reg = <0xd700>; + io-channels = <&pmm8620au_0_adc ADC5_GEN3_DIE_TEMP(0)>; + io-channel-names = "thermal"; + interrupts-extended = <&spmi_bus 0x1 0xd7 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <0>; + }; + }; + pmm8650au_1: pmic@2 { compatible = "qcom,pmm8654au", "qcom,spmi-pmic"; reg = <0x2 SPMI_USID>; @@ -90,4 +136,20 @@ #interrupt-cells = <2>; }; }; + + pmm8620au_sail_1: pmic@3 { + compatible = "qcom,pmm8654au", "qcom,spmi-pmic"; + reg = <0x3 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmm8620au_1_mbg_temp: temperature-sensor@d700 { + compatible = "qcom,pm8775-mbg-tm"; + reg = <0xd700>; + io-channels = <&pmm8650au_1_adc ADC5_GEN3_DIE_TEMP(2)>; + io-channel-names = "thermal"; + interrupts-extended = <&spmi_bus 0x3 0xd7 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <0>; + }; + }; }; diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index cfe39f923224..395d32d36844 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -18,7 +18,6 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/mailbox/qcom-ipcc.h> #include <dt-bindings/power/qcom,rpmhpd.h> -#include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/soc/qcom,gpr.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> diff --git a/arch/arm64/boot/dts/qcom/msm8917-xiaomi-riva.dts b/arch/arm64/boot/dts/qcom/msm8917-xiaomi-riva.dts index 4ea4fbdb5ce7..7c323214abf1 100644 --- a/arch/arm64/boot/dts/qcom/msm8917-xiaomi-riva.dts +++ b/arch/arm64/boot/dts/qcom/msm8917-xiaomi-riva.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include <dt-bindings/leds/common.h> #include "msm8917-xiaomi-wingtech.dtsi" / { @@ -13,6 +14,10 @@ qcom,board-id = <0x1000b 1>, <0x1000b 2>; + chosen { + stdout-path = &blsp1_uart2; + }; + battery: battery { compatible = "simple-battery"; charge-full-design-microamp-hours = <3000000>; @@ -23,6 +28,36 @@ charge-term-current-microamp = <60000>; voltage-min-design-microvolt = <3400000>; }; + + vibrator { + compatible = "gpio-vibrator"; + enable-gpios = <&tlmm 97 GPIO_ACTIVE_HIGH>; + vcc-supply = <&vph_pwr>; + }; +}; + +&blsp1_i2c2 { + status = "okay"; + + led-controller@45 { + compatible = "awinic,aw2013"; + reg = <0x45>; + vcc-supply = <&pm8937_l10>; + vio-supply = <&pm8937_l5>; + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + led-max-microamp = <5000>; + function = LED_FUNCTION_INDICATOR; + color = <LED_COLOR_ID_WHITE>; + }; + }; +}; + +&blsp1_uart2 { + status = "okay"; }; &blsp2_i2c1 { diff --git a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi new file mode 100644 index 000000000000..568fe68cd185 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi @@ -0,0 +1,1820 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include <dt-bindings/clock/qcom,nord-gcc.h> +#include <dt-bindings/clock/qcom,nord-negcc.h> +#include <dt-bindings/clock/qcom,nord-nwgcc.h> +#include <dt-bindings/clock/qcom,nord-segcc.h> +#include <dt-bindings/clock/qcom,nord-tcsrcc.h> +#include <dt-bindings/clock/qcom,rpmh.h> +#include <dt-bindings/interconnect/qcom,icc.h> +#include <dt-bindings/interconnect/qcom,nord-rpmh.h> +#include <dt-bindings/power/qcom,rpmhpd.h> +#include <dt-bindings/soc/qcom,rpmh-rsc.h> + +#include "nord.dtsi" + +/ { + clk_virt: interconnect-clk-virt { + compatible = "qcom,nord-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mc_virt: interconnect-mc-virt { + compatible = "qcom,nord-mc-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; +}; + +&crypto { + interconnects = <&aggre1_noc_tile MASTER_CRYPTO_CORE0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "memory"; + + status = "okay"; +}; + +&i2c0 { + clocks = <&segcc SE_GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + pinctrl-0 = <&qup_i2c0_default>; + pinctrl-names = "default"; +}; + +&i2c1 { + clocks = <&segcc SE_GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + pinctrl-0 = <&qup_i2c1_default>; + pinctrl-names = "default"; +}; + +&i2c2 { + clocks = <&segcc SE_GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + pinctrl-0 = <&qup_i2c2_default>; + pinctrl-names = "default"; +}; + +&i2c3 { + clocks = <&segcc SE_GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + pinctrl-0 = <&qup_i2c3_default>; + pinctrl-names = "default"; +}; + +&i2c4 { + clocks = <&segcc SE_GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + pinctrl-0 = <&qup_i2c4_default>; + pinctrl-names = "default"; +}; + +&i2c5 { + clocks = <&segcc SE_GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + pinctrl-0 = <&qup_i2c5_default>; + pinctrl-names = "default"; +}; + +&i2c7 { + clocks = <&segcc SE_GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + pinctrl-0 = <&qup_i2c7_default>; + pinctrl-names = "default"; +}; + +&i2c8 { + clocks = <&segcc SE_GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + pinctrl-0 = <&qup_i2c8_default>; + pinctrl-names = "default"; +}; + +&i2c9 { + clocks = <&segcc SE_GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + pinctrl-0 = <&qup_i2c9_default>; + pinctrl-names = "default"; +}; + +&i2c10 { + clocks = <&segcc SE_GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + pinctrl-0 = <&qup_i2c10_default>; + pinctrl-names = "default"; +}; + +&i2c11 { + clocks = <&segcc SE_GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + pinctrl-0 = <&qup_i2c11_default>; + pinctrl-names = "default"; +}; + +&i2c12 { + clocks = <&segcc SE_GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + pinctrl-0 = <&qup_i2c12_default>; + pinctrl-names = "default"; +}; + +&i2c13 { + clocks = <&segcc SE_GCC_QUPV3_WRAP1_S6_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + pinctrl-0 = <&qup_i2c13_default>; + pinctrl-names = "default"; +}; + +&i2c14 { + clocks = <&negcc NE_GCC_QUPV3_WRAP2_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc_tile MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + pinctrl-0 = <&qup_i2c14_default>; + pinctrl-names = "default"; +}; + +&i2c16 { + clocks = <&negcc NE_GCC_QUPV3_WRAP2_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc_tile MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + pinctrl-0 = <&qup_i2c16_default>; + pinctrl-names = "default"; +}; + +&i2c17 { + clocks = <&negcc NE_GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc_tile MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + pinctrl-0 = <&qup_i2c17_default>; + pinctrl-names = "default"; +}; + +&i2c18 { + clocks = <&negcc NE_GCC_QUPV3_WRAP2_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc_tile MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + pinctrl-0 = <&qup_i2c18_default>; + pinctrl-names = "default"; +}; + +&i2c19 { + clocks = <&negcc NE_GCC_QUPV3_WRAP2_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc_tile MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + pinctrl-0 = <&qup_i2c19_default>; + pinctrl-names = "default"; +}; + +&i2c20 { + clocks = <&negcc NE_GCC_QUPV3_WRAP2_S6_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc_tile MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + pinctrl-0 = <&qup_i2c20_default>; + pinctrl-names = "default"; +}; + +&qupv3_0 { + clocks = <&segcc SE_GCC_QUPV3_WRAP0_M_AHB_CLK>, + <&segcc SE_GCC_QUPV3_WRAP0_S_AHB_CLK>; + clock-names = "m-ahb", + "s-ahb"; +}; + +&qupv3_1 { + clocks = <&segcc SE_GCC_QUPV3_WRAP1_M_AHB_CLK>, + <&segcc SE_GCC_QUPV3_WRAP1_S_AHB_CLK>; + clock-names = "m-ahb", + "s-ahb"; +}; + +&qupv3_2 { + clocks = <&negcc NE_GCC_QUPV3_WRAP2_M_AHB_CLK>, + <&negcc NE_GCC_QUPV3_WRAP2_S_AHB_CLK>; + clock-names = "m-ahb", + "s-ahb"; +}; + +&spi0 { + clocks = <&segcc SE_GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + pinctrl-0 = <&qup_spi0_default>; + pinctrl-names = "default"; +}; + +&spi1 { + clocks = <&segcc SE_GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + pinctrl-0 = <&qup_spi1_default>; + pinctrl-names = "default"; +}; + +&spi2 { + clocks = <&segcc SE_GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + pinctrl-0 = <&qup_spi2_default>; + pinctrl-names = "default"; +}; + +&spi3 { + clocks = <&segcc SE_GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + pinctrl-0 = <&qup_spi3_default>; + pinctrl-names = "default"; +}; + +&spi4 { + clocks = <&segcc SE_GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + pinctrl-0 = <&qup_spi4_default>; + pinctrl-names = "default"; +}; + +&spi5 { + clocks = <&segcc SE_GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + pinctrl-0 = <&qup_spi5_default>; + pinctrl-names = "default"; +}; + +&spi7 { + clocks = <&segcc SE_GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + pinctrl-0 = <&qup_spi7_default>; + pinctrl-names = "default"; +}; + +&spi8 { + clocks = <&segcc SE_GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + pinctrl-0 = <&qup_spi8_default>; + pinctrl-names = "default"; +}; + +&spi11 { + clocks = <&segcc SE_GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + pinctrl-0 = <&qup_spi11_default>; + pinctrl-names = "default"; +}; + +&spi12 { + clocks = <&segcc SE_GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + pinctrl-0 = <&qup_spi12_default>; + pinctrl-names = "default"; +}; + +&spi13 { + clocks = <&segcc SE_GCC_QUPV3_WRAP1_S6_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + pinctrl-0 = <&qup_spi13_default>; + pinctrl-names = "default"; +}; + +&spi14 { + clocks = <&negcc NE_GCC_QUPV3_WRAP2_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc_tile MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + pinctrl-0 = <&qup_spi14_default>; + pinctrl-names = "default"; +}; + +&spi16 { + clocks = <&negcc NE_GCC_QUPV3_WRAP2_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc_tile MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + pinctrl-0 = <&qup_spi16_default>; + pinctrl-names = "default"; +}; + +&spi17 { + clocks = <&negcc NE_GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc_tile MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + pinctrl-0 = <&qup_spi17_default>; + pinctrl-names = "default"; +}; + +&spi18 { + clocks = <&negcc NE_GCC_QUPV3_WRAP2_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc_tile MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + pinctrl-0 = <&qup_spi18_default>; + pinctrl-names = "default"; +}; + +&spi19 { + clocks = <&negcc NE_GCC_QUPV3_WRAP2_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc_tile MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + pinctrl-0 = <&qup_spi19_default>; + pinctrl-names = "default"; +}; + +&spi20 { + clocks = <&negcc NE_GCC_QUPV3_WRAP2_S6_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc_tile MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + pinctrl-0 = <&qup_spi20_default>; + pinctrl-names = "default"; +}; + +&soc { + gcc: clock-controller@100000 { + compatible = "qcom,nord-gcc"; + reg = <0x0 0x00100000 0x0 0x1f4200>; + clocks = <&bi_tcxo_div2>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + cnoc_main: interconnect@1500000 { + compatible = "qcom,nord-cnoc-main"; + reg = <0x0 0x01500000 0x0 0x1d200>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + config_noc: interconnect@1600000 { + compatible = "qcom,nord-cnoc-cfg"; + reg = <0x0 0x01600000 0x0 0xd200>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect@1680000 { + compatible = "qcom,nord-system-noc"; + reg = <0x0 0x01680000 0x0 0x1c080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre2_noc_tile: interconnect@16c0000 { + compatible = "qcom,nord-aggre2-noc-tile"; + reg = <0x0 0x016c0000 0x0 0x1b400>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@16e0000 { + compatible = "qcom,nord-aggre1-noc"; + reg = <0x0 0x016e0000 0x0 0x1c400>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre2_noc: interconnect@1700000 { + compatible = "qcom,nord-aggre2-noc"; + reg = <0x0 0x01700000 0x0 0x1b400>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&rpmhcc RPMH_IPA_CLK>; + }; + + aggre1_noc_tile: interconnect@1720000 { + compatible = "qcom,nord-aggre1-noc-tile"; + reg = <0x0 0x01720000 0x0 0x23400>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&negcc NE_GCC_AGGRE_NOC_USB2_AXI_CLK>, + <&negcc NE_GCC_AGGRE_NOC_USB3_PRIM_AXI_CLK>, + <&negcc NE_GCC_AGGRE_NOC_USB3_SEC_AXI_CLK>, + <&negcc NE_GCC_AGGRE_NOC_UFS_PHY_AXI_CLK>; + }; + + mmss_noc: interconnect@1780000 { + compatible = "qcom,nord-mmss-noc"; + reg = <0x0 0x01780000 0x0 0x72800>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + pcie_cfg: interconnect@1ba0000 { + compatible = "qcom,nord-pcie-cfg"; + reg = <0x0 0x01ba0000 0x0 0x7200>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + pcie_data_outbound: interconnect@1bc0000 { + compatible = "qcom,nord-pcie-data-outbound"; + reg = <0x0 0x01bc0000 0x0 0x17000>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + pcie_data_inbound: interconnect@1c00000 { + compatible = "qcom,nord-pcie-data-inbound"; + reg = <0x0 0x01c00000 0x0 0x4b080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + ufs_mem_phy: phy@1d40000 { + compatible = "qcom,nord-qmp-ufs-phy", + "qcom,sm8650-qmp-ufs-phy"; + reg = <0x0 0x01d40000 0x0 0x2000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&negcc NE_GCC_UFS_PHY_PHY_AUX_CLK>, + <&tcsrcc TCSR_UFS_CLKREF_EN>; + clock-names = "ref", + "ref_aux", + "qref"; + + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + + power-domains = <&negcc NE_GCC_UFS_MEM_PHY_GDSC>; + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + ice: crypto@1d48000 { + compatible = "qcom,nord-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg = <0x0 0x01d48000 0x0 0x18000>; + clocks = <&negcc NE_GCC_UFS_PHY_ICE_CORE_CLK>, + <&negcc NE_GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&negcc NE_GCC_UFS_PHY_GDSC>; + }; + + hscnoc: interconnect@2000000 { + compatible = "qcom,nord-hscnoc"; + reg = <0x0 0x02000000 0x0 0xb22000>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + hpass_ag_noc: interconnect@5fc0000 { + compatible = "qcom,nord-hpass-ag-noc"; + reg = <0x0 0x05fc0000 0x0 0x37080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + negcc: clock-controller@8900000 { + compatible = "qcom,nord-negcc"; + reg = <0x0 0x08900000 0x0 0xf4200>; + clocks = <&bi_tcxo_div2>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>, + <0>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + segcc: clock-controller@8a00000 { + compatible = "qcom,nord-segcc"; + reg = <0x0 0x08a00000 0x0 0xf4200>; + clocks = <&bi_tcxo_div2>, + <&sleep_clk>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + nwgcc: clock-controller@8b00000 { + compatible = "qcom,nord-nwgcc"; + reg = <0x0 0x08b00000 0x0 0xf4200>; + clocks = <&bi_tcxo_div2>, + <&sleep_clk>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + tcsrcc: clock-controller@f1d9000 { + compatible = "qcom,nord-tcsrcc", + "syscon"; + reg = <0x0 0x0f1d9000 0x0 0xf00c>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + apps_rsc: rsc@18900000 { + compatible = "qcom,rpmh-rsc"; + reg = <0x0 0x18900000 0x0 0x10000>, + <0x0 0x18910000 0x0 0x10000>, + <0x0 0x18920000 0x0 0x10000>; + reg-names = "drv-0", + "drv-1", + "drv-2"; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = <ACTIVE_TCS 3>, + <SLEEP_TCS 2>, + <WAKE_TCS 2>, + <CONTROL_TCS 0>; + label = "apps_rsc"; + power-domains = <&system_pd>; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible = "qcom,nord-rpmh-clk"; + clocks = <&xo_board>; + clock-names = "xo"; + #clock-cells = <1>; + }; + + rpmhpd: power-controller { + compatible = "qcom,nord-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp-0 { + opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; + }; + + rpmhpd_opp_min_svs: opp-1 { + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; + }; + + rpmhpd_opp_low_svs: opp-2 { + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + }; + + rpmhpd_opp_svs: opp-3 { + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + }; + + rpmhpd_opp_svs_l1: opp-4 { + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + }; + + rpmhpd_opp_nom: opp-5 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; + }; + + rpmhpd_opp_nom_l1: opp-6 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; + }; + + rpmhpd_opp_nom_l2: opp-7 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; + }; + + rpmhpd_opp_turbo: opp-8 { + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; + }; + + rpmhpd_opp_turbo_l1: opp-9 { + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; + }; + }; + }; + }; + + nsp_data_noc_0: interconnect@1f200000 { + compatible = "qcom,nord-nsp-data-noc-0"; + reg = <0x0 0x1f200000 0x0 0x2a200>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + nsp_data_noc_1: interconnect@1f600000 { + compatible = "qcom,nord-nsp-data-noc-1"; + reg = <0x0 0x1f600000 0x0 0x2a200>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + nsp_data_noc_2: interconnect@1fa00000 { + compatible = "qcom,nord-nsp-data-noc-2"; + reg = <0x0 0x1fa00000 0x0 0x2a200>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + nsp_data_noc_3: interconnect@1fe00000 { + compatible = "qcom,nord-nsp-data-noc-3"; + reg = <0x0 0x1fe00000 0x0 0x2a200>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; +}; + +&tlmm { + qup_i2c0_default: qup-i2c0-default-state { + pins = "gpio111", "gpio112"; + function = "qup0_se0"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c1_default: qup-i2c1-default-state { + pins = "gpio111", "gpio112"; + function = "qup0_se1"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c2_default: qup-i2c2-default-state { + pins = "gpio113", "gpio114"; + function = "qup0_se2"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c3_default: qup-i2c3-default-state { + pins = "gpio115", "gpio116"; + function = "qup0_se3"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c4_default: qup-i2c4-default-state { + pins = "gpio117", "gpio118"; + function = "qup0_se4"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c5_default: qup-i2c5-default-state { + pins = "gpio121", "gpio122"; + function = "qup0_se5"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c7_default: qup-i2c7-default-state { + pins = "gpio123", "gpio124"; + function = "qup1_se0"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c8_default: qup-i2c8-default-state { + pins = "gpio125", "gpio126"; + function = "qup1_se1"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c9_default: qup-i2c9-default-state { + pins = "gpio127", "gpio128"; + function = "qup1_se2_01"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c10_default: qup-i2c10-default-state { + pins = "gpio129", "gpio130"; + function = "qup1_se3_01"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c11_default: qup-i2c11-default-state { + pins = "gpio131", "gpio132"; + function = "qup1_se4"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c12_default: qup-i2c12-default-state { + pins = "gpio133", "gpio134"; + function = "qup1_se5"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c13_default: qup-i2c13-default-state { + pins = "gpio137", "gpio138"; + function = "qup1_se6"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c14_default: qup-i2c14-default-state { + pins = "gpio139", "gpio140"; + function = "qup2_se0"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c16_default: qup-i2c16-default-state { + pins = "gpio145", "gpio146"; + function = "qup2_se2"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c17_default: qup-i2c17-default-state { + pins = "gpio150", "gpio151"; + function = "qup2_se3"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c18_default: qup-i2c18-default-state { + pins = "gpio154", "gpio155"; + function = "qup2_se4"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c19_default: qup-i2c19-default-state { + pins = "gpio156", "gpio157"; + function = "qup2_se5"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c20_default: qup-i2c20-default-state { + pins = "gpio158", "gpio159"; + function = "qup2_se6"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi0_default: qup-spi0-default-state { + data-pins { + pins = "gpio109", "gpio111", "gpio112"; + function = "qup0_se0"; + drive-strength = <6>; + bias-disable; + }; + + cs-pins { + pins = "gpio110"; + function = "qup0_se0"; + drive-strength = <2>; + bias-disable; + }; + }; + + qup_spi1_default: qup-spi1-default-state { + data-pins { + pins = "gpio109", "gpio111", "gpio112"; + function = "qup0_se1"; + drive-strength = <6>; + bias-disable; + }; + + cs-pins { + pins = "gpio110"; + function = "qup0_se1"; + drive-strength = <2>; + bias-disable; + }; + }; + + qup_spi2_default: qup-spi2-default-state { + data-pins { + pins = "gpio113", "gpio114", "gpio115"; + function = "qup0_se2"; + drive-strength = <6>; + bias-disable; + }; + + cs-pins { + pins = "gpio116"; + function = "qup0_se2"; + drive-strength = <2>; + bias-disable; + }; + }; + + qup_spi3_default: qup-spi3-default-state { + data-pins { + pins = "gpio113", "gpio115", "gpio116"; + function = "qup0_se3"; + drive-strength = <6>; + bias-disable; + }; + + cs-pins { + pins = "gpio114"; + function = "qup0_se3"; + drive-strength = <2>; + bias-disable; + }; + }; + + qup_spi4_default: qup-spi4-default-state { + data-pins { + pins = "gpio117", "gpio118", "gpio119"; + function = "qup0_se4"; + drive-strength = <6>; + bias-disable; + }; + + cs-pins { + pins = "gpio120"; + function = "qup0_se4"; + drive-strength = <2>; + bias-disable; + }; + }; + + qup_spi5_default: qup-spi5-default-state { + data-pins { + pins = "gpio109", "gpio121", "gpio122"; + function = "qup0_se5"; + drive-strength = <6>; + bias-disable; + }; + + cs-pins { + pins = "gpio110"; + function = "qup0_se5"; + drive-strength = <2>; + bias-disable; + }; + }; + + qup_spi7_default: qup-spi7-default-state { + data-pins { + pins = "gpio123", "gpio124", "gpio125"; + function = "qup1_se0"; + drive-strength = <6>; + bias-disable; + }; + + cs-pins { + pins = "gpio126"; + function = "qup1_se0"; + drive-strength = <2>; + bias-disable; + }; + }; + + qup_spi8_default: qup-spi8-default-state { + data-pins { + pins = "gpio123", "gpio125", "gpio126"; + function = "qup1_se1"; + drive-strength = <6>; + bias-disable; + }; + + cs-pins { + pins = "gpio124"; + function = "qup1_se1"; + drive-strength = <2>; + bias-disable; + }; + }; + + qup_spi11_default: qup-spi11-default-state { + data-pins { + pins = "gpio131", "gpio132", "gpio137"; + function = "qup1_se4"; + drive-strength = <6>; + bias-disable; + }; + + cs-pins { + pins = "gpio138"; + function = "qup1_se4"; + drive-strength = <2>; + bias-disable; + }; + }; + + qup_spi12_default: qup-spi12-default-state { + data-pins { + pins = "gpio133", "gpio134", "gpio135"; + function = "qup1_se5"; + drive-strength = <6>; + bias-disable; + }; + + cs-pins { + pins = "gpio136"; + function = "qup1_se5"; + drive-strength = <2>; + bias-disable; + }; + }; + + qup_spi13_default: qup-spi13-default-state { + data-pins { + pins = "gpio131", "gpio137", "gpio138"; + function = "qup1_se6"; + drive-strength = <6>; + bias-disable; + }; + + cs-pins { + pins = "gpio132"; + function = "qup1_se6"; + drive-strength = <2>; + bias-disable; + }; + }; + + qup_spi14_default: qup-spi14-default-state { + data-pins { + pins = "gpio139", "gpio140", "gpio141"; + function = "qup2_se0"; + drive-strength = <6>; + bias-disable; + }; + + cs-pins { + pins = "gpio142"; + function = "qup2_se0"; + drive-strength = <2>; + bias-disable; + }; + }; + + qup_spi16_default: qup-spi16-default-state { + data-pins { + pins = "gpio145", "gpio146", "gpio147"; + function = "qup2_se2"; + drive-strength = <6>; + bias-disable; + }; + + cs-pins { + pins = "gpio148"; + function = "qup2_se2"; + drive-strength = <2>; + bias-disable; + }; + }; + + qup_spi17_default: qup-spi17-default-state { + data-pins { + pins = "gpio150", "gpio151", "gpio152"; + function = "qup2_se3"; + drive-strength = <6>; + bias-disable; + }; + + cs-pins { + pins = "gpio153"; + function = "qup2_se3"; + drive-strength = <2>; + bias-disable; + }; + }; + + qup_spi18_default: qup-spi18-default-state { + data-pins { + pins = "gpio143", "gpio154", "gpio155"; + function = "qup2_se4"; + drive-strength = <6>; + bias-disable; + }; + + cs-pins { + pins = "gpio144"; + function = "qup2_se4"; + drive-strength = <2>; + bias-disable; + }; + }; + + qup_spi19_default: qup-spi19-default-state { + data-pins { + pins = "gpio156", "gpio157", "gpio158"; + function = "qup2_se5"; + drive-strength = <6>; + bias-disable; + }; + + cs-pins { + pins = "gpio159"; + function = "qup2_se5"; + drive-strength = <2>; + bias-disable; + }; + }; + + qup_spi20_default: qup-spi20-default-state { + data-pins { + pins = "gpio156", "gpio158", "gpio159"; + function = "qup2_se6"; + drive-strength = <6>; + bias-disable; + }; + + cs-pins { + pins = "gpio157"; + function = "qup2_se6"; + drive-strength = <2>; + bias-disable; + }; + }; + + qup_uart0_default: qup-uart0-default-state { + pins = "gpio109", "gpio110"; + function = "qup0_se0"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart1_default: qup-uart1-default-state { + pins = "gpio109", "gpio110"; + function = "qup0_se1"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart2_default: qup-uart2-default-state { + pins = "gpio115", "gpio116"; + function = "qup0_se2"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart3_default: qup-uart3-default-state { + pins = "gpio113", "gpio114"; + function = "qup0_se3"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart4_default: qup-uart4-default-state { + pins = "gpio119", "gpio120"; + function = "qup0_se4"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart5_default: qup-uart5-default-state { + pins = "gpio109", "gpio110"; + function = "qup0_se5"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart7_default: qup-uart7-default-state { + pins = "gpio125", "gpio126"; + function = "qup1_se0"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart8_default: qup-uart8-default-state { + pins = "gpio123", "gpio124"; + function = "qup1_se1"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart9_default: qup-uart9-default-state { + pins = "gpio127", "gpio128"; + function = "qup1_se2_23"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart10_default: qup-uart10-default-state { + pins = "gpio129", "gpio130"; + function = "qup1_se3_23"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart11_default: qup-uart11-default-state { + pins = "gpio137", "gpio138"; + function = "qup1_se4"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart12_default: qup-uart12-default-state { + pins = "gpio135", "gpio136"; + function = "qup1_se5"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart13_default: qup-uart13-default-state { + pins = "gpio131", "gpio132"; + function = "qup1_se6"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart14_default: qup-uart14-default-state { + pins = "gpio141", "gpio142"; + function = "qup2_se0"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart15_default: qup-uart15-default-state { + pins = "gpio143", "gpio144"; + function = "qup2_se1"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart16_default: qup-uart16-default-state { + pins = "gpio147", "gpio148"; + function = "qup2_se2"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart17_default: qup-uart17-default-state { + pins = "gpio150", "gpio151", "gpio152", "gpio153"; + function = "qup2_se3"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart18_default: qup-uart18-default-state { + pins = "gpio143", "gpio144"; + function = "qup2_se4"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart19_default: qup-uart19-default-state { + pins = "gpio158", "gpio159"; + function = "qup2_se5"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart20_default: qup-uart20-default-state { + pins = "gpio156", "gpio157"; + function = "qup2_se6"; + drive-strength = <2>; + bias-disable; + }; +}; + +&uart0 { + clocks = <&segcc SE_GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + pinctrl-0 = <&qup_uart0_default>; + pinctrl-names = "default"; +}; + +&uart1 { + clocks = <&segcc SE_GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + pinctrl-0 = <&qup_uart1_default>; + pinctrl-names = "default"; +}; + +&uart2 { + clocks = <&segcc SE_GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + pinctrl-0 = <&qup_uart2_default>; + pinctrl-names = "default"; +}; + +&uart3 { + clocks = <&segcc SE_GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + pinctrl-0 = <&qup_uart3_default>; + pinctrl-names = "default"; +}; + +&uart4 { + clocks = <&segcc SE_GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + pinctrl-0 = <&qup_uart4_default>; + pinctrl-names = "default"; +}; + +&uart5 { + clocks = <&segcc SE_GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + pinctrl-0 = <&qup_uart5_default>; + pinctrl-names = "default"; +}; + +&uart7 { + clocks = <&segcc SE_GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + pinctrl-0 = <&qup_uart7_default>; + pinctrl-names = "default"; +}; + +&uart8 { + clocks = <&segcc SE_GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + pinctrl-0 = <&qup_uart8_default>; + pinctrl-names = "default"; +}; + +&uart9 { + clocks = <&segcc SE_GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + pinctrl-0 = <&qup_uart9_default>; + pinctrl-names = "default"; +}; + +&uart10 { + clocks = <&segcc SE_GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + pinctrl-0 = <&qup_uart10_default>; + pinctrl-names = "default"; +}; + +&uart11 { + clocks = <&segcc SE_GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + pinctrl-0 = <&qup_uart11_default>; + pinctrl-names = "default"; +}; + +&uart12 { + clocks = <&segcc SE_GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + pinctrl-0 = <&qup_uart12_default>; + pinctrl-names = "default"; +}; + +&uart13 { + clocks = <&segcc SE_GCC_QUPV3_WRAP1_S6_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + pinctrl-0 = <&qup_uart13_default>; + pinctrl-names = "default"; +}; + +&uart14 { + clocks = <&negcc NE_GCC_QUPV3_WRAP2_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + pinctrl-0 = <&qup_uart14_default>; + pinctrl-names = "default"; +}; + +&uart15 { + clocks = <&negcc NE_GCC_QUPV3_WRAP2_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + pinctrl-0 = <&qup_uart15_default>; + pinctrl-names = "default"; +}; + +&uart16 { + clocks = <&negcc NE_GCC_QUPV3_WRAP2_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + pinctrl-0 = <&qup_uart16_default>; + pinctrl-names = "default"; +}; + +&uart17 { + clocks = <&negcc NE_GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + pinctrl-0 = <&qup_uart17_default>; + pinctrl-names = "default"; +}; + +&uart18 { + clocks = <&negcc NE_GCC_QUPV3_WRAP2_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + pinctrl-0 = <&qup_uart18_default>; + pinctrl-names = "default"; +}; + +&uart19 { + clocks = <&negcc NE_GCC_QUPV3_WRAP2_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + pinctrl-0 = <&qup_uart19_default>; + pinctrl-names = "default"; +}; + +&uart20 { + clocks = <&negcc NE_GCC_QUPV3_WRAP2_S6_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + pinctrl-0 = <&qup_uart20_default>; + pinctrl-names = "default"; +}; + +&ufs_mem_hc { + clocks = <&negcc NE_GCC_UFS_PHY_AXI_CLK>, + <&negcc NE_GCC_AGGRE_NOC_UFS_PHY_AXI_CLK>, + <&negcc NE_GCC_UFS_PHY_AHB_CLK>, + <&negcc NE_GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&tcsrcc TCSR_UFS_CLKREF_EN>, + <&negcc NE_GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&negcc NE_GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&negcc NE_GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + + resets = <&negcc NE_GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + interconnects = <&aggre1_noc_tile MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "ufs-ddr", + "cpu-ufs"; + + phys = <&ufs_mem_phy>; + phy-names = "ufsphy"; + + power-domains = <&negcc NE_GCC_UFS_PHY_GDSC>; + operating-points-v2 = <&ufs_opp_table>; + required-opps = <&rpmhpd_opp_nom>; + qcom,ice = <&ice>; + #reset-cells = <1>; + + ufs_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <100000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-201500000 { + opp-hz = /bits/ 64 <201500000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <201500000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-403000000 { + opp-hz = /bits/ 64 <403000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <403000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/nord-gearvm.dtsi b/arch/arm64/boot/dts/qcom/nord-gearvm.dtsi new file mode 100644 index 000000000000..5514f9a6f49f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/nord-gearvm.dtsi @@ -0,0 +1,2848 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include "nord.dtsi" + +&firmware { + scmi0: scmi-0 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem0>; + /* We expect the bootloader to update the IRQ number */ + interrupts = <GIC_SPI 963 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi0_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi0_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi0_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi1: scmi-1 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem1>; + interrupts = <GIC_SPI 964 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi1_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi1_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi1_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi2: scmi-2 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem2>; + interrupts = <GIC_SPI 965 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi2_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi2_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi2_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi3: scmi-3 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem3>; + interrupts = <GIC_SPI 966 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi3_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi3_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi3_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi4: scmi-4 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem4>; + interrupts = <GIC_SPI 967 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi4_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi4_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi4_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi5: scmi-5 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem5>; + interrupts = <GIC_SPI 968 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi5_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi5_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi5_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi6: scmi-6 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem6>; + interrupts = <GIC_SPI 969 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi6_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi6_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi6_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi7: scmi-7 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem7>; + interrupts = <GIC_SPI 970 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi7_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi7_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi7_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi8: scmi-8 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem8>; + interrupts = <GIC_SPI 971 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi8_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi8_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi8_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi9: scmi-9 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem9>; + interrupts = <GIC_SPI 972 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi9_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi9_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi9_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi10: scmi-10 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem10>; + interrupts = <GIC_SPI 973 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi10_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi10_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi10_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi11: scmi-11 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem11>; + interrupts = <GIC_SPI 974 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi11_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi11_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi11_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi12: scmi-12 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem12>; + interrupts = <GIC_SPI 975 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi12_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi12_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi12_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi13: scmi-13 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem13>; + interrupts = <GIC_SPI 976 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi13_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi13_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi13_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi14: scmi-14 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem14>; + interrupts = <GIC_SPI 977 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi14_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi14_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi14_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi15: scmi-15 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem15>; + interrupts = <GIC_SPI 978 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi15_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi15_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi15_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi16: scmi-16 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem16>; + interrupts = <GIC_SPI 979 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi16_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi16_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi16_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi17: scmi-17 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem17>; + interrupts = <GIC_SPI 980 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi17_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi17_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi17_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi18: scmi-18 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem18>; + interrupts = <GIC_SPI 981 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi18_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi18_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi18_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi19: scmi-19 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem19>; + interrupts = <GIC_SPI 982 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi19_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi19_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi19_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi20: scmi-20 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem20>; + interrupts = <GIC_SPI 983 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi20_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi20_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi20_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi21: scmi-21 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem21>; + interrupts = <GIC_SPI 984 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi21_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi21_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi21_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi22: scmi-22 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem22>; + interrupts = <GIC_SPI 985 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi22_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi22_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi22_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi23: scmi-23 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem23>; + interrupts = <GIC_SPI 986 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi23_sensor: protocol@15 { + reg = <0x15>; + #thermal-sensor-cells = <1>; + }; + }; + + scmi24: scmi-24 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem24>; + interrupts = <GIC_SPI 987 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi24_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi24_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi24_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi25: scmi-25 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem25>; + interrupts = <GIC_ESPI 0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi25_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi25_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi25_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi26: scmi-26 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem26>; + interrupts = <GIC_ESPI 1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi26_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi26_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi26_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi27: scmi-27 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem27>; + interrupts = <GIC_ESPI 2 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi27_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi27_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi27_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi28: scmi-28 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem28>; + interrupts = <GIC_ESPI 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi28_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi28_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi28_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi29: scmi-29 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem29>; + interrupts = <GIC_ESPI 4 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi29_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi29_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi29_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi30: scmi-30 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem30>; + interrupts = <GIC_ESPI 5 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi30_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi30_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi30_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi31: scmi-31 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem31>; + interrupts = <GIC_ESPI 6 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi31_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi31_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi31_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi32: scmi-32 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem32>; + interrupts = <GIC_ESPI 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi32_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi32_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi32_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi33: scmi-33 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem33>; + interrupts = <GIC_ESPI 8 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi33_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi33_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi33_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi34: scmi-34 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem34>; + interrupts = <GIC_ESPI 9 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi34_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi34_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi34_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi35: scmi-35 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem35>; + interrupts = <GIC_ESPI 10 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi35_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi35_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi35_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi36: scmi-36 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem36>; + interrupts = <GIC_ESPI 11 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi36_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi36_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi36_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi37: scmi-37 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem37>; + interrupts = <GIC_ESPI 12 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi37_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi37_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi37_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi38: scmi-38 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem38>; + interrupts = <GIC_ESPI 13 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi38_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi38_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi38_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi39: scmi-39 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem39>; + interrupts = <GIC_ESPI 14 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi39_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi39_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi39_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi40: scmi-40 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem40>; + interrupts = <GIC_ESPI 15 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi40_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi40_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi40_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi41: scmi-41 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem41>; + interrupts = <GIC_ESPI 16 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi41_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi41_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi41_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi42: scmi-42 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem42>; + interrupts = <GIC_ESPI 17 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi42_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi42_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi42_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi43: scmi-43 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem43>; + interrupts = <GIC_ESPI 18 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi43_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi43_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi43_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi44: scmi-44 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem44>; + interrupts = <GIC_ESPI 19 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi44_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi44_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi44_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi45: scmi-45 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem45>; + interrupts = <GIC_ESPI 20 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi45_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi45_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi45_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi46: scmi-46 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem46>; + interrupts = <GIC_ESPI 21 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi46_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi46_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi46_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi47: scmi-47 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem47>; + interrupts = <GIC_ESPI 22 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi47_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi47_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi47_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi48: scmi-48 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem48>; + interrupts = <GIC_ESPI 23 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi48_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi48_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi48_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi49: scmi-49 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem49>; + interrupts = <GIC_ESPI 24 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi49_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi49_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi49_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi50: scmi-50 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem50>; + interrupts = <GIC_ESPI 25 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi50_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi50_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi50_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi51: scmi-51 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem51>; + interrupts = <GIC_ESPI 26 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi51_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi51_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi51_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi52: scmi-52 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem52>; + interrupts = <GIC_ESPI 27 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi52_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi52_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi52_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi53: scmi-53 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem53>; + interrupts = <GIC_ESPI 28 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi53_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi53_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi53_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi54: scmi-54 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem54>; + interrupts = <GIC_ESPI 29 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi54_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi54_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi54_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi55: scmi-55 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem55>; + interrupts = <GIC_ESPI 30 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi55_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi55_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi55_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi56: scmi-56 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem56>; + interrupts = <GIC_ESPI 31 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi56_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi56_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi56_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi57: scmi-57 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem57>; + interrupts = <GIC_ESPI 32 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi57_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi57_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi57_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi58: scmi-58 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem58>; + interrupts = <GIC_ESPI 33 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi58_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi58_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi58_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi59: scmi-59 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem59>; + interrupts = <GIC_ESPI 34 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi59_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi59_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi59_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi60: scmi-60 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem60>; + interrupts = <GIC_ESPI 35 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi60_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi60_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi60_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi61: scmi-61 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem61>; + interrupts = <GIC_ESPI 36 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi61_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi61_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi61_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi62: scmi-62 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem62>; + interrupts = <GIC_ESPI 37 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi62_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi62_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi62_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi63: scmi-63 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem63>; + interrupts = <GIC_ESPI 38 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi63_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi63_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi63_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; +}; + +&i2c0 { + compatible = "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains = <&scmi9_pd 0>, + <&scmi9_dvfs 0>; + power-domain-names = "power", + "perf"; +}; + +&i2c1 { + compatible = "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains = <&scmi9_pd 1>, + <&scmi9_dvfs 1>; + power-domain-names = "power", + "perf"; +}; + +&i2c2 { + compatible = "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains = <&scmi9_pd 2>, + <&scmi9_dvfs 2>; + power-domain-names = "power", + "perf"; +}; + +&i2c3 { + compatible = "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains = <&scmi9_pd 3>, + <&scmi9_dvfs 3>; + power-domain-names = "power", + "perf"; +}; + +&i2c4 { + compatible = "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains = <&scmi9_pd 4>, + <&scmi9_dvfs 4>; + power-domain-names = "power", + "perf"; +}; + +&i2c5 { + compatible = "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains = <&scmi9_pd 5>, + <&scmi9_dvfs 5>; + power-domain-names = "power", + "perf"; +}; + +&i2c7 { + compatible = "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains = <&scmi9_pd 7>, + <&scmi9_dvfs 7>; + power-domain-names = "power", + "perf"; +}; + +&i2c8 { + compatible = "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains = <&scmi9_pd 8>, + <&scmi9_dvfs 8>; + power-domain-names = "power", + "perf"; +}; + +&i2c9 { + compatible = "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains = <&scmi9_pd 9>, + <&scmi9_dvfs 9>; + power-domain-names = "power", + "perf"; +}; + +&i2c10 { + compatible = "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains = <&scmi9_pd 10>, + <&scmi9_dvfs 10>; + power-domain-names = "power", + "perf"; +}; + +&i2c11 { + compatible = "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains = <&scmi9_pd 11>, + <&scmi9_dvfs 11>; + power-domain-names = "power", + "perf"; +}; + +&i2c12 { + compatible = "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains = <&scmi9_pd 12>, + <&scmi9_dvfs 12>; + power-domain-names = "power", + "perf"; +}; + +&i2c13 { + compatible = "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains = <&scmi9_pd 13>, + <&scmi9_dvfs 13>; + power-domain-names = "power", + "perf"; +}; + +&i2c14 { + compatible = "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains = <&scmi9_pd 14>, + <&scmi9_dvfs 14>; + power-domain-names = "power", + "perf"; +}; + +&i2c15 { + compatible = "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains = <&scmi9_pd 15>, + <&scmi9_dvfs 15>; + power-domain-names = "power", + "perf"; +}; + +&i2c16 { + compatible = "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains = <&scmi9_pd 16>, + <&scmi9_dvfs 16>; + power-domain-names = "power", + "perf"; +}; + +&i2c17 { + compatible = "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains = <&scmi9_pd 17>, + <&scmi9_dvfs 17>; + power-domain-names = "power", + "perf"; +}; + +&i2c18 { + compatible = "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains = <&scmi9_pd 18>, + <&scmi9_dvfs 18>; + power-domain-names = "power", + "perf"; +}; + +&i2c19 { + compatible = "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains = <&scmi9_pd 19>, + <&scmi9_dvfs 19>; + power-domain-names = "power", + "perf"; +}; + +&i2c20 { + compatible = "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains = <&scmi9_pd 20>, + <&scmi9_dvfs 20>; + power-domain-names = "power", + "perf"; +}; + +&qupv3_0 { + compatible = "qcom,sa8797p-geni-se-qup", + "qcom,sa8255p-geni-se-qup"; +}; + +&qupv3_1 { + compatible = "qcom,sa8797p-geni-se-qup", + "qcom,sa8255p-geni-se-qup"; +}; + +&qupv3_2 { + compatible = "qcom,sa8797p-geni-se-qup", + "qcom,sa8255p-geni-se-qup"; +}; + +&reserved_memory { + shmem0: scmi-shmem@d7600000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7600000 0x0 0x1000>; + no-map; + }; + + shmem1: scmi-shmem@d7601000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7601000 0x0 0x1000>; + no-map; + }; + + shmem2: scmi-shmem@d7602000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7602000 0x0 0x1000>; + no-map; + }; + + shmem3: scmi-shmem@d7603000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7603000 0x0 0x1000>; + no-map; + }; + + shmem4: scmi-shmem@d7604000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7604000 0x0 0x1000>; + no-map; + }; + + shmem5: scmi-shmem@d7605000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7605000 0x0 0x1000>; + no-map; + }; + + shmem6: scmi-shmem@d7606000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7606000 0x0 0x1000>; + no-map; + }; + + shmem7: scmi-shmem@d7607000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7607000 0x0 0x1000>; + no-map; + }; + + shmem8: scmi-shmem@d7608000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7608000 0x0 0x1000>; + no-map; + }; + + shmem9: scmi-shmem@d7609000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7609000 0x0 0x1000>; + no-map; + }; + + shmem10: scmi-shmem@d760a000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd760a000 0x0 0x1000>; + no-map; + }; + + shmem11: scmi-shmem@d760b000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd760b000 0x0 0x1000>; + no-map; + }; + + shmem12: scmi-shmem@d760c000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd760c000 0x0 0x1000>; + no-map; + }; + + shmem13: scmi-shmem@d760d000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd760d000 0x0 0x1000>; + no-map; + }; + + shmem14: scmi-shmem@d760e000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd760e000 0x0 0x1000>; + no-map; + }; + + shmem15: scmi-shmem@d760f000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd760f000 0x0 0x1000>; + no-map; + }; + + shmem16: scmi-shmem@d7610000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7610000 0x0 0x1000>; + no-map; + }; + + shmem17: scmi-shmem@d7611000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7611000 0x0 0x1000>; + no-map; + }; + + shmem18: scmi-shmem@d7612000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7612000 0x0 0x1000>; + no-map; + }; + + shmem19: scmi-shmem@d7613000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7613000 0x0 0x1000>; + no-map; + }; + + shmem20: scmi-shmem@d7614000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7614000 0x0 0x1000>; + no-map; + }; + + shmem21: scmi-shmem@d7615000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7615000 0x0 0x1000>; + no-map; + }; + + shmem22: scmi-shmem@d7616000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7616000 0x0 0x1000>; + no-map; + }; + + shmem23: scmi-shmem@d7617000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7617000 0x0 0x1000>; + no-map; + }; + + shmem24: scmi-shmem@d7618000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7618000 0x0 0x1000>; + no-map; + }; + + shmem25: scmi-shmem@d7619000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7619000 0x0 0x1000>; + no-map; + }; + + shmem26: scmi-shmem@d761a000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd761a000 0x0 0x1000>; + no-map; + }; + + shmem27: scmi-shmem@d761b000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd761b000 0x0 0x1000>; + no-map; + }; + + shmem28: scmi-shmem@d761c000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd761c000 0x0 0x1000>; + no-map; + }; + + shmem29: scmi-shmem@d761d000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd761d000 0x0 0x1000>; + no-map; + }; + + shmem30: scmi-shmem@d761e000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd761e000 0x0 0x1000>; + no-map; + }; + + shmem31: scmi-shmem@d761f000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd761f000 0x0 0x1000>; + no-map; + }; + + shmem32: scmi-shmem@d7620000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7620000 0x0 0x1000>; + no-map; + }; + + shmem33: scmi-shmem@d7621000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7621000 0x0 0x1000>; + no-map; + }; + + shmem34: scmi-shmem@d7622000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7622000 0x0 0x1000>; + no-map; + }; + + shmem35: scmi-shmem@d7623000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7623000 0x0 0x1000>; + no-map; + }; + + shmem36: scmi-shmem@d7624000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7624000 0x0 0x1000>; + no-map; + }; + + shmem37: scmi-shmem@d7625000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7625000 0x0 0x1000>; + no-map; + }; + + shmem38: scmi-shmem@d7626000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7626000 0x0 0x1000>; + no-map; + }; + + shmem39: scmi-shmem@d7627000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7627000 0x0 0x1000>; + no-map; + }; + + shmem40: scmi-shmem@d7628000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7628000 0x0 0x1000>; + no-map; + }; + + shmem41: scmi-shmem@d7629000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7629000 0x0 0x1000>; + no-map; + }; + + shmem42: scmi-shmem@d762a000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd762a000 0x0 0x1000>; + no-map; + }; + + shmem43: scmi-shmem@d762b000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd762b000 0x0 0x1000>; + no-map; + }; + + shmem44: scmi-shmem@d762c000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd762c000 0x0 0x1000>; + no-map; + }; + + shmem45: scmi-shmem@d762d000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd762d000 0x0 0x1000>; + no-map; + }; + + shmem46: scmi-shmem@d762e000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd762e000 0x0 0x1000>; + no-map; + }; + + shmem47: scmi-shmem@d762f000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd762f000 0x0 0x1000>; + no-map; + }; + + shmem48: scmi-shmem@d7630000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7630000 0x0 0x1000>; + no-map; + }; + + shmem49: scmi-shmem@d7631000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7631000 0x0 0x1000>; + no-map; + }; + + shmem50: scmi-shmem@d7632000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7632000 0x0 0x1000>; + no-map; + }; + + shmem51: scmi-shmem@d7633000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7633000 0x0 0x1000>; + no-map; + }; + + shmem52: scmi-shmem@d7634000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7634000 0x0 0x1000>; + no-map; + }; + + shmem53: scmi-shmem@d7635000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7635000 0x0 0x1000>; + no-map; + }; + + shmem54: scmi-shmem@d7636000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7636000 0x0 0x1000>; + no-map; + }; + + shmem55: scmi-shmem@d7637000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7637000 0x0 0x1000>; + no-map; + }; + + shmem56: scmi-shmem@d7638000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7638000 0x0 0x1000>; + no-map; + }; + + shmem57: scmi-shmem@d7639000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7639000 0x0 0x1000>; + no-map; + }; + + shmem58: scmi-shmem@d763a000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd763a000 0x0 0x1000>; + no-map; + }; + + shmem59: scmi-shmem@d763b000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd763b000 0x0 0x1000>; + no-map; + }; + + shmem60: scmi-shmem@d763c000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd763c000 0x0 0x1000>; + no-map; + }; + + shmem61: scmi-shmem@d763d000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd763d000 0x0 0x1000>; + no-map; + }; + + shmem62: scmi-shmem@d763e000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd763e000 0x0 0x1000>; + no-map; + }; + + shmem63: scmi-shmem@d763f000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd763f000 0x0 0x1000>; + no-map; + }; +}; + +&spi0 { + compatible = "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains = <&scmi10_pd 0>, + <&scmi10_dvfs 0>; + power-domain-names = "power", + "perf"; +}; + +&spi1 { + compatible = "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains = <&scmi10_pd 1>, + <&scmi10_dvfs 1>; + power-domain-names = "power", + "perf"; +}; + +&spi2 { + compatible = "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains = <&scmi10_pd 2>, + <&scmi10_dvfs 2>; + power-domain-names = "power", + "perf"; +}; + +&spi3 { + compatible = "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains = <&scmi10_pd 3>, + <&scmi10_dvfs 3>; + power-domain-names = "power", + "perf"; +}; + +&spi4 { + compatible = "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains = <&scmi10_pd 4>, + <&scmi10_dvfs 4>; + power-domain-names = "power", + "perf"; +}; + +&spi5 { + compatible = "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains = <&scmi10_pd 5>, + <&scmi10_dvfs 5>; + power-domain-names = "power", + "perf"; +}; + +&spi7 { + compatible = "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains = <&scmi10_pd 7>, + <&scmi10_dvfs 7>; + power-domain-names = "power", + "perf"; +}; + +&spi8 { + compatible = "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains = <&scmi10_pd 8>, + <&scmi10_dvfs 8>; + power-domain-names = "power", + "perf"; +}; + +&spi11 { + compatible = "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains = <&scmi10_pd 11>, + <&scmi10_dvfs 11>; + power-domain-names = "power", + "perf"; +}; + +&spi12 { + compatible = "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains = <&scmi10_pd 12>, + <&scmi10_dvfs 12>; + power-domain-names = "power", + "perf"; +}; + +&spi13 { + compatible = "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains = <&scmi10_pd 13>, + <&scmi10_dvfs 13>; + power-domain-names = "power", + "perf"; +}; + +&spi14 { + compatible = "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains = <&scmi10_pd 14>, + <&scmi10_dvfs 14>; + power-domain-names = "power", + "perf"; +}; + +&spi15 { + compatible = "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains = <&scmi10_pd 15>, + <&scmi10_dvfs 15>; + power-domain-names = "power", + "perf"; +}; + +&spi16 { + compatible = "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains = <&scmi10_pd 16>, + <&scmi10_dvfs 16>; + power-domain-names = "power", + "perf"; +}; + +&spi17 { + compatible = "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains = <&scmi10_pd 17>, + <&scmi10_dvfs 17>; + power-domain-names = "power", + "perf"; +}; + +&spi18 { + compatible = "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains = <&scmi10_pd 18>, + <&scmi10_dvfs 18>; + power-domain-names = "power", + "perf"; +}; + +&spi19 { + compatible = "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains = <&scmi10_pd 19>, + <&scmi10_dvfs 19>; + power-domain-names = "power", + "perf"; +}; + +&spi20 { + compatible = "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains = <&scmi10_pd 20>, + <&scmi10_dvfs 20>; + power-domain-names = "power", + "perf"; +}; + +&uart0 { + compatible = "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains = <&scmi11_pd 0>, + <&scmi11_dvfs 0>; + power-domain-names = "power", + "perf"; +}; + +&uart1 { + compatible = "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains = <&scmi11_pd 1>, + <&scmi11_dvfs 1>; + power-domain-names = "power", + "perf"; +}; + +&uart2 { + compatible = "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains = <&scmi11_pd 2>, + <&scmi11_dvfs 2>; + power-domain-names = "power", + "perf"; +}; + +&uart3 { + compatible = "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains = <&scmi11_pd 3>, + <&scmi11_dvfs 3>; + power-domain-names = "power", + "perf"; +}; + +&uart4 { + compatible = "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains = <&scmi11_pd 4>, + <&scmi11_dvfs 4>; + power-domain-names = "power", + "perf"; +}; + +&uart5 { + compatible = "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains = <&scmi11_pd 5>, + <&scmi11_dvfs 5>; + power-domain-names = "power", + "perf"; +}; + +&uart7 { + compatible = "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains = <&scmi11_pd 7>, + <&scmi11_dvfs 7>; + power-domain-names = "power", + "perf"; +}; + +&uart8 { + compatible = "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains = <&scmi11_pd 8>, + <&scmi11_dvfs 8>; + power-domain-names = "power", + "perf"; +}; + +&uart9 { + compatible = "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains = <&scmi11_pd 9>, + <&scmi11_dvfs 9>; + power-domain-names = "power", + "perf"; +}; + +&uart10 { + compatible = "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains = <&scmi11_pd 10>, + <&scmi11_dvfs 10>; + power-domain-names = "power", + "perf"; +}; + +&uart11 { + compatible = "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains = <&scmi11_pd 11>, + <&scmi11_dvfs 11>; + power-domain-names = "power", + "perf"; +}; + +&uart12 { + compatible = "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains = <&scmi11_pd 12>, + <&scmi11_dvfs 12>; + power-domain-names = "power", + "perf"; +}; + +&uart13 { + compatible = "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains = <&scmi11_pd 13>, + <&scmi11_dvfs 13>; + power-domain-names = "power", + "perf"; +}; + +&uart14 { + compatible = "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains = <&scmi11_pd 14>, + <&scmi11_dvfs 14>; + power-domain-names = "power", + "perf"; +}; + +&uart15 { + compatible = "qcom,sa8797p-geni-debug-uart", + "qcom,sa8255p-geni-debug-uart"; + power-domains = <&scmi11_pd 15>, + <&scmi11_dvfs 15>; + power-domain-names = "power", + "perf"; +}; + +&uart16 { + compatible = "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains = <&scmi11_pd 16>, + <&scmi11_dvfs 16>; + power-domain-names = "power", + "perf"; +}; + +&uart17 { + compatible = "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains = <&scmi11_pd 17>, + <&scmi11_dvfs 17>; + power-domain-names = "power", + "perf"; +}; + +&uart18 { + compatible = "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains = <&scmi11_pd 18>, + <&scmi11_dvfs 18>; + power-domain-names = "power", + "perf"; +}; + +&uart19 { + compatible = "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains = <&scmi11_pd 19>, + <&scmi11_dvfs 19>; + power-domain-names = "power", + "perf"; +}; + +&uart20 { + compatible = "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains = <&scmi11_pd 20>, + <&scmi11_dvfs 20>; + power-domain-names = "power", + "perf"; +}; + +&ufs_mem_hc { + compatible = "qcom,sa8797p-ufshc", + "qcom,sa8255p-ufshc"; + power-domains = <&scmi3_pd 0>; +}; diff --git a/arch/arm64/boot/dts/qcom/nord-ride.dts b/arch/arm64/boot/dts/qcom/nord-ride.dts new file mode 100644 index 000000000000..1af4117d24d7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/nord-ride.dts @@ -0,0 +1,254 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include "nord-gearvm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8797P Ride"; + compatible = "qcom,sa8797p-ride", "qcom,nord"; + + aliases { + i2c18 = &i2c18; + serial0 = &uart15; + serial1 = &uart4; + spi16 = &spi16; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + clocks { + xo_board_clk: xo-board-clk { + compatible = "fixed-clock"; + clock-frequency = <38400000>; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + }; +}; + +&i2c18 { + status = "okay"; +}; + +&scmi3 { + status = "okay"; +}; + +&scmi9 { + status = "okay"; +}; + +&scmi10 { + status = "okay"; +}; + +&scmi11 { + status = "okay"; +}; + +&scmi23 { + status = "okay"; +}; + +&spi16 { + status = "okay"; +}; + +&thermal_zones { + pmic_kobra_thermal: pmic-a-die-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&scmi23_sensor 3>; + + trips { + trip0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + pmic_kai_0_thermal: pmic-e-die-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&scmi23_sensor 4>; + + trips { + trip0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + pmic_kai_1_thermal: pmic-f-die-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&scmi23_sensor 5>; + + trips { + trip0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + pmic_kai_2_thermal: pmic-g-die-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&scmi23_sensor 6>; + + trips { + trip0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + pmic_kai_3_thermal: pmic-h-die-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&scmi23_sensor 7>; + + trips { + trip0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + pmic_kai_4_thermal: pmic-i-die-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&scmi23_sensor 8>; + + trips { + trip0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + pmic_kai_5_thermal: pmic-j-die-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&scmi23_sensor 9>; + + trips { + trip0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + pmic_kai_6_thermal: pmic-k-die-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&scmi23_sensor 10>; + + trips { + trip0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + pmic_kai_7_thermal: pmic-l-die-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&scmi23_sensor 11>; + + trips { + trip0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + pmic_kai_ufs_thermal: ufs-thermal { + polling-delay-passive = <0>; + thermal-sensors = <&scmi23_sensor 0>; + + trips { + trip0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <5000>; + type = "critical"; + }; + }; + }; + + pmic_kai_sdram0_thermal: sdram0-thermal { + polling-delay-passive = <0>; + thermal-sensors = <&scmi23_sensor 1>; + + trips { + trip0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <5000>; + type = "critical"; + }; + }; + }; + + pmic_kai_sdram1_thermal: sdram1-thermal { + polling-delay-passive = <0>; + thermal-sensors = <&scmi23_sensor 2>; + + trips { + trip0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <5000>; + type = "critical"; + }; + }; + }; +}; + +&uart4 { + status = "okay"; +}; + +&uart15 { + status = "okay"; +}; + +&ufs_mem_hc { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/nord-rrd.dts b/arch/arm64/boot/dts/qcom/nord-rrd.dts new file mode 100644 index 000000000000..3673003c8b21 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/nord-rrd.dts @@ -0,0 +1,424 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> + +#include "nord-embedded.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IQ10 RRD"; + compatible = "qcom,iq10-rrd", "qcom,nord"; + + aliases { + serial0 = &uart15; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + clocks { + xo_board: xo-board-clk { + compatible = "fixed-clock"; + clock-frequency = <38400000>; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + + bi_tcxo_div2: bi-tcxo-div2-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-mult = <1>; + clock-div = <2>; + }; + + bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&rpmhcc RPMH_CXO_CLK_A>; + clock-mult = <1>; + clock-div = <2>; + }; + }; +}; + +&apps_rsc { + /* PMIC A - Kobra_MM (PMM8650AU) - SID 0x0, Bus E0 */ + regulators-0 { + compatible = "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id = "A_E0"; + + vreg_l4a_1p2: ldo4 { + regulator-name = "vreg_l4a_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6a_1p2: ldo6 { + regulator-name = "vreg_l6a_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7a_1p2: ldo7 { + regulator-name = "vreg_l7a_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-always-on; + regulator-boot-on; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8a_1p8: ldo8 { + regulator-name = "vreg_l8a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-always-on; + regulator-boot-on; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s1a_vdd2h_l: smps1 { + regulator-name = "vreg_s1a_vdd2h_l"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-always-on; + regulator-boot-on; + }; + + vreg_s3a_1p8: smps3 { + regulator-name = "vreg_s3a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-always-on; + regulator-boot-on; + }; + + vreg_s5a_mv: smps5 { + regulator-name = "vreg_s5a_mv"; + regulator-min-microvolt = <1328000>; + regulator-max-microvolt = <1370000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-always-on; + regulator-boot-on; + }; + + vreg_s6a_vddq_l: smps6 { + regulator-name = "vreg_s6a_vddq_l"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <570000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + }; + + /* PMIC E - Kai_MV - SID 0x4, Bus E0 */ + regulators-1 { + compatible = "qcom,pmau0102-rpmh-regulators"; + qcom,pmic-id = "E_E0"; + + vreg_l1e_0p9: ldo1 { + regulator-name = "vreg_l1e_0p9"; + regulator-min-microvolt = <936000>; + regulator-max-microvolt = <936000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2e_0p9: ldo2 { + regulator-name = "vreg_l2e_0p9"; + regulator-min-microvolt = <936000>; + regulator-max-microvolt = <936000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3e_1p8: ldo3 { + regulator-name = "vreg_l3e_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + }; + + /* PMIC F - Kai_MV - SID 0x5, Bus E0 */ + regulators-2 { + compatible = "qcom,pmau0102-rpmh-regulators"; + qcom,pmic-id = "F_E0"; + + vreg_l1f_vdd2l: ldo1 { + regulator-name = "vreg_l1f_vdd2l"; + regulator-min-microvolt = <904000>; + regulator-max-microvolt = <904000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-always-on; + regulator-boot-on; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3f_vdd1: ldo3 { + regulator-name = "vreg_l3f_vdd1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-always-on; + regulator-boot-on; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s7f_lv_sub: smps7 { + regulator-name = "vreg_s7f_lv_sub"; + regulator-min-microvolt = <1036000>; + regulator-max-microvolt = <1136000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-always-on; + regulator-boot-on; + }; + + vreg_s8f_vddq_h: smps8 { + regulator-name = "vreg_s8f_vddq_h"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <570000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + }; + + /* PMIC G - Kai_MV - SID 0x6, Bus E0 */ + regulators-3 { + compatible = "qcom,pmau0102-rpmh-regulators"; + qcom,pmic-id = "G_E0"; + + vreg_l2g_0p7: ldo2 { + regulator-name = "vreg_l2g_0p7"; + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <752000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s5g_vdd2h_h: smps5 { + regulator-name = "vreg_s5g_vdd2h_h"; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1150000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-always-on; + regulator-boot-on; + }; + }; + + /* PMIC H - Kai_MV - SID 0x7, Bus E0 */ + regulators-4 { + compatible = "qcom,pmau0102-rpmh-regulators"; + qcom,pmic-id = "H_E0"; + + vreg_l1h_0p9: ldo1 { + regulator-name = "vreg_l1h_0p9"; + regulator-min-microvolt = <904000>; + regulator-max-microvolt = <904000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2h_1p2: ldo2 { + regulator-name = "vreg_l2h_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + /* PMIC I - Kai_MV - SID 0x8, Bus E0 */ + regulators-5 { + compatible = "qcom,pmau0102-rpmh-regulators"; + qcom,pmic-id = "I_E0"; + + vreg_l1i_0p9: ldo1 { + regulator-name = "vreg_l1i_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2i_1p2: ldo2 { + regulator-name = "vreg_l2i_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3i_2p5: ldo3 { + regulator-name = "vreg_l3i_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + }; + + /* PMIC K - Kai_MV - SID 0xA, Bus E0 */ + regulators-6 { + compatible = "qcom,pmau0102-rpmh-regulators"; + qcom,pmic-id = "K_E0"; + + vreg_l1k_vdd2l: ldo1 { + regulator-name = "vreg_l1k_vdd2l"; + regulator-min-microvolt = <904000>; + regulator-max-microvolt = <904000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-always-on; + regulator-boot-on; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2k_0p9: ldo2 { + regulator-name = "vreg_l2k_0p9"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3k_vdd1: ldo3 { + regulator-name = "vreg_l3k_vdd1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-always-on; + regulator-boot-on; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + }; + + /* PMIC L - Kai_MV - SID 0xB, Bus E0 */ + regulators-7 { + compatible = "qcom,pmau0102-rpmh-regulators"; + qcom,pmic-id = "L_E0"; + + vreg_l3l_1p8: ldo3 { + regulator-name = "vreg_l3l_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + }; +}; + +&i2c7 { + clock-frequency = <400000>; + + status = "okay"; + + rtc@32 { + compatible = "epson,rx8900"; + reg = <0x32>; + }; +}; + +&qupv3_0 { + firmware-name = "qcom/nord/qupv3fw.elf"; + + status = "okay"; +}; + +&qupv3_1 { + firmware-name = "qcom/nord/qupv3fw.elf"; + + status = "okay"; +}; + +&qupv3_2 { + firmware-name = "qcom/nord/qupv3fw.elf"; + + status = "okay"; +}; + +&spi16 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&uart15 { + status = "okay"; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 181 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l3i_2p5>; + vcc-max-microamp = <1300000>; + vccq-supply = <&vreg_l2i_1p2>; + vccq-max-microamp = <1200000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l1i_0p9>; + vdda-pll-supply = <&vreg_l2h_1p2>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/nord.dtsi b/arch/arm64/boot/dts/qcom/nord.dtsi new file mode 100644 index 000000000000..e0496fd40c30 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/nord.dtsi @@ -0,0 +1,4605 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + interrupt-parent = <&intc>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,oryon-1-5"; + reg = <0x0 0x0>; + enable-method = "psci"; + power-domains = <&cpu0_pd>, <&cpu_perf 0>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + + l2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,oryon-1-5"; + reg = <0x0 0x100>; + enable-method = "psci"; + power-domains = <&cpu1_pd>, <&cpu_perf 0>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,oryon-1-5"; + reg = <0x0 0x200>; + enable-method = "psci"; + power-domains = <&cpu2_pd>, <&cpu_perf 0>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,oryon-1-5"; + reg = <0x0 0x300>; + enable-method = "psci"; + power-domains = <&cpu3_pd>, <&cpu_perf 0>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + cpu4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,oryon-1-5"; + reg = <0x0 0x400>; + enable-method = "psci"; + power-domains = <&cpu4_pd>, <&cpu_perf 0>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + cpu5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,oryon-1-5"; + reg = <0x0 0x500>; + enable-method = "psci"; + power-domains = <&cpu5_pd>, <&cpu_perf 0>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + cpu6: cpu@10000 { + device_type = "cpu"; + compatible = "qcom,oryon-1-5"; + reg = <0x0 0x10000>; + power-domains = <&cpu6_pd>, <&cpu_perf 1>; + power-domain-names = "psci", "perf"; + enable-method = "psci"; + next-level-cache = <&l2_10000>; + #cooling-cells = <2>; + + l2_10000: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + }; + + cpu7: cpu@10100 { + device_type = "cpu"; + compatible = "qcom,oryon-1-5"; + reg = <0x0 0x10100>; + enable-method = "psci"; + power-domains = <&cpu7_pd>, <&cpu_perf 1>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_10000>; + #cooling-cells = <2>; + }; + + cpu8: cpu@10200 { + device_type = "cpu"; + compatible = "qcom,oryon-1-5"; + reg = <0x0 0x10200>; + enable-method = "psci"; + power-domains = <&cpu8_pd>, <&cpu_perf 1>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_10000>; + #cooling-cells = <2>; + }; + + cpu9: cpu@10300 { + device_type = "cpu"; + compatible = "qcom,oryon-1-5"; + reg = <0x0 0x10300>; + enable-method = "psci"; + power-domains = <&cpu9_pd>, <&cpu_perf 1>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_10000>; + #cooling-cells = <2>; + }; + + cpu10: cpu@10400 { + device_type = "cpu"; + compatible = "qcom,oryon-1-5"; + reg = <0x0 0x10400>; + enable-method = "psci"; + power-domains = <&cpu10_pd>, <&cpu_perf 1>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_10000>; + #cooling-cells = <2>; + }; + + cpu11: cpu@10500 { + device_type = "cpu"; + compatible = "qcom,oryon-1-5"; + reg = <0x0 0x10500>; + enable-method = "psci"; + power-domains = <&cpu11_pd>, <&cpu_perf 1>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_10000>; + #cooling-cells = <2>; + }; + + cpu12: cpu@20000 { + device_type = "cpu"; + compatible = "qcom,oryon-1-5"; + reg = <0x0 0x20000>; + enable-method = "psci"; + power-domains = <&cpu12_pd>, <&cpu_perf 2>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_20000>; + #cooling-cells = <2>; + + l2_20000: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + }; + + cpu13: cpu@20100 { + device_type = "cpu"; + compatible = "qcom,oryon-1-5"; + reg = <0x0 0x20100>; + enable-method = "psci"; + power-domains = <&cpu13_pd>, <&cpu_perf 2>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_20000>; + #cooling-cells = <2>; + }; + + cpu14: cpu@20200 { + device_type = "cpu"; + compatible = "qcom,oryon-1-5"; + reg = <0x0 0x20200>; + enable-method = "psci"; + power-domains = <&cpu14_pd>, <&cpu_perf 2>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_20000>; + #cooling-cells = <2>; + }; + + cpu15: cpu@20300 { + device_type = "cpu"; + compatible = "qcom,oryon-1-5"; + reg = <0x0 0x20300>; + enable-method = "psci"; + power-domains = <&cpu15_pd>, <&cpu_perf 2>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_20000>; + #cooling-cells = <2>; + }; + + cpu16: cpu@20400 { + device_type = "cpu"; + compatible = "qcom,oryon-1-5"; + reg = <0x0 0x20400>; + enable-method = "psci"; + power-domains = <&cpu16_pd>, <&cpu_perf 2>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_20000>; + #cooling-cells = <2>; + }; + + cpu17: cpu@20500 { + device_type = "cpu"; + compatible = "qcom,oryon-1-5"; + reg = <0x0 0x20500>; + enable-method = "psci"; + power-domains = <&cpu17_pd>, <&cpu_perf 2>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_20000>; + #cooling-cells = <2>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + + core4 { + cpu = <&cpu4>; + }; + + core5 { + cpu = <&cpu5>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu6>; + }; + + core1 { + cpu = <&cpu7>; + }; + + core2 { + cpu = <&cpu8>; + }; + + core3 { + cpu = <&cpu9>; + }; + + core4 { + cpu = <&cpu10>; + }; + + core5 { + cpu = <&cpu11>; + }; + }; + + cluster2 { + core0 { + cpu = <&cpu12>; + }; + + core1 { + cpu = <&cpu13>; + }; + + core2 { + cpu = <&cpu14>; + }; + + core3 { + cpu = <&cpu15>; + }; + + core4 { + cpu = <&cpu16>; + }; + + core5 { + cpu = <&cpu17>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + core_off_c4: cluster-c4 { + compatible = "arm,idle-state"; + idle-state-name = "retention"; + entry-latency-us = <93>; + exit-latency-us = <129>; + min-residency-us = <560>; + arm,psci-suspend-param = <0x00000003>; + }; + }; + + domain-idle-states { + cluster_pwr_dn: cluster-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x01000053>; + entry-latency-us = <2150>; + exit-latency-us = <1983>; + min-residency-us = <9144>; + }; + + domain_ss3: domain-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x02000153>; + entry-latency-us = <2800>; + exit-latency-us = <4400>; + min-residency-us = <10150>; + }; + }; + }; + + firmware: firmware { + scm { + compatible = "qcom,scm-nord", + "qcom,scm"; + qcom,dload-mode = <&tcsr 0x79000>; + }; + + pdp_scmi: scmi { + compatible = "arm,scmi"; + mboxes = <&pdp0_mbox 0>, + <&pdp0_mbox 11>, + <&pdp0_mbox 1>; + mbox-names = "tx", + "tx_reply", + "rx"; + shmem = <&pdp0_a2p>, + <&pdp0_p2a>; + #address-cells = <1>; + #size-cells = <0>; + + cpu_perf: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* Size will be updated by bootloader */ + reg = <0x0 0x80000000 0x0 0x0>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + cpu0_pd: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&cluster0_pd>; + domain-idle-states = <&core_off_c4>; + }; + + cpu1_pd: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&cluster0_pd>; + domain-idle-states = <&core_off_c4>; + }; + + cpu2_pd: power-domain-cpu2 { + #power-domain-cells = <0>; + power-domains = <&cluster0_pd>; + domain-idle-states = <&core_off_c4>; + }; + + cpu3_pd: power-domain-cpu3 { + #power-domain-cells = <0>; + power-domains = <&cluster0_pd>; + domain-idle-states = <&core_off_c4>; + }; + + cpu4_pd: power-domain-cpu4 { + #power-domain-cells = <0>; + power-domains = <&cluster0_pd>; + domain-idle-states = <&core_off_c4>; + }; + + cpu5_pd: power-domain-cpu5 { + #power-domain-cells = <0>; + power-domains = <&cluster0_pd>; + domain-idle-states = <&core_off_c4>; + }; + + cpu6_pd: power-domain-cpu6 { + #power-domain-cells = <0>; + power-domains = <&cluster1_pd>; + domain-idle-states = <&core_off_c4>; + }; + + cpu7_pd: power-domain-cpu7 { + #power-domain-cells = <0>; + power-domains = <&cluster1_pd>; + domain-idle-states = <&core_off_c4>; + }; + + cpu8_pd: power-domain-cpu8 { + #power-domain-cells = <0>; + power-domains = <&cluster1_pd>; + domain-idle-states = <&core_off_c4>; + }; + + cpu9_pd: power-domain-cpu9 { + #power-domain-cells = <0>; + power-domains = <&cluster1_pd>; + domain-idle-states = <&core_off_c4>; + }; + + cpu10_pd: power-domain-cpu10 { + #power-domain-cells = <0>; + power-domains = <&cluster1_pd>; + domain-idle-states = <&core_off_c4>; + }; + + cpu11_pd: power-domain-cpu11 { + #power-domain-cells = <0>; + power-domains = <&cluster1_pd>; + domain-idle-states = <&core_off_c4>; + }; + + cpu12_pd: power-domain-cpu12 { + #power-domain-cells = <0>; + power-domains = <&cluster2_pd>; + domain-idle-states = <&core_off_c4>; + }; + + cpu13_pd: power-domain-cpu13 { + #power-domain-cells = <0>; + power-domains = <&cluster2_pd>; + domain-idle-states = <&core_off_c4>; + }; + + cpu14_pd: power-domain-cpu14 { + #power-domain-cells = <0>; + power-domains = <&cluster2_pd>; + domain-idle-states = <&core_off_c4>; + }; + + cpu15_pd: power-domain-cpu15 { + #power-domain-cells = <0>; + power-domains = <&cluster2_pd>; + domain-idle-states = <&core_off_c4>; + }; + + cpu16_pd: power-domain-cpu16 { + #power-domain-cells = <0>; + power-domains = <&cluster2_pd>; + domain-idle-states = <&core_off_c4>; + }; + + cpu17_pd: power-domain-cpu17 { + #power-domain-cells = <0>; + power-domains = <&cluster2_pd>; + domain-idle-states = <&core_off_c4>; + }; + + cluster0_pd: power-domain-cluster0 { + #power-domain-cells = <0>; + power-domains = <&system_pd>; + domain-idle-states = <&cluster_pwr_dn>; + }; + + cluster1_pd: power-domain-cluster1 { + #power-domain-cells = <0>; + power-domains = <&system_pd>; + domain-idle-states = <&cluster_pwr_dn>; + }; + + cluster2_pd: power-domain-cluster2 { + #power-domain-cells = <0>; + power-domains = <&system_pd>; + domain-idle-states = <&cluster_pwr_dn>; + }; + + system_pd: power-domain-system { + #power-domain-cells = <0>; + domain-idle-states = <&domain_ss3>; + }; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cpucp_scandump_mem: cpucp-scandump-region@80000000 { + reg = <0x0 0x80000000 0x0 0x800000>; + no-map; + }; + + tme_sail_mem: tme-sail-region@81ff0000 { + reg = <0x0 0x81ff0000 0x0 0x10000>; + no-map; + }; + + tz_sail_mailbox_mem: tz-sail-mailbox-region@82000000 { + reg = <0x0 0x82000000 0x0 0x8000>; + no-map; + }; + + sail_mailbox_mem: sail-mailbox-region@82008000 { + reg = <0x0 0x82008000 0x0 0x1f8000>; + no-map; + }; + + sail_ota_mem: sail-ota-region@82200000 { + reg = <0x0 0x82200000 0x0 0x5ff000>; + no-map; + }; + + sail_vdt_mem: sail-vdt-region@827ff000 { + reg = <0x0 0x827ff000 0x0 0x1000>; + no-map; + }; + + hyp_mem: hyp-region@82800000 { + reg = <0x0 0x82800000 0x0 0x2400000>; + no-map; + }; + + deepsleep_mem: deepsleep-region@84c00000 { + reg = <0x0 0x84c00000 0x0 0x800000>; + no-map; + }; + + deepsleep_backup_mem: deepsleep-backup-region@86a00000 { + reg = <0x0 0x86a00000 0x0 0x200000>; + no-map; + }; + + soccp_fe_vm_0: soccp-fe-vm-0-region@86c00000 { + reg = <0x0 0x86c00000 0x0 0xac000>; + no-map; + }; + + soccp_fe_vm_1: soccp-fe-vm-1-region@86cac000 { + reg = <0x0 0x86cac000 0x0 0x18d000>; + no-map; + }; + + soccp_fe_vm_2: soccp-fe-vm-2-region@86e39000 { + reg = <0x0 0x86e39000 0x0 0x1c7000>; + no-map; + }; + + tme_crash_dump_mem: tme-crash-dump-region@87000000 { + reg = <0x0 0x87000000 0x0 0xa0000>; + no-map; + }; + + tme_log_mem: tme-log-region@87140000 { + reg = <0x0 0x87140000 0x0 0x4000>; + no-map; + }; + + aop_cmd_db_p_mem: aop-cmd-db-p-region@87148000 { + compatible = "qcom,cmd-db"; + reg = <0x0 0x87148000 0x0 0x20000>; + no-map; + }; + + nsp_sync_buffer_mem: nsp-sync-buffer-region@871ff000 { + reg = <0x0 0x871ff000 0x0 0x1000>; + no-map; + }; + + ddr_training_checksum_data_mem: ddr-training-checksum-data-region@87200000 { + reg = <0x0 0x87200000 0x0 0x2000>; + no-map; + }; + + xbl_dtlog_mem: xbl-dtlog-region@87202000 { + reg = <0x0 0x87202000 0x0 0x60000>; + no-map; + }; + + xbl_ramdump_mem: xbl-ramdump-region@87262000 { + reg = <0x0 0x87262000 0x0 0x1c0000>; + no-map; + }; + + uefi_log: uefi-log@87442000 { + reg = <0x0 0x87442000 0x0 0x10000>; + no-map; + }; + + secdata_apss_mem: secdata-apss-region@87452000 { + reg = <0x0 0x87452000 0x0 0x1000>; + no-map; + }; + + antireplay_emulation_mem: antireplay-emulation-region@87453000 { + reg = <0x0 0x87453000 0x0 0x1000>; + no-map; + }; + + soccp_sdi_mem: soccp-sdi-region@87454000 { + reg = <0x0 0x87454000 0x0 0x40000>; + no-map; + }; + + hyp_mem_database_mem: hyp-mem-database-region@87494000 { + reg = <0x0 0x87494000 0x0 0x60000>; + no-map; + }; + + pmic_mini_dump_mem: pmic-mini-dump-region@874f4000 { + reg = <0x0 0x874f4000 0x0 0x80000>; + no-map; + }; + + qup_fw_mem: qup-fw-region@87574000 { + reg = <0x0 0x87574000 0x0 0x20000>; + no-map; + }; + + softsku_mem: softsku-region@87594000 { + reg = <0x0 0x87594000 0x0 0x9000>; + no-map; + }; + + resource_scheduler_mem: resource-scheduler-region@8759d000 { + reg = <0x0 0x8759d000 0x0 0x20000>; + no-map; + }; + + pdp_ns_mem: pdp-ns-mem-region@87600000 { + reg = <0x0 0x87600000 0x0 0x8000>, + <0x0 0x87609000 0x0 0x1f7000>; + no-map; + }; + + pdp0_p2a: scmi-shmem@87608000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x87608000 0x0 0x80>; + no-map; + }; + + pdp0_a2p: scmi-shmem@87608180 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x87608180 0x0 0x80>; + no-map; + }; + + tz_stat_mem: tz-stat-region@87a00000 { + reg = <0x0 0x87a00000 0x0 0x100000>; + no-map; + }; + + qdss_apps_mem: qdss-apps-region@87b00000 { + reg = <0x0 0x87b00000 0x0 0x2000000>; + no-map; + }; + + global_sync_mem: global-sync-region@89f00000 { + reg = <0x0 0x89f00000 0x0 0x400000>; + no-map; + }; + + tzffi_mem: tzffi-region@8a300000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x8a300000 0x0 0x1400000>; + no-map; + }; + + gunyah_md_mem: gunyah-md-region@8b700000 { + reg = <0x0 0x8b700000 0x0 0x80000>; + no-map; + }; + + flashless_qntm_tool_mem: flashless-qntm-tool-region@8b780000 { + reg = <0x0 0x8b780000 0x0 0x182000>; + no-map; + }; + + ipa_fw_mem: ipa-fw-region@8bb00000 { + reg = <0x0 0x8bb00000 0x0 0x10000>; + no-map; + }; + + ipa_gsi_mem: ipa-gsi-region@8bb10000 { + reg = <0x0 0x8bb10000 0x0 0xa000>; + no-map; + }; + + gpu_microcode_mem: gpu-microcode-region@8bb1a000 { + reg = <0x0 0x8bb1a000 0x0 0x2000>; + no-map; + }; + + gpu_microcode_2_mem: gpu-microcode-2-region@8bb1c000 { + reg = <0x0 0x8bb1c000 0x0 0x2000>; + no-map; + }; + + soccp_mem: soccp-region@8bc00000 { + reg = <0x0 0x8bc00000 0x0 0x300000>; + no-map; + }; + + cvp_mem: cvp-region@8d100000 { + reg = <0x0 0x8d100000 0x0 0x800000>; + no-map; + }; + + cdsp0_mem: cdsp0-region@8d900000 { + reg = <0x0 0x8d900000 0x0 0x2300000>; + no-map; + }; + + cdsp1_mem: cdsp1-region@8fc00000 { + reg = <0x0 0x8fc00000 0x0 0x2300000>; + no-map; + }; + + cdsp2_mem: cdsp2-region@91f00000 { + reg = <0x0 0x91f00000 0x0 0x2300000>; + no-map; + }; + + cdsp3_mem: cdsp3-region@94200000 { + reg = <0x0 0x94200000 0x0 0x2300000>; + no-map; + }; + + hpass_dsp0_mem: hpass-dsp0-region@96500000 { + reg = <0x0 0x96500000 0x0 0x2800000>; + no-map; + }; + + hpass_dsp1_mem: hpass-dsp1-region@98d00000 { + reg = <0x0 0x98d00000 0x0 0x2800000>; + no-map; + }; + + hpass_dsp2_mem: hpass-dsp2-region@9b500000 { + reg = <0x0 0x9b500000 0x0 0x2800000>; + no-map; + }; + + q6_cdsp0_dtb_mem: q6-cdsp0-dtb-region@9dd00000 { + reg = <0x0 0x9dd00000 0x0 0x80000>; + no-map; + }; + + q6_cdsp1_dtb_mem: q6-cdsp1-dtb-region@9dd80000 { + reg = <0x0 0x9dd80000 0x0 0x80000>; + no-map; + }; + + q6_cdsp2_dtb_mem: q6-cdsp2-dtb-region@9de00000 { + reg = <0x0 0x9de00000 0x0 0x80000>; + no-map; + }; + + q6_cdsp3_dtb_mem: q6-cdsp3-dtb-region@9de80000 { + reg = <0x0 0x9de80000 0x0 0x80000>; + no-map; + }; + + hpass_dsp0_dtb_mem: hpass-dsp0-dtb-region@9df00000 { + reg = <0x0 0x9df00000 0x0 0x80000>; + no-map; + }; + + hpass_dsp1_dtb_mem: hpass-dsp1-dtb-region@9df80000 { + reg = <0x0 0x9df80000 0x0 0x80000>; + no-map; + }; + + hpass_dsp2_dtb_mem: hpass-dsp2-dtb-region@9e000000 { + reg = <0x0 0x9e000000 0x0 0x100000>; + no-map; + }; + + camera_icp_1_mem: camera-icp-1-region@9e100000 { + reg = <0x0 0x9e100000 0x0 0x800000>; + no-map; + }; + + camera_icp_2_mem: camera-icp-2-region@9e900000 { + reg = <0x0 0x9e900000 0x0 0x800000>; + no-map; + }; + + camera_qup_1_mem: camera-qup-1-region@9f100000 { + reg = <0x0 0x9f100000 0x0 0x200000>; + no-map; + }; + + camera_qup_2_mem: camera-qup-2-region@9f300000 { + reg = <0x0 0x9f300000 0x0 0x200000>; + no-map; + }; + + video_mem: video-region@9f500000 { + reg = <0x0 0x9f500000 0x0 0xc00000>; + no-map; + }; + + pil_umd_reserved: mdt-load-region@a0100000 { + reg = <0x0 0xa0100000 0x0 0x100000>; + no-map; + }; + + mm_dspq: mm-dspq-region@ba200000 { + reg = <0x0 0xba200000 0x0 0x200000>; + no-map; + }; + + display_config_reserved: display-config-region@ba400000 { + reg = <0x0 0xba400000 0x0 0xa00000>; + no-map; + }; + + mm_calibration_data_mem: mm-calibration-data-region@bae00000 { + reg = <0x0 0xbae00000 0x0 0x800000>; + no-map; + }; + + audio_config_mem: audio-config-region@bb600000 { + reg = <0x0 0xbb600000 0x0 0xa00000>; + no-map; + }; + + dare_tz_mem: dare-tz-region@bc000000 { + reg = <0x0 0xbc000000 0x0 0xa300000>; + no-map; + }; + + hpass_rpc_remote_heap_mem: hpass-rpc-remote-heap-region@d4600000 { + reg = <0x0 0xd4600000 0x0 0x800000>; + no-map; + }; + + mdf_mem: mdf-region@d4e00000 { + reg = <0x0 0xd4e00000 0x0 0x2000000>; + no-map; + }; + + firmware_mem: firmware-region@d6e00000 { + reg = <0x0 0xd6e00000 0x0 0x800000>; + no-map; + }; + + firmware_shared_mem: firmware-shared-region@d7650000 { + reg = <0x0 0xd7650000 0x0 0x180000>; + no-map; + }; + + firmware_logs_mem: firmware-logs-region@d77d0000 { + reg = <0x0 0xd77d0000 0x0 0x20000>; + no-map; + }; + + sail_p_mem: sail-p-region@8c0000000 { + reg = <0x8 0xc0000000 0x0 0x8000000>; + no-map; + }; + + reserved_mem2: reserved-region@8c8000000 { + reg = <0x8 0xc8000000 0x0 0x18000000>; + no-map; + }; + + dump_mem: mem-dump-region { + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + size = <0x0 0x79b0000>; + }; + }; + + soc: soc@0 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + dma-ranges = <0 0 0 0 0x10 0>; + ranges = <0 0 0 0 0x10 0>; + + qupv3_2: geniqup@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x008c0000 0x0 0x2000>; + #address-cells = <2>; + #size-cells = <2>; + iommus = <&apps_smmu_0 0x15a3 0x0>; + ranges; + + i2c14: i2c@880000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00880000 0x0 0x4000>; + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi14: spi@880000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00880000 0x0 0x4000>; + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + + uart14: serial@880000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00880000 0x0 0x4000>; + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + + i2c15: i2c@884000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00884000 0x0 0x4000>; + interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi15: spi@884000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00884000 0x0 0x4000>; + interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + + uart15: serial@884000 { + compatible = "qcom,geni-debug-uart"; + reg = <0x0 0x00884000 0x0 0x4000>; + interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + + i2c16: i2c@888000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00888000 0x0 0x4000>; + interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi16: spi@888000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00888000 0x0 0x4000>; + interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + + uart16: serial@888000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00888000 0x0 0x4000>; + interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + + i2c17: i2c@88c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x0088c000 0x0 0x4000>; + interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi17: spi@88c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x0088c000 0x0 0x4000>; + interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + + uart17: serial@88c000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x0088c000 0x0 0x4000>; + interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + + i2c18: i2c@890000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00890000 0x0 0x4000>; + interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi18: spi@890000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00890000 0x0 0x4000>; + interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + + uart18: serial@890000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00890000 0x0 0x4000>; + interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + + i2c19: i2c@894000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00894000 0x0 0x4000>; + interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi19: spi@894000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00894000 0x0 0x4000>; + interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + + uart19: serial@894000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00894000 0x0 0x4000>; + interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + + i2c20: i2c@898000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00898000 0x0 0x4000>; + interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi20: spi@898000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00898000 0x0 0x4000>; + interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + + uart20: serial@898000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00898000 0x0 0x4000>; + interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + }; + + qupv3_0: geniqup@9c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x009c0000 0x0 0x2000>; + #address-cells = <2>; + #size-cells = <2>; + iommus = <&apps_smmu_2 0x1003 0x0>; + ranges; + + i2c0: i2c@980000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00980000 0x0 0x4000>; + interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi0: spi@980000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00980000 0x0 0x4000>; + interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + + uart0: serial@980000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00980000 0x0 0x4000>; + interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + + i2c1: i2c@984000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00984000 0x0 0x4000>; + interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi1: spi@984000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00984000 0x0 0x4000>; + interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + + uart1: serial@984000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00984000 0x0 0x4000>; + interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + + i2c2: i2c@988000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00988000 0x0 0x4000>; + interrupts = <GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi2: spi@988000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00988000 0x0 0x4000>; + interrupts = <GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + + uart2: serial@988000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00988000 0x0 0x4000>; + interrupts = <GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + + i2c3: i2c@98c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x0098c000 0x0 0x4000>; + interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi3: spi@98c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x0098c000 0x0 0x4000>; + interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + + uart3: serial@98c000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x0098c000 0x0 0x4000>; + interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + + i2c4: i2c@990000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00990000 0x0 0x4000>; + interrupts = <GIC_SPI 516 IRQ_TYPE_LEVEL_HIGH>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi4: spi@990000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00990000 0x0 0x4000>; + interrupts = <GIC_SPI 516 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + + uart4: serial@990000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00990000 0x0 0x4000>; + interrupts = <GIC_SPI 516 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + + i2c5: i2c@994000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00994000 0x0 0x4000>; + interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi5: spi@994000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00994000 0x0 0x4000>; + interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + + uart5: serial@994000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00994000 0x0 0x4000>; + interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + }; + + qupv3_1: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x00ac0000 0x0 0x2000>; + #address-cells = <2>; + #size-cells = <2>; + iommus = <&apps_smmu_2 0x1043 0x0>; + ranges; + + i2c7: i2c@a80000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a80000 0x0 0x4000>; + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi7: spi@a80000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a80000 0x0 0x4000>; + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + + uart7: serial@a80000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00a80000 0x0 0x4000>; + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + + i2c8: i2c@a84000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a84000 0x0 0x4000>; + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi8: spi@a84000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a84000 0x0 0x4000>; + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + + uart8: serial@a84000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00a84000 0x0 0x4000>; + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + + i2c9: i2c@a88000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a88000 0x0 0x4000>; + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart9: serial@a88000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00a88000 0x0 0x4000>; + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + + i2c10: i2c@a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a8c000 0x0 0x4000>; + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart10: serial@a8c000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00a8c000 0x0 0x4000>; + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + + i2c11: i2c@a90000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a90000 0x0 0x4000>; + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi11: spi@a90000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a90000 0x0 0x4000>; + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + + uart11: serial@a90000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00a90000 0x0 0x4000>; + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + + i2c12: i2c@a94000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a94000 0x0 0x4000>; + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi12: spi@a94000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a94000 0x0 0x4000>; + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + + uart12: serial@a94000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00a94000 0x0 0x4000>; + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + + i2c13: i2c@a98000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a98000 0x0 0x4000>; + interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi13: spi@a98000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a98000 0x0 0x4000>; + interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + + uart13: serial@a98000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00a98000 0x0 0x4000>; + interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + }; + + rng: rng@10c3000 { + compatible = "qcom,nord-trng", + "qcom,trng"; + reg = <0x0 0x010c3000 0x0 0x1000>; + }; + + ufs_mem_hc: ufshc@1d44000 { + compatible = "qcom,nord-ufshc", + "qcom,ufshc", + "jedec,ufs-2.0"; + reg = <0x0 0x01d44000 0x0 0x3000>, + <0x0 0x01d60000 0x0 0x15000>; + reg-names = "std", + "mcq"; + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; + lanes-per-direction = <2>; + iommus = <&apps_smmu_0 0x14c0 0x0>; + dma-coherent; + msi-parent = <&gic_its 0x14c0>; + + status = "disabled"; + }; + + cryptobam: dma-controller@1dc4000 { + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg = <0x0 0x01dc4000 0x0 0x28000>; + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + iommus = <&apps_smmu_0 0x1689 0>; + qcom,ee = <0>; + qcom,num-ees = <4>; + num-channels = <20>; + qcom,controlled-remotely; + }; + + crypto: crypto@1dfa000 { + compatible = "qcom,nord-qce", "qcom,sm8150-qce", "qcom,qce"; + reg = <0x0 0x01dfa000 0x0 0x6000>; + dmas = <&cryptobam 4>, <&cryptobam 5>; + dma-names = "rx", "tx"; + iommus = <&apps_smmu_0 0x1689 0>; + + /* It stops nord-gearvm variant from booting to console */ + status = "disabled"; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x01f40000 0x0 0x20000>; + #hwlock-cells = <1>; + }; + + tcsr: syscon@1f60000 { + compatible = "qcom,nord-tcsr", + "syscon"; + reg = <0x0 0x01f60000 0x0 0xa0000>; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,nord-pdc", + "qcom,pdc"; + reg = <0x0 0x0b220000 0x0 0x10000>; + qcom,pdc-ranges = <0 745 43>, + <67 543 31>, + <98 609 32>, + <130 717 12>, + <142 251 5>, + <147 796 16>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + tsens0: thermal-sensor@c22c000 { + compatible = "qcom,nord-tsens", + "qcom,tsens-v2"; + reg = <0x0 0x0c22c000 0x0 0x1000>, + <0x0 0x0c222000 0x0 0x1000>; + interrupts = <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 484 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", + "critical"; + #qcom,sensors = <16>; + #thermal-sensor-cells = <1>; + }; + + tsens1: thermal-sensor@c22d000 { + compatible = "qcom,nord-tsens", + "qcom,tsens-v2"; + reg = <0x0 0x0c22d000 0x0 0x1000>, + <0x0 0x0c223000 0x0 0x1000>; + interrupts = <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 485 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", + "critical"; + #qcom,sensors = <16>; + #thermal-sensor-cells = <1>; + }; + + tsens2: thermal-sensor@c22e000 { + compatible = "qcom,nord-tsens", + "qcom,tsens-v2"; + reg = <0x0 0x0c22e000 0x0 0x1000>, + <0x0 0x0c224000 0x0 0x1000>; + interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", + "critical"; + #qcom,sensors = <16>; + #thermal-sensor-cells = <1>; + }; + + tsens3: thermal-sensor@c22f000 { + compatible = "qcom,nord-tsens", + "qcom,tsens-v2"; + reg = <0x0 0x0c22f000 0x0 0x1000>, + <0x0 0x0c225000 0x0 0x1000>; + interrupts = <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", + "critical"; + #qcom,sensors = <16>; + #thermal-sensor-cells = <1>; + }; + + tsens4: thermal-sensor@c230000 { + compatible = "qcom,nord-tsens", + "qcom,tsens-v2"; + reg = <0x0 0x0c230000 0x0 0x1000>, + <0x0 0x0c226000 0x0 0x1000>; + interrupts = <GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", + "critical"; + #qcom,sensors = <16>; + #thermal-sensor-cells = <1>; + }; + + tsens5: thermal-sensor@c231000 { + compatible = "qcom,nord-tsens", + "qcom,tsens-v2"; + reg = <0x0 0x0c231000 0x0 0x1000>, + <0x0 0x0c227000 0x0 0x1000>; + interrupts = <GIC_SPI 776 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", + "critical"; + #qcom,sensors = <16>; + #thermal-sensor-cells = <1>; + }; + + tsens6: thermal-sensor@c232000 { + compatible = "qcom,nord-tsens", + "qcom,tsens-v2"; + reg = <0x0 0x0c232000 0x0 0x1000>, + <0x0 0x0c228000 0x0 0x1000>; + interrupts = <GIC_SPI 777 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", + "critical"; + #qcom,sensors = <16>; + #thermal-sensor-cells = <1>; + }; + + tsens7: thermal-sensor@c233000 { + compatible = "qcom,nord-tsens", + "qcom,tsens-v2"; + reg = <0x0 0x0c233000 0x0 0x1000>, + <0x0 0x0c229000 0x0 0x1000>; + interrupts = <GIC_SPI 778 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", + "critical"; + #qcom,sensors = <16>; + #thermal-sensor-cells = <1>; + }; + + tlmm: pinctrl@f100000 { + compatible = "qcom,nord-tlmm"; + reg = <0x0 0x0f100000 0x0 0xc0000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 181>; + wakeup-parent = <&pdc>; + }; + + apps_smmu_0: iommu@15a00000 { + compatible = "qcom,nord-smmu-500", + "qcom,smmu-500", + "arm,mmu-500"; + reg = <0x0 0x15a00000 0x0 0x100000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + dma-coherent; + interrupts = <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 33 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 34 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 35 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 36 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 37 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 38 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 39 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 41 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 45 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 46 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 47 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 48 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 49 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 50 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 51 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 52 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 53 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 54 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 55 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 56 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 57 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 58 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 59 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 60 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 61 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 62 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 63 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 64 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 65 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 66 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 67 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 69 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 71 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 73 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 74 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 75 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 76 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 77 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 78 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 79 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 80 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 81 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 82 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 83 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 84 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 85 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 86 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 87 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 88 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 89 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 90 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 91 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 92 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 93 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 94 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 95 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 96 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 119 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 127 IRQ_TYPE_LEVEL_HIGH>; + }; + + apps_smmu_1: iommu@15c00000 { + compatible = "qcom,nord-smmu-500", + "qcom,smmu-500", + "arm,mmu-500"; + reg = <0x0 0x15c00000 0x0 0x100000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + dma-coherent; + interrupts = <GIC_SPI 882 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 128 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 129 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 130 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 131 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 133 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 134 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 135 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 136 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 137 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 138 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 139 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 140 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 150 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 151 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 152 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 154 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 156 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 157 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 158 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 159 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 160 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 161 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 162 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 163 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 164 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 165 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 166 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 167 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 168 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 169 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 171 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 172 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 173 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 174 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 175 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 176 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 177 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 178 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 179 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 180 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 181 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 182 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 183 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 184 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 185 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 186 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 187 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 188 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 189 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 190 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 191 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 192 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 193 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 194 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 195 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 196 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 197 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 198 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 199 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 200 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 201 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 202 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 203 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 204 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 205 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 206 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 207 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 208 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 209 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 210 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 211 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 212 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 213 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 214 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 215 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 216 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 217 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 218 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 219 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 220 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 221 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 222 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 223 IRQ_TYPE_LEVEL_HIGH>; + }; + + apps_smmu_2: iommu@15e00000 { + compatible = "qcom,nord-smmu-500", + "qcom,smmu-500", + "arm,mmu-500"; + reg = <0x0 0x15e00000 0x0 0x100000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + dma-coherent; + interrupts = <GIC_SPI 877 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 224 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 225 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 226 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 227 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 228 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 229 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 230 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 231 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 232 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 233 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 234 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 235 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 236 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 237 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 238 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 239 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 240 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 241 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 242 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 243 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 244 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 245 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 246 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 247 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 248 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 249 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 250 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 251 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 252 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 253 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 254 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 255 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 256 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 257 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 258 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 259 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 260 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 261 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 262 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 263 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 264 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 265 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 266 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 267 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 268 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 269 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 270 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 271 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 272 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 273 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 274 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 275 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 276 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 277 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 278 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 279 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 280 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 281 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 282 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 283 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 284 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 285 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 286 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 287 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 288 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 289 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 290 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 291 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 292 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 293 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 294 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 295 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 296 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 297 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 298 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 299 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 300 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 301 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 302 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 303 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 304 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 305 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 306 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 307 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 308 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 309 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 310 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 311 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 312 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 313 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 314 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 316 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 317 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 318 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 319 IRQ_TYPE_LEVEL_HIGH>; + }; + + intc: interrupt-controller@17000000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x17000000 0x0 0x10000>, + <0x0 0x17080000 0x0 0x480000>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x40000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic_its: msi-controller@17040000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x17040000 0x0 0x40000>; + msi-controller; + #msi-cells = <1>; + }; + }; + + pdp0_mbox: mailbox@17610000 { + compatible = "qcom,nord-cpucp-mbox", + "qcom,x1e80100-cpucp-mbox"; + reg = <0x0 0x17610000 0x0 0x4c08>, + <0x0 0x19980000 0x0 0x300>; + #mbox-cells = <1>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + }; + + memtimer: timer@17810000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x17810000 0x0 0x1000>; + ranges = <0x0 0x0 0x0 0x20000000>; + #address-cells = <1>; + #size-cells = <1>; + + frame@17811000 { + reg = <0x17811000 0x1000>, + <0x17812000 0x1000>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <0>; + }; + + frame@17813000 { + reg = <0x17813000 0x1000>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <1>; + + status = "disabled"; + }; + + frame@17815000 { + reg = <0x17815000 0x1000>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <2>; + + status = "disabled"; + }; + + frame@17817000 { + reg = <0x17817000 0x1000>; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <3>; + + status = "disabled"; + }; + + frame@17819000 { + reg = <0x17819000 0x1000>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <4>; + + status = "disabled"; + }; + + frame@1781b000 { + reg = <0x1781b000 0x1000>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <5>; + + status = "disabled"; + }; + + frame@1781d000 { + reg = <0x1781d000 0x1000>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <6>; + + status = "disabled"; + }; + }; + + watchdog@17826000 { + compatible = "qcom,apss-wdt-nord", + "qcom,kpss-wdt"; + reg = <0x0 0x17826000 0x0 0x1000>; + clocks = <&sleep_clk>; + interrupts = <GIC_ESPI 848 IRQ_TYPE_EDGE_RISING>; + }; + }; + + arch_timer: timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + }; + + thermal_zones: thermal-zones { + ddr-0-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 0>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-0-0-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 1>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-0-1-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 2>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-0-2-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 3>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-0-3-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 4>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-0-4-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 5>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-0-5-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 6>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpullc-0-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 7>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-1-0-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 8>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-1-1-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 9>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-1-2-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 10>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-1-3-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 11>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-1-4-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 12>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-1-5-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 13>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpullc-1-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 14>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + ddr-1-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 15>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + ddr-0-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 0>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-0-0-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 1>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-0-1-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 2>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-0-2-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 3>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-0-3-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 4>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-0-4-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 5>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-0-5-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 6>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpullc-0-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 7>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-1-0-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 8>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-1-1-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 9>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-1-2-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 10>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-1-3-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 11>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-1-4-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 12>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-1-5-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 13>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpullc-1-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 14>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + ddr-1-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 15>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + amux-2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 0>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-2-0-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 1>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-2-1-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 2>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-2-2-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 3>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-2-3-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 4>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-2-4-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 5>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-2-5-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 6>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpullc-2-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 7>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + audhvx-0-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 8>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + audhmx-0-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 9>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + audhvx-1-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 10>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + audhmx-1-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 11>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + audhvx-2-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 12>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + audhmx-2-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 13>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + pcie-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 15>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + amux-3-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens3 0>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-2-0-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens3 1>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-2-1-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens3 2>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-2-2-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens3 3>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-2-3-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens3 4>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-2-4-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens3 5>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-2-5-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens3 6>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpullc-2-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens3 7>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + audhvx-0-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens3 8>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + audhmx-0-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens3 9>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + audhvx-1-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens3 10>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + audhmx-1-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens3 11>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + audhvx-2-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens3 12>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + audhmx-2-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens3 13>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + pcie-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens3 15>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsphvx-0-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens4 0>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsphvx-0-2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens4 1>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsp-0-0-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens4 2>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsp-0-1-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens4 3>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsphvx-1-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens4 4>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsphvx-1-2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens4 5>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsp-1-0-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens4 6>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsp-1-1-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens4 7>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsphvx-2-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens4 8>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsphvx-2-2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens4 9>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsp-2-0-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens4 10>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsp-2-1-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens4 11>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsphvx-3-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens4 12>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsphvx-3-2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens4 13>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsp-3-0-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens4 14>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsp-3-1-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens4 15>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsphvx-0-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens5 0>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsphvx-0-3-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens5 1>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsp-0-0-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens5 2>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsp-0-1-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens5 3>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsphvx-1-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens5 4>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsphvx-1-3-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens5 5>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsp-1-0-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens5 6>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsp-1-1-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens5 7>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsphvx-2-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens5 8>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsphvx-2-3-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens5 9>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsp-2-0-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens5 10>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsp-2-1-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens5 11>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsphvx-3-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens5 12>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsphvx-3-3-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens5 13>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsp-3-0-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens5 14>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsp-3-1-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens5 15>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + amux-6-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens6 0>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + gpuss-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens6 1>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + gpuss-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens6 2>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + gpuss-2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens6 3>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + gpu-0-0-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens6 4>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + gpuss-1-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens6 5>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + gpuss-1-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens6 6>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cv-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens6 7>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + video-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens6 8>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + camera-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens6 9>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + ddr-2-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens6 10>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + ddr-3-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens6 11>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + gpuss-0-1-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens6 12>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + gpuss-1-1-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens6 13>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + gpuss-2-1-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens6 14>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + gpu-0-1-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens6 15>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + amux-7-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens7 0>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + gpuss-0-1-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens7 1>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + gpuss-1-1-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens7 2>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + gpuss-2-1-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens7 3>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + gpu-0-1-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens7 4>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + gpuss-1-2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens7 5>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + gpu-1-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens7 6>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cv-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens7 7>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + video-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens7 8>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + camera-2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens7 9>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + ddr-2-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens7 10>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + ddr-3-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens7 11>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + gpuss-0-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens7 12>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + gpuss-1-0-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens7 13>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + gpuss-2-0-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens7 14>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + gpu-0-0-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens7 15>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts b/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts index ad503beec1d3..6fc6fe7c0899 100644 --- a/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts +++ b/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts @@ -471,32 +471,6 @@ regulator-boot-on; }; - /* - * TODO: These two regulators are actually part of the removable M.2 - * card and not the EVK mainboard. Need to describe this differently. - * Functionally it works correctly, because all we need to do is to - * turn on the actual 3.3V supply above. - */ - vreg_wcn_0p95: regulator-wcn-0p95 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_WCN_0P95"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <950000>; - - vin-supply = <&vreg_wcn_3p3>; - }; - - vreg_wcn_1p9: regulator-wcn-1p9 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_WCN_1P9"; - regulator-min-microvolt = <1900000>; - regulator-max-microvolt = <1900000>; - - vin-supply = <&vreg_wcn_3p3>; - }; - vreg_wcn_3p3: regulator-wcn-3p3 { compatible = "regulator-fixed"; @@ -618,61 +592,40 @@ }; }; - wcn7850-pmu { - compatible = "qcom,wcn7850-pmu"; - - vdd-supply = <&vreg_wcn_0p95>; - vddio-supply = <&vreg_l15b_1p8>; - vddaon-supply = <&vreg_wcn_0p95>; - vdddig-supply = <&vreg_wcn_0p95>; - vddrfa1p2-supply = <&vreg_wcn_1p9>; - vddrfa1p8-supply = <&vreg_wcn_1p9>; + wifi-bt-connector { + compatible = "pcie-m2-e-connector"; + vpcie3v3-supply = <&vreg_wcn_3p3>; - bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; - wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; + w-disable1-gpios = <&tlmm 117 GPIO_ACTIVE_LOW>; + w-disable2-gpios = <&tlmm 116 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&wcn_bt_en>, <&wcn_wlan_en>; + pinctrl-0 = <&wcn_wlan_en>, <&wcn_bt_en>; pinctrl-names = "default"; - regulators { - vreg_pmu_rfa_cmn: ldo0 { - regulator-name = "vreg_pmu_rfa_cmn"; - }; - - vreg_pmu_aon_0p59: ldo1 { - regulator-name = "vreg_pmu_aon_0p59"; - }; - - vreg_pmu_wlcx_0p8: ldo2 { - regulator-name = "vreg_pmu_wlcx_0p8"; - }; - - vreg_pmu_wlmx_0p85: ldo3 { - regulator-name = "vreg_pmu_wlmx_0p85"; - }; - - vreg_pmu_btcmx_0p85: ldo4 { - regulator-name = "vreg_pmu_btcmx_0p85"; - }; - - vreg_pmu_rfa_0p8: ldo5 { - regulator-name = "vreg_pmu_rfa_0p8"; - }; + ports { + #address-cells = <1>; + #size-cells = <0>; - vreg_pmu_rfa_1p2: ldo6 { - regulator-name = "vreg_pmu_rfa_1p2"; - }; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; - vreg_pmu_rfa_1p8: ldo7 { - regulator-name = "vreg_pmu_rfa_1p8"; + m2_e_pcie_ep: endpoint@0 { + reg = <0>; + remote-endpoint = <&pcie4_port0_ep>; + }; }; - vreg_pmu_pcie_0p9: ldo8 { - regulator-name = "vreg_pmu_pcie_0p9"; - }; + port@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; - vreg_pmu_pcie_1p8: ldo9 { - regulator-name = "vreg_pmu_pcie_1p8"; + m2_e_uart_ep: endpoint@0 { + reg = <0>; + remote-endpoint = <&uart14_ep>; + }; }; }; }; @@ -1012,21 +965,10 @@ &pcie4_port0 { reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; +}; - wifi@0 { - compatible = "pci17cb,1107"; - reg = <0x10000 0x0 0x0 0x0 0x0>; - - vddaon-supply = <&vreg_pmu_aon_0p59>; - vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; - vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; - vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; - vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; - vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; - vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; - vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; - vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; - }; +&pcie4_port0_ep { + remote-endpoint = <&m2_e_pcie_ep>; }; &pcie5 { @@ -1499,19 +1441,10 @@ &uart14 { status = "okay"; +}; - bluetooth { - compatible = "qcom,wcn7850-bt"; - max-speed = <3200000>; - - vddaon-supply = <&vreg_pmu_aon_0p59>; - vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; - vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; - vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; - vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; - vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; - vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; - }; +&uart14_ep { + remote-endpoint = <&m2_e_uart_ep>; }; &uart21 { diff --git a/arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi b/arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi index 488e98413c3a..4ef3a5407ce8 100644 --- a/arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi +++ b/arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi @@ -476,6 +476,27 @@ status = "okay"; }; +&tcsr { + vdda-qrefrpt0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrpt1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrpt4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qrefrx0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrx1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrx4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qreftx0-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx0-1p2-supply = <&vreg_l2j_1p2>; + vdda-qreftx1-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx1-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen0-0p9-supply = <&vreg_l3i_0p8>; + vdda-refgen0-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen2-0p9-supply = <&vreg_l3j_0p8>; + vdda-refgen2-1p2-supply = <&vreg_l2j_1p2>; +}; + &tlmm { gpio-reserved-ranges = <34 2>; /* TPM LP & INT */ diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso index 46bb52c667a4..5259f4f4f857 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso @@ -130,20 +130,12 @@ ranges; bus-range = <0x5 0xff>; - pcie@0,0 { + dev@0,0 { reg = <0x50000 0x0 0x0 0x0 0x0>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges; }; - pcie@0,1 { + dev@0,1 { reg = <0x50100 0x0 0x0 0x0 0x0>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges; }; }; @@ -225,20 +217,12 @@ ranges; bus-range = <0x5 0xff>; - pcie@0,0 { + dev@0,0 { reg = <0x50000 0x0 0x0 0x0 0x0>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges; }; - pcie@0,1 { + dev@0,1 { reg = <0x50100 0x0 0x0 0x0 0x0>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dtso index b9e4a5214f70..aceafea45343 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dtso @@ -51,8 +51,8 @@ reset-gpios = <&tlmm 78 GPIO_ACTIVE_LOW>; pinctrl-names = "default", "suspend"; - pinctrl-0 = <&cam2_default>; - pinctrl-1 = <&cam2_suspend>; + pinctrl-0 = <&cam_mclk3_default>; + pinctrl-1 = <&cam_mclk3_suspend>; clocks = <&camcc CAM_CC_MCLK3_CLK>; assigned-clocks = <&camcc CAM_CC_MCLK3_CLK>; @@ -73,14 +73,7 @@ }; &tlmm { - cam2_default: cam2-default-state { - pins = "gpio67"; - function = "cam_mclk"; - drive-strength = <2>; - bias-disable; - }; - - cam2_suspend: cam2-suspend-state { + cam_mclk3_suspend: cam-mclk3-suspend-state { pins = "gpio67"; function = "cam_mclk"; drive-strength = <2>; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index a13315bf0fb0..3bb5fca8e2b1 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -954,20 +954,12 @@ ranges; bus-range = <0x5 0xff>; - pcie@0,0 { + dev@0,0 { reg = <0x50000 0x0 0x0 0x0 0x0>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges; }; - pcie@0,1 { + dev@0,1 { reg = <0x50100 0x0 0x0 0x0 0x0>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts index 31bafa2cf51d..51b59a75c1e0 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts @@ -790,20 +790,12 @@ ranges; bus-range = <0x5 0xff>; - pcie@0,0 { + dev@0,0 { reg = <0x50000 0x0 0x0 0x0 0x0>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges; }; - pcie@0,1 { + dev@0,1 { reg = <0x50100 0x0 0x0 0x0 0x0>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3-cam1-imx219.dtso b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3-cam1-imx219.dtso new file mode 100644 index 000000000000..b6d7a8235720 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3-cam1-imx219.dtso @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2026, Thundercomm All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> + +&{/} { + cam1_imx219_clk: clock-camera1-24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + leds-camera1 { + compatible = "gpio-leds"; + + pinctrl-0 = <&cam1_privacy_led_state>; + pinctrl-names = "default"; + + cam1_privacy_led: led-camera1 { + function = LED_FUNCTION_INDICATOR; + function-enumerator = <1>; + gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + /* Camera module power domain controlled through connector PWR_EN. */ + vreg_cam1_pwr: regulator-camera1-pwr { + compatible = "regulator-fixed"; + + regulator-name = "vreg_camera1_pwr"; + + gpio = <&tlmm 57 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&cam1_pwr_en>; + pinctrl-names = "default"; + + vin-supply = <&vreg_vcc3v3_output>; + }; +}; + +&camss { + vdda-phy-supply = <&vreg_l10c_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + csiphy1_ep: endpoint { + data-lanes = <0 1>; + remote-endpoint = <&cam1_imx219_ep>; + }; + }; + }; +}; + +&cci1 { + status = "okay"; +}; + +&cci1_i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + camera@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&cam1_imx219_clk>; + + VANA-supply = <&vreg_cam1_pwr>; + VDIG-supply = <&vreg_cam1_pwr>; + VDDL-supply = <&vreg_cam1_pwr>; + + leds = <&cam1_privacy_led>; + led-names = "privacy"; + + port { + cam1_imx219_ep: endpoint { + data-lanes = <1 2>; + link-frequencies = /bits/ 64 <456000000>; + remote-endpoint = <&csiphy1_ep>; + }; + }; + }; +}; + +&tlmm { + cam1_privacy_led_state: cam1-privacy-led-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + cam1_pwr_en: cam1-pwr-en-state { + pins = "gpio57"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3-cam2-imx219.dtso b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3-cam2-imx219.dtso new file mode 100644 index 000000000000..ff1ccf965df8 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3-cam2-imx219.dtso @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2026, Thundercomm All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> + +&{/} { + cam2_imx219_clk: clock-camera2-24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + leds-camera2 { + compatible = "gpio-leds"; + + pinctrl-0 = <&cam2_privacy_led_state>; + pinctrl-names = "default"; + + cam2_privacy_led: led-camera2 { + function = LED_FUNCTION_INDICATOR; + function-enumerator = <2>; + gpios = <&tlmm 19 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + /* Camera module power domain controlled through connector PWR_EN. */ + vreg_cam2_pwr: regulator-camera2-pwr { + compatible = "regulator-fixed"; + + regulator-name = "vreg_camera2_pwr"; + + gpio = <&tlmm 58 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&cam2_pwr_en>; + pinctrl-names = "default"; + + vin-supply = <&vreg_vcc3v3_output>; + }; +}; + +&camss { + vdda-phy-supply = <&vreg_l10c_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@4 { + reg = <4>; + + csiphy4_ep: endpoint { + data-lanes = <0 1>; + remote-endpoint = <&cam2_imx219_ep>; + }; + }; + }; +}; + +&cci0 { + status = "okay"; +}; + +&cci0_i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + camera@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&cam2_imx219_clk>; + + VANA-supply = <&vreg_cam2_pwr>; + VDIG-supply = <&vreg_cam2_pwr>; + VDDL-supply = <&vreg_cam2_pwr>; + + leds = <&cam2_privacy_led>; + led-names = "privacy"; + + port { + cam2_imx219_ep: endpoint { + data-lanes = <1 2>; + link-frequencies = /bits/ 64 <456000000>; + remote-endpoint = <&csiphy4_ep>; + }; + }; + }; +}; + +&tlmm { + cam2_privacy_led_state: cam2-privacy-led-state { + pins = "gpio19"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + cam2_pwr_en: cam2-pwr-en-state { + pins = "gpio58"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts index 13e8e62f6205..0f21777c480b 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts @@ -214,6 +214,22 @@ regulator-boot-on; }; + vreg_vcc3v3_output: regulator-vcc3v3-output { + compatible = "regulator-fixed"; + + regulator-name = "vcc3v3_output"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&vcc3v3_output_en>; + pinctrl-names = "default"; + + regulator-always-on; + }; + vph_pwr: regulator-vph-pwr { compatible = "regulator-fixed"; @@ -1251,6 +1267,13 @@ bias-disable; }; + vcc3v3_output_en: vcc3v3-output-en-state { + pins = "gpio14"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + wifi_reset_active: wifi-reset-active-state { pins = "gpio16"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts b/arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts index 9df8dcd6c62b..e6340f7d30dd 100644 --- a/arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts @@ -1126,20 +1126,12 @@ ranges; bus-range = <0x5 0xff>; - pci@0,0 { + dev@0,0 { reg = <0x50000 0x0 0x0 0x0 0x0>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges; }; - pci@0,1 { + dev@0,1 { reg = <0x50100 0x0 0x0 0x0 0x0>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sar2130p.dtsi b/arch/arm64/boot/dts/qcom/sar2130p.dtsi index a2d93fd68299..2ecead79806c 100644 --- a/arch/arm64/boot/dts/qcom/sar2130p.dtsi +++ b/arch/arm64/boot/dts/qcom/sar2130p.dtsi @@ -15,7 +15,6 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/mailbox/qcom-ipcc.h> #include <dt-bindings/phy/phy-qcom-qmp.h> -#include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/power/qcom,rpmhpd.h> #include <dt-bindings/soc/qcom,gpr.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index 1eea9d710d5b..f4af4f2b6827 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -493,14 +493,17 @@ }; &gpi_dma0 { + dma-channel-mask = <0x3>; status = "okay"; }; &gpi_dma1 { + dma-channel-mask = <0x3>; status = "okay"; }; &gpi_dma2 { + dma-channel-mask = <0x3>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts b/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts index adce0302d92e..da82b51cbf40 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts @@ -582,14 +582,17 @@ }; &gpi_dma0 { + dma-channel-mask = <0xb>; status = "okay"; }; &gpi_dma1 { + dma-channel-mask = <0x3>; status = "okay"; }; &gpi_dma2 { + dma-channel-mask = <0xb>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 218573a97785..52e5e239382b 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -705,14 +705,17 @@ }; &gpi_dma0 { + dma-channel-mask = <0x3>; status = "okay"; }; &gpi_dma1 { + dma-channel-mask = <0x3>; status = "okay"; }; &gpi_dma2 { + dma-channel-mask = <0x3>; status = "okay"; }; @@ -734,6 +737,7 @@ &mdss0_dp0_out { data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; remote-endpoint = <&usb_0_qmpphy_dp_in>; }; @@ -743,6 +747,7 @@ &mdss0_dp1_out { data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; remote-endpoint = <&usb_1_qmpphy_dp_in>; }; @@ -1213,6 +1218,38 @@ "VA DMIC2", "MIC BIAS3", "TX SWR_ADC1", "ADC2_OUTPUT"; + dp0-dai-link { + link-name = "DP0 Playback"; + + codec { + sound-dai = <&mdss0_dp0>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + dp1-dai-link { + link-name = "DP1 Playback"; + + codec { + sound-dai = <&mdss0_dp1>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_1>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + wcd-playback-dai-link { link-name = "WCD Playback"; cpu { diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts index 89c4ba267b07..765b029f8412 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts @@ -564,14 +564,17 @@ }; &gpi_dma0 { + dma-channel-mask = <0x3>; status = "okay"; }; &gpi_dma1 { + dma-channel-mask = <0x3>; status = "okay"; }; &gpi_dma2 { + dma-channel-mask = <0x23>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts index 4f4b5f4285ec..58e6c6ffe128 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts @@ -561,14 +561,17 @@ }; &gpi_dma0 { + dma-channel-mask = <0x3>; status = "okay"; }; &gpi_dma1 { + dma-channel-mask = <0x3>; status = "okay"; }; &gpi_dma2 { + dma-channel-mask = <0x23>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index fbcfd3883bbb..07da335bc6d3 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -885,7 +885,6 @@ <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; dma-channels = <12>; - dma-channel-mask = <0xfff>; #dma-cells = <3>; iommus = <&apps_smmu 0xb6 0x0>; @@ -1311,7 +1310,6 @@ <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; dma-channels = <13>; - dma-channel-mask = <0x1fff>; #dma-cells = <3>; iommus = <&apps_smmu 0x576 0x0>; @@ -1718,7 +1716,6 @@ <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; dma-channels = <12>; - dma-channel-mask = <0xfff>; #dma-cells = <3>; iommus = <&apps_smmu 0x96 0x0>; @@ -2910,18 +2907,21 @@ compatible = "qcom,fastrpc-compute-cb"; reg = <1>; iommus = <&apps_smmu 0x0521 0x0>; + dma-coherent; }; compute-cb@2 { compatible = "qcom,fastrpc-compute-cb"; reg = <2>; iommus = <&apps_smmu 0x0522 0x0>; + dma-coherent; }; compute-cb@3 { compatible = "qcom,fastrpc-compute-cb"; reg = <3>; iommus = <&apps_smmu 0x0523 0x0>; + dma-coherent; }; }; }; @@ -2978,18 +2978,21 @@ compatible = "qcom,fastrpc-compute-cb"; reg = <3>; iommus = <&apps_smmu 0x0c03 0x0>; + dma-coherent; }; compute-cb@4 { compatible = "qcom,fastrpc-compute-cb"; reg = <4>; iommus = <&apps_smmu 0x0c04 0x0>; + dma-coherent; }; compute-cb@5 { compatible = "qcom,fastrpc-compute-cb"; reg = <5>; iommus = <&apps_smmu 0x0c05 0x0>; + dma-coherent; }; }; @@ -6235,84 +6238,98 @@ compatible = "qcom,fastrpc-compute-cb"; reg = <1>; iommus = <&apps_smmu 0x3181 0x0420>; + dma-coherent; }; compute-cb@2 { compatible = "qcom,fastrpc-compute-cb"; reg = <2>; iommus = <&apps_smmu 0x3182 0x0420>; + dma-coherent; }; compute-cb@3 { compatible = "qcom,fastrpc-compute-cb"; reg = <3>; iommus = <&apps_smmu 0x3183 0x0420>; + dma-coherent; }; compute-cb@4 { compatible = "qcom,fastrpc-compute-cb"; reg = <4>; iommus = <&apps_smmu 0x3184 0x0420>; + dma-coherent; }; compute-cb@5 { compatible = "qcom,fastrpc-compute-cb"; reg = <5>; iommus = <&apps_smmu 0x3185 0x0420>; + dma-coherent; }; compute-cb@6 { compatible = "qcom,fastrpc-compute-cb"; reg = <6>; iommus = <&apps_smmu 0x3186 0x0420>; + dma-coherent; }; compute-cb@7 { compatible = "qcom,fastrpc-compute-cb"; reg = <7>; iommus = <&apps_smmu 0x3187 0x0420>; + dma-coherent; }; compute-cb@8 { compatible = "qcom,fastrpc-compute-cb"; reg = <8>; iommus = <&apps_smmu 0x3188 0x0420>; + dma-coherent; }; compute-cb@9 { compatible = "qcom,fastrpc-compute-cb"; reg = <9>; iommus = <&apps_smmu 0x318b 0x0420>; + dma-coherent; }; compute-cb@10 { compatible = "qcom,fastrpc-compute-cb"; reg = <10>; iommus = <&apps_smmu 0x318b 0x0420>; + dma-coherent; }; compute-cb@11 { compatible = "qcom,fastrpc-compute-cb"; reg = <11>; iommus = <&apps_smmu 0x318c 0x0420>; + dma-coherent; }; compute-cb@12 { compatible = "qcom,fastrpc-compute-cb"; reg = <12>; iommus = <&apps_smmu 0x318d 0x0420>; + dma-coherent; }; compute-cb@13 { compatible = "qcom,fastrpc-compute-cb"; reg = <13>; iommus = <&apps_smmu 0x318e 0x0420>; + dma-coherent; }; compute-cb@14 { compatible = "qcom,fastrpc-compute-cb"; reg = <14>; iommus = <&apps_smmu 0x318f 0x0420>; + dma-coherent; }; }; }; @@ -7084,7 +7101,19 @@ }; thermal-zones { - cpu0-thermal { + aoss-0-thermal { + thermal-sensors = <&tsens0 0>; + + trips { + aoss-critical { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu0-0-thermal { thermal-sensors = <&tsens0 1>; trips { @@ -7096,7 +7125,7 @@ }; }; - cpu1-thermal { + cpu1-0-thermal { thermal-sensors = <&tsens0 2>; trips { @@ -7108,7 +7137,7 @@ }; }; - cpu2-thermal { + cpu2-0-thermal { thermal-sensors = <&tsens0 3>; trips { @@ -7120,7 +7149,7 @@ }; }; - cpu3-thermal { + cpu3-0-thermal { thermal-sensors = <&tsens0 4>; trips { @@ -7132,7 +7161,7 @@ }; }; - cpu4-thermal { + cpu4-0-thermal { thermal-sensors = <&tsens0 5>; trips { @@ -7144,7 +7173,7 @@ }; }; - cpu5-thermal { + cpu5-0-thermal { thermal-sensors = <&tsens0 6>; trips { @@ -7156,7 +7185,7 @@ }; }; - cpu6-thermal { + cpu6-0-thermal { thermal-sensors = <&tsens0 7>; trips { @@ -7168,7 +7197,7 @@ }; }; - cpu7-thermal { + cpu7-0-thermal { thermal-sensors = <&tsens0 8>; trips { @@ -7180,7 +7209,7 @@ }; }; - cluster0-thermal { + cpuss0-thermal { thermal-sensors = <&tsens0 9>; trips { @@ -7192,10 +7221,262 @@ }; }; - gpu-thermal { + nsp0-0-thermal { + thermal-sensors = <&tsens0 10>; + + trips { + nsp0-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + nsp1-0-thermal { + thermal-sensors = <&tsens0 11>; + + trips { + nsp1-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + smss-0-thermal { + thermal-sensors = <&tsens0 12>; + + trips { + smss-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + camss-0-thermal { + thermal-sensors = <&tsens0 13>; + + trips { + camss-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + aoss-1-thermal { + thermal-sensors = <&tsens1 0>; + + trips { + aoss-critical { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu0-1-thermal { + thermal-sensors = <&tsens1 1>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu1-1-thermal { + thermal-sensors = <&tsens1 2>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu2-1-thermal { + thermal-sensors = <&tsens1 3>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu3-1-thermal { + thermal-sensors = <&tsens1 4>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu4-1-thermal { + thermal-sensors = <&tsens1 5>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu5-1-thermal { + thermal-sensors = <&tsens1 6>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu6-1-thermal { + thermal-sensors = <&tsens1 7>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu7-1-thermal { + thermal-sensors = <&tsens1 8>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpuss1-thermal { + thermal-sensors = <&tsens1 9>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + nsp0-2-thermal { + thermal-sensors = <&tsens1 10>; + + trips { + nsp0-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + nsp1-2-thermal { + thermal-sensors = <&tsens1 11>; + + trips { + nsp1-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + smss-1-thermal { + thermal-sensors = <&tsens1 12>; + + trips { + smss-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + camss-1-thermal { + thermal-sensors = <&tsens1 13>; + + trips { + camss-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + pcie-0-thermal { + thermal-sensors = <&tsens1 14>; + + trips { + pcie-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + ddrss-0-thermal { + thermal-sensors = <&tsens1 15>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + aoss-2-thermal { + thermal-sensors = <&tsens2 0>; + + trips { + aoss-critical { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss-0-thermal { polling-delay-passive = <250>; - thermal-sensors = <&tsens2 2>; + thermal-sensors = <&tsens2 1>; cooling-maps { map0 { @@ -7219,8 +7500,101 @@ }; }; - mem-thermal { - thermal-sensors = <&tsens1 15>; + gpuss-1-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens2 2>; + + cooling-maps { + map0 { + trip = <&gpu_alert1>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + gpu_alert1: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpuss-2-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens2 3>; + + cooling-maps { + map0 { + trip = <&gpu_alert2>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + gpu_alert2: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpuss-3-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens2 4>; + + cooling-maps { + map0 { + trip = <&gpu_alert3>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + gpu_alert3: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + pcie-1-thermal { + thermal-sensors = <&tsens2 5>; + + trips { + pcie-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + ddrss-1-thermal { + thermal-sensors = <&tsens2 6>; trips { trip-point0 { @@ -7230,6 +7604,174 @@ }; }; }; + + audio-thermal { + thermal-sensors = <&tsens2 7>; + + trips { + audio-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + video-thermal { + thermal-sensors = <&tsens2 8>; + + trips { + video-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + nsp0-1-thermal { + thermal-sensors = <&tsens2 9>; + + trips { + nsp0-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + nsp1-1-thermal { + thermal-sensors = <&tsens2 10>; + + trips { + nsp1-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + aoss-3-thermal { + thermal-sensors = <&tsens3 0>; + + trips { + aoss-critical { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss-4-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens3 1>; + + cooling-maps { + map0 { + trip = <&gpu_alert4>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + gpu_alert4: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpuss-5-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens3 2>; + + cooling-maps { + map0 { + trip = <&gpu_alert5>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + gpu_alert5: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpuss-6-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens3 3>; + + cooling-maps { + map0 { + trip = <&gpu_alert6>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + gpu_alert6: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpuss-7-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens3 4>; + + cooling-maps { + map0 { + trip = <&gpu_alert7>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + gpu_alert7: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; }; timer { diff --git a/arch/arm64/boot/dts/qcom/sdm670-google-common.dtsi b/arch/arm64/boot/dts/qcom/sdm670-google-common.dtsi index b4854801a5f5..5c2613e53679 100644 --- a/arch/arm64/boot/dts/qcom/sdm670-google-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670-google-common.dtsi @@ -490,6 +490,25 @@ firmware-name = "qcom/sdm670/sargo/a615_zap.mbn"; }; +&i2c3 { + clock-frequency = <400000>; + + status = "okay"; + + nfc@28 { + compatible = "nxp,pn557", "nxp,nxp-nci-i2c"; + reg = <0x28>; + + interrupts-extended = <&tlmm 44 IRQ_TYPE_EDGE_RISING>; + + enable-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>; + firmware-gpios = <&tlmm 43 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&nfc_default>; + pinctrl-names = "default"; + }; +}; + &i2c9 { clock-frequency = <100000>; status = "okay"; @@ -691,6 +710,29 @@ output-low; }; }; + + nfc_default: nfc-default-state { + enable-pins { + pins = "gpio12"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + firmware-pins { + pins = "gpio43"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + irq-pins { + pins = "gpio44"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; }; &usb_1_hsphy { diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi index 9e952f9862f2..f1379857e274 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi @@ -392,6 +392,8 @@ }; &i2c3 { + clock-frequency = <400000>; + status = "okay"; nfc@28 { @@ -403,7 +405,7 @@ enable-gpios = <&tlmm 25 GPIO_ACTIVE_HIGH>; firmware-gpios = <&tlmm 79 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&nfc_int_default &nfc_enable_default>; + pinctrl-0 = <&nfc_default>; pinctrl-names = "default"; }; }; @@ -476,18 +478,28 @@ gpio-reserved-ranges = < 0 4>, /* SPI (Intel MNH Pixel Visual Core) */ <81 4>; /* SPI (most likely Fingerprint Cards FPC1075) */ - nfc_int_default: nfc-int-default-state { - pins = "gpio63"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; + nfc_default: nfc-default-state { + enable-pins { + pins = "gpio25"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + irq-pins { + pins = "gpio63"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + firmware-pins { + pins = "gpio79"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; - nfc_enable_default: nfc-enable-default-state { - pins = "gpio25", "gpio79"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; }; touchscreen_reset: ts-reset-state { diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index 439779f308e3..d98e3b2f1c30 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -510,7 +510,6 @@ bq27441_fg: bq27441-battery@55 { compatible = "ti,bq27411"; - status = "okay"; reg = <0x55>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi index 4c63286d8b04..05e5a3674e5f 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi @@ -754,6 +754,8 @@ }; &uart6 { + pinctrl-0 = <&qup_uart6_4pin>; + status = "okay"; bluetooth { diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi index 85cc9c6e6f83..81292850e531 100644 --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -15,7 +15,6 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/mailbox/qcom-ipcc.h> #include <dt-bindings/power/qcom,rpmhpd.h> -#include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> / { @@ -1137,7 +1136,6 @@ interrupt-names = "periph_irq"; qcom,ee = <0>; qcom,channel = <0>; - qcom,bus-id = <0>; #address-cells = <2>; #size-cells = <0>; interrupt-controller; diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi index 8ac42ff625a0..fde7fc035bf5 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi @@ -197,7 +197,6 @@ &tlmm { gpio-reserved-ranges = <6 4>, /* Fingerprint SPI */ - <14 4>, /* eSE SPI */ <30 2>, /* NFC SPI */ <138 1>, /* NFC Secure IO */ <155 11>; /* eMMC Boot */ diff --git a/arch/arm64/boot/dts/qcom/shikra-evk.dtsi b/arch/arm64/boot/dts/qcom/shikra-evk.dtsi index 6eb4184f7642..0115fc9095b3 100644 --- a/arch/arm64/boot/dts/qcom/shikra-evk.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra-evk.dtsi @@ -3,12 +3,30 @@ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/shikra/a704_zap.mbn"; +}; + &qupv3_0 { firmware-name = "qcom/shikra/qupv3fw.elf"; status = "okay"; }; +&spi5 { + status = "okay"; + + tpm@0 { + compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi"; + reg = <0>; + spi-max-frequency = <20000000>; + }; +}; + &uart0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi b/arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi index 4ff97945274d..e119ace54e58 100644 --- a/arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi @@ -219,7 +219,6 @@ &tlmm { gpio-reserved-ranges = <6 4>, /* Fingerprint SPI */ - <14 4>, /* eSE SPI */ <30 2>, /* NFC SPI */ <138 1>, /* NFC Secure IO */ <155 11>; /* eMMC Boot */ diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 92d22e3b6931..c1f06f692f66 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -150,6 +150,88 @@ }; }; + dummy-eud { + compatible = "arm,coresight-dummy-sink"; + + label = "eud"; + + in-ports { + port { + eud_in: endpoint { + remote-endpoint = <&replicator_eud_out1>; + }; + }; + }; + }; + + etm0 { + compatible = "arm,coresight-etm4x-sysreg"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + cpu = <&cpu0>; + qcom,skip-power-up; + + out-ports { + port { + etm0_out: endpoint { + remote-endpoint = <&funnel_cpuss0_in0>; + }; + }; + }; + }; + + etm1 { + compatible = "arm,coresight-etm4x-sysreg"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + cpu = <&cpu1>; + qcom,skip-power-up; + + out-ports { + port { + etm1_out: endpoint { + remote-endpoint = <&funnel_cpuss0_in1>; + }; + }; + }; + }; + + etm2 { + compatible = "arm,coresight-etm4x-sysreg"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + cpu = <&cpu2>; + qcom,skip-power-up; + + out-ports { + port { + etm2_out: endpoint { + remote-endpoint = <&funnel_cpuss0_in2>; + }; + }; + }; + }; + + etm3 { + compatible = "arm,coresight-etm4x-sysreg"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + cpu = <&cpu3>; + qcom,skip-power-up; + + out-ports { + port { + etm3_out: endpoint { + remote-endpoint = <&funnel_cpuss0_in3>; + }; + }; + }; + }; + firmware { scm { compatible = "qcom,scm-shikra", "qcom,scm"; @@ -248,6 +330,21 @@ }; }; + modem-etm0 { + compatible = "arm,coresight-dummy-source"; + + label = "modem_etm0"; + arm,static-trace-id = <36>; + + out-ports { + port { + modem_etm0_out: endpoint { + remote-endpoint = <&funnel_in1_in4>; + }; + }; + }; + }; + pmu-a55 { compatible = "arm,cortex-a55-pmu"; interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; @@ -962,6 +1059,41 @@ #interconnect-cells = <2>; }; + cryptobam: dma-controller@1b04000 { + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg = <0x0 0x01b04000 0x0 0x24000>; + interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>; + #dma-cells = <1>; + iommus = <&apps_smmu 0x84 0x0011>, + <&apps_smmu 0x86 0x0011>, + <&apps_smmu 0x92 0x0>, + <&apps_smmu 0x94 0x0011>, + <&apps_smmu 0x96 0x0011>, + <&apps_smmu 0x98 0x0001>, + <&apps_smmu 0x9f 0x0>; + qcom,ee = <0>; + qcom,controlled-remotely; + num-channels = <16>; + qcom,num-ees = <4>; + }; + + crypto: crypto@1b3a000 { + compatible = "qcom,shikra-qce", "qcom,sm8150-qce", "qcom,qce"; + reg = <0x0 0x01b3a000 0x0 0x6000>; + dmas = <&cryptobam 4>, <&cryptobam 5>; + dma-names = "rx", "tx"; + iommus = <&apps_smmu 0x84 0x0011>, + <&apps_smmu 0x86 0x0011>, + <&apps_smmu 0x92 0x0>, + <&apps_smmu 0x94 0x0011>, + <&apps_smmu 0x96 0x0011>, + <&apps_smmu 0x98 0x0001>, + <&apps_smmu 0x9f 0x0>; + interconnects = <&system_noc MASTER_CRYPTO_CORE0 0 + &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "memory"; + }; + qfprom: efuse@1b44000 { compatible = "qcom,shikra-qfprom", "qcom,qfprom"; reg = <0x0 0x01b44000 0x0 0x3000>; @@ -1013,6 +1145,11 @@ #thermal-sensor-cells = <1>; }; + rng: rng@4454000 { + compatible = "qcom,shikra-trng", "qcom,trng"; + reg = <0x0 0x04454000 0x0 0x1000>; + }; + rpm_msg_ram: sram@45f0000 { compatible = "qcom,rpm-msg-ram", "mmio-sram"; reg = <0x0 0x045f0000 0x0 0x7000>; @@ -1074,6 +1211,7 @@ mmc-hs400-enhanced-strobe; resets = <&gcc GCC_SDCC1_BCR>; + qcom,ice = <&sdhc_ice>; status = "disabled"; @@ -1124,6 +1262,17 @@ iommus = <&apps_smmu 0xf6 0x0>; }; + sdhc_ice: crypto@4748000 { + compatible = "qcom,shikra-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg = <0x0 0x04748000 0x0 0x18000>; + clocks = <&gcc GCC_SDCC1_ICE_CORE_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&rpmpd RPMHPD_CX>; + }; + qupv3_0: geniqup@4ac0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x04ac0000 0x0 0x2000>; @@ -1992,6 +2141,104 @@ }; }; + gpu: gpu@5900000 { + compatible = "qcom,adreno-07000400", "qcom,adreno"; + reg = <0x0 0x05900000 0x0 0x40000>, + <0x0 0x0599e000 0x0 0x1000>, + <0x0 0x05961000 0x0 0x800>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH 0>; + + clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>; + clock-names = "core", + "iface", + "mem_iface", + "alt_mem_iface", + "gmu", + "xo"; + + interconnects = <&mem_noc MASTER_GRAPHICS_3D RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + interconnect-names = "gfx-mem"; + + iommus = <&adreno_smmu 0 1>; + operating-points-v2 = <&gpu_opp_table>; + power-domains = <&rpmpd RPMPD_VDDCX>; + qcom,gmu = <&gmu_wrapper>; + + #cooling-cells = <2>; + + status = "disabled"; + + gpu_zap_shader: zap-shader { + memory-region = <&gpu_micro_code_mem>; + }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-1142400000 { + opp-hz = /bits/ 64 <1142400000>; + required-opps = <&rpmpd_opp_turbo_plus>; + opp-peak-kBps = <8171875>; + }; + + opp-1017600000 { + opp-hz = /bits/ 64 <1017600000>; + required-opps = <&rpmpd_opp_turbo>; + opp-peak-kBps = <8171875>; + }; + + opp-921600000 { + opp-hz = /bits/ 64 <921600000>; + required-opps = <&rpmpd_opp_nom_plus>; + opp-peak-kBps = <7046875>; + }; + + opp-844800000 { + opp-hz = /bits/ 64 <844800000>; + required-opps = <&rpmpd_opp_nom>; + opp-peak-kBps = <6074218>; + }; + + opp-672000000 { + opp-hz = /bits/ 64 <672000000>; + required-opps = <&rpmpd_opp_svs_plus>; + opp-peak-kBps = <5285156>; + }; + + opp-537600000 { + opp-hz = /bits/ 64 <537600000>; + required-opps = <&rpmpd_opp_svs>; + opp-peak-kBps = <3972656>; + }; + + opp-355200000 { + opp-hz = /bits/ 64 <355200000>; + required-opps = <&rpmpd_opp_low_svs>; + opp-peak-kBps = <2136718>; + }; + }; + }; + + gmu_wrapper: gmu@596a000 { + compatible = "qcom,adreno-gmu-wrapper"; + reg = <0x0 0x0596a000 0x0 0x30000>; + reg-names = "gmu"; + power-domains = <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names = "cx", + "gx"; + }; + gpucc: clock-controller@5990000 { compatible = "qcom,shikra-gpucc"; reg = <0x0 0x05990000 0x0 0x9000>; @@ -2005,6 +2252,35 @@ #power-domain-cells = <1>; }; + adreno_smmu: iommu@59a0000 { + compatible = "qcom,shikra-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x059a0000 0x0 0x10000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + + interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH 0>; + + clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>; + clock-names = "hlos", + "bus", + "iface", + "ahb"; + + power-domains = <&gpucc GPU_CX_GDSC>; + }; + dispcc: clock-controller@5f00000 { compatible = "qcom,shikra-dispcc", "qcom,qcm2290-dispcc"; reg = <0x0 0x05f00000 0x0 0x20000>; @@ -2026,6 +2302,1189 @@ #power-domain-cells = <1>; }; + ctcu@8001000 { + compatible = "qcom,shikra-ctcu", "qcom,sa8775p-ctcu"; + reg = <0x0 0x08001000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb"; + + in-ports { + port { + ctcu_in0: endpoint { + remote-endpoint = <&etr0_out>; + }; + }; + }; + }; + + stm@8002000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0x0 0x08002000 0x0 0x1000>, + <0x0 0x0e280000 0x0 0x180000>; + reg-names = "stm-base", + "stm-stimulus-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + stm_out: endpoint { + remote-endpoint = <&funnel_in0_in7>; + }; + }; + }; + }; + + tpdm@8003000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x08003000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + label = "tpdm_dcc"; + qcom,cmb-element-bits = <32>; + + out-ports { + port { + tpdm_dcc_out: endpoint { + remote-endpoint = <&tpda_qdss_in0>; + }; + }; + }; + }; + + tpda@8004000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x08004000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tpda_qdss_in0: endpoint { + remote-endpoint = <&tpdm_dcc_out>; + }; + }; + + port@1 { + reg = <1>; + + tpda_qdss_in1: endpoint { + remote-endpoint = <&tpdm_spdm_out>; + }; + }; + }; + + out-ports { + port { + tpda_qdss_out: endpoint { + remote-endpoint = <&funnel_in0_in6>; + }; + }; + }; + }; + + tpdm@800f000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x0800f000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + label = "tpdm_spdm"; + qcom,cmb-element-bits = <32>; + + out-ports { + port { + tpdm_spdm_out: endpoint { + remote-endpoint = <&tpda_qdss_in1>; + }; + }; + }; + }; + + funnel@8041000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x08041000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@5 { + reg = <5>; + + funnel_in0_in5: endpoint { + remote-endpoint = <&snoc_out>; + }; + }; + + port@6 { + reg = <6>; + + funnel_in0_in6: endpoint { + remote-endpoint = <&tpda_qdss_out>; + }; + }; + + port@7 { + reg = <7>; + + funnel_in0_in7: endpoint { + remote-endpoint = <&stm_out>; + }; + }; + }; + + out-ports { + port { + funnel_in0_out: endpoint { + remote-endpoint = <&funnel_merg_in0>; + }; + }; + }; + }; + + funnel@8042000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x08042000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + funnel_in1_in1: endpoint { + remote-endpoint = <&tpda_aodbg_out>; + }; + }; + + port@4 { + reg = <4>; + + funnel_in1_in4: endpoint { + remote-endpoint = <&modem_etm0_out>; + }; + }; + + port@6 { + reg = <6>; + + funnel_in1_in6: endpoint { + remote-endpoint = <&funnel_cpuss1_out>; + }; + }; + + port@7 { + reg = <7>; + + funnel_in1_in7: endpoint { + remote-endpoint = <&funnel_center_out>; + }; + }; + }; + + out-ports { + port { + funnel_in1_out: endpoint { + remote-endpoint = <&funnel_merg_in1>; + }; + }; + }; + }; + + funnel@8045000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x08045000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + funnel_merg_in0: endpoint { + remote-endpoint = <&funnel_in0_out>; + }; + }; + + port@1 { + reg = <1>; + + funnel_merg_in1: endpoint { + remote-endpoint = <&funnel_in1_out>; + }; + }; + }; + + out-ports { + port { + funnel_merg_out: endpoint { + remote-endpoint = <&tmc_etf_in>; + }; + }; + }; + }; + + replicator@8046000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x0 0x08046000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + in-ports { + port { + replicator_qdss_in: endpoint { + remote-endpoint = <&tmc_etf_out>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + replicator_qdss_out0: endpoint { + remote-endpoint = <&etr0_in>; + }; + }; + + port@1 { + reg = <1>; + + replicator_qdss_out1: endpoint { + remote-endpoint = <&replicator_eud_in>; + }; + }; + }; + }; + + tmc@8047000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x08047000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + in-ports { + port { + tmc_etf_in: endpoint { + remote-endpoint = <&funnel_merg_out>; + }; + }; + }; + + out-ports { + port { + tmc_etf_out: endpoint { + remote-endpoint = <&replicator_qdss_in>; + }; + }; + }; + }; + + tmc@8048000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x08048000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + iommus = <&apps_smmu 0x0160 0x0>; + arm,scatter-gather; + + in-ports { + port { + etr0_in: endpoint { + remote-endpoint = <&replicator_qdss_out0>; + }; + }; + }; + + out-ports { + port { + etr0_out: endpoint { + remote-endpoint = <&ctcu_in0>; + }; + }; + }; + }; + + replicator@804a000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x0 0x0804a000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + in-ports { + port { + replicator_eud_in: endpoint { + remote-endpoint = <&replicator_qdss_out1>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + replicator_eud_out1: endpoint { + remote-endpoint = <&eud_in>; + }; + }; + }; + }; + + tpdm@8800000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x08800000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + label = "tpdm_cdsp"; + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <4>; + + out-ports { + port { + tpdm_cdsp_out: endpoint { + remote-endpoint = <&funnel_cdsp_in0>; + }; + }; + }; + }; + + funnel@8801000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x08801000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + in-ports { + port { + funnel_cdsp_in0: endpoint { + remote-endpoint = <&tpdm_cdsp_out>; + }; + }; + }; + + out-ports { + port { + funnel_cdsp_out0: endpoint { + remote-endpoint = <&tpda_center_in3>; + }; + }; + }; + }; + + cti@8807000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x08807000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + label = "cti_turing_q6"; + }; + + cti@8833000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x08833000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + label = "cti_mss_q6"; + }; + + tpdm@8840000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x08840000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + label = "tpdm_vsense"; + qcom,cmb-element-bits = <32>; + + out-ports { + port { + tpdm_vsense_out: endpoint { + remote-endpoint = <&tpda_center_in6>; + }; + }; + }; + }; + + tpdm@8844000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x08844000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + label = "tpdm_dlct_1"; + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_dlct_1_out: endpoint { + remote-endpoint = <&tpda_center_in13>; + }; + }; + }; + }; + + tpda@8845000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x08845000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tpda_center_in0: endpoint { + remote-endpoint = <&funnel_mcu_out>; + }; + }; + + port@2 { + reg = <2>; + + tpda_center_in2: endpoint { + remote-endpoint = <&tpdm_dlct_out>; + }; + }; + + port@3 { + reg = <3>; + + tpda_center_in3: endpoint { + remote-endpoint = <&funnel_cdsp_out0>; + }; + }; + + port@4 { + reg = <4>; + + tpda_center_in4: endpoint { + remote-endpoint = <&funnel_ddr_out0>; + }; + }; + + port@6 { + reg = <6>; + + tpda_center_in6: endpoint { + remote-endpoint = <&tpdm_vsense_out>; + }; + }; + + port@7 { + reg = <7>; + + tpda_center_in7: endpoint { + remote-endpoint = <&tpdm_prng_out>; + }; + }; + + port@8 { + reg = <8>; + + tpda_center_in8: endpoint { + remote-endpoint = <&tpdm_west_out>; + }; + }; + + port@9 { + reg = <9>; + + tpda_center_in9: endpoint { + remote-endpoint = <&tpdm_qm_out>; + }; + }; + + port@a { + reg = <0xa>; + + tpda_center_in10: endpoint { + remote-endpoint = <&tpdm_pimem_out>; + }; + }; + + port@d { + reg = <0xd>; + + tpda_center_in13: endpoint { + remote-endpoint = <&tpdm_dlct_1_out>; + }; + }; + }; + + out-ports { + port { + tpda_center_out: endpoint { + remote-endpoint = <&funnel_center_in0>; + }; + }; + }; + }; + + funnel@8846000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x08846000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + in-ports { + port { + funnel_center_in0: endpoint { + remote-endpoint = <&tpda_center_out>; + }; + }; + }; + + out-ports { + port { + funnel_center_out: endpoint { + remote-endpoint = <&funnel_in1_in7>; + }; + }; + }; + }; + + tpdm@884c000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x0884c000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + label = "tpdm_prng"; + qcom,cmb-element-bits = <32>; + + out-ports { + port { + tpdm_prng_out: endpoint { + remote-endpoint = <&tpda_center_in7>; + }; + }; + }; + }; + + tpdm@8850000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x08850000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + label = "tpdm_pimem"; + qcom,cmb-element-bits = <64>; + qcom,dsb-element-bits = <32>; + + out-ports { + port { + tpdm_pimem_out: endpoint { + remote-endpoint = <&tpda_center_in10>; + }; + }; + }; + }; + + tpdm@8980000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x08980000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + label = "tpdm_mcu"; + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <16>; + + out-ports { + port { + tpdm_mcu_out: endpoint { + remote-endpoint = <&funnel_mcu_in0>; + }; + }; + }; + }; + + funnel@8982000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x08982000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + in-ports { + port { + funnel_mcu_in0: endpoint { + remote-endpoint = <&tpdm_mcu_out>; + }; + }; + }; + + out-ports { + port { + funnel_mcu_out: endpoint { + remote-endpoint = <&tpda_center_in0>; + }; + }; + }; + }; + + tpdm@89d0000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x089d0000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + label = "tpdm_qm"; + qcom,dsb-element-bits = <32>; + + out-ports { + port { + tpdm_qm_out: endpoint { + remote-endpoint = <&tpda_center_in9>; + }; + }; + }; + }; + + tpdm@8a01000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x08a01000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + label = "tpdm_mapss"; + qcom,cmb-element-bits = <32>; + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <16>; + + out-ports { + port { + tpdm_mapss_out: endpoint { + remote-endpoint = <&tpda_aodbg_in>; + }; + }; + }; + }; + + cti@8a02000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x08a02000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + label = "cti_mapss"; + }; + + tpda@8a04000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x08a04000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + in-ports { + port { + tpda_aodbg_in: endpoint { + remote-endpoint = <&tpdm_mapss_out>; + }; + }; + }; + + out-ports { + port { + tpda_aodbg_out: endpoint { + remote-endpoint = <&funnel_in1_in1>; + }; + }; + }; + }; + + tpdm@8a58000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x08a58000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + label = "tpdm_west"; + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <16>; + + out-ports { + port { + tpdm_west_out: endpoint { + remote-endpoint = <&tpda_center_in8>; + }; + }; + }; + }; + + cti@8b30000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x08b30000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + label = "cti_cortex_m3"; + }; + + tpdm@8b58000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x08b58000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + label = "tpdm_dlct"; + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <16>; + + out-ports { + port { + tpdm_dlct_out: endpoint { + remote-endpoint = <&tpda_center_in2>; + }; + }; + }; + }; + + cti@8b59000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x08b59000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + label = "cti_dlct_0"; + }; + + cti@8b5a000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x08b5a000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + label = "cti_dlct_1"; + }; + + cti@8b5b000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x08b5b000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + label = "cti_dlct_2"; + }; + + cti@8b5c000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x08b5c000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + label = "cti_dlct_3"; + }; + + tpdm@8b60000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x08b60000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + label = "tpdm_ddr"; + qcom,cmb-element-bits = <32>; + qcom,cmb-msrs-num = <1>; + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_ddr_out: endpoint { + remote-endpoint = <&funnel_ddr_in0>; + }; + }; + }; + }; + + cti@8b62000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x08b62000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + label = "cti_ddr_dl_0"; + }; + + funnel@8b65000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x08b65000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + funnel_ddr_in0: endpoint { + remote-endpoint = <&tpdm_ddr_out>; + }; + }; + }; + + out-ports { + port { + funnel_ddr_out0: endpoint { + remote-endpoint = <&tpda_center_in4>; + }; + }; + }; + }; + + cti@8b70000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x08b70000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + label = "cti_ddr_dl_0_1"; + }; + + cti@8b71000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x08b71000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + label = "cti_ddr_dl_1_1"; + }; + + cti@9020000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x09020000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + label = "cti_apss_pe0"; + }; + + cti@90e0000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x090e0000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + label = "cti_apss_cluster"; + }; + + cti@9120000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x09120000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + label = "cti_apss_pe1"; + }; + + cti@9220000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x09220000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + label = "cti_apss_pe2"; + }; + + cti@9320000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x09320000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + label = "cti_apss_pe3"; + }; + + funnel@9800000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x09800000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + funnel_cpuss0_in0: endpoint { + remote-endpoint = <&etm0_out>; + }; + }; + + port@1 { + reg = <1>; + + funnel_cpuss0_in1: endpoint { + remote-endpoint = <&etm1_out>; + }; + }; + + port@2 { + reg = <2>; + + funnel_cpuss0_in2: endpoint { + remote-endpoint = <&etm2_out>; + }; + }; + + port@3 { + reg = <3>; + + funnel_cpuss0_in3: endpoint { + remote-endpoint = <&etm3_out>; + }; + }; + }; + + out-ports { + port { + funnel_cpuss0_out: endpoint { + remote-endpoint = <&funnel_cpuss1_in0>; + }; + }; + }; + }; + + funnel@9810000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x09810000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + funnel_cpuss1_in0: endpoint { + remote-endpoint = <&funnel_cpuss0_out>; + }; + }; + + port@3 { + reg = <3>; + + funnel_cpuss1_in3: endpoint { + remote-endpoint = <&tpda_apss_out>; + }; + }; + }; + + out-ports { + port { + funnel_cpuss1_out: endpoint { + remote-endpoint = <&funnel_in1_in6>; + }; + }; + }; + }; + + cti@982b000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x0982b000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + label = "cti_riscv"; + }; + + tpdm@9860000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x09860000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + label = "tpdm_actpm"; + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <1>; + + out-ports { + port { + tpdm_actpm_out: endpoint { + remote-endpoint = <&tpda_apss_in2>; + }; + }; + }; + }; + + tpdm@9861000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x09861000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + label = "tpdm_hwe"; + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_hwe_out: endpoint { + remote-endpoint = <&tpda_apss_in3>; + }; + }; + }; + }; + + tpda@9863000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x09863000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tpda_apss_in0: endpoint { + remote-endpoint = <&tpdm_llm_silver_out>; + }; + }; + + port@2 { + reg = <2>; + + tpda_apss_in2: endpoint { + remote-endpoint = <&tpdm_actpm_out>; + }; + }; + + port@3 { + reg = <3>; + + tpda_apss_in3: endpoint { + remote-endpoint = <&tpdm_hwe_out>; + }; + }; + }; + + out-ports { + port { + tpda_apss_out: endpoint { + remote-endpoint = <&funnel_cpuss1_in3>; + }; + }; + }; + }; + + tpdm@98a0000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x098a0000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + label = "tpdm_llm_silver"; + qcom,cmb-element-bits = <32>; + qcom,cmb-msrs-num = <12>; + + out-ports { + port { + tpdm_llm_silver_out: endpoint { + remote-endpoint = <&tpda_apss_in0>; + }; + }; + }; + }; + + cti@98e0000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x098e0000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + label = "cti_apss_0"; + }; + + cti@98f0000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x098f0000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + label = "cti_apss_1"; + }; + + cti@9900000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x09900000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + label = "cti_apss_2"; + }; + sram@c11e000 { compatible = "qcom,shikra-imem", "mmio-sram"; reg = <0x0 0x0c11e000 0x0 0x1000>; @@ -2377,6 +3836,7 @@ }; gpuss-thermal { + polling-delay-passive = <10>; thermal-sensors = <&tsens0 6>; trips { @@ -2386,12 +3846,25 @@ type = "hot"; }; - gpuss-critical { + gpuss_alert0: gpuss-alert0 { temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + gpuss-critical { + temperature = <120000>; hysteresis = <0>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&gpuss_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; nsp-thermal { @@ -2521,6 +3994,21 @@ }; }; + snoc { + compatible = "arm,coresight-dummy-source"; + + label = "snoc"; + arm,static-trace-id = <18>; + + out-ports { + port { + snoc_out: endpoint { + remote-endpoint = <&funnel_in0_in5>; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi index b7dc40f3778c..bc9c788b92b1 100644 --- a/arch/arm64/boot/dts/qcom/sm4450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi @@ -11,7 +11,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/qcom,rpmhpd.h> -#include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> / { diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts index 5d20ad93b0c5..773304b4759e 100644 --- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts @@ -992,6 +992,10 @@ }; }; +&pmk8350_pon { + status = "disabled"; +}; + &pmk8350_rtc { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts b/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts index 7db9ae1c3cef..8d8fef940264 100644 --- a/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts +++ b/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts @@ -1455,5 +1455,7 @@ }; &wifi { + qcom,calibration-variant = "Nothing_Spacewar"; + status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 90f8b091634e..8483a1bc56f4 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -16,7 +16,6 @@ #include <dt-bindings/interconnect/qcom,sm8250.h> #include <dt-bindings/mailbox/qcom-ipcc.h> #include <dt-bindings/phy/phy-qcom-qmp.h> -#include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/power/qcom,rpmhpd.h> #include <dt-bindings/soc/qcom,apr.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> diff --git a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi index 4b62ee50da7b..969c8cb31df9 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi @@ -893,9 +893,20 @@ }; }; -/* BIG WARNING! DO NOT TOUCH UFS, YOUR DEVICE WILL DIE! */ -&ufs_mem_hc { status = "disabled"; }; -&ufs_mem_phy { status = "disabled"; }; +&ufs_mem_hc { + status = "okay"; + reset-gpios = <&tlmm 203 GPIO_ACTIVE_LOW>; + vcc-supply = <&pm8350_l7>; + vcc-max-microamp = <800000>; + vccq-supply = <&pm8350_l9>; + vcc-max-microamp = <900000>; +}; + +&ufs_mem_phy { + status = "okay"; + vdda-phy-supply = <&pm8350_l5>; + vdda-pll-supply = <&pm8350_l6>; +}; &usb_1 { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 32b47f5ec1f6..100faea925a3 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -18,7 +18,6 @@ #include <dt-bindings/interconnect/qcom,sm8350.h> #include <dt-bindings/mailbox/qcom-ipcc.h> #include <dt-bindings/phy/phy-qcom-qmp.h> -#include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/power/qcom,rpmhpd.h> #include <dt-bindings/reset/qcom,sm8350-videocc.h> #include <dt-bindings/soc/qcom,apr.h> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index b8793482b181..484ec8ec8c10 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -17,7 +17,6 @@ #include <dt-bindings/mailbox/qcom-ipcc.h> #include <dt-bindings/phy/phy-qcom-qmp.h> #include <dt-bindings/power/qcom,rpmhpd.h> -#include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/interconnect/qcom,icc.h> #include <dt-bindings/interconnect/qcom,sm8450.h> #include <dt-bindings/reset/qcom,sm8450-gpucc.h> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 0e701e709235..23604436add3 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -19,7 +19,6 @@ #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h> #include <dt-bindings/interconnect/qcom,osm-l3.h> #include <dt-bindings/mailbox/qcom-ipcc.h> -#include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/power/qcom,rpmhpd.h> #include <dt-bindings/soc/qcom,gpr.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> @@ -4692,7 +4691,6 @@ interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; qcom,ee = <0>; qcom,channel = <0>; - qcom,bus-id = <0>; #address-cells = <2>; #size-cells = <0>; interrupt-controller; diff --git a/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts b/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts index 6ddf30ecabfe..00a56385dc0d 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts @@ -221,7 +221,7 @@ }; sound { - compatible = "qcom,sm8650-sndcard", "qcom,sm8450-sndcard"; + compatible = "ayaneo,pocket-s2-sndcard"; model = "SM8650-APS2"; audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT", "SpkrRight IN", "WSA_SPK2 OUT", @@ -325,6 +325,23 @@ }; }; + sy7758_vdd33_reg: sy7758-vdd33-regulator { + compatible = "regulator-fixed"; + + regulator-name = "sy7758_vdd33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + + gpios = <&tlmm 163 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vph_pwr>; + + pinctrl-0 = <&sy7758_vdd33>; + pinctrl-names = "default"; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; @@ -986,6 +1003,10 @@ }; }; +&gpu { + status = "okay"; +}; + &i2c3 { clock-frequency = <100000>; @@ -1016,6 +1037,30 @@ }; }; +&i2c4 { + clock-frequency = <400000>; + + status = "okay"; + + touchscreen@5d { + compatible = "goodix,gt911"; + reg = <0x5d>; + + interrupt-parent = <&tlmm>; + interrupts = <162 IRQ_TYPE_EDGE_FALLING>; + + reset-gpios = <&tlmm 161 GPIO_ACTIVE_HIGH>; + VDDIO-supply = <&vreg_l14b_3p2>; + AVDD28-supply = <&vreg_l14b_3p2>; + + touchscreen-size-x = <1440>; + touchscreen-size-y = <2560>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts_reset_default>, <&ts_irq_default>; + }; +}; + &i2c6 { clock-frequency = <100000>; @@ -1053,6 +1098,51 @@ }; }; +&i2c9 { + status = "okay"; + + /* Screen power */ + regulator@3e { + compatible = "sgmicro,sgm3804"; + reg = <0x3e>; + + pinctrl-0 = <&sgm3804_default>; + pinctrl-names = "default"; + + vin-supply = <&vph_pwr>; + + sgm3804_pos: pos { + regulator-name = "panel-avdd-pos"; + regulator-min-microvolt = <5200000>; + regulator-max-microvolt = <5200000>; + regulator-active-discharge = <1>; + regulator-boot-on; + enable-gpios = <&tlmm 59 GPIO_ACTIVE_HIGH>; + }; + + sgm3804_neg: neg { + regulator-name = "panel-avdd-neg"; + regulator-min-microvolt = <5200000>; + regulator-max-microvolt = <5200000>; + regulator-active-discharge = <1>; + regulator-boot-on; + enable-gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>; + }; + }; + + /* Backlight */ + backlight: backlight@2e { + compatible = "silergy,sy7758"; + reg = <0x2e>; + + pinctrl-0 = <&sy7758_default>; + pinctrl-names = "default"; + + vdd-supply = <&sy7758_vdd33_reg>; + enable-gpios = <&tlmm 164 GPIO_ACTIVE_HIGH>; + }; +}; + &iris { status = "okay"; }; @@ -1073,6 +1163,93 @@ status = "okay"; }; +&mdss_dsi0 { + vdda-supply = <&vreg_l3i_1p2>; + + qcom,master-dsi; + qcom,dual-dsi-mode; + qcom,sync-dual-dsi; + + status = "okay"; + + panel@0 { + status = "okay"; + compatible = "ayaneo,wt0630-2k", "renesas,r63419"; + reg = <0>; + + pinctrl-0 = <&disp0_reset_n_active>; + pinctrl-1 = <&disp0_reset_n_suspend>; + pinctrl-names = "default", "sleep"; + + vddio-supply = <&vreg_l12b_1p8>; + vdd-supply = <&vreg_l11b_1p2>; + vsp-supply = <&sgm3804_pos>; + vsn-supply = <&sgm3804_neg>; + vci-supply = <&vreg_l13b_3p0>; + + backlight = <&backlight>; + + reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>; + + rotation = <90>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel0_in_0: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@1{ + reg = <1>; + panel0_in_1: endpoint { + remote-endpoint = <&mdss_dsi1_out>; + }; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel0_in_0>; + + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l1i_0p88>; + + status = "okay"; +}; + +&mdss_dsi1 { + vdda-supply = <&vreg_l3i_1p2>; + + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; + + qcom,dual-dsi-mode; + qcom,sync-dual-dsi; + + status = "okay"; +}; + +&mdss_dsi1_out { + remote-endpoint = <&panel0_in_1>; + + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi1_phy { + vdds-supply = <&vreg_l1i_0p88>; + + status = "okay"; +}; + &pcie0 { wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; @@ -1390,6 +1567,20 @@ }; }; + disp0_reset_n_active: disp0-reset-n-active-state { + pins = "gpio133"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + disp0_reset_n_suspend: disp0-reset-n-suspend-state { + pins = "gpio133"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + fan_pwr_pins: fan-pwr-state { pins = "gpio125"; function = "gpio"; @@ -1440,6 +1631,13 @@ output-high; }; + sgm3804_default: sgm3804-default-state { + pins = "gpio58", "gpio59"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + spkr_23_sd_n_active: spkr-23-sd-n-active-state { pins = "gpio77"; function = "gpio"; @@ -1454,6 +1652,34 @@ bias-disable; }; + sy7758_default: sy7758-default-state { + pins = "gpio164"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + sy7758_vdd33: sy7758-vdd33-state { + pins = "gpio163"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + ts_irq_default: ts-irq-active-state { + pins = "gpio162"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + ts_reset_default: ts-reset-active-state { + pins = "gpio161"; + function = "gpio"; + drive-strength = <8>; + bias-pull-down; + }; + wcd_default: wcd-reset-n-active-state { pins = "gpio107"; function = "gpio"; @@ -1549,3 +1775,7 @@ &xo_board { clock-frequency = <76800000>; }; + +&gpu_zap_shader { + firmware-name = "qcom/sm8650/ayaneo/ps2/gen70900_zap.mbn"; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index b679fd8afb7d..99509305f970 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -21,7 +21,6 @@ #include <dt-bindings/mailbox/qcom-ipcc.h> #include <dt-bindings/phy/phy-qcom-qmp.h> #include <dt-bindings/power/qcom,rpmhpd.h> -#include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/reset/qcom,sm8650-gpucc.h> #include <dt-bindings/soc/qcom,gpr.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> @@ -6154,7 +6153,6 @@ qcom,ee = <0>; qcom,channel = <0>; - qcom,bus-id = <0>; interrupt-controller; #interrupt-cells = <4>; diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index dd738d13df8e..28cf22da854d 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -5,10 +5,12 @@ #include <dt-bindings/clock/qcom,dsi-phy-28nm.h> #include <dt-bindings/clock/qcom,rpmh.h> +#include <dt-bindings/clock/qcom,kaanapali-gxclkctl.h> #include <dt-bindings/clock/qcom,sm8750-cambistmclkcc.h> #include <dt-bindings/clock/qcom,sm8750-camcc.h> #include <dt-bindings/clock/qcom,sm8750-dispcc.h> #include <dt-bindings/clock/qcom,sm8750-gcc.h> +#include <dt-bindings/clock/qcom,sm8750-gpucc.h> #include <dt-bindings/clock/qcom,sm8750-tcsr.h> #include <dt-bindings/clock/qcom,sm8750-videocc.h> #include <dt-bindings/dma/qcom-gpi.h> @@ -20,7 +22,6 @@ #include <dt-bindings/mailbox/qcom-ipcc.h> #include <dt-bindings/phy/phy-qcom-qmp.h> #include <dt-bindings/power/qcom,rpmhpd.h> -#include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/soc/qcom,gpr.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> @@ -2180,6 +2181,72 @@ #hwlock-cells = <1>; }; + gxclkctl: clock-controller@3d64000 { + compatible = "qcom,sm8750-gxclkctl"; + reg = <0x0 0x03d64000 0x0 0x6000>; + + power-domains = <&rpmhpd RPMHPD_GFX>, + <&rpmhpd RPMHPD_GMXC>, + <&gpucc GPU_CC_CX_GDSC>; + + #power-domain-cells = <1>; + }; + + gpucc: clock-controller@3d90000 { + compatible = "qcom,sm8750-gpucc"; + reg = <0x0 0x03d90000 0x0 0x9800>; + + clocks = <&bi_tcxo_div2>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + + power-domains = <&rpmhpd RPMHPD_MX>, + <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + adreno_smmu: iommu@3da0000 { + compatible = "qcom,sm8750-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x03da0000 0x0 0x40000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + clock-names = "hlos"; + power-domains = <&gpucc GPU_CC_CX_GDSC>; + dma-coherent; + }; + remoteproc_mpss: remoteproc@4080000 { compatible = "qcom,sm8750-mpss-pas"; reg = <0x0 0x04080000 0x0 0x10000>; @@ -3609,7 +3676,6 @@ qcom,ee = <0>; qcom,channel = <0>; - qcom,bus-id = <0>; interrupt-controller; #interrupt-cells = <4>; diff --git a/arch/arm64/boot/dts/qcom/talos-evk-rpi-display-2-5in.dtso b/arch/arm64/boot/dts/qcom/talos-evk-rpi-display-2-5in.dtso new file mode 100644 index 000000000000..e49da096d9e3 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/talos-evk-rpi-display-2-5in.dtso @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> + +&{/} { + display_bl: backlight { + compatible = "pwm-backlight"; + pwms = <&mcu 0 255 0>; + }; + + reg_display: regulator-display { + compatible = "regulator-fixed"; + regulator-name = "rpi-display"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_dsi_touch: regulator-dsi-touch { + compatible = "regulator-fixed"; + gpio = <&mcu 1 GPIO_ACTIVE_HIGH>; + regulator-name = "rpi-touch"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <50000>; + enable-active-high; + }; +}; + +&hdmi_bridge { + status = "disabled"; +}; + +&i2c1 { + clock-frequency = <400000>; + + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + mcu: gpio@45 { + compatible = "raspberrypi,touchscreen-panel-regulator-v2"; + reg = <0x45>; + gpio-controller; + #gpio-cells = <2>; + #pwm-cells = <3>; + }; + + touchscreen@5d { + compatible = "goodix,gt911"; + reg = <0x5d>; + AVDD28-supply = <®_dsi_touch>; + touchscreen-size-x = <720>; + touchscreen-size-y = <1280>; + }; +}; + +&mdss_dsi0 { + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + panel: panel@0 { + compatible = "raspberrypi,dsi-5inch", "ilitek,ili9881c"; + reg = <0>; + + backlight = <&display_bl>; + power-supply = <®_display>; + reset-gpios = <&mcu 0 GPIO_ACTIVE_LOW>; + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel_in>; + data-lanes = <0 1>; +}; diff --git a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi index a31bed7fad07..bd7f1642f5ee 100644 --- a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi +++ b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi @@ -411,10 +411,14 @@ }; &qupv3_id_0 { + firmware-name = "qcom/qcs615/qupv3fw.elf"; + status = "okay"; }; &qupv3_id_1 { + firmware-name = "qcom/qcs615/qupv3fw.elf"; + status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index eedfdce3c479..531cf41b94dc 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -17,7 +17,6 @@ #include <dt-bindings/interconnect/qcom,qcs615-rpmh.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/phy/phy-qcom-qmp.h> -#include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/power/qcom,rpmhpd.h> #include <dt-bindings/soc/qcom,gpr.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> diff --git a/arch/arm64/boot/dts/qcom/x1-asus-vivobook-s15.dtsi b/arch/arm64/boot/dts/qcom/x1-asus-vivobook-s15.dtsi index 0dc7c1b5a14a..6bf12d8f0431 100644 --- a/arch/arm64/boot/dts/qcom/x1-asus-vivobook-s15.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-asus-vivobook-s15.dtsi @@ -1036,6 +1036,27 @@ vdd3-supply = <&vreg_l14b_3p0>; }; +&tcsr { + vdda-qrefrpt0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrpt1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrpt4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qrefrx0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrx1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrx4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qreftx0-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx0-1p2-supply = <&vreg_l2j_1p2>; + vdda-qreftx1-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx1-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen0-0p9-supply = <&vreg_l3i_0p8>; + vdda-refgen0-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen2-0p9-supply = <&vreg_l3j_0p8>; + vdda-refgen2-1p2-supply = <&vreg_l2j_1p2>; +}; + &tlmm { gpio-reserved-ranges = <34 2>, /* Unused */ <44 4>, /* SPI (TPM) */ diff --git a/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi b/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi index 59cbbfbce490..7b1486469730 100644 --- a/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi @@ -1272,6 +1272,27 @@ }; }; +&tcsr { + vdda-qrefrpt0-0p9-supply = <&vreg_l3c_0p9>; + vdda-qrefrpt1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrpt4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qrefrx0-0p9-supply = <&vreg_l3c_0p9>; + vdda-qrefrx1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrx4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qreftx0-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx0-1p2-supply = <&vreg_l2j_1p2>; + vdda-qreftx1-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx1-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen0-0p9-supply = <&vreg_l3i_0p8>; + vdda-refgen0-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen2-0p9-supply = <&vreg_l3j_0p8>; + vdda-refgen2-1p2-supply = <&vreg_l2j_1p2>; +}; + &tlmm { gpio-reserved-ranges = <44 4>, /* SPI11, TZ Protected */ <90 1>; /* Unknown, TZ Protected */ diff --git a/arch/arm64/boot/dts/qcom/x1-crd.dtsi b/arch/arm64/boot/dts/qcom/x1-crd.dtsi index 60db83b8985f..ef9c8836c33a 100644 --- a/arch/arm64/boot/dts/qcom/x1-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-crd.dtsi @@ -1528,6 +1528,27 @@ }; }; +&tcsr { + vdda-qrefrpt0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrpt1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrpt4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qrefrx0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrx1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrx4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qreftx0-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx0-1p2-supply = <&vreg_l2j_1p2>; + vdda-qreftx1-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx1-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen0-0p9-supply = <&vreg_l3i_0p8>; + vdda-refgen0-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen2-0p9-supply = <&vreg_l3j_0p8>; + vdda-refgen2-1p2-supply = <&vreg_l2j_1p2>; +}; + &tlmm { gpio-reserved-ranges = <34 2>, /* Unused */ <44 4>, /* SPI (TPM) */ diff --git a/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi b/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi index 4cda708455d8..2ebb42906c9b 100644 --- a/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi @@ -1301,6 +1301,27 @@ }; }; +&tcsr { + vdda-qrefrpt0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrpt1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrpt4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qrefrx0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrx1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrx4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qreftx0-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx0-1p2-supply = <&vreg_l2j_1p2>; + vdda-qreftx1-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx1-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen0-0p9-supply = <&vreg_l3i_0p8>; + vdda-refgen0-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen2-0p9-supply = <&vreg_l3j_0p8>; + vdda-refgen2-1p2-supply = <&vreg_l2j_1p2>; +}; + &tlmm { gpio-reserved-ranges = <44 4>, /* SPI11 (TPM) */ <76 4>, /* SPI19 (TZ Protected) */ diff --git a/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi b/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi index dba8cee43e29..6b4b17acc069 100644 --- a/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi @@ -1284,6 +1284,27 @@ }; }; +&tcsr { + vdda-qrefrpt0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrpt1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrpt4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qrefrx0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrx1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrx4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qreftx0-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx0-1p2-supply = <&vreg_l2j_1p2>; + vdda-qreftx1-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx1-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen0-0p9-supply = <&vreg_l3i_0p8>; + vdda-refgen0-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen2-0p9-supply = <&vreg_l3j_0p8>; + vdda-refgen2-1p2-supply = <&vreg_l2j_1p2>; +}; + &tlmm { gpio-reserved-ranges = <34 2>, /* Unused */ <44 4>, /* SPI (TPM) */ diff --git a/arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi b/arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi index ce7d958ca687..1e5a3a9323a6 100644 --- a/arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi @@ -20,9 +20,27 @@ gpio-keys { compatible = "gpio-keys"; - pinctrl-0 = <&hall_int_n_default>; + pinctrl-0 = <&vol_down_n>, <&vol_up_n>, <&hall_int_n_default>; pinctrl-names = "default"; + key-vol-down { + debounce-interval = <15>; + gpios = <&pm8550_gpios 8 GPIO_ACTIVE_LOW>; + label = "Volume Down"; + linux,can-disable; + linux,code = <KEY_VOLUMEDOWN>; + wakeup-source; + }; + + key-vol-up { + debounce-interval = <15>; + gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>; + label = "Volume Up"; + linux,can-disable; + linux,code = <KEY_VOLUMEUP>; + wakeup-source; + }; + switch-lid { gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; linux,input-type = <EV_SW>; @@ -314,6 +332,38 @@ "VA DMIC0", "vdd-micb", "VA DMIC1", "vdd-micb"; + displayport-0-dai-link { + link-name = "DisplayPort0 Playback"; + + codec { + sound-dai = <&mdss_dp0>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + displayport-1-dai-link { + link-name = "DisplayPort1 Playback"; + + codec { + sound-dai = <&mdss_dp1>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_1>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + wsa-dai-link { link-name = "WSA Playback"; @@ -984,6 +1034,22 @@ }; &pm8550_gpios { + vol_up_n: vol-up-n-state { + pins = "gpio6"; + function = "normal"; + bias-pull-up; + input-enable; + power-source = <1>; /* 1.8V */ + }; + + vol_down_n: vol-down-n-state { + pins = "gpio8"; + function = "normal"; + bias-pull-up; + input-enable; + power-source = <1>; /* 1.8V */ + }; + rtmr0_default: rtmr0-reset-n-active-state { pins = "gpio10"; function = "normal"; @@ -1107,6 +1173,27 @@ }; }; +&tcsr { + vdda-qrefrpt0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrpt1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrpt4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qrefrx0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrx1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrx4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qreftx0-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx0-1p2-supply = <&vreg_l2j_1p2>; + vdda-qreftx1-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx1-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen0-0p9-supply = <&vreg_l3i_0p8>; + vdda-refgen0-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen2-0p9-supply = <&vreg_l3j_0p8>; + vdda-refgen2-1p2-supply = <&vreg_l2j_1p2>; +}; + &tlmm { gpio-reserved-ranges = <44 4>, /* SPI (TPM) */ <238 1>; /* UFS Reset */ diff --git a/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts b/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts index be1a8ac8c699..21303340a530 100644 --- a/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts +++ b/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts @@ -1193,6 +1193,27 @@ }; }; +&tcsr { + vdda-qrefrpt0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrpt1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrpt4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qrefrx0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrx1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrx4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qreftx0-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx0-1p2-supply = <&vreg_l2j_1p2>; + vdda-qreftx1-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx1-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen0-0p9-supply = <&vreg_l3i_0p8>; + vdda-refgen0-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen2-0p9-supply = <&vreg_l3j_0p8>; + vdda-refgen2-1p2-supply = <&vreg_l2j_1p2>; +}; + &tlmm { gpio-reserved-ranges = <44 4>; /* SPI (TPM) */ diff --git a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi index 0bee2a3d6e7a..75ad74bcb042 100644 --- a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi @@ -1382,6 +1382,27 @@ }; }; +&tcsr { + vdda-qrefrpt0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrpt1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrpt4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qrefrx0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrx1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrx4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qreftx0-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx0-1p2-supply = <&vreg_l2j_1p2>; + vdda-qreftx1-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx1-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen0-0p9-supply = <&vreg_l3i_0p8>; + vdda-refgen0-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen2-0p9-supply = <&vreg_l3j_0p8>; + vdda-refgen2-1p2-supply = <&vreg_l2j_1p2>; +}; + &tlmm { gpio-reserved-ranges = <34 2>, /* Unused */ <44 4>, /* SPI (TPM) */ diff --git a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts index 429deffcf3e9..29150fe91250 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts @@ -11,6 +11,95 @@ / { model = "Qualcomm Technologies, Inc. X1E80100 CRD"; compatible = "qcom,x1e80100-crd", "qcom,x1e80100"; + + thermal-zones { + soc-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX1_GPIO_100K_PU(1)>; + }; + + keyboard-thermal { + critical-action = "shutdown"; + polling-delay-passive = <1000>; + + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX2_GPIO_100K_PU(1)>; + + trips { + keyboard_alert0: trip-point0 { + temperature = <53000>; + hysteresis = <1000>; + type = "passive"; + }; + + keyboard-critical { + temperature = <73000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&keyboard_alert0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu8 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu9 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu10 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu11 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + backcover-thermal { + critical-action = "shutdown"; + polling-delay-passive = <400>; + + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX1_THM_100K_PU(1)>; + + trips { + backcover_alert0: trip-point0 { + temperature = <64000>; + hysteresis = <1000>; + type = "passive"; + }; + + backcover-critical { + temperature = <73000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&backcover_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + smb-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX2_THM_100K_PU(1)>; + }; + + sdx-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX3_THM_100K_PU(1)>; + }; + + east-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX4_THM_100K_PU(1)>; + }; + + west-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX5_THM_100K_PU(1)>; + }; + }; }; &gpu_zap_shader { @@ -20,3 +109,33 @@ &iris { status = "okay"; }; + +&pmk8550_vadc { + channel@144 { + qcom,adc-tm; + }; + + channel@145 { + qcom,adc-tm; + }; + + channel@146 { + qcom,adc-tm; + }; + + channel@147 { + qcom,adc-tm; + }; + + channel@148 { + qcom,adc-tm; + }; + + channel@14a { + qcom,adc-tm; + }; + + channel@14b { + qcom,adc-tm; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts b/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts index 2be5a37c00cc..ad62350ba670 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts @@ -1069,6 +1069,27 @@ vdd3-supply = <&vreg_l14b_3p0>; }; +&tcsr { + vdda-qrefrpt0-0p9-supply = <&vreg_l3c_0p9>; + vdda-qrefrpt1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrpt4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qrefrx0-0p9-supply = <&vreg_l3c_0p9>; + vdda-qrefrx1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrx4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qreftx0-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx0-1p2-supply = <&vreg_l2j_1p2>; + vdda-qreftx1-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx1-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen0-0p9-supply = <&vreg_l3i_0p8>; + vdda-refgen0-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen2-0p9-supply = <&vreg_l3j_0p8>; + vdda-refgen2-1p2-supply = <&vreg_l2j_1p2>; +}; + &tlmm { gpio-reserved-ranges = <44 4>, /* SPI11 (TPM) */ <76 4>, /* SPI19 (TZ Protected) */ diff --git a/arch/arm64/boot/dts/qcom/x1e80100-honor-magicbook-art-14.dts b/arch/arm64/boot/dts/qcom/x1e80100-honor-magicbook-art-14.dts index b70c1e094bbf..603f6d7717f3 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-honor-magicbook-art-14.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-honor-magicbook-art-14.dts @@ -1066,6 +1066,27 @@ }; }; +&tcsr { + vdda-qrefrpt0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrpt1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrpt4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qrefrx0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrx1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrx4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qreftx0-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx0-1p2-supply = <&vreg_l2j_1p2>; + vdda-qreftx1-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx1-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen0-0p9-supply = <&vreg_l3i_0p8>; + vdda-refgen0-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen2-0p9-supply = <&vreg_l3j_0p8>; + vdda-refgen2-1p2-supply = <&vreg_l2j_1p2>; +}; + &tlmm { gpio-reserved-ranges = <34 2>, /* Unused */ <44 4>; /* SPI (TPM) */ diff --git a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts index 9eb2dfd99f20..2692e48537aa 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts @@ -1347,6 +1347,27 @@ }; }; +&tcsr { + vdda-qrefrpt0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrpt1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrpt4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qrefrx0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrx1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrx4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qreftx0-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx0-1p2-supply = <&vreg_l2j_1p2>; + vdda-qreftx1-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx1-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen0-0p9-supply = <&vreg_l3i_0p8>; + vdda-refgen0-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen2-0p9-supply = <&vreg_l3j_0p8>; + vdda-refgen2-1p2-supply = <&vreg_l2j_1p2>; +}; + &tlmm { gpio-reserved-ranges = <34 2>, /* Unused */ <44 4>, /* SPI (TPM) */ diff --git a/arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts b/arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts index e4a0b86847cd..6d26d73c18fc 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts @@ -971,8 +971,6 @@ }; &mdss_dp0 { - sound-name-prefix = "DisplayPort0"; - status = "okay"; }; @@ -981,8 +979,6 @@ }; &mdss_dp2 { - sound-name-prefix = "DisplayPort2"; - status = "okay"; }; @@ -1248,6 +1244,27 @@ }; }; +&tcsr { + vdda-qrefrpt0-0p9-supply = <&vreg_l3c_0p9>; + vdda-qrefrpt1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrpt4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qrefrx0-0p9-supply = <&vreg_l3c_0p9>; + vdda-qrefrx1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrx4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qreftx0-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx0-1p2-supply = <&vreg_l2j_1p2>; + vdda-qreftx1-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx1-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen0-0p9-supply = <&vreg_l3i_0p8>; + vdda-refgen0-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen2-0p9-supply = <&vreg_l3j_0p8>; + vdda-refgen2-1p2-supply = <&vreg_l2j_1p2>; +}; + &tlmm { gpio-reserved-ranges = <28 4>, /* Unused */ <44 4>, /* SPI (TPM) */ diff --git a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi index 13d0f09e0c2a..9f45ad9305e8 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi @@ -1322,6 +1322,27 @@ }; }; +&tcsr { + vdda-qrefrpt0-0p9-supply = <&vreg_l3c>; + vdda-qrefrpt1-0p9-supply = <&vreg_l3i>; + vdda-qrefrpt2-0p9-supply = <&vreg_l3i>; + vdda-qrefrpt3-0p9-supply = <&vreg_l3j>; + vdda-qrefrpt4-0p9-supply = <&vreg_l1d>; + vdda-qrefrx0-0p9-supply = <&vreg_l3c>; + vdda-qrefrx1-0p9-supply = <&vreg_l3i>; + vdda-qrefrx2-0p9-supply = <&vreg_l3i>; + vdda-qrefrx3-0p9-supply = <&vreg_l3j>; + vdda-qrefrx4-0p9-supply = <&vreg_l1d>; + vdda-qreftx0-0p9-supply = <&vreg_l3j>; + vdda-qreftx0-1p2-supply = <&vreg_l2j>; + vdda-qreftx1-0p9-supply = <&vreg_l3j>; + vdda-qreftx1-1p2-supply = <&vreg_l3e>; + vdda-refgen0-0p9-supply = <&vreg_l3i>; + vdda-refgen0-1p2-supply = <&vreg_l3e>; + vdda-refgen2-0p9-supply = <&vreg_l3j>; + vdda-refgen2-1p2-supply = <&vreg_l2j>; +}; + &tlmm { gpio-reserved-ranges = <44 4>, /* SPI (TPM) */ <238 1>; /* UFS Reset */ diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts index 78380fec8839..9d4fa442d158 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts @@ -1177,6 +1177,27 @@ }; }; +&tcsr { + vdda-qrefrpt0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrpt1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrpt4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qrefrx0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrx1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrx4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qreftx0-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx0-1p2-supply = <&vreg_l2j_1p2>; + vdda-qreftx1-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx1-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen0-0p9-supply = <&vreg_l3i_0p8>; + vdda-refgen0-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen2-0p9-supply = <&vreg_l3j_0p8>; + vdda-refgen2-1p2-supply = <&vreg_l2j_1p2>; +}; + &tlmm { gpio-reserved-ranges = <33 3>, /* Unused */ <44 4>, /* SPI (TPM) */ diff --git a/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts b/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts index c2f21fcb1b09..8891ad6188ed 100644 --- a/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts +++ b/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts @@ -1325,6 +1325,27 @@ }; }; +&tcsr { + vdda-qrefrpt0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrpt1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrpt4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qrefrx0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrx1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrx4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qreftx0-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx0-1p2-supply = <&vreg_l2j_1p2>; + vdda-qreftx1-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx1-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen0-0p9-supply = <&vreg_l3i_0p8>; + vdda-refgen0-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen2-0p9-supply = <&vreg_l3j_0p8>; + vdda-refgen2-1p2-supply = <&vreg_l2j_1p2>; +}; + &tlmm { gpio-reserved-ranges = <34 2>, /* Unused */ <72 2>; /* Secure EC I2C connection (?) */ diff --git a/arch/arm64/boot/dts/qcom/x1p42100-microsoft-sp12in.dts b/arch/arm64/boot/dts/qcom/x1p42100-microsoft-sp12in.dts index 0314b2246cdb..edcb6b99a384 100644 --- a/arch/arm64/boot/dts/qcom/x1p42100-microsoft-sp12in.dts +++ b/arch/arm64/boot/dts/qcom/x1p42100-microsoft-sp12in.dts @@ -968,6 +968,27 @@ }; }; +&tcsr { + vdda-qrefrpt0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrpt1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrpt3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrpt4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qrefrx0-0p9-supply = <&vreg_l3c_0p8>; + vdda-qrefrx1-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx2-0p9-supply = <&vreg_l3i_0p8>; + vdda-qrefrx3-0p9-supply = <&vreg_l3j_0p8>; + vdda-qrefrx4-0p9-supply = <&vreg_l1d_0p8>; + vdda-qreftx0-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx0-1p2-supply = <&vreg_l2j_1p2>; + vdda-qreftx1-0p9-supply = <&vreg_l3j_0p8>; + vdda-qreftx1-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen0-0p9-supply = <&vreg_l3i_0p8>; + vdda-refgen0-1p2-supply = <&vreg_l3e_1p2>; + vdda-refgen2-0p9-supply = <&vreg_l3j_0p8>; + vdda-refgen2-1p2-supply = <&vreg_l2j_1p2>; +}; + &tlmm { gpio-reserved-ranges = <34 2>, /* Unused */ <44 4>; /* SPI (TPM) */ diff --git a/drivers/firmware/qcom/Kconfig b/drivers/firmware/qcom/Kconfig index c7f8413ab996..691db0ded8e8 100644 --- a/drivers/firmware/qcom/Kconfig +++ b/drivers/firmware/qcom/Kconfig @@ -7,7 +7,7 @@ menu "Qualcomm firmware drivers" config QCOM_PAS - tristate "Qualcomm generic PAS interface driver" + tristate "Qualcomm generic PAS interface driver" if COMPILE_TEST help Enable the generic Peripheral Authentication Service (PAS) provided by the firmware. It acts as the common layer with different TZ @@ -16,6 +16,7 @@ config QCOM_PAS config QCOM_PAS_TEE tristate "Qualcomm PAS TEE interface driver" + depends on ARCH_QCOM || COMPILE_TEST select QCOM_PAS depends on TEE depends on !CPU_BIG_ENDIAN @@ -26,6 +27,7 @@ config QCOM_PAS_TEE config QCOM_SCM tristate "Qualcomm PAS SCM interface driver" + depends on ARCH_QCOM || COMPILE_TEST select QCOM_PAS select QCOM_TZMEM default y if ARCH_QCOM diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c index 3eaa4c9ccf3c..162444f8bc8b 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -2302,6 +2302,7 @@ EXPORT_SYMBOL_GPL(qcom_scm_qseecom_app_send); static const struct of_device_id qcom_scm_qseecom_allowlist[] __maybe_unused = { { .compatible = "asus,vivobook-s15" }, { .compatible = "asus,vivobook-s15-x1p4" }, + { .compatible = "asus,zenbook-a14-ux3407na" }, { .compatible = "asus,zenbook-a14-ux3407qa" }, { .compatible = "asus,zenbook-a14-ux3407ra" }, { .compatible = "asus,zenbook-a16-ux3607oa" }, @@ -2311,6 +2312,7 @@ static const struct of_device_id qcom_scm_qseecom_allowlist[] __maybe_unused = { { .compatible = "ecs,liva-qc710" }, { .compatible = "honor,magicbook-art-14-snapdragon" }, { .compatible = "hp,elitebook-ultra-g1q" }, + { .compatible = "hp,elitebook-x-g2q" }, { .compatible = "hp,omnibook-x14" }, { .compatible = "huawei,gaokun3" }, { .compatible = "lenovo,flex-5g" }, @@ -2319,6 +2321,7 @@ static const struct of_device_id qcom_scm_qseecom_allowlist[] __maybe_unused = { { .compatible = "lenovo,thinkpad-t14s" }, { .compatible = "lenovo,thinkpad-x13s", }, { .compatible = "lenovo,yoga-slim7x" }, + { .compatible = "lenovo,yoga-slim7x-gen11" }, { .compatible = "medion,sprchrgd14s1" }, { .compatible = "microsoft,arcata", }, { .compatible = "microsoft,surface-pro-12in", }, @@ -2844,17 +2847,15 @@ static int qcom_scm_probe(struct platform_device *pdev) if (ret) return ret; - ret = of_reserved_mem_device_init(scm->dev); + ret = devm_of_reserved_mem_device_init(scm->dev); if (ret && ret != -ENODEV) return dev_err_probe(scm->dev, ret, "Failed to setup the reserved memory region for TZ mem\n"); ret = qcom_tzmem_enable(scm->dev); - if (ret) { - ret = dev_err_probe(scm->dev, ret, - "Failed to enable the TrustZone memory allocator\n"); - goto err_rmem; - } + if (ret) + return dev_err_probe(scm->dev, ret, + "Failed to enable the TrustZone memory allocator\n"); memset(&pool_config, 0, sizeof(pool_config)); pool_config.initial_size = 0; @@ -2862,11 +2863,9 @@ static int qcom_scm_probe(struct platform_device *pdev) pool_config.max_size = SZ_256K; scm->mempool = devm_qcom_tzmem_pool_new(scm->dev, &pool_config); - if (IS_ERR(scm->mempool)) { - ret = dev_err_probe(scm->dev, PTR_ERR(scm->mempool), - "Failed to create the SCM memory pool\n"); - goto err_rmem; - } + if (IS_ERR(scm->mempool)) + return dev_err_probe(scm->dev, PTR_ERR(scm->mempool), + "Failed to create the SCM memory pool\n"); ret = qcom_scm_query_waitq_count(scm); scm->wq_cnt = ret < 0 ? QCOM_SCM_DEFAULT_WAITQ_COUNT : ret; @@ -2942,10 +2941,6 @@ static int qcom_scm_probe(struct platform_device *pdev) qcom_scm_gunyah_wdt_init(scm); return 0; - -err_rmem: - of_reserved_mem_device_release(scm->dev); - return ret; } static void qcom_scm_shutdown(struct platform_device *pdev) diff --git a/drivers/gpu/drm/ci/build.sh b/drivers/gpu/drm/ci/build.sh index d00d549cbd9c..fdaa26ad79d6 100644 --- a/drivers/gpu/drm/ci/build.sh +++ b/drivers/gpu/drm/ci/build.sh @@ -26,7 +26,6 @@ if [[ "$KERNEL_ARCH" = "arm64" ]]; then DEVICE_TREES+=" arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtb" DEVICE_TREES+=" arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dtb" DEVICE_TREES+=" arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dtb" - DEVICE_TREES+=" arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r5.dtb" DEVICE_TREES+=" arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dtb" DEVICE_TREES+=" arch/arm64/boot/dts/qcom/sm8350-hdk.dtb" elif [[ "$KERNEL_ARCH" = "arm" ]]; then diff --git a/drivers/gpu/drm/ci/test.yml b/drivers/gpu/drm/ci/test.yml index f6bee5b67931..3777189e9737 100644 --- a/drivers/gpu/drm/ci/test.yml +++ b/drivers/gpu/drm/ci/test.yml @@ -102,16 +102,6 @@ KERNEL_IMAGE_TYPE: "" LAVA_FIRMWARE: qcom-lava -msm:sc7180-trogdor-lazor-limozeen: - extends: - - .msm-sc7180 - parallel: 4 - variables: - DEVICE_TYPE: sc7180-trogdor-lazor-limozeen - DTB: sc7180-trogdor-lazor-limozeen-nots-r5 - GPU_VERSION: ${DEVICE_TYPE} - RUNNER_TAG: mesa-ci-x86-64-lava-sc7180-trogdor-lazor-limozeen - msm:sc7180-trogdor-kingoftown: extends: - .msm-sc7180 diff --git a/drivers/gpu/drm/ci/xfails/msm-sc7180-trogdor-lazor-limozeen-fails.txt b/drivers/gpu/drm/ci/xfails/msm-sc7180-trogdor-lazor-limozeen-fails.txt deleted file mode 100644 index 2daf4ab879a9..000000000000 --- a/drivers/gpu/drm/ci/xfails/msm-sc7180-trogdor-lazor-limozeen-fails.txt +++ /dev/null @@ -1,22 +0,0 @@ -core_setmaster@master-drop-set-user,Fail -kms_color@ctm-0-25,Fail -kms_color@ctm-0-50,Fail -kms_color@ctm-0-75,Fail -kms_color@ctm-blue-to-red,Fail -kms_color@ctm-green-to-red,Fail -kms_color@ctm-negative,Fail -kms_color@ctm-red-to-blue,Fail -kms_color@ctm-signed,Fail -kms_color@gamma,Fail -kms_color@legacy-gamma,Fail -kms_cursor_legacy@cursor-vs-flip-toggle,Fail -kms_cursor_legacy@cursor-vs-flip-varying-size,Fail -kms_flip@flip-vs-modeset-vs-hang,Fail -kms_flip@flip-vs-panning-vs-hang,Fail -kms_lease@lease-uevent,Fail -kms_pipe_crc_basic@compare-crc-sanitycheck-nv12,Fail -kms_plane_alpha_blend@alpha-7efc,Fail -kms_plane_alpha_blend@coverage-7efc,Fail -kms_plane_alpha_blend@coverage-vs-premult-vs-constant,Fail -kms_plane@pixel-format,Fail -kms_plane@pixel-format-source-clamping,Fail diff --git a/drivers/gpu/drm/ci/xfails/msm-sc7180-trogdor-lazor-limozeen-flakes.txt b/drivers/gpu/drm/ci/xfails/msm-sc7180-trogdor-lazor-limozeen-flakes.txt deleted file mode 100644 index cafc802cecea..000000000000 --- a/drivers/gpu/drm/ci/xfails/msm-sc7180-trogdor-lazor-limozeen-flakes.txt +++ /dev/null @@ -1,20 +0,0 @@ -# Board Name: sc7180-trogdor-lazor-limozeen-nots-r5 -# Bug Report: https://lore.kernel.org/linux-arm-msm/661483c8-ad82-400d-bcd8-e94986d20d7d@collabora.com/T/#u -# Failure Rate: 50 -# IGT Version: 1.28-g0df7b9b97 -# Linux Version: 6.9.0-rc7 -msm/msm_mapping@shadow - -# Board Name: sc7180-trogdor-lazor-limozeen-nots-r5 -# Bug Report: https://lore.kernel.org/linux-arm-msm/661483c8-ad82-400d-bcd8-e94986d20d7d@collabora.com/T/#u -# Failure Rate: 100 -# IGT Version: 1.28-gf13702b8e -# Linux Version: 6.10.0-rc5 -kms_lease@page-flip-implicit-plane - -# Board Name: sc7180-trogdor-lazor-limozeen-nots-r5 -# Bug Report: https://gitlab.freedesktop.org/drm/msm/-/issues/74 -# Failure Rate: 20 -# IGT Version: 1.30-g04bedb923 -# Linux Version: 6.14.0-rc4 -kms_cursor_crc@cursor-random-128x128 diff --git a/drivers/gpu/drm/ci/xfails/msm-sc7180-trogdor-lazor-limozeen-skips.txt b/drivers/gpu/drm/ci/xfails/msm-sc7180-trogdor-lazor-limozeen-skips.txt deleted file mode 100644 index a9bb3e1ad75c..000000000000 --- a/drivers/gpu/drm/ci/xfails/msm-sc7180-trogdor-lazor-limozeen-skips.txt +++ /dev/null @@ -1,30 +0,0 @@ -# Suspend to RAM seems to be broken on this machine -.*suspend.* - -# Skip driver specific tests -^amdgpu.* -nouveau_.* -^panfrost.* -^v3d.* -^vc4.* -^vmwgfx* - -# Skip intel specific tests -gem_.* -i915_.* -tools_test.* -kms_dp_link_training.* - -# Currently fails and causes coverage loss for other tests -# since core_getversion also fails. -core_hotunplug.* - -# IGT issue. is_joiner_mode() should return false for non-Intel hardware. -# https://gitlab.freedesktop.org/drm/igt-gpu-tools/-/issues/162 -kms_display_modes@extended-mode-basic -kms_display_modes@mst-extended-mode-negative - -# sc7180 does not have APRIV, so memptrs is not protected. -# (Preemption is not supported on devices that do not have -# APRIV, so this is ok) -msm/msm_mapping@memptrs diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index 0b8f2cafed19..1e246616f83f 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -24,6 +24,8 @@ adreno-y := \ adreno/a6xx_gmu.o \ adreno/a6xx_hfi.o \ adreno/a6xx_preempt.o \ + adreno/a7xx_catalog.o \ + adreno/a8xx_catalog.o \ adreno/a8xx_gpu.o \ adreno/a8xx_preempt.o \ diff --git a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c index df4cded9143f..59d2f1684e6a 100644 --- a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c @@ -489,6 +489,23 @@ static u32 a2xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) return ring->memptrs->rptr; } +static bool a2xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring) +{ + struct msm_cp_state cp_state = { + .ib1_base = gpu_read(gpu, REG_AXXX_CP_IB1_BASE), + .ib2_base = gpu_read(gpu, REG_AXXX_CP_IB2_BASE), + .ib1_rem = gpu_read(gpu, REG_AXXX_CP_IB1_BUFSZ), + .ib2_rem = gpu_read(gpu, REG_AXXX_CP_IB2_BUFSZ), + }; + bool progress; + + progress = !!memcmp(&cp_state, &ring->last_cp_state, sizeof(cp_state)); + + ring->last_cp_state = cp_state; + + return progress; +} + static struct msm_gpu *a2xx_gpu_init(struct drm_device *dev) { struct a2xx_gpu *a2xx_gpu = NULL; @@ -553,6 +570,7 @@ const struct adreno_gpu_funcs a2xx_gpu_funcs = { .gpu_state_put = adreno_gpu_state_put, .create_vm = a2xx_create_vm, .get_rptr = a2xx_get_rptr, + .progress = a2xx_progress, }, .init = a2xx_gpu_init, }; diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c index 0259e60b8011..160d302e16a3 100644 --- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c @@ -500,14 +500,18 @@ static u64 a3xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate) static int a3xx_vbif_halt(struct msm_gpu *gpu) { + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + u32 mask = A3XX_VBIF_XIN_HALT_CTRL0_MASK; u32 ack; int ret; - gpu_write(gpu, REG_A3XX_VBIF_XIN_HALT_CTRL0, - A3XX_VBIF_XIN_HALT_CTRL0_MASK); + /* A306(A) only have three VBIF XIN ports. */ + if (adreno_is_a306(adreno_gpu) || adreno_is_a306a(adreno_gpu)) + mask = GENMASK(2, 0); + + gpu_write(gpu, REG_A3XX_VBIF_XIN_HALT_CTRL0, mask); ret = spin_until(((ack = gpu_read(gpu, REG_A3XX_VBIF_XIN_HALT_CTRL1)) & - A3XX_VBIF_XIN_HALT_CTRL0_MASK) == - A3XX_VBIF_XIN_HALT_CTRL0_MASK); + mask) == mask); gpu_write(gpu, REG_A3XX_VBIF_XIN_HALT_CTRL0, 0); if (ret) @@ -536,6 +540,23 @@ static u32 a3xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) return ring->memptrs->rptr; } +static bool a3xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring) +{ + struct msm_cp_state cp_state = { + .ib1_base = gpu_read(gpu, REG_AXXX_CP_IB1_BASE), + .ib2_base = gpu_read(gpu, REG_AXXX_CP_IB2_BASE), + .ib1_rem = gpu_read(gpu, REG_AXXX_CP_IB1_BUFSZ), + .ib2_rem = gpu_read(gpu, REG_AXXX_CP_IB2_BUFSZ), + }; + bool progress; + + progress = !!memcmp(&cp_state, &ring->last_cp_state, sizeof(cp_state)); + + ring->last_cp_state = cp_state; + + return progress; +} + static struct msm_gpu *a3xx_gpu_init(struct drm_device *dev) { struct a3xx_gpu *a3xx_gpu = NULL; @@ -630,6 +651,7 @@ const struct adreno_gpu_funcs a3xx_gpu_funcs = { .gpu_state_put = adreno_gpu_state_put, .create_vm = adreno_create_vm, .get_rptr = a3xx_get_rptr, + .progress = a3xx_progress, }, .init = a3xx_gpu_init, }; diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index 5d96b8f63156..16c7335c4b1f 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -748,6 +748,9 @@ static int a5xx_hw_init(struct msm_gpu *gpu) /* Select RBBM0 to countable 6 to get the busy status for devfreq */ gpu_write(gpu, REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0, 6); + /* Select SP0 to count ALU cycles for hangcheck progress detection */ + gpu_write(gpu, REG_A5XX_SP_PERFCTR_SP_SEL_0, PERF_SP_ALU_WORKING_CYCLES); + /* Increase VFD cache access so LRZ and other data gets evicted less */ gpu_write(gpu, REG_A5XX_UCHE_CACHE_WAYS, 0x02); @@ -1337,9 +1340,14 @@ static const u32 a5xx_registers[] = { 0xE800, 0xE806, 0xE810, 0xE89A, 0xE8A0, 0xE8A4, 0xE8AA, 0xE8EB, 0xE900, 0xE905, 0xEB80, 0xEB8F, 0xEBB0, 0xEBB0, 0xEC00, 0xEC05, 0xEC08, 0xECE9, 0xECF0, 0xECF0, 0xEA80, 0xEA80, 0xEA82, 0xEAA3, - 0xEAA5, 0xEAC2, 0xA800, 0xA800, 0xA820, 0xA828, 0xA840, 0xA87D, - 0XA880, 0xA88D, 0xA890, 0xA8A3, 0xA8D0, 0xA8D8, 0xA8E0, 0xA8F5, - 0xAC60, 0xAC60, ~0, + 0xEAA5, 0xEAC2, ~0, +}; + +/* GPMU registers, only valid on parts with a GPMU (a530/a540) */ +static const u32 a5xx_gpmu_registers[] = { + 0xA800, 0xA800, 0xA820, 0xA828, 0xA840, 0xA87D, 0xA880, 0xA88D, + 0xA890, 0xA8A3, 0xA8D0, 0xA8D8, 0xA8E0, 0xA8F5, 0xAC60, 0xAC60, + ~0, }; static void a5xx_dump(struct msm_gpu *gpu) @@ -1448,6 +1456,7 @@ struct a5xx_crashdumper { struct a5xx_gpu_state { struct msm_gpu_state base; u32 *hlsqregs; + u32 *gpmuregs; }; static int a5xx_crashdumper_init(struct msm_gpu *gpu, @@ -1565,8 +1574,30 @@ static void a5xx_gpu_state_get_hlsq_regs(struct msm_gpu *gpu, msm_gem_kernel_put(dumper.bo, gpu->vm); } +static void a5xx_gpu_state_get_gpmu_regs(struct msm_gpu *gpu, + struct a5xx_gpu_state *a5xx_state) +{ + u32 count = 0, pos = 0; + int i; + + for (i = 0; a5xx_gpmu_registers[i] != ~0; i += 2) + count += a5xx_gpmu_registers[i + 1] - a5xx_gpmu_registers[i] + 1; + + a5xx_state->gpmuregs = kcalloc(count, sizeof(u32), GFP_KERNEL); + if (!a5xx_state->gpmuregs) + return; + + for (i = 0; a5xx_gpmu_registers[i] != ~0; i += 2) { + u32 addr; + + for (addr = a5xx_gpmu_registers[i]; addr <= a5xx_gpmu_registers[i + 1]; addr++) + a5xx_state->gpmuregs[pos++] = gpu_read(gpu, addr); + } +} + static struct msm_gpu_state *a5xx_gpu_state_get(struct msm_gpu *gpu) { + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct a5xx_gpu_state *a5xx_state = kzalloc_obj(*a5xx_state); bool stalled = !!(gpu_read(gpu, REG_A5XX_RBBM_STATUS3) & BIT(24)); @@ -1581,6 +1612,9 @@ static struct msm_gpu_state *a5xx_gpu_state_get(struct msm_gpu *gpu) a5xx_state->base.rbbm_status = gpu_read(gpu, REG_A5XX_RBBM_STATUS); + if (adreno_is_a530(adreno_gpu) || adreno_is_a540(adreno_gpu)) + a5xx_gpu_state_get_gpmu_regs(gpu, a5xx_state); + /* * Get the HLSQ regs with the help of the crashdumper, but only if * we are not stalled in an iommu fault (in which case the crashdumper @@ -1602,6 +1636,7 @@ static void a5xx_gpu_state_destroy(struct kref *kref) struct a5xx_gpu_state, base); kfree(a5xx_state->hlsqregs); + kfree(a5xx_state->gpmuregs); adreno_gpu_state_destroy(state); kfree(a5xx_state); @@ -1630,6 +1665,17 @@ static void a5xx_show(struct msm_gpu *gpu, struct msm_gpu_state *state, adreno_show(gpu, state, p); + if (a5xx_state->gpmuregs) { + u32 o, pos = 0; + + drm_printf(p, "registers-gpmu:\n"); + + for (i = 0; a5xx_gpmu_registers[i] != ~0; i += 2) + for (o = a5xx_gpmu_registers[i]; o <= a5xx_gpmu_registers[i + 1]; o++) + drm_printf(p, " - { offset: 0x%04x, value: 0x%08x }\n", + o << 2, a5xx_state->gpmuregs[pos++]); + } + /* Dump the additional a5xx HLSQ registers */ if (!a5xx_state->hlsqregs) return; @@ -1687,6 +1733,29 @@ static uint32_t a5xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) return ring->memptrs->rptr = gpu_read(gpu, REG_A5XX_CP_RB_RPTR); } +static bool a5xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu); + struct msm_cp_state cp_state = { + .ib1_base = gpu_read64(gpu, REG_A5XX_CP_IB1_BASE), + .ib2_base = gpu_read64(gpu, REG_A5XX_CP_IB2_BASE), + .ib1_rem = gpu_read(gpu, REG_A5XX_CP_IB1_BUFSZ), + .ib2_rem = gpu_read(gpu, REG_A5XX_CP_IB2_BUFSZ), + }; + u64 alu_cycles = gpu_read64(gpu, REG_A5XX_RBBM_PERFCTR_SP_0_LO); + bool progress; + + /* The CP can stall on one packet while shaders keep running */ + progress = !!memcmp(&cp_state, &ring->last_cp_state, sizeof(cp_state)) || + alu_cycles != a5xx_gpu->last_alu_cycles; + + ring->last_cp_state = cp_state; + a5xx_gpu->last_alu_cycles = alu_cycles; + + return progress; +} + static void check_speed_bin(struct device *dev) { struct nvmem_cell *cell; @@ -1800,6 +1869,7 @@ const struct adreno_gpu_funcs a5xx_gpu_funcs = { .gpu_state_put = a5xx_gpu_state_put, .create_vm = adreno_create_vm, .get_rptr = a5xx_get_rptr, + .progress = a5xx_progress, }, .init = a5xx_gpu_init, .get_timestamp = a5xx_get_timestamp, diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.h b/drivers/gpu/drm/msm/adreno/a5xx_gpu.h index 407bb950d350..fb05f1ca3e81 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.h @@ -36,6 +36,8 @@ struct a5xx_gpu { uint64_t preempt_iova[MSM_GPU_MAX_RINGS]; uint32_t last_seqno[MSM_GPU_MAX_RINGS]; + uint64_t last_alu_cycles; + atomic_t preempt_state; spinlock_t preempt_start_lock; struct timer_list preempt_timer; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c index 90a0c7ffb3c8..4ef2bd6e7ad2 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -9,7 +9,6 @@ #include "adreno_gpu.h" #include "a6xx_gpu.h" #include "a6xx.xml.h" -#include "a6xx_gmu.xml.h" static const struct adreno_reglist a612_hwcg[] = { {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222}, @@ -678,6 +677,65 @@ static const struct adreno_reglist a640_gbif[] = { { }, }; +static const struct adreno_reglist a702_hwcg[] = { + { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222 }, + { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220 }, + { REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000081 }, + { REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf }, + { REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222 }, + { REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222 }, + { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222 }, + { REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222 }, + { REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111 }, + { REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111 }, + { REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111 }, + { REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111 }, + { REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777 }, + { REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777 }, + { REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777 }, + { REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777 }, + { REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222 }, + { REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01202222 }, + { REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220 }, + { REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00 }, + { REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05522022 }, + { REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555 }, + { REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011 }, + { REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044 }, + { REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222 }, + { REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222 }, + { REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222222 }, + { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002 }, + { REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222 }, + { REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000 }, + { REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222 }, + { REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200 }, + { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 }, + { REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222 }, + { REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004 }, + { REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002 }, + { REG_A6XX_RBBM_ISDB_CNT, 0x00000182 }, + { REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000 }, + { REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222 }, + { REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111 }, + { REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555 }, + { REG_A6XX_RBBM_CLOCK_CNTL_FCHE, 0x00000222 }, + { REG_A6XX_RBBM_CLOCK_DELAY_FCHE, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_HYST_FCHE, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_CNTL_GLC, 0x00222222 }, + { REG_A6XX_RBBM_CLOCK_DELAY_GLC, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_HYST_GLC, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_CNTL_MHUB, 0x00000002 }, + { REG_A6XX_RBBM_CLOCK_DELAY_MHUB, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_HYST_MHUB, 0x00000000 }, + {} +}; + static const struct adreno_info a6xx_gpus[] = { { .chip_ids = ADRENO_CHIP_IDS(0x06010000), @@ -1129,331 +1187,7 @@ static const struct adreno_info a6xx_gpus[] = { .gmu_cgc_mode = 0x00020200, .prim_fifo_threshold = 0x00800200, }, - } -}; -DECLARE_ADRENO_GPULIST(a6xx); - -static const struct adreno_reglist a702_hwcg[] = { - { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222 }, - { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220 }, - { REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000081 }, - { REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf }, - { REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222 }, - { REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222 }, - { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222 }, - { REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222 }, - { REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111 }, - { REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111 }, - { REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111 }, - { REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111 }, - { REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777 }, - { REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777 }, - { REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777 }, - { REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777 }, - { REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222 }, - { REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01202222 }, - { REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220 }, - { REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00 }, - { REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05522022 }, - { REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555 }, - { REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011 }, - { REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044 }, - { REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222 }, - { REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222 }, - { REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222222 }, - { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002 }, - { REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222 }, - { REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000 }, - { REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222 }, - { REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200 }, - { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000 }, - { REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000 }, - { REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000 }, - { REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 }, - { REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000 }, - { REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222 }, - { REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004 }, - { REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002 }, - { REG_A6XX_RBBM_ISDB_CNT, 0x00000182 }, - { REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000 }, - { REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000 }, - { REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222 }, - { REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111 }, - { REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555 }, - { REG_A6XX_RBBM_CLOCK_CNTL_FCHE, 0x00000222 }, - { REG_A6XX_RBBM_CLOCK_DELAY_FCHE, 0x00000000 }, - { REG_A6XX_RBBM_CLOCK_HYST_FCHE, 0x00000000 }, - { REG_A6XX_RBBM_CLOCK_CNTL_GLC, 0x00222222 }, - { REG_A6XX_RBBM_CLOCK_DELAY_GLC, 0x00000000 }, - { REG_A6XX_RBBM_CLOCK_HYST_GLC, 0x00000000 }, - { REG_A6XX_RBBM_CLOCK_CNTL_MHUB, 0x00000002 }, - { REG_A6XX_RBBM_CLOCK_DELAY_MHUB, 0x00000000 }, - { REG_A6XX_RBBM_CLOCK_HYST_MHUB, 0x00000000 }, - {} -}; - -static const struct adreno_reglist a730_hwcg[] = { - { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222 }, - { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022222 }, - { REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf }, - { REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080 }, - { REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222220 }, - { REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222 }, - { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22220222 }, - { REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00222222 }, - { REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777 }, - { REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777 }, - { REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777 }, - { REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777 }, - { REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111 }, - { REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111 }, - { REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111 }, - { REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111 }, - { REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222 }, - { REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004 }, - { REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002 }, - { REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222 }, - { REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222 }, - { REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220 }, - { REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x44000f00 }, - { REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022 }, - { REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00555555 }, - { REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011 }, - { REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00440044 }, - { REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222 }, - { REG_A7XX_RBBM_CLOCK_MODE2_GRAS, 0x00000222 }, - { REG_A7XX_RBBM_CLOCK_MODE_BV_GRAS, 0x00222222 }, - { REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222223 }, - { REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222 }, - { REG_A7XX_RBBM_CLOCK_MODE_BV_GPC, 0x00222222 }, - { REG_A7XX_RBBM_CLOCK_MODE_BV_VFD, 0x00002222 }, - { REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000 }, - { REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 }, - { REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000 }, - { REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000 }, - { REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200 }, - { REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222 }, - { REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222 }, - { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000 }, - { REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000 }, - { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002 }, - { REG_A7XX_RBBM_CLOCK_MODE_BV_LRZ, 0x55555552 }, - { REG_A7XX_RBBM_CLOCK_MODE_CP, 0x00000223 }, - { REG_A6XX_RBBM_CLOCK_CNTL, 0x8aa8aa82 }, - { REG_A6XX_RBBM_ISDB_CNT, 0x00000182 }, - { REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000 }, - { REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000 }, - { REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222 }, - { REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111 }, - { REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555 }, - {}, -}; - -static const struct adreno_reglist a740_hwcg[] = { - { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222 }, - { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x22022222 }, - { REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x003cf3cf }, - { REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080 }, - { REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222220 }, - { REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222 }, - { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222 }, - { REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00222222 }, - { REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777 }, - { REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777 }, - { REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777 }, - { REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777 }, - { REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111 }, - { REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111 }, - { REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111 }, - { REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111 }, - { REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222 }, - { REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x00222222 }, - { REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000444 }, - { REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000222 }, - { REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222 }, - { REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222 }, - { REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220 }, - { REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x44000f00 }, - { REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022 }, - { REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00555555 }, - { REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011 }, - { REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00440044 }, - { REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222 }, - { REG_A7XX_RBBM_CLOCK_MODE2_GRAS, 0x00000222 }, - { REG_A7XX_RBBM_CLOCK_MODE_BV_GRAS, 0x00222222 }, - { REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222223 }, - { REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00222222 }, - { REG_A7XX_RBBM_CLOCK_MODE_BV_GPC, 0x00222222 }, - { REG_A7XX_RBBM_CLOCK_MODE_BV_VFD, 0x00002222 }, - { REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000 }, - { REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 }, - { REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000 }, - { REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00000000 }, - { REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200 }, - { REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00000000 }, - { REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222 }, - { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000 }, - { REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000 }, - { REG_A7XX_RBBM_CLOCK_MODE_BV_LRZ, 0x55555552 }, - { REG_A7XX_RBBM_CLOCK_HYST2_VFD, 0x00000000 }, - { REG_A7XX_RBBM_CLOCK_MODE_CP, 0x00000222 }, - { REG_A6XX_RBBM_CLOCK_CNTL, 0x8aa8aa82 }, - { REG_A6XX_RBBM_ISDB_CNT, 0x00000182 }, - { REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000 }, - { REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000 }, - { REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222 }, - { REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111 }, - { REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555 }, - {}, -}; - -static const u32 a730_protect_regs[] = { - A6XX_PROTECT_RDONLY(0x00000, 0x04ff), - A6XX_PROTECT_RDONLY(0x0050b, 0x0058), - A6XX_PROTECT_NORDWR(0x0050e, 0x0000), - A6XX_PROTECT_NORDWR(0x00510, 0x0000), - A6XX_PROTECT_NORDWR(0x00534, 0x0000), - A6XX_PROTECT_RDONLY(0x005fb, 0x009d), - A6XX_PROTECT_NORDWR(0x00699, 0x01e9), - A6XX_PROTECT_NORDWR(0x008a0, 0x0008), - A6XX_PROTECT_NORDWR(0x008ab, 0x0024), - /* 0x008d0-0x008dd and 0x008e0-0x008e6 are unprotected on purpose for tools like perfetto */ - A6XX_PROTECT_NORDWR(0x008de, 0x0001), - A6XX_PROTECT_RDONLY(0x008e7, 0x014b), - A6XX_PROTECT_NORDWR(0x00900, 0x004d), - A6XX_PROTECT_NORDWR(0x0098d, 0x00b2), - A6XX_PROTECT_NORDWR(0x00a41, 0x01be), - A6XX_PROTECT_NORDWR(0x00df0, 0x0001), - A6XX_PROTECT_NORDWR(0x00e01, 0x0000), - A6XX_PROTECT_NORDWR(0x00e07, 0x0008), - A6XX_PROTECT_NORDWR(0x03c00, 0x00c3), - A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff), - A6XX_PROTECT_NORDWR(0x08630, 0x01cf), - A6XX_PROTECT_NORDWR(0x08e00, 0x0000), - A6XX_PROTECT_NORDWR(0x08e08, 0x0000), - A6XX_PROTECT_NORDWR(0x08e50, 0x001f), - A6XX_PROTECT_NORDWR(0x08e80, 0x0280), - A6XX_PROTECT_NORDWR(0x09624, 0x01db), - A6XX_PROTECT_NORDWR(0x09e40, 0x0000), - A6XX_PROTECT_NORDWR(0x09e64, 0x000d), - A6XX_PROTECT_NORDWR(0x09e78, 0x0187), - A6XX_PROTECT_NORDWR(0x0a630, 0x01cf), - A6XX_PROTECT_NORDWR(0x0ae02, 0x0000), - A6XX_PROTECT_NORDWR(0x0ae50, 0x000f), - A6XX_PROTECT_NORDWR(0x0ae66, 0x0003), - A6XX_PROTECT_NORDWR(0x0ae6f, 0x0003), - A6XX_PROTECT_NORDWR(0x0b604, 0x0003), - A6XX_PROTECT_NORDWR(0x0ec00, 0x0fff), - A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), - A6XX_PROTECT_NORDWR(0x18400, 0x0053), - A6XX_PROTECT_RDONLY(0x18454, 0x0004), - A6XX_PROTECT_NORDWR(0x18459, 0x1fff), - A6XX_PROTECT_NORDWR(0x1a459, 0x1fff), - A6XX_PROTECT_NORDWR(0x1c459, 0x1fff), - A6XX_PROTECT_NORDWR(0x1f400, 0x0443), - A6XX_PROTECT_RDONLY(0x1f844, 0x007b), - A6XX_PROTECT_NORDWR(0x1f860, 0x0000), - A6XX_PROTECT_NORDWR(0x1f878, 0x002a), - /* CP_PROTECT_REG[45, 46] are left untouched! */ - 0, - 0, - A6XX_PROTECT_NORDWR(0x1f8c0, 0x00000), -}; -DECLARE_ADRENO_PROTECT(a730_protect, 48); - -static const uint32_t a7xx_pwrup_reglist_regs[] = { - REG_A6XX_UCHE_TRAP_BASE, - REG_A6XX_UCHE_TRAP_BASE + 1, - REG_A6XX_UCHE_WRITE_THRU_BASE, - REG_A6XX_UCHE_WRITE_THRU_BASE + 1, - REG_A6XX_UCHE_GMEM_RANGE_MIN, - REG_A6XX_UCHE_GMEM_RANGE_MIN + 1, - REG_A6XX_UCHE_GMEM_RANGE_MAX, - REG_A6XX_UCHE_GMEM_RANGE_MAX + 1, - REG_A6XX_UCHE_CACHE_WAYS, - REG_A6XX_UCHE_MODE_CNTL, - REG_A6XX_RB_NC_MODE_CNTL, - REG_A6XX_RB_CMP_DBG_ECO_CNTL, - REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE, - REG_A6XX_UCHE_GBIF_GX_CONFIG, - REG_A6XX_UCHE_CLIENT_PF, - REG_A6XX_TPL1_DBG_ECO_CNTL1, -}; - -DECLARE_ADRENO_REGLIST_LIST(a7xx_pwrup_reglist); - -/* Applicable for X185, A750 */ -static const u32 a750_ifpc_reglist_regs[] = { - REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(0), - REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(1), - REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(2), - REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(3), - REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(4), - REG_A6XX_RBBM_PERFCTR_CNTL, - REG_A6XX_TPL1_NC_MODE_CNTL, - REG_A6XX_SP_NC_MODE_CNTL, - REG_A6XX_CP_DBG_ECO_CNTL, - REG_A6XX_CP_PROTECT_CNTL, - REG_A6XX_CP_PROTECT(0), - REG_A6XX_CP_PROTECT(1), - REG_A6XX_CP_PROTECT(2), - REG_A6XX_CP_PROTECT(3), - REG_A6XX_CP_PROTECT(4), - REG_A6XX_CP_PROTECT(5), - REG_A6XX_CP_PROTECT(6), - REG_A6XX_CP_PROTECT(7), - REG_A6XX_CP_PROTECT(8), - REG_A6XX_CP_PROTECT(9), - REG_A6XX_CP_PROTECT(10), - REG_A6XX_CP_PROTECT(11), - REG_A6XX_CP_PROTECT(12), - REG_A6XX_CP_PROTECT(13), - REG_A6XX_CP_PROTECT(14), - REG_A6XX_CP_PROTECT(15), - REG_A6XX_CP_PROTECT(16), - REG_A6XX_CP_PROTECT(17), - REG_A6XX_CP_PROTECT(18), - REG_A6XX_CP_PROTECT(19), - REG_A6XX_CP_PROTECT(20), - REG_A6XX_CP_PROTECT(21), - REG_A6XX_CP_PROTECT(22), - REG_A6XX_CP_PROTECT(23), - REG_A6XX_CP_PROTECT(24), - REG_A6XX_CP_PROTECT(25), - REG_A6XX_CP_PROTECT(26), - REG_A6XX_CP_PROTECT(27), - REG_A6XX_CP_PROTECT(28), - REG_A6XX_CP_PROTECT(29), - REG_A6XX_CP_PROTECT(30), - REG_A6XX_CP_PROTECT(31), - REG_A6XX_CP_PROTECT(32), - REG_A6XX_CP_PROTECT(33), - REG_A6XX_CP_PROTECT(34), - REG_A6XX_CP_PROTECT(35), - REG_A6XX_CP_PROTECT(36), - REG_A6XX_CP_PROTECT(37), - REG_A6XX_CP_PROTECT(38), - REG_A6XX_CP_PROTECT(39), - REG_A6XX_CP_PROTECT(40), - REG_A6XX_CP_PROTECT(41), - REG_A6XX_CP_PROTECT(42), - REG_A6XX_CP_PROTECT(43), - REG_A6XX_CP_PROTECT(44), - REG_A6XX_CP_PROTECT(45), - REG_A6XX_CP_PROTECT(46), - REG_A6XX_CP_PROTECT(47), -}; - -DECLARE_ADRENO_REGLIST_LIST(a750_ifpc_reglist); - -static const struct adreno_reglist_pipe a7xx_dyn_pwrup_reglist_regs[] = { - { REG_A7XX_GRAS_NC_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, -}; - -DECLARE_ADRENO_REGLIST_PIPE_LIST(a7xx_dyn_pwrup_reglist); - -static const struct adreno_info a7xx_gpus[] = { - { + }, { .chip_ids = ADRENO_CHIP_IDS(0x07000200, 0x07000400), .family = ADRENO_6XX_GEN1, /* NOT a mistake! */ .fw = { @@ -1477,1057 +1211,9 @@ static const struct adreno_info a7xx_gpus[] = { { 178, 2 }, { 142, 3 }, ), - }, { - .chip_ids = ADRENO_CHIP_IDS(0x07030001), - .family = ADRENO_7XX_GEN1, - .fw = { - [ADRENO_FW_SQE] = "a730_sqe.fw", - [ADRENO_FW_GMU] = "gmu_gen70000.bin", - }, - .gmem = SZ_2M, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV | - ADRENO_QUIRK_PREEMPTION, - .funcs = &a7xx_gpu_funcs, - .zapfw = "a730_zap.mdt", - .a6xx = &(const struct a6xx_info) { - .hwcg = a730_hwcg, - .protect = &a730_protect, - .pwrup_reglist = &a7xx_pwrup_reglist, - .dyn_pwrup_reglist = &a7xx_dyn_pwrup_reglist, - .gbif_cx = a640_gbif, - .gmu_cgc_mode = 0x00020000, - }, - .preempt_record_size = 2860 * SZ_1K, - }, { - .chip_ids = ADRENO_CHIP_IDS(0x43020100), - .family = ADRENO_7XX_GEN1, - .fw = { - [ADRENO_FW_SQE] = "qcom/gen71700_sqe.fw", - [ADRENO_FW_GMU] = "qcom/gen71700_gmu.bin", - }, - .gmem = SZ_1M, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV | - ADRENO_QUIRK_PREEMPTION, - .funcs = &a7xx_gpu_funcs, - .a6xx = &(const struct a6xx_info) { - .hwcg = a730_hwcg, - .protect = &a730_protect, - .pwrup_reglist = &a7xx_pwrup_reglist, - .dyn_pwrup_reglist = &a7xx_dyn_pwrup_reglist, - .gbif_cx = a640_gbif, - .gmu_chipid = 0x07110000, - .gmu_cgc_mode = 0x00020000, - .bcms = (const struct a6xx_bcm[]) { - { .name = "SH0", .buswidth = 16 }, - { .name = "MC0", .buswidth = 4 }, - { - .name = "ACV", - .fixed = true, - .perfmode = BIT(3), - .perfmode_bw = 16500000, - }, - { /* sentinel */ }, - }, - }, - .preempt_record_size = 1536 * SZ_1K, - }, { - .chip_ids = ADRENO_CHIP_IDS(0x43050a01), /* "C510v2" */ - .family = ADRENO_7XX_GEN2, - .fw = { - [ADRENO_FW_SQE] = "a740_sqe.fw", - [ADRENO_FW_GMU] = "gmu_gen70200.bin", - }, - .gmem = 3 * SZ_1M, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV | - ADRENO_QUIRK_PREEMPTION, - .funcs = &a7xx_gpu_funcs, - .zapfw = "a740_zap.mdt", - .a6xx = &(const struct a6xx_info) { - .hwcg = a740_hwcg, - .protect = &a730_protect, - .pwrup_reglist = &a7xx_pwrup_reglist, - .dyn_pwrup_reglist = &a7xx_dyn_pwrup_reglist, - .gbif_cx = a640_gbif, - .gmu_chipid = 0x7020100, - .gmu_cgc_mode = 0x00020202, - .bcms = (const struct a6xx_bcm[]) { - { .name = "SH0", .buswidth = 16 }, - { .name = "MC0", .buswidth = 4 }, - { - .name = "ACV", - .fixed = true, - .perfmode = BIT(3), - .perfmode_bw = 16500000, - }, - { /* sentinel */ }, - }, - }, - .preempt_record_size = 4192 * SZ_1K, - }, { - .chip_ids = ADRENO_CHIP_IDS(0x43050c01), /* "C512v2" */ - .family = ADRENO_7XX_GEN2, - .fw = { - [ADRENO_FW_SQE] = "gen70500_sqe.fw", - [ADRENO_FW_GMU] = "gen70500_gmu.bin", - }, - .gmem = 3 * SZ_1M, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV | - ADRENO_QUIRK_PREEMPTION | - ADRENO_QUIRK_IFPC, - .funcs = &a7xx_gpu_funcs, - .a6xx = &(const struct a6xx_info) { - .hwcg = a740_hwcg, - .protect = &a730_protect, - .pwrup_reglist = &a7xx_pwrup_reglist, - .dyn_pwrup_reglist = &a7xx_dyn_pwrup_reglist, - .ifpc_reglist = &a750_ifpc_reglist, - .gbif_cx = a640_gbif, - .gmu_chipid = 0x7050001, - .gmu_cgc_mode = 0x00020202, - .bcms = (const struct a6xx_bcm[]) { - { .name = "SH0", .buswidth = 16 }, - { .name = "MC0", .buswidth = 4 }, - { - .name = "ACV", - .fixed = true, - .perfmode = BIT(3), - .perfmode_bw = 16500000, - }, - { /* sentinel */ }, - }, - }, - .preempt_record_size = 4192 * SZ_1K, - .speedbins = ADRENO_SPEEDBINS( - { 0, 0 }, - { 59, 1 }, - { 7, 2 }, - { 232, 3 }, - { 146, 4 }, - ), - }, { - .chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */ - .family = ADRENO_7XX_GEN3, - .fw = { - [ADRENO_FW_SQE] = "gen70900_sqe.fw", - [ADRENO_FW_GMU] = "gmu_gen70900.bin", - }, - .gmem = 3 * SZ_1M, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV | - ADRENO_QUIRK_PREEMPTION | - ADRENO_QUIRK_IFPC, - .funcs = &a7xx_gpu_funcs, - .zapfw = "gen70900_zap.mbn", - .a6xx = &(const struct a6xx_info) { - .protect = &a730_protect, - .pwrup_reglist = &a7xx_pwrup_reglist, - .dyn_pwrup_reglist = &a7xx_dyn_pwrup_reglist, - .ifpc_reglist = &a750_ifpc_reglist, - .gbif_cx = a640_gbif, - .gmu_chipid = 0x7090100, - .gmu_cgc_mode = 0x00020202, - .bcms = (const struct a6xx_bcm[]) { - { .name = "SH0", .buswidth = 16 }, - { .name = "MC0", .buswidth = 4 }, - { - .name = "ACV", - .fixed = true, - .perfmode = BIT(2), - .perfmode_bw = 10687500, - }, - { /* sentinel */ }, - }, - }, - .preempt_record_size = 3572 * SZ_1K, - }, { - .chip_ids = ADRENO_CHIP_IDS(0x43030c00), - .family = ADRENO_7XX_GEN2, - .fw = { - [ADRENO_FW_SQE] = "gen71500_sqe.fw", - [ADRENO_FW_GMU] = "gen71500_gmu.bin", - }, - .gmem = SZ_1M + SZ_512K, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV | - ADRENO_QUIRK_PREEMPTION, - .funcs = &a7xx_gpu_funcs, - .a6xx = &(const struct a6xx_info) { - .hwcg = a740_hwcg, - .protect = &a730_protect, - .pwrup_reglist = &a7xx_pwrup_reglist, - .dyn_pwrup_reglist = &a7xx_dyn_pwrup_reglist, - .gbif_cx = a640_gbif, - .gmu_chipid = 0x70f0000, - .gmu_cgc_mode = 0x00020222, - .bcms = (const struct a6xx_bcm[]) { - { .name = "SH0", .buswidth = 16 }, - { .name = "MC0", .buswidth = 4 }, - { - .name = "ACV", - .fixed = true, - .perfmode = BIT(3), - .perfmode_bw = 16500000, - }, - { /* sentinel */ }, - }, - }, - .preempt_record_size = 4192 * SZ_1K, - .speedbins = ADRENO_SPEEDBINS( - { 0, 0 }, - { 294, 1 }, - { 263, 2 }, - { 233, 3 }, - { 141, 4 }, - ), - } -}; -DECLARE_ADRENO_GPULIST(a7xx); - -static const struct adreno_reglist_pipe x285_nonctxt_regs[] = { - { REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) }, - { REG_A8XX_GRAS_DBG_ECO_CNTL, 0x00000800, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_GRAS_TSEFE_DBG_ECO_CNTL, 0x00200000, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_PC_VIS_STREAM_CNTL, 0x10010000, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0x00000002, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_PC_CHICKEN_BITS_1, 0x00000003, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_PC_CHICKEN_BITS_2, 0x00000200, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_PC_CHICKEN_BITS_3, 0x00500000, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_PC_CHICKEN_BITS_4, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_RB_GC_GMEM_PROTECT, 0x15000000, BIT(PIPE_BR) }, - { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0x00000007, BIT(PIPE_BR) }, - { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0x00004000, BIT(PIPE_BR) }, - { REG_A8XX_RBBM_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) }, - { REG_A8XX_RBBM_SLICE_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) }, - { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL, 0x00000030, BIT(PIPE_NONE) }, - { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL2, 0x00000030, BIT(PIPE_NONE) }, - { REG_A8XX_RBBM_INTERFACE_HANG_INT_CNTL, 0x0fffffff, BIT(PIPE_NONE) }, - { REG_A8XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x22122212, BIT(PIPE_NONE) }, - { REG_A8XX_RBBM_CGC_P2S_CNTL, 0x00000040, BIT(PIPE_NONE) }, - { REG_A7XX_SP_CHICKEN_BITS_2, 0x00820800, BIT(PIPE_NONE) }, - { REG_A7XX_SP_CHICKEN_BITS_3, 0x00300000, BIT(PIPE_NONE) }, - { REG_A6XX_SP_PERFCTR_SHADER_MASK, 0x0000003f, BIT(PIPE_NONE) }, - /* Disable CS dead batch merge */ - { REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_2, BIT(31), BIT(PIPE_NONE) }, - { REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, 0x00000080, BIT(PIPE_NONE) }, - { REG_A7XX_SP_READ_SEL, 0x0001ff00, BIT(PIPE_NONE) }, - { REG_A6XX_TPL1_DBG_ECO_CNTL, 0x10000000, BIT(PIPE_NONE) }, - /* BIT(26): Disable final clamp for bicubic filtering */ - { REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x04000720, BIT(PIPE_NONE) }, - { REG_A6XX_UCHE_MODE_CNTL, 0x80080000, BIT(PIPE_NONE) }, - { REG_A8XX_UCHE_CCHE_MODE_CNTL, 0x00001000, BIT(PIPE_NONE) }, - { REG_A8XX_UCHE_CCHE_CACHE_WAYS, 0x00000800, BIT(PIPE_NONE) }, - { REG_A8XX_UCHE_GBIF_GX_CONFIG, 0x010240e0, BIT(PIPE_NONE) }, - { REG_A8XX_UCHE_VARB_IDLE_TIMEOUT, 0x00000020, BIT(PIPE_NONE) }, - { REG_A7XX_VFD_DBG_ECO_CNTL, 0x00008000, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_VFD_CB_BV_THRESHOLD, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_VFD_CB_BR_THRESHOLD, 0x00600060, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0x00200020, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_VFD_CB_LP_REQ_CNT, 0x00000020, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { }, -}; - -static const u32 x285_protect_regs[] = { - A6XX_PROTECT_RDONLY(0x00008, 0x039b), - A6XX_PROTECT_RDONLY(0x003b4, 0x008b), - A6XX_PROTECT_NORDWR(0x00440, 0x001f), - A6XX_PROTECT_RDONLY(0x00580, 0x005f), - A6XX_PROTECT_NORDWR(0x005e0, 0x011f), - A6XX_PROTECT_RDONLY(0x0074a, 0x0005), - A6XX_PROTECT_RDONLY(0x00759, 0x0026), - A6XX_PROTECT_RDONLY(0x00789, 0x0000), - A6XX_PROTECT_RDONLY(0x0078c, 0x0013), - A6XX_PROTECT_NORDWR(0x00800, 0x0029), - A6XX_PROTECT_NORDWR(0x0082c, 0x0000), - A6XX_PROTECT_NORDWR(0x00837, 0x00af), - A6XX_PROTECT_RDONLY(0x008e7, 0x00c9), - A6XX_PROTECT_NORDWR(0x008ec, 0x00c3), - A6XX_PROTECT_NORDWR(0x009b1, 0x0250), - A6XX_PROTECT_RDONLY(0x00ce0, 0x0001), - A6XX_PROTECT_RDONLY(0x00df0, 0x0000), - A6XX_PROTECT_NORDWR(0x00df1, 0x0000), - A6XX_PROTECT_NORDWR(0x00e01, 0x0000), - A6XX_PROTECT_NORDWR(0x00e03, 0x1fff), - A6XX_PROTECT_NORDWR(0x03c00, 0x00c5), - A6XX_PROTECT_RDONLY(0x03cc6, 0x0039), - A6XX_PROTECT_NORDWR(0x03d00, 0x1fff), - A6XX_PROTECT_NORDWR(0x08600, 0x01ff), - A6XX_PROTECT_NORDWR(0x08e00, 0x00ff), - A6XX_PROTECT_RDONLY(0x08f00, 0x0000), - A6XX_PROTECT_NORDWR(0x08f01, 0x01be), - A6XX_PROTECT_NORDWR(0x09600, 0x01ff), - A6XX_PROTECT_RDONLY(0x0981a, 0x02e5), - A6XX_PROTECT_NORDWR(0x09e00, 0x01ff), - A6XX_PROTECT_NORDWR(0x0a600, 0x01ff), - A6XX_PROTECT_NORDWR(0x0a82e, 0x0000), - A6XX_PROTECT_NORDWR(0x0ae00, 0x0006), - A6XX_PROTECT_NORDWR(0x0ae08, 0x0006), - A6XX_PROTECT_NORDWR(0x0ae10, 0x00bf), - A6XX_PROTECT_RDONLY(0x0aed0, 0x002f), - A6XX_PROTECT_NORDWR(0x0af00, 0x027f), - A6XX_PROTECT_NORDWR(0x0b600, 0x1fff), - A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff), - A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), - A6XX_PROTECT_NORDWR(0x18400, 0x003f), - A6XX_PROTECT_RDONLY(0x18440, 0x013f), - A6XX_PROTECT_NORDWR(0x18580, 0x1fff), - A6XX_PROTECT_NORDWR(0x1b400, 0x1fff), - A6XX_PROTECT_NORDWR(0x1f400, 0x0477), - A6XX_PROTECT_RDONLY(0x1f878, 0x0507), - A6XX_PROTECT_NORDWR(0x1f930, 0x0329), - A6XX_PROTECT_NORDWR(0x1fd80, 0x1fff), - A6XX_PROTECT_NORDWR(0x27800, 0x007f), - A6XX_PROTECT_RDONLY(0x27880, 0x0385), - A6XX_PROTECT_NORDWR(0x27882, 0x000a), - A6XX_PROTECT_NORDWR(0x27c06, 0x0000), -}; - -DECLARE_ADRENO_PROTECT(x285_protect, 15); - -static const struct adreno_reglist_pipe x285_dyn_pwrup_reglist_regs[] = { - { REG_A8XX_GRAS_TSEFE_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_GRAS_NC_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_GRAS_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_PC_CHICKEN_BITS_1, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_PC_CHICKEN_BITS_2, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_PC_CHICKEN_BITS_3, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_PC_CHICKEN_BITS_4, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_PC_VIS_STREAM_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A7XX_RB_CCU_CNTL, 0, BIT(PIPE_BR) }, - { REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0, BIT(PIPE_BR)}, - { REG_A8XX_RB_CCU_NC_MODE_CNTL, 0, BIT(PIPE_BR) }, - { REG_A8XX_RB_CMP_NC_MODE_CNTL, 0, BIT(PIPE_BR) }, - { REG_A6XX_RB_RBP_CNTL, 0, BIT(PIPE_BR) }, - { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0, BIT(PIPE_BR) }, - { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0, BIT(PIPE_BR) }, - { REG_A7XX_VFD_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_VFD_CB_BV_THRESHOLD, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_VFD_CB_BR_THRESHOLD, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_VFD_CB_LP_REQ_CNT, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_CP_HW_FAULT_STATUS_MASK_PIPE, 0, BIT(PIPE_BR) | - BIT(PIPE_BV) | BIT(PIPE_LPAC) | BIT(PIPE_AQE0) | - BIT(PIPE_AQE1) | BIT(PIPE_DDE_BR) | BIT(PIPE_DDE_BV) }, - { REG_A8XX_CP_INTERRUPT_STATUS_MASK_PIPE, 0, BIT(PIPE_BR) | - BIT(PIPE_BV) | BIT(PIPE_LPAC) | BIT(PIPE_AQE0) | - BIT(PIPE_AQE1) | BIT(PIPE_DDE_BR) | BIT(PIPE_DDE_BV) }, - { REG_A8XX_CP_PROTECT_CNTL_PIPE, 0, BIT(PIPE_BR) | BIT(PIPE_BV) | BIT(PIPE_LPAC)}, - { REG_A8XX_CP_PROTECT_PIPE(15), 0, BIT(PIPE_BR) | BIT(PIPE_BV) | BIT(PIPE_LPAC) }, - { REG_A8XX_RB_GC_GMEM_PROTECT, 0, BIT(PIPE_BR) }, - { REG_A8XX_RB_LPAC_GMEM_PROTECT, 0, BIT(PIPE_BR) }, - { REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE, 0, BIT(PIPE_BR) }, -}; -DECLARE_ADRENO_REGLIST_PIPE_LIST(x285_dyn_pwrup_reglist); - -static const struct adreno_reglist_pipe a810_nonctxt_regs[] = { - { REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) }, - { REG_A8XX_GRAS_DBG_ECO_CNTL, 0x00f80800, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_PC_VIS_STREAM_CNTL, 0x10010000, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0x00000002, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_PC_CHICKEN_BITS_1, 0x00000003, BIT(PIPE_BR) }, - { REG_A8XX_PC_CHICKEN_BITS_1, 0x00000023, BIT(PIPE_BV) }, /* Avoid partial waves at VFD */ - { REG_A8XX_PC_CHICKEN_BITS_2, 0x00000200, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_PC_CHICKEN_BITS_3, 0x00500000, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_PC_CHICKEN_BITS_4, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A7XX_RB_CCU_CNTL, 0x00000068, BIT(PIPE_BR) }, - /* Partially enable perf clear, Disable DINT to c/z be data forwarding */ - { REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0x00002200, BIT(PIPE_BR) }, - { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0x00000007, BIT(PIPE_BR) }, - { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0x00004000, BIT(PIPE_BR) }, - { REG_A8XX_RBBM_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) }, - { REG_A8XX_RBBM_SLICE_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) }, - { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL, 0x00000030, BIT(PIPE_NONE) }, - { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL2, 0x00000030, BIT(PIPE_NONE) }, - { REG_A8XX_UCHE_GBIF_GX_CONFIG, 0x010240e0, BIT(PIPE_NONE) }, - { REG_A8XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x22122212, BIT(PIPE_NONE) }, - { REG_A8XX_RBBM_CGC_P2S_CNTL, 0x00000040, BIT(PIPE_NONE) }, - /* - * BIT(22): Disable PS out of order retire - * BIT(23): Enable half wave mode and MM instruction src&dst is half precision - */ - { REG_A7XX_SP_CHICKEN_BITS_2, BIT(22) | BIT(23), BIT(PIPE_NONE) }, - { REG_A7XX_SP_CHICKEN_BITS_3, 0x00300000, BIT(PIPE_NONE) }, - { REG_A6XX_SP_PERFCTR_SHADER_MASK, 0x0000003f, BIT(PIPE_NONE) }, - { REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, 0x00000080, BIT(PIPE_NONE) }, - { REG_A6XX_TPL1_DBG_ECO_CNTL, 0x10100000, BIT(PIPE_NONE) }, - { REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x04000724, BIT(PIPE_NONE) }, - { REG_A6XX_UCHE_MODE_CNTL, 0x00020000, BIT(PIPE_NONE) }, - { REG_A8XX_UCHE_CCHE_MODE_CNTL, 0x00001000, BIT(PIPE_NONE) }, - { REG_A8XX_UCHE_CCHE_CACHE_WAYS, 0x00000800, BIT(PIPE_NONE) }, - /* Disable write slow pointer in data phase queue */ - { REG_A8XX_UCHE_HW_DBG_CNTL, BIT(8), BIT(PIPE_NONE) }, - { REG_A8XX_UCHE_VARB_IDLE_TIMEOUT, 0x00000020, BIT(PIPE_NONE) }, - { REG_A7XX_VFD_DBG_ECO_CNTL, 0x00008000, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_VFD_CB_BV_THRESHOLD, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_VFD_CB_BR_THRESHOLD, 0x00600060, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0x00200020, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_VFD_CB_LP_REQ_CNT, 0x00100020, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_RB_GC_GMEM_PROTECT, 0x00900000, BIT(PIPE_BR) }, - { }, -}; - -static const u32 a810_protect_regs[] = { - A6XX_PROTECT_RDONLY(0x00000, 0x03a3), - A6XX_PROTECT_RDONLY(0x003b4, 0x008b), - A6XX_PROTECT_NORDWR(0x00440, 0x001f), - A6XX_PROTECT_RDONLY(0x00580, 0x005f), - A6XX_PROTECT_NORDWR(0x005e0, 0x011f), - A6XX_PROTECT_RDONLY(0x0074a, 0x0005), - A6XX_PROTECT_RDONLY(0x00759, 0x0026), - A6XX_PROTECT_RDONLY(0x00789, 0x0000), - A6XX_PROTECT_RDONLY(0x0078c, 0x0013), - A6XX_PROTECT_NORDWR(0x00800, 0x0029), - A6XX_PROTECT_NORDWR(0x00837, 0x00af), - A6XX_PROTECT_RDONLY(0x008e7, 0x00c9), - A6XX_PROTECT_NORDWR(0x008ec, 0x00c3), - A6XX_PROTECT_NORDWR(0x009b1, 0x0250), - A6XX_PROTECT_RDONLY(0x00ce0, 0x0001), - A6XX_PROTECT_RDONLY(0x00df0, 0x0000), - A6XX_PROTECT_NORDWR(0x00df1, 0x0000), - A6XX_PROTECT_NORDWR(0x00e01, 0x0000), - A6XX_PROTECT_NORDWR(0x00e03, 0x1fff), - A6XX_PROTECT_NORDWR(0x03c00, 0x00c5), - A6XX_PROTECT_RDONLY(0x03cc6, 0x1fff), - A6XX_PROTECT_NORDWR(0x08600, 0x01ff), - A6XX_PROTECT_NORDWR(0x08e00, 0x00ff), - A6XX_PROTECT_RDONLY(0x08f00, 0x0000), - A6XX_PROTECT_NORDWR(0x08f01, 0x01be), - A6XX_PROTECT_NORDWR(0x09600, 0x01ff), - A6XX_PROTECT_RDONLY(0x0981a, 0x02e5), - A6XX_PROTECT_NORDWR(0x09e00, 0x01ff), - A6XX_PROTECT_NORDWR(0x0a600, 0x01ff), - A6XX_PROTECT_NORDWR(0x0ae00, 0x0006), - A6XX_PROTECT_NORDWR(0x0ae08, 0x0006), - A6XX_PROTECT_NORDWR(0x0ae10, 0x036f), - A6XX_PROTECT_NORDWR(0x0b600, 0x1fff), - A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff), - A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), - A6XX_PROTECT_NORDWR(0x18400, 0x003f), - A6XX_PROTECT_RDONLY(0x18440, 0x013f), - A6XX_PROTECT_NORDWR(0x18580, 0x1fff), - A6XX_PROTECT_NORDWR(0x1b400, 0x1fff), - A6XX_PROTECT_NORDWR(0x1f400, 0x0477), - A6XX_PROTECT_RDONLY(0x1f878, 0x0787), - A6XX_PROTECT_NORDWR(0x1f930, 0x0329), - A6XX_PROTECT_NORDWR(0x20000, 0x1fff), - A6XX_PROTECT_NORDWR(0x27800, 0x007f), - A6XX_PROTECT_RDONLY(0x27880, 0x0381), - A6XX_PROTECT_NORDWR(0x27882, 0x0001), - A6XX_PROTECT_NORDWR(0x27c02, 0x0000), -}; -DECLARE_ADRENO_PROTECT(a810_protect, 64); - -static const uint32_t a810_pwrup_reglist_regs[] = { - REG_A6XX_UCHE_MODE_CNTL, - REG_A8XX_UCHE_VARB_IDLE_TIMEOUT, - REG_A8XX_UCHE_GBIF_GX_CONFIG, - REG_A8XX_UCHE_CACHE_WAYS, - REG_A8XX_UCHE_CCHE_MODE_CNTL, - REG_A8XX_UCHE_CCHE_CACHE_WAYS, - REG_A8XX_UCHE_CCHE_GC_GMEM_RANGE_MIN, - REG_A8XX_UCHE_CCHE_GC_GMEM_RANGE_MIN + 1, - REG_A8XX_UCHE_CCHE_TRAP_BASE, - REG_A8XX_UCHE_CCHE_TRAP_BASE + 1, - REG_A8XX_UCHE_CCHE_WRITE_THRU_BASE, - REG_A8XX_UCHE_CCHE_WRITE_THRU_BASE + 1, - REG_A8XX_UCHE_HW_DBG_CNTL, - REG_A8XX_UCHE_WRITE_THRU_BASE, - REG_A8XX_UCHE_WRITE_THRU_BASE + 1, - REG_A8XX_UCHE_TRAP_BASE, - REG_A8XX_UCHE_TRAP_BASE + 1, - REG_A8XX_UCHE_CLIENT_PF, - REG_A8XX_RB_CMP_NC_MODE_CNTL, - REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, - REG_A8XX_SP_HLSQ_GC_GMEM_RANGE_MIN, - REG_A8XX_SP_HLSQ_GC_GMEM_RANGE_MIN + 1, - REG_A7XX_SP_READ_SEL, - REG_A6XX_TPL1_NC_MODE_CNTL, - REG_A6XX_TPL1_DBG_ECO_CNTL, - REG_A6XX_TPL1_DBG_ECO_CNTL1, - REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(1), - REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(2), - REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(3), - REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(4), - REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(5), - REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(6), - REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(7), - REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(8), - REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(9), - REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(10), - REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(11), - REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(12), - REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(13), - REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(14), - REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(15), - REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(16), - REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(17), - REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(18), - REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(19), + }, }; -DECLARE_ADRENO_REGLIST_LIST(a810_pwrup_reglist); - -static const u32 a810_ifpc_reglist_regs[] = { - REG_A8XX_RBBM_NC_MODE_CNTL, - REG_A8XX_RBBM_PERFCTR_CNTL, - REG_A8XX_RBBM_SLICE_INTERFACE_HANG_INT_CNTL, - REG_A8XX_RBBM_SLICE_NC_MODE_CNTL, - REG_A6XX_SP_NC_MODE_CNTL, - REG_A7XX_SP_CHICKEN_BITS_2, - REG_A7XX_SP_CHICKEN_BITS_3, - REG_A6XX_SP_PERFCTR_SHADER_MASK, - REG_A8XX_CP_PROTECT_GLOBAL(0), - REG_A8XX_CP_PROTECT_GLOBAL(1), - REG_A8XX_CP_PROTECT_GLOBAL(2), - REG_A8XX_CP_PROTECT_GLOBAL(3), - REG_A8XX_CP_PROTECT_GLOBAL(4), - REG_A8XX_CP_PROTECT_GLOBAL(5), - REG_A8XX_CP_PROTECT_GLOBAL(6), - REG_A8XX_CP_PROTECT_GLOBAL(7), - REG_A8XX_CP_PROTECT_GLOBAL(8), - REG_A8XX_CP_PROTECT_GLOBAL(9), - REG_A8XX_CP_PROTECT_GLOBAL(10), - REG_A8XX_CP_PROTECT_GLOBAL(11), - REG_A8XX_CP_PROTECT_GLOBAL(12), - REG_A8XX_CP_PROTECT_GLOBAL(13), - REG_A8XX_CP_PROTECT_GLOBAL(14), - REG_A8XX_CP_PROTECT_GLOBAL(15), - REG_A8XX_CP_PROTECT_GLOBAL(16), - REG_A8XX_CP_PROTECT_GLOBAL(17), - REG_A8XX_CP_PROTECT_GLOBAL(18), - REG_A8XX_CP_PROTECT_GLOBAL(19), - REG_A8XX_CP_PROTECT_GLOBAL(20), - REG_A8XX_CP_PROTECT_GLOBAL(21), - REG_A8XX_CP_PROTECT_GLOBAL(22), - REG_A8XX_CP_PROTECT_GLOBAL(23), - REG_A8XX_CP_PROTECT_GLOBAL(24), - REG_A8XX_CP_PROTECT_GLOBAL(25), - REG_A8XX_CP_PROTECT_GLOBAL(26), - REG_A8XX_CP_PROTECT_GLOBAL(27), - REG_A8XX_CP_PROTECT_GLOBAL(28), - REG_A8XX_CP_PROTECT_GLOBAL(29), - REG_A8XX_CP_PROTECT_GLOBAL(30), - REG_A8XX_CP_PROTECT_GLOBAL(31), - REG_A8XX_CP_PROTECT_GLOBAL(32), - REG_A8XX_CP_PROTECT_GLOBAL(33), - REG_A8XX_CP_PROTECT_GLOBAL(34), - REG_A8XX_CP_PROTECT_GLOBAL(35), - REG_A8XX_CP_PROTECT_GLOBAL(36), - REG_A8XX_CP_PROTECT_GLOBAL(37), - REG_A8XX_CP_PROTECT_GLOBAL(38), - REG_A8XX_CP_PROTECT_GLOBAL(39), - REG_A8XX_CP_PROTECT_GLOBAL(40), - REG_A8XX_CP_PROTECT_GLOBAL(41), - REG_A8XX_CP_PROTECT_GLOBAL(42), - REG_A8XX_CP_PROTECT_GLOBAL(43), - REG_A8XX_CP_PROTECT_GLOBAL(44), - REG_A8XX_CP_PROTECT_GLOBAL(45), - REG_A8XX_CP_PROTECT_GLOBAL(46), - REG_A8XX_CP_PROTECT_GLOBAL(47), - REG_A8XX_CP_PROTECT_GLOBAL(48), - REG_A8XX_CP_PROTECT_GLOBAL(49), - REG_A8XX_CP_PROTECT_GLOBAL(50), - REG_A8XX_CP_PROTECT_GLOBAL(51), - REG_A8XX_CP_PROTECT_GLOBAL(52), - REG_A8XX_CP_PROTECT_GLOBAL(53), - REG_A8XX_CP_PROTECT_GLOBAL(54), - REG_A8XX_CP_PROTECT_GLOBAL(55), - REG_A8XX_CP_PROTECT_GLOBAL(56), - REG_A8XX_CP_PROTECT_GLOBAL(57), - REG_A8XX_CP_PROTECT_GLOBAL(58), - REG_A8XX_CP_PROTECT_GLOBAL(59), - REG_A8XX_CP_PROTECT_GLOBAL(60), - REG_A8XX_CP_PROTECT_GLOBAL(61), - REG_A8XX_CP_PROTECT_GLOBAL(62), - REG_A8XX_CP_PROTECT_GLOBAL(63), -}; -DECLARE_ADRENO_REGLIST_LIST(a810_ifpc_reglist); - -static const struct adreno_reglist_pipe a810_dyn_pwrup_reglist_regs[] = { - { REG_A8XX_CP_PROTECT_CNTL_PIPE, 0, BIT(PIPE_BR) | BIT(PIPE_BV) }, - { REG_A8XX_CP_PROTECT_PIPE(15), 0, BIT(PIPE_BR) | BIT(PIPE_BV) }, - { REG_A8XX_GRAS_TSEFE_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_GRAS_NC_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_GRAS_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A7XX_RB_CCU_CNTL, 0, BIT(PIPE_BR) }, - { REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0, BIT(PIPE_BR) }, - { REG_A8XX_RB_CCU_NC_MODE_CNTL, 0, BIT(PIPE_BR) }, - { REG_A8XX_RB_CMP_NC_MODE_CNTL, 0, BIT(PIPE_BR) }, - { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0, BIT(PIPE_BR) }, - { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0, BIT(PIPE_BR) }, - { REG_A8XX_RB_GC_GMEM_PROTECT, 0, BIT(PIPE_BR) }, - { REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE, 0, BIT(PIPE_BR) }, - { REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_PC_CHICKEN_BITS_1, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_PC_CHICKEN_BITS_2, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_PC_CHICKEN_BITS_3, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_PC_CHICKEN_BITS_4, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0, BIT(PIPE_BR) | BIT(PIPE_BV) }, - { REG_A8XX_PC_VIS_STREAM_CNTL, 0, BIT(PIPE_BR) | BIT(PIPE_BV) }, - { REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0, BIT(PIPE_BR) | BIT(PIPE_BV) }, - { REG_A8XX_VFD_CB_BV_THRESHOLD, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_VFD_CB_BR_THRESHOLD, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_VFD_CB_LP_REQ_CNT, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A7XX_VFD_DBG_ECO_CNTL, 0, BIT(PIPE_BR) | BIT(PIPE_BV) }, -}; -DECLARE_ADRENO_REGLIST_PIPE_LIST(a810_dyn_pwrup_reglist); - -static const struct adreno_reglist_pipe a840_nonctxt_regs[] = { - { REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) }, - { REG_A8XX_GRAS_DBG_ECO_CNTL, 0x00000800, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_GRAS_TSEFE_DBG_ECO_CNTL, 0x00200000, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_PC_VIS_STREAM_CNTL, 0x10010000, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0x00000002, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_PC_CHICKEN_BITS_1, 0x00000003, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_PC_CHICKEN_BITS_2, 0x00000200, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_PC_CHICKEN_BITS_3, 0x00500000, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_PC_CHICKEN_BITS_4, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) }, - /* Disable Dead Draw Merge scheme on RB-HLSQ */ - { REG_A6XX_RB_RBP_CNTL, BIT(5), BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A7XX_RB_CCU_CNTL, 0x00000068, BIT(PIPE_BR) }, - /* Partially enable perf clear, Disable DINT to c/z be data forwarding */ - { REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0x00002200, BIT(PIPE_BR) }, - { REG_A8XX_RB_GC_GMEM_PROTECT, 0x12000000, BIT(PIPE_BR) }, - { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0x00000007, BIT(PIPE_BR) }, - { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0x00004000, BIT(PIPE_BR) }, - { REG_A8XX_RBBM_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) }, - { REG_A8XX_RBBM_SLICE_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) }, - { REG_A8XX_RBBM_POWER_UP_RESET_SW_OVERRIDE, 0x70809060, BIT(PIPE_NONE) }, - { REG_A8XX_RBBM_POWER_UP_RESET_SW_BV_OVERRIDE, 0x30000000, BIT(PIPE_NONE) }, - { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL, 0x00000030, BIT(PIPE_NONE) }, - { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL2, 0x00000030, BIT(PIPE_NONE) }, - { REG_A8XX_RBBM_INTERFACE_HANG_INT_CNTL, 0x0fffffff, BIT(PIPE_NONE) }, - { REG_A8XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x22122212, BIT(PIPE_NONE) }, - { REG_A8XX_RBBM_CGC_P2S_CNTL, 0x00000040, BIT(PIPE_NONE) }, - /* Disable mode_switch optimization in UMAS */ - { REG_A6XX_SP_CHICKEN_BITS, BIT(24) | BIT(26), BIT(PIPE_NONE) }, - /* Disable LPAC large-LM mode */ - { REG_A8XX_SP_SS_CHICKEN_BITS_0, BIT(3), BIT(PIPE_NONE) }, - /* Disable PS out of order retire */ - { REG_A7XX_SP_CHICKEN_BITS_2, 0x00c21800, BIT(PIPE_NONE) }, - { REG_A7XX_SP_CHICKEN_BITS_3, 0x00300000, BIT(PIPE_NONE) }, - /* Disable SP2TP info attribute */ - { REG_A8XX_SP_CHICKEN_BITS_4, 0x00000002, BIT(PIPE_NONE) }, - { REG_A6XX_SP_PERFCTR_SHADER_MASK, 0x0000003f, BIT(PIPE_NONE) }, - { REG_A7XX_SP_HLSQ_DBG_ECO_CNTL, BIT(14), BIT(PIPE_NONE) }, - /* Ignore HLSQ shared constant feedback from SP */ - { REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_1, BIT(17), BIT(PIPE_NONE) }, - /* Disable CS dead batch merge */ - { REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_2, BIT(24), BIT(PIPE_NONE) }, - { REG_A8XX_SP_HLSQ_DBG_ECO_CNTL_3, BIT(7), BIT(PIPE_NONE) }, - { REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, 0x00000080, BIT(PIPE_NONE) }, - { REG_A7XX_SP_READ_SEL, 0x0001ff00, BIT(PIPE_NONE) }, - { REG_A6XX_TPL1_DBG_ECO_CNTL, 0x10100000, BIT(PIPE_NONE) }, - /* BIT(26): Disable final clamp for bicubic filtering */ - { REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x04000720, BIT(PIPE_NONE) }, - { REG_A6XX_UCHE_MODE_CNTL, 0x80080000, BIT(PIPE_NONE) }, - { REG_A8XX_UCHE_CCHE_MODE_CNTL, 0x00001000, BIT(PIPE_NONE) }, - { REG_A8XX_UCHE_CCHE_CACHE_WAYS, 0x00000800, BIT(PIPE_NONE) }, - { REG_A8XX_UCHE_GBIF_GX_CONFIG, 0x010240e0, BIT(PIPE_NONE) }, - { REG_A8XX_UCHE_VARB_IDLE_TIMEOUT, 0x00000020, BIT(PIPE_NONE) }, - { REG_A7XX_VFD_DBG_ECO_CNTL, 0x00008000, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_VFD_CB_BV_THRESHOLD, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_VFD_CB_BR_THRESHOLD, 0x00600060, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0x00200020, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_VFD_CB_LP_REQ_CNT, 0x00000020, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { }, -}; - -static const u32 a840_protect_regs[] = { - A6XX_PROTECT_RDONLY(0x00008, 0x039b), - A6XX_PROTECT_RDONLY(0x003b4, 0x008b), - A6XX_PROTECT_NORDWR(0x00440, 0x001f), - A6XX_PROTECT_RDONLY(0x00580, 0x005f), - A6XX_PROTECT_NORDWR(0x005e0, 0x011f), - A6XX_PROTECT_RDONLY(0x0074a, 0x0005), - A6XX_PROTECT_RDONLY(0x00759, 0x001b), - A6XX_PROTECT_NORDWR(0x00775, 0x000a), - A6XX_PROTECT_RDONLY(0x00789, 0x0000), - A6XX_PROTECT_RDONLY(0x0078c, 0x0013), - A6XX_PROTECT_NORDWR(0x00800, 0x0029), - A6XX_PROTECT_NORDWR(0x00837, 0x00af), - A6XX_PROTECT_RDONLY(0x008e7, 0x00c9), - A6XX_PROTECT_NORDWR(0x008ec, 0x00c3), - A6XX_PROTECT_NORDWR(0x009b1, 0x0250), - A6XX_PROTECT_NORDWR(0x00c07, 0x0008), - A6XX_PROTECT_RDONLY(0x00ce0, 0x0001), - A6XX_PROTECT_RDONLY(0x00df0, 0x0000), - A6XX_PROTECT_NORDWR(0x00df1, 0x0000), - A6XX_PROTECT_NORDWR(0x00e01, 0x0000), - A6XX_PROTECT_NORDWR(0x00e03, 0x1fff), - A6XX_PROTECT_NORDWR(0x03c00, 0x00c5), - A6XX_PROTECT_RDONLY(0x03cc6, 0x0039), - A6XX_PROTECT_NORDWR(0x03d00, 0x1fff), - A6XX_PROTECT_NORDWR(0x08600, 0x01ff), - A6XX_PROTECT_NORDWR(0x08e00, 0x00ff), - A6XX_PROTECT_RDONLY(0x08f00, 0x0000), - A6XX_PROTECT_NORDWR(0x08f01, 0x01be), - A6XX_PROTECT_NORDWR(0x09600, 0x01ff), - A6XX_PROTECT_RDONLY(0x0981a, 0x02e5), - A6XX_PROTECT_NORDWR(0x09e00, 0x01ff), - A6XX_PROTECT_NORDWR(0x0a600, 0x01ff), - A6XX_PROTECT_NORDWR(0x0a82e, 0x0000), - A6XX_PROTECT_NORDWR(0x0ae00, 0x0000), - A6XX_PROTECT_NORDWR(0x0ae02, 0x0004), - A6XX_PROTECT_NORDWR(0x0ae08, 0x0006), - A6XX_PROTECT_NORDWR(0x0ae10, 0x00bf), - A6XX_PROTECT_RDONLY(0x0aed0, 0x002f), - A6XX_PROTECT_NORDWR(0x0af00, 0x027f), - A6XX_PROTECT_NORDWR(0x0b600, 0x1fff), - A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff), - A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), - A6XX_PROTECT_NORDWR(0x18400, 0x003f), - A6XX_PROTECT_RDONLY(0x18440, 0x013f), - A6XX_PROTECT_NORDWR(0x18580, 0x1fff), - A6XX_PROTECT_NORDWR(0x1b400, 0x1fff), - A6XX_PROTECT_NORDWR(0x1f400, 0x0477), - A6XX_PROTECT_RDONLY(0x1f878, 0x0507), - A6XX_PROTECT_NORDWR(0x1f930, 0x0329), - A6XX_PROTECT_NORDWR(0x1fd80, 0x1fff), - A6XX_PROTECT_NORDWR(0x27800, 0x007f), - A6XX_PROTECT_RDONLY(0x27880, 0x0385), - A6XX_PROTECT_NORDWR(0x27882, 0x0009), - A6XX_PROTECT_NORDWR(0x27c06, 0x0000), -}; -DECLARE_ADRENO_PROTECT(a840_protect, 15); - -static const struct adreno_reglist a840_gbif[] = { - { REG_A6XX_GBIF_QSB_SIDE0, 0x00071e20 }, - { REG_A6XX_GBIF_QSB_SIDE1, 0x00071e20 }, - { REG_A6XX_GBIF_QSB_SIDE2, 0x00071e20 }, - { REG_A6XX_GBIF_QSB_SIDE3, 0x00071e20 }, - { REG_A6XX_GBIF_CX_CONFIG, 0x20023000 }, - { }, -}; - -static const uint32_t a840_pwrup_reglist_regs[] = { - REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, - REG_A7XX_SP_READ_SEL, - REG_A6XX_UCHE_MODE_CNTL, - REG_A8XX_UCHE_VARB_IDLE_TIMEOUT, - REG_A8XX_UCHE_GBIF_GX_CONFIG, - REG_A8XX_UCHE_CCHE_MODE_CNTL, - REG_A8XX_UCHE_CCHE_CACHE_WAYS, - REG_A8XX_UCHE_CACHE_WAYS, - REG_A8XX_UCHE_CCHE_GC_GMEM_RANGE_MIN, - REG_A8XX_UCHE_CCHE_GC_GMEM_RANGE_MIN + 1, - REG_A8XX_UCHE_CCHE_LPAC_GMEM_RANGE_MIN, - REG_A8XX_UCHE_CCHE_LPAC_GMEM_RANGE_MIN + 1, - REG_A8XX_UCHE_CCHE_TRAP_BASE, - REG_A8XX_UCHE_CCHE_TRAP_BASE + 1, - REG_A8XX_UCHE_CCHE_WRITE_THRU_BASE, - REG_A8XX_UCHE_CCHE_WRITE_THRU_BASE + 1, - REG_A8XX_UCHE_HW_DBG_CNTL, - REG_A8XX_UCHE_WRITE_THRU_BASE, - REG_A8XX_UCHE_WRITE_THRU_BASE + 1, - REG_A8XX_UCHE_TRAP_BASE, - REG_A8XX_UCHE_TRAP_BASE + 1, - REG_A8XX_UCHE_CLIENT_PF, - REG_A8XX_RB_CMP_NC_MODE_CNTL, - REG_A8XX_SP_HLSQ_GC_GMEM_RANGE_MIN, - REG_A8XX_SP_HLSQ_GC_GMEM_RANGE_MIN + 1, - REG_A6XX_TPL1_NC_MODE_CNTL, - REG_A6XX_TPL1_DBG_ECO_CNTL, - REG_A6XX_TPL1_DBG_ECO_CNTL1, - REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(0), - REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(1), - REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(2), - REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(3), - REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(4), - REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(5), - REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(6), - REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(7), - REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(8), - REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(9), - REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(10), - REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(11), - REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(12), - REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(13), - REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(14), - REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(15), - REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(16), - REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(17), - REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(18), - REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(19), -}; -DECLARE_ADRENO_REGLIST_LIST(a840_pwrup_reglist); - -static const u32 a840_ifpc_reglist_regs[] = { - REG_A8XX_RBBM_NC_MODE_CNTL, - REG_A8XX_RBBM_SLICE_NC_MODE_CNTL, - REG_A6XX_SP_NC_MODE_CNTL, - REG_A6XX_SP_CHICKEN_BITS, - REG_A8XX_SP_SS_CHICKEN_BITS_0, - REG_A7XX_SP_CHICKEN_BITS_1, - REG_A7XX_SP_CHICKEN_BITS_2, - REG_A7XX_SP_CHICKEN_BITS_3, - REG_A8XX_SP_CHICKEN_BITS_4, - REG_A6XX_SP_PERFCTR_SHADER_MASK, - REG_A8XX_RBBM_SLICE_PERFCTR_CNTL, - REG_A8XX_RBBM_SLICE_INTERFACE_HANG_INT_CNTL, - REG_A7XX_SP_HLSQ_DBG_ECO_CNTL, - REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_1, - REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_2, - REG_A8XX_SP_HLSQ_DBG_ECO_CNTL_3, - REG_A8XX_SP_HLSQ_LPAC_GMEM_RANGE_MIN, - REG_A8XX_SP_HLSQ_LPAC_GMEM_RANGE_MIN + 1, - REG_A8XX_CP_INTERRUPT_STATUS_MASK_GLOBAL, - REG_A8XX_RBBM_PERFCTR_CNTL, - REG_A8XX_CP_PROTECT_GLOBAL(0), - REG_A8XX_CP_PROTECT_GLOBAL(1), - REG_A8XX_CP_PROTECT_GLOBAL(2), - REG_A8XX_CP_PROTECT_GLOBAL(3), - REG_A8XX_CP_PROTECT_GLOBAL(4), - REG_A8XX_CP_PROTECT_GLOBAL(5), - REG_A8XX_CP_PROTECT_GLOBAL(6), - REG_A8XX_CP_PROTECT_GLOBAL(7), - REG_A8XX_CP_PROTECT_GLOBAL(8), - REG_A8XX_CP_PROTECT_GLOBAL(9), - REG_A8XX_CP_PROTECT_GLOBAL(10), - REG_A8XX_CP_PROTECT_GLOBAL(11), - REG_A8XX_CP_PROTECT_GLOBAL(12), - REG_A8XX_CP_PROTECT_GLOBAL(13), - REG_A8XX_CP_PROTECT_GLOBAL(14), - REG_A8XX_CP_PROTECT_GLOBAL(15), - REG_A8XX_CP_PROTECT_GLOBAL(16), - REG_A8XX_CP_PROTECT_GLOBAL(17), - REG_A8XX_CP_PROTECT_GLOBAL(18), - REG_A8XX_CP_PROTECT_GLOBAL(19), - REG_A8XX_CP_PROTECT_GLOBAL(20), - REG_A8XX_CP_PROTECT_GLOBAL(21), - REG_A8XX_CP_PROTECT_GLOBAL(22), - REG_A8XX_CP_PROTECT_GLOBAL(23), - REG_A8XX_CP_PROTECT_GLOBAL(24), - REG_A8XX_CP_PROTECT_GLOBAL(25), - REG_A8XX_CP_PROTECT_GLOBAL(26), - REG_A8XX_CP_PROTECT_GLOBAL(27), - REG_A8XX_CP_PROTECT_GLOBAL(28), - REG_A8XX_CP_PROTECT_GLOBAL(29), - REG_A8XX_CP_PROTECT_GLOBAL(30), - REG_A8XX_CP_PROTECT_GLOBAL(31), - REG_A8XX_CP_PROTECT_GLOBAL(32), - REG_A8XX_CP_PROTECT_GLOBAL(33), - REG_A8XX_CP_PROTECT_GLOBAL(34), - REG_A8XX_CP_PROTECT_GLOBAL(35), - REG_A8XX_CP_PROTECT_GLOBAL(36), - REG_A8XX_CP_PROTECT_GLOBAL(37), - REG_A8XX_CP_PROTECT_GLOBAL(38), - REG_A8XX_CP_PROTECT_GLOBAL(39), - REG_A8XX_CP_PROTECT_GLOBAL(40), - REG_A8XX_CP_PROTECT_GLOBAL(41), - REG_A8XX_CP_PROTECT_GLOBAL(42), - REG_A8XX_CP_PROTECT_GLOBAL(43), - REG_A8XX_CP_PROTECT_GLOBAL(44), - REG_A8XX_CP_PROTECT_GLOBAL(45), - REG_A8XX_CP_PROTECT_GLOBAL(46), - REG_A8XX_CP_PROTECT_GLOBAL(47), - REG_A8XX_CP_PROTECT_GLOBAL(48), - REG_A8XX_CP_PROTECT_GLOBAL(49), - REG_A8XX_CP_PROTECT_GLOBAL(50), - REG_A8XX_CP_PROTECT_GLOBAL(51), - REG_A8XX_CP_PROTECT_GLOBAL(52), - REG_A8XX_CP_PROTECT_GLOBAL(53), - REG_A8XX_CP_PROTECT_GLOBAL(54), - REG_A8XX_CP_PROTECT_GLOBAL(55), - REG_A8XX_CP_PROTECT_GLOBAL(56), - REG_A8XX_CP_PROTECT_GLOBAL(57), - REG_A8XX_CP_PROTECT_GLOBAL(58), - REG_A8XX_CP_PROTECT_GLOBAL(59), - REG_A8XX_CP_PROTECT_GLOBAL(60), - REG_A8XX_CP_PROTECT_GLOBAL(61), - REG_A8XX_CP_PROTECT_GLOBAL(62), - REG_A8XX_CP_PROTECT_GLOBAL(63), -}; -DECLARE_ADRENO_REGLIST_LIST(a840_ifpc_reglist); - -static const struct adreno_reglist_pipe a840_dyn_pwrup_reglist_regs[] = { - { REG_A8XX_GRAS_TSEFE_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_GRAS_NC_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_GRAS_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_PC_CHICKEN_BITS_1, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_PC_CHICKEN_BITS_2, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_PC_CHICKEN_BITS_3, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_PC_CHICKEN_BITS_4, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_PC_VIS_STREAM_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A7XX_RB_CCU_CNTL, 0, BIT(PIPE_BR) }, - { REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0, BIT(PIPE_BR)}, - { REG_A8XX_RB_CCU_NC_MODE_CNTL, 0, BIT(PIPE_BR) }, - { REG_A8XX_RB_CMP_NC_MODE_CNTL, 0, BIT(PIPE_BR) }, - { REG_A6XX_RB_RBP_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0, BIT(PIPE_BR) }, - { REG_A6XX_RB_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0, BIT(PIPE_BR) }, - { REG_A7XX_VFD_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_VFD_CB_BV_THRESHOLD, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_VFD_CB_BR_THRESHOLD, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_VFD_CB_LP_REQ_CNT, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, - { REG_A8XX_CP_HW_FAULT_STATUS_MASK_PIPE, 0, BIT(PIPE_BR) | - BIT(PIPE_BV) | BIT(PIPE_LPAC) | BIT(PIPE_AQE0) | - BIT(PIPE_AQE1) | BIT(PIPE_DDE_BR) | BIT(PIPE_DDE_BV) }, - { REG_A8XX_CP_INTERRUPT_STATUS_MASK_PIPE, 0, BIT(PIPE_BR) | - BIT(PIPE_BV) | BIT(PIPE_LPAC) | BIT(PIPE_AQE0) | - BIT(PIPE_AQE1) | BIT(PIPE_DDE_BR) | BIT(PIPE_DDE_BV) }, - { REG_A8XX_CP_PROTECT_CNTL_PIPE, 0, BIT(PIPE_BR) | BIT(PIPE_BV) | BIT(PIPE_LPAC)}, - { REG_A8XX_CP_PROTECT_PIPE(15), 0, BIT(PIPE_BR) | BIT(PIPE_BV) | BIT(PIPE_LPAC) }, - { REG_A8XX_RB_GC_GMEM_PROTECT, 0, BIT(PIPE_BR) }, - { REG_A8XX_RB_LPAC_GMEM_PROTECT, 0, BIT(PIPE_BR) }, - { REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE, 0, BIT(PIPE_BR) }, -}; -DECLARE_ADRENO_REGLIST_PIPE_LIST(a840_dyn_pwrup_reglist); - -static const struct adreno_info a8xx_gpus[] = { - { - .chip_ids = ADRENO_CHIP_IDS(0x44070001), - .family = ADRENO_8XX_GEN2, - .fw = { - [ADRENO_FW_SQE] = "gen80100_sqe.fw", - [ADRENO_FW_GMU] = "gen80100_gmu.bin", - }, - .gmem = 21 * SZ_1M, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV | - ADRENO_QUIRK_PREEMPTION | - ADRENO_QUIRK_SOFTFUSE, - .funcs = &a8xx_gpu_funcs, - .a6xx = &(const struct a6xx_info) { - .protect = &x285_protect, - .nonctxt_reglist = x285_nonctxt_regs, - .pwrup_reglist = &a840_pwrup_reglist, - .dyn_pwrup_reglist = &x285_dyn_pwrup_reglist, - .ifpc_reglist = &a840_ifpc_reglist, - .gbif_cx = a840_gbif, - .max_slices = 4, - .gmu_chipid = 0x8010100, - .bcms = (const struct a6xx_bcm[]) { - { .name = "SH0", .buswidth = 16 }, - { .name = "MC0", .buswidth = 4 }, - { - .name = "ACV", - .fixed = true, - .perfmode = BIT(2), - .perfmode_bw = 16500000, - }, - { /* sentinel */ }, - }, - }, - .speedbins = ADRENO_SPEEDBINS( - { 0, 0 }, - { 388, 1 }, - { 357, 2 }, - { 284, 3 }, - ), - }, { - .chip_ids = ADRENO_CHIP_IDS(0x44050a01), - .family = ADRENO_8XX_GEN2, - .fw = { - [ADRENO_FW_SQE] = "gen80200_sqe.fw", - [ADRENO_FW_GMU] = "gen80200_gmu.bin", - [ADRENO_FW_AQE] = "gen80200_aqe.fw", - }, - .gmem = 18 * SZ_1M, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV | - ADRENO_QUIRK_PREEMPTION | - ADRENO_QUIRK_IFPC, - .funcs = &a8xx_gpu_funcs, - .a6xx = &(const struct a6xx_info) { - .protect = &a840_protect, - .nonctxt_reglist = a840_nonctxt_regs, - .pwrup_reglist = &a840_pwrup_reglist, - .dyn_pwrup_reglist = &a840_dyn_pwrup_reglist, - .ifpc_reglist = &a840_ifpc_reglist, - .gbif_cx = a840_gbif, - .max_slices = 3, - .gmu_chipid = 0x8020100, - .bcms = (const struct a6xx_bcm[]) { - { .name = "SH0", .buswidth = 16 }, - { .name = "MC0", .buswidth = 4 }, - { - .name = "ACV", - .fixed = true, - .perfmode = BIT(2), - .perfmode_bw = 10687500, - }, - { /* sentinel */ }, - }, - }, - .preempt_record_size = 19708 * SZ_1K, - .speedbins = ADRENO_SPEEDBINS( - { 0, 0 }, - { 273, 1 }, - { 252, 2 }, - { 221, 3 }, - ), - }, { - .chip_ids = ADRENO_CHIP_IDS(0x44010000), - .family = ADRENO_8XX_GEN1, - .fw = { - [ADRENO_FW_SQE] = "gen80300_sqe.fw", - [ADRENO_FW_GMU] = "gen80300_gmu.bin", - }, - .gmem = SZ_512K + SZ_64K, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV | - ADRENO_QUIRK_PREEMPTION | - ADRENO_QUIRK_IFPC, - .funcs = &a8xx_gpu_funcs, - .zapfw = "gen80300_zap.mbn", - .a6xx = &(const struct a6xx_info) { - .protect = &a810_protect, - .nonctxt_reglist = a810_nonctxt_regs, - .pwrup_reglist = &a810_pwrup_reglist, - .dyn_pwrup_reglist = &a810_dyn_pwrup_reglist, - .ifpc_reglist = &a810_ifpc_reglist, - .gbif_cx = a840_gbif, - .max_slices = 1, - .gmu_chipid = 0x8030000, - .bcms = (const struct a6xx_bcm[]) { - { .name = "SH0", .buswidth = 16 }, - { .name = "MC0", .buswidth = 4 }, - { - .name = "ACV", - .fixed = true, - .perfmode = BIT(2), - .perfmode_bw = 10687500, - }, - { /* sentinel */ }, - }, - }, - .preempt_record_size = 4558 * SZ_1K, - .speedbins = ADRENO_SPEEDBINS( - { 0, 0 }, - { 242, 1 }, - { 221, 2 }, - ), - } -}; - -DECLARE_ADRENO_GPULIST(a8xx); +DECLARE_ADRENO_GPULIST(a6xx); static inline __always_unused void __build_asserts(void) { @@ -2535,6 +1221,4 @@ static inline __always_unused void __build_asserts(void) BUILD_BUG_ON(a650_protect.count > a650_protect.count_max); BUILD_BUG_ON(a660_protect.count > a660_protect.count_max); BUILD_BUG_ON(a690_protect.count > a690_protect.count_max); - BUILD_BUG_ON(a730_protect.count > a730_protect.count_max); - BUILD_BUG_ON(a810_protect.count > a810_protect.count_max); } diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 6d49c51df1a2..662f09bec9d5 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -145,6 +145,19 @@ bool a8xx_gmu_gx_is_on(struct adreno_gpu *adreno_gpu) if (!gmu->initialized) return false; + /* + * Use the CX_MISC_GFX_PWR_CLK_STATUS register instead of the GMUCX + * register to ensure correct GDSC and clock status reporting even + * when the GMU MX domain is powered off + */ + if (adreno_is_a850_family(adreno_gpu)) { + val = a6xx_cx_misc_read(a6xx_gpu, REG_A8XX_CX_MISC_GFX_PWR_CLK_STATUS); + + return !(val & + (A8XX_CX_MISC_GFX_PWR_CLK_STATUS_GX_GDSC_POWER_OFF | + A8XX_CX_MISC_GFX_PWR_CLK_STATUS_GX_CLK_OFF)); + } + val = gmu_read(gmu, REG_A8XX_GMU_PWR_CLK_STATUS); return !(val & @@ -645,7 +658,7 @@ static void a6xx_rpmh_stop(struct a6xx_gmu *gmu) if (!test_and_clear_bit(GMU_STATUS_FW_START, &gmu->status)) return; - if (adreno_is_a840(adreno_gpu)) + if (adreno_is_a840(adreno_gpu) || adreno_is_a850_family(adreno_gpu)) bitmask = BIT(30); gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1); @@ -1656,8 +1669,12 @@ static int a6xx_gmu_rpmh_bw_votes_init(struct adreno_gpu *adreno_gpu, if (bcm->fixed) { u32 perfmode = 0; - /* GMU on A6xx votes perfmode on all valid bandwidth */ - if (!adreno_is_a7xx(adreno_gpu) || + /* + * GMU on A6xx votes perfmode on all valid + * bandwidth. A7xx and A8xx only vote perfmode + * above the perfmode_bw threshold. + */ + if (adreno_is_a6xx(adreno_gpu) || (bcm->perfmode_bw && bw >= bcm->perfmode_bw)) perfmode = bcm->perfmode; @@ -1707,70 +1724,85 @@ static unsigned int a6xx_gmu_get_arc_level(struct device *dev, return val; } +static const u16 *a6xx_gmu_rpmh_read_arc(const char *id, size_t *count) +{ + const u16 *vals; + + vals = cmd_db_read_aux_data(id, count); + if (IS_ERR(vals)) + return vals; + + *count >>= 1; + /* Exclude the trailing zero paddings if there are any */ + while (*count && !vals[*count - 1]) + (*count)--; + + if (!*count) + return ERR_PTR(-EINVAL); + + return vals; +} + +/* + * Find the first index in an arc level array whose level is greater than or + * equal to the target. If no level is high enough, either clamp to the + * highest available level (@clamp) or fail, dumping the list. + */ +static int a6xx_gmu_rpmh_arc_index(struct device *dev, const u16 *arc, + size_t arc_count, unsigned int level, bool clamp) +{ + int j; + + for (j = 0; j < arc_count; j++) { + if (arc[j] >= level) + return j; + } + + if (clamp) + return arc_count - 1; + + DRM_DEV_ERROR(dev, "Level %u not found in the RPMh list\n", level); + DRM_DEV_ERROR(dev, "Available levels:\n"); + for (j = 0; j < arc_count; j++) + DRM_DEV_ERROR(dev, " %u\n", arc[j]); + + return -EINVAL; +} + static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes, unsigned long *freqs, int freqs_count, const char *pri_id, const char *sec_id) { - int i, j; + int i; const u16 *pri, *sec; size_t pri_count, sec_count; - pri = cmd_db_read_aux_data(pri_id, &pri_count); + pri = a6xx_gmu_rpmh_read_arc(pri_id, &pri_count); if (IS_ERR(pri)) return PTR_ERR(pri); - /* - * The data comes back as an array of unsigned shorts so adjust the - * count accordingly - */ - pri_count >>= 1; - if (!pri_count) - return -EINVAL; - sec = cmd_db_read_aux_data(sec_id, &sec_count); + sec = a6xx_gmu_rpmh_read_arc(sec_id, &sec_count); if (IS_ERR(sec)) return PTR_ERR(sec); - sec_count >>= 1; - if (!sec_count) - return -EINVAL; - /* Construct a vote for each frequency */ for (i = 0; i < freqs_count; i++) { - u8 pindex = 0, sindex = 0; unsigned int level = a6xx_gmu_get_arc_level(dev, freqs[i]); + int pindex, sindex; - /* Get the primary index that matches the arc level */ - for (j = 0; j < pri_count; j++) { - if (pri[j] >= level) { - pindex = j; - break; - } - } - - if (j == pri_count) { - DRM_DEV_ERROR(dev, - "Level %u not found in the RPMh list\n", - level); - DRM_DEV_ERROR(dev, "Available levels:\n"); - for (j = 0; j < pri_count; j++) - DRM_DEV_ERROR(dev, " %u\n", pri[j]); - - return -EINVAL; - } + pindex = a6xx_gmu_rpmh_arc_index(dev, pri, pri_count, level, false); + if (pindex < 0) + return pindex; /* - * Look for a level in in the secondary list that matches. If - * nothing fits, use the maximum non zero vote + * Look for a matching level in the secondary list; if nothing + * fits, clamp to the highest available vote. The secondary rail + * depends on the primary rail, so match it against the selected + * primary voltage (which is >= the requested level), not the + * requested level itself. */ - - for (j = 0; j < sec_count; j++) { - if (sec[j] >= level) { - sindex = j; - break; - } else if (sec[j]) { - sindex = j; - } - } + sindex = a6xx_gmu_rpmh_arc_index(dev, sec, sec_count, + pri[pindex], true); /* Construct the vote */ votes[i] = ((pri[pindex] & 0xffff) << 16) | @@ -1780,22 +1812,33 @@ static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes, return 0; } +#define GMU_BX_MASK GENMASK(25, 20) + static int a6xx_gmu_rpmh_dep_votes_init(struct device *dev, u32 *votes, unsigned long *freqs, int freqs_count) { - const u16 *mx; - size_t count; + const u16 *mx, *gx = NULL, *gbx; + size_t count, gx_count = 0, gbx_count = 0; - mx = cmd_db_read_aux_data("mx.lvl", &count); + mx = a6xx_gmu_rpmh_read_arc("mx.lvl", &count); if (IS_ERR(mx)) return PTR_ERR(mx); + /* - * The data comes back as an array of unsigned shorts so adjust the - * count accordingly + * Targets with a third memory rail (BX), in addition to GX and MX, + * expect a per-corner BX vote packed into the dependency vote. Detect + * such targets by the presence of the "gbx.lvl" RPMh resource. The BX + * corner is matched against the Gx rail level, so the "gfx.lvl" corners + * are needed as well. */ - count >>= 1; - if (!count) - return -EINVAL; + gbx = a6xx_gmu_rpmh_read_arc("gbx.lvl", &gbx_count); + if (IS_ERR(gbx)) { + gbx = NULL; + } else { + gx = a6xx_gmu_rpmh_read_arc("gfx.lvl", &gx_count); + if (IS_ERR(gx)) + return PTR_ERR(gx); + } /* Fix the vote for zero frequency */ votes[0] = 0xffffffff; @@ -1803,29 +1846,28 @@ static int a6xx_gmu_rpmh_dep_votes_init(struct device *dev, u32 *votes, /* Construct a vote for rest of the corners */ for (int i = 1; i < freqs_count; i++) { unsigned int level = a6xx_gmu_get_arc_level(dev, freqs[i]); - u8 j, index = 0; + int index = a6xx_gmu_rpmh_arc_index(dev, mx, count, level, true); + int bx; - /* Get the primary index that matches the arc level */ - for (j = 0; j < count; j++) { - if (mx[j] >= level) { - index = j; - break; - } - } - - if (j == count) { - DRM_DEV_ERROR(dev, - "Mx Level %u not found in the RPMh list\n", - level); - DRM_DEV_ERROR(dev, "Available levels:\n"); - for (j = 0; j < count; j++) - DRM_DEV_ERROR(dev, " %u\n", mx[j]); - - return -EINVAL; - } + if (index < 0) + return index; /* Construct the vote */ votes[i] = (0x3fff << 14) | (index << 8) | (0xff); + + if (!gbx) + continue; + + index = a6xx_gmu_rpmh_arc_index(dev, gx, gx_count, level, false); + if (index < 0) + return index; + + /* + * Find the BX corner that satisfies that Gx level, falling + * back to the highest BX corner if none is high enough. + */ + bx = a6xx_gmu_rpmh_arc_index(dev, gbx, gbx_count, gx[index], true); + FIELD_MODIFY(GMU_BX_MASK, &votes[i], bx); } return 0; @@ -1860,13 +1902,13 @@ static int a6xx_gmu_rpmh_votes_init(struct a6xx_gmu *gmu) ret = a6xx_gmu_rpmh_arc_votes_init(&gpu->pdev->dev, gmu->gx_arc_votes, gmu->gpu_freqs, gmu->nr_gpu_freqs, "gfx.lvl", sec_id); + ret |= a6xx_gmu_rpmh_dep_votes_init(&gpu->pdev->dev, gmu->dep_arc_votes, + gmu->gpu_freqs, gmu->nr_gpu_freqs); + /* Build the CX votes */ ret |= a6xx_gmu_rpmh_arc_votes_init(gmu->dev, gmu->cx_arc_votes, gmu->gmu_freqs, gmu->nr_gmu_freqs, "cx.lvl", "mx.lvl"); - ret |= a6xx_gmu_rpmh_dep_votes_init(gmu->dev, gmu->dep_arc_votes, - gmu->gpu_freqs, gmu->nr_gpu_freqs); - /* Build the interconnect votes */ if (info->bcms && gmu->nr_gpu_bws > 1) ret |= a6xx_gmu_rpmh_bw_votes_init(adreno_gpu, info, gmu); @@ -2141,6 +2183,9 @@ void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu) dev_pm_domain_detach(gmu->gxpd, false); } + if (!IS_ERR_OR_NULL(gmu->gmu_mxpd)) + dev_pm_domain_detach(gmu->gmu_mxpd, false); + if (!IS_ERR_OR_NULL(gmu->qmp)) qmp_put(gmu->qmp); @@ -2285,7 +2330,8 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; struct msm_gpu *gpu = &adreno_gpu->base; struct a6xx_gmu *gmu = &a6xx_gpu->gmu; - struct device_link *link; + struct device_link *gmu_mx_link = NULL; + struct device_link *cx_link; resource_size_t start; struct resource *res; int ret; @@ -2432,12 +2478,27 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) goto err_mmio; } - link = device_link_add(gmu->dev, gmu->cxpd, DL_FLAG_PM_RUNTIME); - if (!link) { + cx_link = device_link_add(gmu->dev, gmu->cxpd, DL_FLAG_PM_RUNTIME); + if (!cx_link) { ret = -ENODEV; goto detach_cxpd; } + /* Optionally attach the GMU MX power domain */ + gmu->gmu_mxpd = dev_pm_domain_attach_by_name(gmu->dev, "gmu_mx"); + if (IS_ERR(gmu->gmu_mxpd)) { + ret = PTR_ERR(gmu->gmu_mxpd); + goto detach_cxpd_link; + } + + if (gmu->gmu_mxpd) { + gmu_mx_link = device_link_add(gmu->dev, gmu->gmu_mxpd, DL_FLAG_PM_RUNTIME); + if (!gmu_mx_link) { + ret = -ENODEV; + goto detach_gmu_mxpd; + } + } + /* Other errors are handled during GPU ACD probe */ gmu->qmp = qmp_get(gmu->dev); if (PTR_ERR_OR_ZERO(gmu->qmp) == -EPROBE_DEFER) { @@ -2479,7 +2540,15 @@ detach_gxpd: if (!IS_ERR_OR_NULL(gmu->qmp)) qmp_put(gmu->qmp); - device_link_del(link); + if (!IS_ERR_OR_NULL(gmu_mx_link)) + device_link_del(gmu_mx_link); + +detach_gmu_mxpd: + if (gmu->gmu_mxpd) + dev_pm_domain_detach(gmu->gmu_mxpd, false); + +detach_cxpd_link: + device_link_del(cx_link); detach_cxpd: dev_pm_domain_detach(gmu->cxpd, false); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h index 3f96b10b5f61..d3f6cd8b9741 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h @@ -77,6 +77,7 @@ struct a6xx_gmu { struct device *gxpd; struct device *cxpd; + struct device *gmu_mxpd; int idle_level; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 081e79ea4652..92e8c8abb86d 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -225,7 +225,7 @@ static void get_stats_counter(struct msm_ringbuffer *ring, u32 counter, OUT_PKT7(ring, CP_REG_TO_MEM, 3); OUT_RING(ring, CP_REG_TO_MEM_0_REG(counter) | CP_REG_TO_MEM_0_CNT(2) | - CP_REG_TO_MEM_0_64B); + CP_REG_TO_MEM_0_IS_64B); OUT_RING(ring, lower_32_bits(iova)); OUT_RING(ring, upper_32_bits(iova)); } @@ -2181,44 +2181,48 @@ static int a6xx_pm_resume(struct msm_gpu *gpu) opp = dev_pm_opp_find_freq_ceil(&gpu->pdev->dev, &freq); if (IS_ERR(opp)) { ret = PTR_ERR(opp); - goto err_set_opp; + goto err_unlock; } - dev_pm_opp_put(opp); /* Set the core clock and bus bw, having VDD scaling in mind */ dev_pm_opp_set_opp(&gpu->pdev->dev, opp); + dev_pm_opp_put(opp); - pm_runtime_resume_and_get(gmu->dev); - pm_runtime_resume_and_get(gmu->gxpd); + ret = pm_runtime_resume_and_get(gmu->dev); + if (ret < 0) + goto err_opp_clear; + ret = pm_runtime_resume_and_get(gmu->gxpd); + if (ret < 0) + goto err_put_dev; ret = clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks); if (ret) - goto err_bulk_clk; + goto err_put_gxpd; ret = clk_bulk_prepare_enable(gmu->nr_clocks, gmu->clocks); if (ret) { clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks); - goto err_bulk_clk; + goto err_put_gxpd; } if (adreno_is_a619_holi(adreno_gpu)) a6xx_sptprac_enable(gmu); - /* If anything goes south, tear the GPU down piece by piece.. */ - if (ret) { -err_bulk_clk: - pm_runtime_put(gmu->gxpd); - pm_runtime_put(gmu->dev); - dev_pm_opp_set_opp(&gpu->pdev->dev, NULL); - } -err_set_opp: mutex_unlock(&a6xx_gpu->gmu.lock); + msm_devfreq_resume(gpu); + a6xx_llc_activate(a6xx_gpu); - if (!ret) { - msm_devfreq_resume(gpu); - a6xx_llc_activate(a6xx_gpu); - } + return 0; + /* If anything goes south, tear the GPU down piece by piece.. */ +err_put_gxpd: + pm_runtime_put(gmu->gxpd); +err_put_dev: + pm_runtime_put(gmu->dev); +err_opp_clear: + dev_pm_opp_set_opp(&gpu->pdev->dev, NULL); +err_unlock: + mutex_unlock(&a6xx_gpu->gmu.lock); return ret; } diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h index b50c57f427b4..79912a33e17c 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -36,12 +36,26 @@ struct cpu_gpu_lock { uint64_t regs[]; }; +struct a6xx_limits_tbl { + /** @tbl: List of limits table **/ + struct a6xx_hfi_limits_tbl *tbl; + /** @count: Number of entries in the list **/ + u32 count; +}; + +#define DECLARE_ADRENO_LIMITS_TABLE(name) \ +static const struct a6xx_limits_tbl name = { \ + .tbl = name ## _tbl, \ + .count = ARRAY_SIZE(name ## _tbl), \ +} + /** * struct a6xx_info - a6xx specific information from device table * * @hwcg: hw clock gating register sequence * @protect: CP_PROTECT settings * @pwrup_reglist pwrup reglist for preemption + * @thinmem_config: GMU thinmem configuration */ struct a6xx_info { const struct adreno_reglist *hwcg; @@ -56,6 +70,9 @@ struct a6xx_info { u32 gmu_cgc_mode; u32 prim_fifo_threshold; const struct a6xx_bcm *bcms; + const struct a6xx_hfi_clx_table_v2_cmd *clx_tbl; + const struct a6xx_limits_tbl *limits_tbl; + u32 thinmem_config; }; struct a6xx_gpu { diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c index 186a73c0b99c..6b34e704a70d 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c @@ -888,6 +888,94 @@ static int a6xx_hfi_enable_acd(struct a6xx_gmu *gmu) return 0; } +static int a6xx_hfi_enable_iff_pclx(struct a6xx_gmu *gmu, const struct a6xx_limits_tbl *limits) +{ + struct a6xx_hfi_table_entry *entry; + struct a6xx_hfi_table *tbl; + size_t entry_size; + size_t size; + int ret; + + if (!limits) + return 0; + + ret = a6xx_hfi_feature_ctrl_msg(gmu, HFI_FEATURE_IFF_PCLX, 1, 0); + if (ret) { + DRM_DEV_ERROR(gmu->dev, "Unable to enable IFF PCLX (%d)\n", ret); + return ret; + } + + entry_size = limits->count * sizeof(struct a6xx_hfi_limits_tbl); + size = sizeof(*tbl) + sizeof(*entry) + entry_size; + + tbl = kzalloc(size, GFP_KERNEL); + if (!tbl) + return -ENOMEM; + + tbl->type = HFI_TABLE_LIMITS_MIT; + entry = &tbl->entry[0]; + entry->count = limits->count; + entry->stride = sizeof(struct a6xx_hfi_limits_tbl) >> 2; + + memcpy(entry->data, limits->tbl, entry_size); + + ret = a6xx_hfi_send_msg(gmu, HFI_H2F_MSG_TABLE, tbl, size, NULL, 0); + if (ret) + DRM_DEV_ERROR(gmu->dev, "Unable to send PCLX table (%d)\n", ret); + + kfree(tbl); + return ret; +} + +static int a6xx_hfi_enable_clx(struct a6xx_gmu *gmu) +{ + struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); + struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; + const struct a6xx_info *info = adreno_gpu->info->a6xx; + struct a6xx_hfi_clx_table_v2_cmd cmd = { 0 }; + int ret; + + if (!info->clx_tbl) + return 0; + + ret = a6xx_hfi_feature_ctrl_msg(gmu, HFI_FEATURE_CLX, 1, 0); + if (ret) { + DRM_DEV_ERROR(gmu->dev, "Unable to enable CLX (%d)\n", ret); + return ret; + } + + memcpy(&cmd, info->clx_tbl, sizeof(cmd)); + + ret = a6xx_hfi_send_msg(gmu, HFI_H2F_MSG_CLX_TBL, &cmd, sizeof(cmd), NULL, 0); + if (ret) { + DRM_DEV_ERROR(gmu->dev, "Unable to send CLX table (%d)\n", ret); + return ret; + } + + return a6xx_hfi_enable_iff_pclx(gmu, info->limits_tbl); +} + +static int a6xx_hfi_send_thinmem_config(struct a6xx_gmu *gmu) +{ + struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); + struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; + const struct a6xx_info *info = adreno_gpu->info->a6xx; + u32 data; + int ret; + + if (!info->thinmem_config) + return 0; + + /* Bits [7:4] contain the thinmem_cfg data. */ + data = FIELD_PREP(GENMASK(7, 4), info->thinmem_config); + + ret = a6xx_hfi_feature_ctrl_msg(gmu, HFI_FEATURE_THINMEM_CFG, 1, data); + if (ret) + DRM_DEV_ERROR(gmu->dev, "Unable to send THINMEM_CFG (%d)\n", ret); + + return ret; +} + static int a6xx_hfi_send_test(struct a6xx_gmu *gmu) { struct a6xx_hfi_msg_test msg = { 0 }; @@ -989,10 +1077,18 @@ int a6xx_hfi_start(struct a6xx_gmu *gmu, int boot_state) if (ret) return ret; + ret = a6xx_hfi_enable_clx(gmu); + if (ret) + return ret; + ret = a6xx_hfi_enable_ifpc(gmu); if (ret) return ret; + ret = a6xx_hfi_send_thinmem_config(gmu); + if (ret) + return ret; + ret = a6xx_hfi_send_core_fw_start(gmu); if (ret) return ret; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.h b/drivers/gpu/drm/msm/adreno/a6xx_hfi.h index e10d32ce93e0..5123349a3de6 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.h @@ -244,6 +244,7 @@ struct a6xx_hfi_msg_feature_ctrl { #define HFI_FEATURE_TDCVS 30 #define HFI_FEATURE_DCE 31 #define HFI_FEATURE_IFF_PCLX 32 +#define HFI_FEATURE_THINMEM_CFG 38 #define HFI_FEATURE_SOFT_RESET 0x10000001 #define HFI_FEATURE_DCVS_PROFILE 0x10000002 #define HFI_FEATURE_FAST_CTX_DESTROY 0x10000003 diff --git a/drivers/gpu/drm/msm/adreno/a7xx_catalog.c b/drivers/gpu/drm/msm/adreno/a7xx_catalog.c new file mode 100644 index 000000000000..6f704898cea6 --- /dev/null +++ b/drivers/gpu/drm/msm/adreno/a7xx_catalog.c @@ -0,0 +1,502 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2013-2014 Red Hat + * Author: Rob Clark <robdclark@gmail.com> + * + * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved. + */ + +#include "adreno_gpu.h" +#include "a6xx_gpu.h" +#include "a6xx.xml.h" + +/* gbif reglist is same as a640: */ +static const struct adreno_reglist a640_gbif[] = { + { REG_A6XX_GBIF_QSB_SIDE0, 0x00071620 }, + { REG_A6XX_GBIF_QSB_SIDE1, 0x00071620 }, + { REG_A6XX_GBIF_QSB_SIDE2, 0x00071620 }, + { REG_A6XX_GBIF_QSB_SIDE3, 0x00071620 }, + { }, +}; + +static const struct adreno_reglist a730_hwcg[] = { + { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222 }, + { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022222 }, + { REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf }, + { REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080 }, + { REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222220 }, + { REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222 }, + { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22220222 }, + { REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00222222 }, + { REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777 }, + { REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777 }, + { REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777 }, + { REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777 }, + { REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111 }, + { REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111 }, + { REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111 }, + { REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111 }, + { REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222 }, + { REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004 }, + { REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002 }, + { REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222 }, + { REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222 }, + { REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220 }, + { REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x44000f00 }, + { REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022 }, + { REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00555555 }, + { REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011 }, + { REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00440044 }, + { REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222 }, + { REG_A7XX_RBBM_CLOCK_MODE2_GRAS, 0x00000222 }, + { REG_A7XX_RBBM_CLOCK_MODE_BV_GRAS, 0x00222222 }, + { REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222223 }, + { REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222 }, + { REG_A7XX_RBBM_CLOCK_MODE_BV_GPC, 0x00222222 }, + { REG_A7XX_RBBM_CLOCK_MODE_BV_VFD, 0x00002222 }, + { REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 }, + { REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000 }, + { REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200 }, + { REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222 }, + { REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222 }, + { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002 }, + { REG_A7XX_RBBM_CLOCK_MODE_BV_LRZ, 0x55555552 }, + { REG_A7XX_RBBM_CLOCK_MODE_CP, 0x00000223 }, + { REG_A6XX_RBBM_CLOCK_CNTL, 0x8aa8aa82 }, + { REG_A6XX_RBBM_ISDB_CNT, 0x00000182 }, + { REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000 }, + { REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222 }, + { REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111 }, + { REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555 }, + {}, +}; + +static const struct adreno_reglist a740_hwcg[] = { + { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222 }, + { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x22022222 }, + { REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x003cf3cf }, + { REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080 }, + { REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222220 }, + { REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222 }, + { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222 }, + { REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00222222 }, + { REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777 }, + { REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777 }, + { REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777 }, + { REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777 }, + { REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111 }, + { REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111 }, + { REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111 }, + { REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111 }, + { REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222 }, + { REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x00222222 }, + { REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000444 }, + { REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000222 }, + { REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222 }, + { REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222 }, + { REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220 }, + { REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x44000f00 }, + { REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022 }, + { REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00555555 }, + { REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011 }, + { REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00440044 }, + { REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222 }, + { REG_A7XX_RBBM_CLOCK_MODE2_GRAS, 0x00000222 }, + { REG_A7XX_RBBM_CLOCK_MODE_BV_GRAS, 0x00222222 }, + { REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222223 }, + { REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00222222 }, + { REG_A7XX_RBBM_CLOCK_MODE_BV_GPC, 0x00222222 }, + { REG_A7XX_RBBM_CLOCK_MODE_BV_VFD, 0x00002222 }, + { REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 }, + { REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200 }, + { REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222 }, + { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000 }, + { REG_A7XX_RBBM_CLOCK_MODE_BV_LRZ, 0x55555552 }, + { REG_A7XX_RBBM_CLOCK_HYST2_VFD, 0x00000000 }, + { REG_A7XX_RBBM_CLOCK_MODE_CP, 0x00000222 }, + { REG_A6XX_RBBM_CLOCK_CNTL, 0x8aa8aa82 }, + { REG_A6XX_RBBM_ISDB_CNT, 0x00000182 }, + { REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000 }, + { REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222 }, + { REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111 }, + { REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555 }, + {}, +}; + +static const u32 a730_protect_regs[] = { + A6XX_PROTECT_RDONLY(0x00000, 0x04ff), + A6XX_PROTECT_RDONLY(0x0050b, 0x0058), + A6XX_PROTECT_NORDWR(0x0050e, 0x0000), + A6XX_PROTECT_NORDWR(0x00510, 0x0000), + A6XX_PROTECT_NORDWR(0x00534, 0x0000), + A6XX_PROTECT_RDONLY(0x005fb, 0x009d), + A6XX_PROTECT_NORDWR(0x00699, 0x01e9), + A6XX_PROTECT_NORDWR(0x008a0, 0x0008), + A6XX_PROTECT_NORDWR(0x008ab, 0x0024), + /* 0x008d0-0x008dd and 0x008e0-0x008e6 are unprotected on purpose for tools like perfetto */ + A6XX_PROTECT_NORDWR(0x008de, 0x0001), + A6XX_PROTECT_RDONLY(0x008e7, 0x014b), + A6XX_PROTECT_NORDWR(0x00900, 0x004d), + A6XX_PROTECT_NORDWR(0x0098d, 0x00b2), + A6XX_PROTECT_NORDWR(0x00a41, 0x01be), + A6XX_PROTECT_NORDWR(0x00df0, 0x0001), + A6XX_PROTECT_NORDWR(0x00e01, 0x0000), + A6XX_PROTECT_NORDWR(0x00e07, 0x0008), + A6XX_PROTECT_NORDWR(0x03c00, 0x00c3), + A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff), + A6XX_PROTECT_NORDWR(0x08630, 0x01cf), + A6XX_PROTECT_NORDWR(0x08e00, 0x0000), + A6XX_PROTECT_NORDWR(0x08e08, 0x0000), + A6XX_PROTECT_NORDWR(0x08e50, 0x001f), + A6XX_PROTECT_NORDWR(0x08e80, 0x0280), + A6XX_PROTECT_NORDWR(0x09624, 0x01db), + A6XX_PROTECT_NORDWR(0x09e40, 0x0000), + A6XX_PROTECT_NORDWR(0x09e64, 0x000d), + A6XX_PROTECT_NORDWR(0x09e78, 0x0187), + A6XX_PROTECT_NORDWR(0x0a630, 0x01cf), + A6XX_PROTECT_NORDWR(0x0ae02, 0x0000), + A6XX_PROTECT_NORDWR(0x0ae50, 0x000f), + A6XX_PROTECT_NORDWR(0x0ae66, 0x0003), + A6XX_PROTECT_NORDWR(0x0ae6f, 0x0003), + A6XX_PROTECT_NORDWR(0x0b604, 0x0003), + A6XX_PROTECT_NORDWR(0x0ec00, 0x0fff), + A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), + A6XX_PROTECT_NORDWR(0x18400, 0x0053), + A6XX_PROTECT_RDONLY(0x18454, 0x0004), + A6XX_PROTECT_NORDWR(0x18459, 0x1fff), + A6XX_PROTECT_NORDWR(0x1a459, 0x1fff), + A6XX_PROTECT_NORDWR(0x1c459, 0x1fff), + A6XX_PROTECT_NORDWR(0x1f400, 0x0443), + A6XX_PROTECT_RDONLY(0x1f844, 0x007b), + A6XX_PROTECT_NORDWR(0x1f860, 0x0000), + A6XX_PROTECT_NORDWR(0x1f878, 0x002a), + /* CP_PROTECT_REG[45, 46] are left untouched! */ + 0, + 0, + A6XX_PROTECT_NORDWR(0x1f8c0, 0x00000), +}; +DECLARE_ADRENO_PROTECT(a730_protect, 48); + +static const uint32_t a7xx_pwrup_reglist_regs[] = { + REG_A6XX_UCHE_TRAP_BASE, + REG_A6XX_UCHE_TRAP_BASE + 1, + REG_A6XX_UCHE_WRITE_THRU_BASE, + REG_A6XX_UCHE_WRITE_THRU_BASE + 1, + REG_A6XX_UCHE_GMEM_RANGE_MIN, + REG_A6XX_UCHE_GMEM_RANGE_MIN + 1, + REG_A6XX_UCHE_GMEM_RANGE_MAX, + REG_A6XX_UCHE_GMEM_RANGE_MAX + 1, + REG_A6XX_UCHE_CACHE_WAYS, + REG_A6XX_UCHE_MODE_CNTL, + REG_A6XX_RB_NC_MODE_CNTL, + REG_A6XX_RB_CMP_DBG_ECO_CNTL, + REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE, + REG_A6XX_UCHE_GBIF_GX_CONFIG, + REG_A6XX_UCHE_CLIENT_PF, + REG_A6XX_TPL1_DBG_ECO_CNTL1, +}; + +DECLARE_ADRENO_REGLIST_LIST(a7xx_pwrup_reglist); + +/* Applicable for X185, A750 */ +static const u32 a750_ifpc_reglist_regs[] = { + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(0), + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(1), + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(2), + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(3), + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(4), + REG_A6XX_RBBM_PERFCTR_CNTL, + REG_A6XX_TPL1_NC_MODE_CNTL, + REG_A6XX_SP_NC_MODE_CNTL, + REG_A6XX_CP_DBG_ECO_CNTL, + REG_A6XX_CP_PROTECT_CNTL, + REG_A6XX_CP_PROTECT(0), + REG_A6XX_CP_PROTECT(1), + REG_A6XX_CP_PROTECT(2), + REG_A6XX_CP_PROTECT(3), + REG_A6XX_CP_PROTECT(4), + REG_A6XX_CP_PROTECT(5), + REG_A6XX_CP_PROTECT(6), + REG_A6XX_CP_PROTECT(7), + REG_A6XX_CP_PROTECT(8), + REG_A6XX_CP_PROTECT(9), + REG_A6XX_CP_PROTECT(10), + REG_A6XX_CP_PROTECT(11), + REG_A6XX_CP_PROTECT(12), + REG_A6XX_CP_PROTECT(13), + REG_A6XX_CP_PROTECT(14), + REG_A6XX_CP_PROTECT(15), + REG_A6XX_CP_PROTECT(16), + REG_A6XX_CP_PROTECT(17), + REG_A6XX_CP_PROTECT(18), + REG_A6XX_CP_PROTECT(19), + REG_A6XX_CP_PROTECT(20), + REG_A6XX_CP_PROTECT(21), + REG_A6XX_CP_PROTECT(22), + REG_A6XX_CP_PROTECT(23), + REG_A6XX_CP_PROTECT(24), + REG_A6XX_CP_PROTECT(25), + REG_A6XX_CP_PROTECT(26), + REG_A6XX_CP_PROTECT(27), + REG_A6XX_CP_PROTECT(28), + REG_A6XX_CP_PROTECT(29), + REG_A6XX_CP_PROTECT(30), + REG_A6XX_CP_PROTECT(31), + REG_A6XX_CP_PROTECT(32), + REG_A6XX_CP_PROTECT(33), + REG_A6XX_CP_PROTECT(34), + REG_A6XX_CP_PROTECT(35), + REG_A6XX_CP_PROTECT(36), + REG_A6XX_CP_PROTECT(37), + REG_A6XX_CP_PROTECT(38), + REG_A6XX_CP_PROTECT(39), + REG_A6XX_CP_PROTECT(40), + REG_A6XX_CP_PROTECT(41), + REG_A6XX_CP_PROTECT(42), + REG_A6XX_CP_PROTECT(43), + REG_A6XX_CP_PROTECT(44), + REG_A6XX_CP_PROTECT(45), + REG_A6XX_CP_PROTECT(46), + REG_A6XX_CP_PROTECT(47), +}; + +DECLARE_ADRENO_REGLIST_LIST(a750_ifpc_reglist); + +static const struct adreno_reglist_pipe a7xx_dyn_pwrup_reglist_regs[] = { + { REG_A7XX_GRAS_NC_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, +}; + +DECLARE_ADRENO_REGLIST_PIPE_LIST(a7xx_dyn_pwrup_reglist); + +static const struct adreno_info a7xx_gpus[] = { + { + .chip_ids = ADRENO_CHIP_IDS(0x07030001), + .family = ADRENO_7XX_GEN1, + .fw = { + [ADRENO_FW_SQE] = "a730_sqe.fw", + [ADRENO_FW_GMU] = "gmu_gen70000.bin", + }, + .gmem = SZ_2M, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV | + ADRENO_QUIRK_PREEMPTION, + .funcs = &a7xx_gpu_funcs, + .zapfw = "a730_zap.mdt", + .a6xx = &(const struct a6xx_info) { + .hwcg = a730_hwcg, + .protect = &a730_protect, + .pwrup_reglist = &a7xx_pwrup_reglist, + .dyn_pwrup_reglist = &a7xx_dyn_pwrup_reglist, + .gbif_cx = a640_gbif, + .gmu_cgc_mode = 0x00020000, + }, + .preempt_record_size = 2860 * SZ_1K, + }, { + .chip_ids = ADRENO_CHIP_IDS(0x43020100), + .family = ADRENO_7XX_GEN1, + .fw = { + [ADRENO_FW_SQE] = "qcom/gen71700_sqe.fw", + [ADRENO_FW_GMU] = "qcom/gen71700_gmu.bin", + }, + .gmem = SZ_1M, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV | + ADRENO_QUIRK_PREEMPTION, + .funcs = &a7xx_gpu_funcs, + .a6xx = &(const struct a6xx_info) { + .hwcg = a730_hwcg, + .protect = &a730_protect, + .pwrup_reglist = &a7xx_pwrup_reglist, + .dyn_pwrup_reglist = &a7xx_dyn_pwrup_reglist, + .gbif_cx = a640_gbif, + .gmu_chipid = 0x07110000, + .gmu_cgc_mode = 0x00020000, + .bcms = (const struct a6xx_bcm[]) { + { .name = "SH0", .buswidth = 16 }, + { .name = "MC0", .buswidth = 4 }, + { + .name = "ACV", + .fixed = true, + .perfmode = BIT(3), + .perfmode_bw = 16500000, + }, + { /* sentinel */ }, + }, + }, + .preempt_record_size = 1536 * SZ_1K, + }, { + .chip_ids = ADRENO_CHIP_IDS(0x43050a01), /* "C510v2" */ + .family = ADRENO_7XX_GEN2, + .fw = { + [ADRENO_FW_SQE] = "a740_sqe.fw", + [ADRENO_FW_GMU] = "gmu_gen70200.bin", + }, + .gmem = 3 * SZ_1M, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV | + ADRENO_QUIRK_PREEMPTION, + .funcs = &a7xx_gpu_funcs, + .zapfw = "a740_zap.mdt", + .a6xx = &(const struct a6xx_info) { + .hwcg = a740_hwcg, + .protect = &a730_protect, + .pwrup_reglist = &a7xx_pwrup_reglist, + .dyn_pwrup_reglist = &a7xx_dyn_pwrup_reglist, + .gbif_cx = a640_gbif, + .gmu_chipid = 0x7020100, + .gmu_cgc_mode = 0x00020202, + .bcms = (const struct a6xx_bcm[]) { + { .name = "SH0", .buswidth = 16 }, + { .name = "MC0", .buswidth = 4 }, + { + .name = "ACV", + .fixed = true, + .perfmode = BIT(3), + .perfmode_bw = 16500000, + }, + { /* sentinel */ }, + }, + }, + .preempt_record_size = 4192 * SZ_1K, + }, { + .chip_ids = ADRENO_CHIP_IDS(0x43050c01), /* "C512v2" */ + .family = ADRENO_7XX_GEN2, + .fw = { + [ADRENO_FW_SQE] = "gen70500_sqe.fw", + [ADRENO_FW_GMU] = "gen70500_gmu.bin", + }, + .gmem = 3 * SZ_1M, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV | + ADRENO_QUIRK_PREEMPTION | + ADRENO_QUIRK_IFPC, + .funcs = &a7xx_gpu_funcs, + .a6xx = &(const struct a6xx_info) { + .hwcg = a740_hwcg, + .protect = &a730_protect, + .pwrup_reglist = &a7xx_pwrup_reglist, + .dyn_pwrup_reglist = &a7xx_dyn_pwrup_reglist, + .ifpc_reglist = &a750_ifpc_reglist, + .gbif_cx = a640_gbif, + .gmu_chipid = 0x7050001, + .gmu_cgc_mode = 0x00020202, + .bcms = (const struct a6xx_bcm[]) { + { .name = "SH0", .buswidth = 16 }, + { .name = "MC0", .buswidth = 4 }, + { + .name = "ACV", + .fixed = true, + .perfmode = BIT(3), + .perfmode_bw = 16500000, + }, + { /* sentinel */ }, + }, + }, + .preempt_record_size = 4192 * SZ_1K, + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 59, 1 }, + { 7, 2 }, + { 232, 3 }, + { 146, 4 }, + ), + }, { + .chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */ + .family = ADRENO_7XX_GEN3, + .fw = { + [ADRENO_FW_SQE] = "gen70900_sqe.fw", + [ADRENO_FW_GMU] = "gmu_gen70900.bin", + }, + .gmem = 3 * SZ_1M, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV | + ADRENO_QUIRK_PREEMPTION | + ADRENO_QUIRK_IFPC, + .funcs = &a7xx_gpu_funcs, + .zapfw = "gen70900_zap.mbn", + .a6xx = &(const struct a6xx_info) { + .protect = &a730_protect, + .pwrup_reglist = &a7xx_pwrup_reglist, + .dyn_pwrup_reglist = &a7xx_dyn_pwrup_reglist, + .ifpc_reglist = &a750_ifpc_reglist, + .gbif_cx = a640_gbif, + .gmu_chipid = 0x7090100, + .gmu_cgc_mode = 0x00020202, + .bcms = (const struct a6xx_bcm[]) { + { .name = "SH0", .buswidth = 16 }, + { .name = "MC0", .buswidth = 4 }, + { + .name = "ACV", + .fixed = true, + .perfmode = BIT(2), + .perfmode_bw = 10687500, + }, + { /* sentinel */ }, + }, + }, + .preempt_record_size = 3572 * SZ_1K, + }, { + .chip_ids = ADRENO_CHIP_IDS(0x43030c00), + .family = ADRENO_7XX_GEN2, + .fw = { + [ADRENO_FW_SQE] = "gen71500_sqe.fw", + [ADRENO_FW_GMU] = "gen71500_gmu.bin", + }, + .gmem = SZ_1M + SZ_512K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV | + ADRENO_QUIRK_PREEMPTION, + .funcs = &a7xx_gpu_funcs, + .a6xx = &(const struct a6xx_info) { + .hwcg = a740_hwcg, + .protect = &a730_protect, + .pwrup_reglist = &a7xx_pwrup_reglist, + .dyn_pwrup_reglist = &a7xx_dyn_pwrup_reglist, + .gbif_cx = a640_gbif, + .gmu_chipid = 0x70f0000, + .gmu_cgc_mode = 0x00020222, + .bcms = (const struct a6xx_bcm[]) { + { .name = "SH0", .buswidth = 16 }, + { .name = "MC0", .buswidth = 4 }, + { + .name = "ACV", + .fixed = true, + .perfmode = BIT(3), + .perfmode_bw = 16500000, + }, + { /* sentinel */ }, + }, + }, + .preempt_record_size = 4192 * SZ_1K, + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 294, 1 }, + { 263, 2 }, + { 233, 3 }, + { 141, 4 }, + ), + } +}; +DECLARE_ADRENO_GPULIST(a7xx); + +static inline __always_unused void __build_asserts(void) +{ + BUILD_BUG_ON(a730_protect.count > a730_protect.count_max); +} diff --git a/drivers/gpu/drm/msm/adreno/a8xx_catalog.c b/drivers/gpu/drm/msm/adreno/a8xx_catalog.c new file mode 100644 index 000000000000..55a805ab438c --- /dev/null +++ b/drivers/gpu/drm/msm/adreno/a8xx_catalog.c @@ -0,0 +1,1846 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2013-2014 Red Hat + * Author: Rob Clark <robdclark@gmail.com> + * + * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved. + */ + +#include "adreno_gpu.h" +#include "a6xx_gpu.h" +#include "a6xx.xml.h" + +static const struct adreno_reglist_pipe a830_nonctxt_regs[] = { + { REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) }, + { REG_A8XX_GRAS_DBG_ECO_CNTL, 0x00000800, BIT(PIPE_BR) | BIT(PIPE_BV) }, + { REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0x00000001, BIT(PIPE_BR) | BIT(PIPE_BV) }, + { REG_A8XX_PC_VIS_STREAM_CNTL, 0x10010000, BIT(PIPE_BR) | BIT(PIPE_BV) }, + { REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0x00000002, BIT(PIPE_BR) | BIT(PIPE_BV) }, + { REG_A8XX_PC_CHICKEN_BITS_1, 0x00000003, BIT(PIPE_BR) | BIT(PIPE_BV) }, + { REG_A8XX_PC_CHICKEN_BITS_2, 0x00000200, BIT(PIPE_BR) | BIT(PIPE_BV) }, + { REG_A8XX_PC_CHICKEN_BITS_3, 0x00400000, BIT(PIPE_BR) | BIT(PIPE_BV) }, + { REG_A8XX_PC_CHICKEN_BITS_4, 0x00500050, BIT(PIPE_BR) | BIT(PIPE_BV) }, + /* Configure GBIF GX registers */ + { REG_A8XX_UCHE_GBIF_GX_CONFIG, 0x010240e0, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x22122212, BIT(PIPE_NONE) }, + /* Enable full concurrent resolve and unresolves */ + { REG_A7XX_RB_CCU_CNTL, 0x00000068, BIT(PIPE_BR) }, + /* Partially enable perf clear, Disable DINT to c/z be data forwarding */ + { REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0x00002200, BIT(PIPE_BR) }, + { REG_A8XX_RB_GC_GMEM_PROTECT, 0x0c000000, BIT(PIPE_BR) }, + /* Configure number of outstanding transactions to 32 */ + { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0x00000007, BIT(PIPE_BR) }, + /* Configure UCHE request time out to 16 cycles for CCU/UCHE arbitration */ + { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0x00004000, BIT(PIPE_BR) }, + { REG_A8XX_RBBM_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_SLICE_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL, 0x00000030, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL2, 0x00000030, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_CGC_P2S_CNTL, 0x00000040, BIT(PIPE_NONE) }, + /* Enable contribution of all shader stages to SP perfcounters */ + { REG_A6XX_SP_PERFCTR_SHADER_MASK, 0x0000003f, BIT(PIPE_NONE) }, + /* + * BIT(26): Limit the number of wave-slots for Eviction buffer to 1 per ALU GRP + * BIT(30): Disable LPAC auto-promotion + */ + { REG_A7XX_SP_CHICKEN_BITS_1, BIT(26) | BIT(30), BIT(PIPE_NONE) }, + /* + * BIT(22): Disable PS out of order retire + * BIT(23): Enable half wave mode and MM instruction src&dst is half precision + */ + { REG_A7XX_SP_CHICKEN_BITS_2, BIT(22) | BIT(23), BIT(PIPE_NONE) }, + { REG_A7XX_SP_CHICKEN_BITS_3, 0x00300000, BIT(PIPE_NONE) }, + { REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, 0x00000080, BIT(PIPE_NONE) }, + { REG_A6XX_TPL1_DBG_ECO_CNTL, 0x10000000, BIT(PIPE_NONE) }, + /* Enable cubemap small miplevel optimization settings */ + /* BIT(26): Disable final clamp for bicubic filtering */ + { REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x04000724, BIT(PIPE_NONE) }, + /* Disable tag bank id hashing */ + { REG_A6XX_UCHE_MODE_CNTL, 0x00080000, BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_CCHE_MODE_CNTL, 0x00001000, BIT(PIPE_NONE) }, + /* Limit gmem number of ways for GMEM requests in each set */ + { REG_A8XX_UCHE_CCHE_CACHE_WAYS, 0x00000800, BIT(PIPE_NONE)}, + /* Disable write slow pointer in data phase queue */ + { REG_A8XX_UCHE_HW_DBG_CNTL, BIT(8), BIT(PIPE_NONE) }, + /* Configure UCHE to CCU switchthreshold timeout cycles */ + { REG_A8XX_UCHE_VARB_IDLE_TIMEOUT, 0x00000020, BIT(PIPE_NONE) }, + { REG_A7XX_VFD_DBG_ECO_CNTL, 0x00008000, BIT(PIPE_BR) | BIT(PIPE_BV) }, + { REG_A8XX_VFD_CB_BV_THRESHOLD, 0x00500050, BIT(PIPE_BR) | BIT(PIPE_BV) }, + { REG_A8XX_VFD_CB_BR_THRESHOLD, 0x00600060, BIT(PIPE_BR) | BIT(PIPE_BV) }, + { REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0x00200020, BIT(PIPE_BR) | BIT(PIPE_BV) }, + { REG_A8XX_VFD_CB_LP_REQ_CNT, 0x00100020, BIT(PIPE_BR) | BIT(PIPE_BV) }, + { REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0x00000001, BIT(PIPE_BR) | BIT(PIPE_BV) }, + /* Disable redundant tile data optimization */ + { REG_A8XX_VSC_KMD_DBG_ECO_CNTL, BIT(11), BIT(PIPE_NONE)}, + { }, +}; + +static const u32 a830_protect_regs[] = { + A6XX_PROTECT_RDONLY(0x00000, 0x03a3), + A6XX_PROTECT_RDONLY(0x003b4, 0x008b), + A6XX_PROTECT_NORDWR(0x00440, 0x001f), + A6XX_PROTECT_RDONLY(0x00580, 0x005f), + A6XX_PROTECT_NORDWR(0x005e0, 0x011f), + A6XX_PROTECT_RDONLY(0x0074a, 0x0005), + A6XX_PROTECT_RDONLY(0x00759, 0x0026), + A6XX_PROTECT_RDONLY(0x00789, 0x0000), + A6XX_PROTECT_RDONLY(0x0078c, 0x0013), + A6XX_PROTECT_NORDWR(0x00800, 0x0029), + A6XX_PROTECT_NORDWR(0x00837, 0x00af), + A6XX_PROTECT_RDONLY(0x008e7, 0x00c9), + A6XX_PROTECT_NORDWR(0x008ec, 0x00c3), + A6XX_PROTECT_NORDWR(0x009b1, 0x0250), + A6XX_PROTECT_RDONLY(0x00ce0, 0x0001), + A6XX_PROTECT_RDONLY(0x00df0, 0x0000), + A6XX_PROTECT_NORDWR(0x00df1, 0x0000), + A6XX_PROTECT_NORDWR(0x00e01, 0x0000), + A6XX_PROTECT_NORDWR(0x00e03, 0x1fff), + A6XX_PROTECT_NORDWR(0x03c00, 0x00c5), + A6XX_PROTECT_RDONLY(0x03cc6, 0x1fff), + A6XX_PROTECT_NORDWR(0x08600, 0x01ff), + A6XX_PROTECT_NORDWR(0x08e00, 0x00ff), + A6XX_PROTECT_RDONLY(0x08f00, 0x0000), + A6XX_PROTECT_NORDWR(0x08f01, 0x01be), + A6XX_PROTECT_NORDWR(0x09600, 0x01ff), + A6XX_PROTECT_RDONLY(0x0981a, 0x02e5), + A6XX_PROTECT_NORDWR(0x09e00, 0x01ff), + A6XX_PROTECT_NORDWR(0x0a600, 0x01ff), + A6XX_PROTECT_NORDWR(0x0ae00, 0x0000), + A6XX_PROTECT_NORDWR(0x0ae02, 0x0004), + A6XX_PROTECT_NORDWR(0x0ae08, 0x0006), + A6XX_PROTECT_NORDWR(0x0ae10, 0x036f), + A6XX_PROTECT_NORDWR(0x0b600, 0x1fff), + A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff), + A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), + A6XX_PROTECT_NORDWR(0x18400, 0x003f), + A6XX_PROTECT_RDONLY(0x18440, 0x013f), + A6XX_PROTECT_NORDWR(0x18580, 0x1fff), + A6XX_PROTECT_NORDWR(0x1b400, 0x1fff), + A6XX_PROTECT_NORDWR(0x1f400, 0x0477), + A6XX_PROTECT_RDONLY(0x1f878, 0x0787), + A6XX_PROTECT_NORDWR(0x1f930, 0x0329), + A6XX_PROTECT_NORDWR(0x20000, 0x1fff), + A6XX_PROTECT_NORDWR(0x27800, 0x007f), + A6XX_PROTECT_RDONLY(0x27880, 0x0381), + A6XX_PROTECT_NORDWR(0x27882, 0x0001), + A6XX_PROTECT_NORDWR(0x27c02, 0x0000), +}; +DECLARE_ADRENO_PROTECT(a830_protect, 64); + +static const u32 a830_pwrup_reglist_regs[] = { + REG_A6XX_UCHE_MODE_CNTL, + REG_A8XX_UCHE_VARB_IDLE_TIMEOUT, + REG_A8XX_UCHE_GBIF_GX_CONFIG, + REG_A8XX_UCHE_CACHE_WAYS, + REG_A8XX_UCHE_CCHE_MODE_CNTL, + REG_A8XX_UCHE_CCHE_CACHE_WAYS, + REG_A8XX_UCHE_CCHE_GC_GMEM_RANGE_MIN, + REG_A8XX_UCHE_CCHE_GC_GMEM_RANGE_MIN + 1, + REG_A8XX_UCHE_CCHE_LPAC_GMEM_RANGE_MIN, + REG_A8XX_UCHE_CCHE_LPAC_GMEM_RANGE_MIN + 1, + REG_A8XX_UCHE_CCHE_TRAP_BASE, + REG_A8XX_UCHE_CCHE_TRAP_BASE + 1, + REG_A8XX_UCHE_CCHE_WRITE_THRU_BASE, + REG_A8XX_UCHE_CCHE_WRITE_THRU_BASE + 1, + REG_A8XX_UCHE_HW_DBG_CNTL, + REG_A8XX_UCHE_WRITE_THRU_BASE, + REG_A8XX_UCHE_WRITE_THRU_BASE + 1, + REG_A8XX_UCHE_TRAP_BASE, + REG_A8XX_UCHE_TRAP_BASE + 1, + REG_A8XX_UCHE_CLIENT_PF, + REG_A8XX_VSC_KMD_DBG_ECO_CNTL, + REG_A8XX_RB_CMP_NC_MODE_CNTL, + REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, + REG_A8XX_SP_HLSQ_GC_GMEM_RANGE_MIN, + REG_A8XX_SP_HLSQ_GC_GMEM_RANGE_MIN + 1, + REG_A7XX_SP_READ_SEL, + REG_A6XX_TPL1_NC_MODE_CNTL, + REG_A6XX_TPL1_DBG_ECO_CNTL, + REG_A6XX_TPL1_DBG_ECO_CNTL1, + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(0), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(1), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(2), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(3), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(4), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(5), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(6), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(7), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(8), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(9), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(10), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(11), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(12), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(13), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(14), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(15), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(16), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(17), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(18), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(19), +}; +DECLARE_ADRENO_REGLIST_LIST(a830_pwrup_reglist); + +static const u32 a830_ifpc_reglist_regs[] = { + REG_A8XX_RBBM_NC_MODE_CNTL, + REG_A8XX_RBBM_SLICE_INTERFACE_HANG_INT_CNTL, + REG_A8XX_RBBM_SLICE_NC_MODE_CNTL, + REG_A6XX_SP_NC_MODE_CNTL, + REG_A8XX_SP_HLSQ_LPAC_GMEM_RANGE_MIN, + REG_A8XX_SP_HLSQ_LPAC_GMEM_RANGE_MIN + 1, + REG_A7XX_SP_CHICKEN_BITS_1, + REG_A7XX_SP_CHICKEN_BITS_2, + REG_A7XX_SP_CHICKEN_BITS_3, + REG_A6XX_SP_PERFCTR_SHADER_MASK, + REG_A7XX_SP_HLSQ_DBG_ECO_CNTL, + REG_A8XX_CP_INTERRUPT_STATUS_MASK_GLOBAL, + REG_A8XX_RBBM_PERFCTR_CNTL, + REG_A8XX_CP_PROTECT_GLOBAL(0), + REG_A8XX_CP_PROTECT_GLOBAL(1), + REG_A8XX_CP_PROTECT_GLOBAL(2), + REG_A8XX_CP_PROTECT_GLOBAL(3), + REG_A8XX_CP_PROTECT_GLOBAL(4), + REG_A8XX_CP_PROTECT_GLOBAL(5), + REG_A8XX_CP_PROTECT_GLOBAL(6), + REG_A8XX_CP_PROTECT_GLOBAL(7), + REG_A8XX_CP_PROTECT_GLOBAL(8), + REG_A8XX_CP_PROTECT_GLOBAL(9), + REG_A8XX_CP_PROTECT_GLOBAL(10), + REG_A8XX_CP_PROTECT_GLOBAL(11), + REG_A8XX_CP_PROTECT_GLOBAL(12), + REG_A8XX_CP_PROTECT_GLOBAL(13), + REG_A8XX_CP_PROTECT_GLOBAL(14), + REG_A8XX_CP_PROTECT_GLOBAL(15), + REG_A8XX_CP_PROTECT_GLOBAL(16), + REG_A8XX_CP_PROTECT_GLOBAL(17), + REG_A8XX_CP_PROTECT_GLOBAL(18), + REG_A8XX_CP_PROTECT_GLOBAL(19), + REG_A8XX_CP_PROTECT_GLOBAL(20), + REG_A8XX_CP_PROTECT_GLOBAL(21), + REG_A8XX_CP_PROTECT_GLOBAL(22), + REG_A8XX_CP_PROTECT_GLOBAL(23), + REG_A8XX_CP_PROTECT_GLOBAL(24), + REG_A8XX_CP_PROTECT_GLOBAL(25), + REG_A8XX_CP_PROTECT_GLOBAL(26), + REG_A8XX_CP_PROTECT_GLOBAL(27), + REG_A8XX_CP_PROTECT_GLOBAL(28), + REG_A8XX_CP_PROTECT_GLOBAL(29), + REG_A8XX_CP_PROTECT_GLOBAL(30), + REG_A8XX_CP_PROTECT_GLOBAL(31), + REG_A8XX_CP_PROTECT_GLOBAL(32), + REG_A8XX_CP_PROTECT_GLOBAL(33), + REG_A8XX_CP_PROTECT_GLOBAL(34), + REG_A8XX_CP_PROTECT_GLOBAL(35), + REG_A8XX_CP_PROTECT_GLOBAL(36), + REG_A8XX_CP_PROTECT_GLOBAL(37), + REG_A8XX_CP_PROTECT_GLOBAL(38), + REG_A8XX_CP_PROTECT_GLOBAL(39), + REG_A8XX_CP_PROTECT_GLOBAL(40), + REG_A8XX_CP_PROTECT_GLOBAL(41), + REG_A8XX_CP_PROTECT_GLOBAL(42), + REG_A8XX_CP_PROTECT_GLOBAL(43), + REG_A8XX_CP_PROTECT_GLOBAL(44), + REG_A8XX_CP_PROTECT_GLOBAL(45), + REG_A8XX_CP_PROTECT_GLOBAL(46), + REG_A8XX_CP_PROTECT_GLOBAL(47), + REG_A8XX_CP_PROTECT_GLOBAL(48), + REG_A8XX_CP_PROTECT_GLOBAL(49), + REG_A8XX_CP_PROTECT_GLOBAL(50), + REG_A8XX_CP_PROTECT_GLOBAL(51), + REG_A8XX_CP_PROTECT_GLOBAL(52), + REG_A8XX_CP_PROTECT_GLOBAL(53), + REG_A8XX_CP_PROTECT_GLOBAL(54), + REG_A8XX_CP_PROTECT_GLOBAL(55), + REG_A8XX_CP_PROTECT_GLOBAL(56), + REG_A8XX_CP_PROTECT_GLOBAL(57), + REG_A8XX_CP_PROTECT_GLOBAL(58), + REG_A8XX_CP_PROTECT_GLOBAL(59), + REG_A8XX_CP_PROTECT_GLOBAL(60), + REG_A8XX_CP_PROTECT_GLOBAL(61), + REG_A8XX_CP_PROTECT_GLOBAL(62), + REG_A8XX_CP_PROTECT_GLOBAL(63), +}; +DECLARE_ADRENO_REGLIST_LIST(a830_ifpc_reglist); + +static const struct adreno_reglist_pipe a830_dyn_pwrup_reglist_regs[] = { + { REG_A8XX_CP_HW_FAULT_STATUS_MASK_PIPE, 0, BIT(PIPE_BR) | + BIT(PIPE_BV) | BIT(PIPE_LPAC) | BIT(PIPE_AQE0) | + BIT(PIPE_AQE1) | BIT(PIPE_DDE_BR) | BIT(PIPE_DDE_BV) }, + { REG_A8XX_CP_INTERRUPT_STATUS_MASK_PIPE, 0, BIT(PIPE_BR) | + BIT(PIPE_BV) | BIT(PIPE_LPAC) | BIT(PIPE_AQE0) | + BIT(PIPE_AQE1) | BIT(PIPE_DDE_BR) | BIT(PIPE_DDE_BV) }, + { REG_A8XX_CP_PROTECT_CNTL_PIPE, 0, BIT(PIPE_BR) | BIT(PIPE_BV) | BIT(PIPE_LPAC) }, + { REG_A8XX_CP_PROTECT_PIPE(15), 0, BIT(PIPE_BR) | BIT(PIPE_BV) | BIT(PIPE_LPAC) }, + { REG_A8XX_GRAS_TSEFE_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_GRAS_NC_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_GRAS_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A7XX_RB_CCU_CNTL, 0, BIT(PIPE_BR) }, + { REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0, BIT(PIPE_BR) }, + { REG_A8XX_RB_CCU_NC_MODE_CNTL, 0, BIT(PIPE_BR) }, + { REG_A8XX_RB_CMP_NC_MODE_CNTL, 0, BIT(PIPE_BR) }, + { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0, BIT(PIPE_BR) }, + { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0, BIT(PIPE_BR) }, + { REG_A8XX_RB_GC_GMEM_PROTECT, 0, BIT(PIPE_BR) }, + { REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE, 0, BIT(PIPE_BR) }, + { REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_1, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_2, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_3, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_4, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0, BIT(PIPE_BR) | BIT(PIPE_BV) }, + { REG_A8XX_PC_VIS_STREAM_CNTL, 0, BIT(PIPE_BR) | BIT(PIPE_BV) }, + { REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0, BIT(PIPE_BR) | BIT(PIPE_BV) }, + { REG_A8XX_VFD_CB_BV_THRESHOLD, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BR_THRESHOLD, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_LP_REQ_CNT, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A7XX_VFD_DBG_ECO_CNTL, 0, BIT(PIPE_BR) | BIT(PIPE_BV) }, + { }, +}; +DECLARE_ADRENO_REGLIST_PIPE_LIST(a830_dyn_pwrup_reglist); + +static const struct adreno_reglist_pipe x285_nonctxt_regs[] = { + { REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) }, + { REG_A8XX_GRAS_DBG_ECO_CNTL, 0x00000800, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_GRAS_TSEFE_DBG_ECO_CNTL, 0x00200000, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_VIS_STREAM_CNTL, 0x10010000, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0x00000002, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_1, 0x00000003, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_2, 0x00000200, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_3, 0x00500000, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_4, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_RB_GC_GMEM_PROTECT, 0x15000000, BIT(PIPE_BR) }, + { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0x00000007, BIT(PIPE_BR) }, + { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0x00004000, BIT(PIPE_BR) }, + { REG_A8XX_RBBM_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_SLICE_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL, 0x00000030, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL2, 0x00000030, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_INTERFACE_HANG_INT_CNTL, 0x0fffffff, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x22122212, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_CGC_P2S_CNTL, 0x00000040, BIT(PIPE_NONE) }, + { REG_A7XX_SP_CHICKEN_BITS_2, 0x00820800, BIT(PIPE_NONE) }, + { REG_A7XX_SP_CHICKEN_BITS_3, 0x00300000, BIT(PIPE_NONE) }, + { REG_A6XX_SP_PERFCTR_SHADER_MASK, 0x0000003f, BIT(PIPE_NONE) }, + /* Disable CS dead batch merge */ + { REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_2, BIT(31), BIT(PIPE_NONE) }, + { REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, 0x00000080, BIT(PIPE_NONE) }, + { REG_A7XX_SP_READ_SEL, 0x0001ff00, BIT(PIPE_NONE) }, + { REG_A6XX_TPL1_DBG_ECO_CNTL, 0x10000000, BIT(PIPE_NONE) }, + /* BIT(26): Disable final clamp for bicubic filtering */ + { REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x04000720, BIT(PIPE_NONE) }, + { REG_A6XX_UCHE_MODE_CNTL, 0x80080000, BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_CCHE_MODE_CNTL, 0x00001000, BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_CCHE_CACHE_WAYS, 0x00000800, BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_GBIF_GX_CONFIG, 0x010240e0, BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_VARB_IDLE_TIMEOUT, 0x00000020, BIT(PIPE_NONE) }, + { REG_A7XX_VFD_DBG_ECO_CNTL, 0x00008000, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BV_THRESHOLD, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BR_THRESHOLD, 0x00600060, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0x00200020, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_LP_REQ_CNT, 0x00000020, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { }, +}; + +static const u32 x285_protect_regs[] = { + A6XX_PROTECT_RDONLY(0x00008, 0x039b), + A6XX_PROTECT_RDONLY(0x003b4, 0x008b), + A6XX_PROTECT_NORDWR(0x00440, 0x001f), + A6XX_PROTECT_RDONLY(0x00580, 0x005f), + A6XX_PROTECT_NORDWR(0x005e0, 0x011f), + A6XX_PROTECT_RDONLY(0x0074a, 0x0005), + A6XX_PROTECT_RDONLY(0x00759, 0x0026), + A6XX_PROTECT_RDONLY(0x00789, 0x0000), + A6XX_PROTECT_RDONLY(0x0078c, 0x0013), + A6XX_PROTECT_NORDWR(0x00800, 0x0029), + A6XX_PROTECT_NORDWR(0x0082c, 0x0000), + A6XX_PROTECT_NORDWR(0x00837, 0x00af), + A6XX_PROTECT_RDONLY(0x008e7, 0x00c9), + A6XX_PROTECT_NORDWR(0x008ec, 0x00c3), + A6XX_PROTECT_NORDWR(0x009b1, 0x0250), + A6XX_PROTECT_RDONLY(0x00ce0, 0x0001), + A6XX_PROTECT_RDONLY(0x00df0, 0x0000), + A6XX_PROTECT_NORDWR(0x00df1, 0x0000), + A6XX_PROTECT_NORDWR(0x00e01, 0x0000), + A6XX_PROTECT_NORDWR(0x00e03, 0x1fff), + A6XX_PROTECT_NORDWR(0x03c00, 0x00c5), + A6XX_PROTECT_RDONLY(0x03cc6, 0x0039), + A6XX_PROTECT_NORDWR(0x03d00, 0x1fff), + A6XX_PROTECT_NORDWR(0x08600, 0x01ff), + A6XX_PROTECT_NORDWR(0x08e00, 0x00ff), + A6XX_PROTECT_RDONLY(0x08f00, 0x0000), + A6XX_PROTECT_NORDWR(0x08f01, 0x01be), + A6XX_PROTECT_NORDWR(0x09600, 0x01ff), + A6XX_PROTECT_RDONLY(0x0981a, 0x02e5), + A6XX_PROTECT_NORDWR(0x09e00, 0x01ff), + A6XX_PROTECT_NORDWR(0x0a600, 0x01ff), + A6XX_PROTECT_NORDWR(0x0a82e, 0x0000), + A6XX_PROTECT_NORDWR(0x0ae00, 0x0006), + A6XX_PROTECT_NORDWR(0x0ae08, 0x0006), + A6XX_PROTECT_NORDWR(0x0ae10, 0x00bf), + A6XX_PROTECT_RDONLY(0x0aed0, 0x002f), + A6XX_PROTECT_NORDWR(0x0af00, 0x027f), + A6XX_PROTECT_NORDWR(0x0b600, 0x1fff), + A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff), + A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), + A6XX_PROTECT_NORDWR(0x18400, 0x003f), + A6XX_PROTECT_RDONLY(0x18440, 0x013f), + A6XX_PROTECT_NORDWR(0x18580, 0x1fff), + A6XX_PROTECT_NORDWR(0x1b400, 0x1fff), + A6XX_PROTECT_NORDWR(0x1f400, 0x0477), + A6XX_PROTECT_RDONLY(0x1f878, 0x0507), + A6XX_PROTECT_NORDWR(0x1f930, 0x0329), + A6XX_PROTECT_NORDWR(0x1fd80, 0x1fff), + A6XX_PROTECT_NORDWR(0x27800, 0x007f), + A6XX_PROTECT_RDONLY(0x27880, 0x0385), + A6XX_PROTECT_NORDWR(0x27882, 0x000a), + A6XX_PROTECT_NORDWR(0x27c06, 0x0000), +}; + +DECLARE_ADRENO_PROTECT(x285_protect, 15); + +static const struct adreno_reglist_pipe x285_dyn_pwrup_reglist_regs[] = { + { REG_A8XX_GRAS_TSEFE_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_GRAS_NC_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_GRAS_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_1, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_2, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_3, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_4, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_VIS_STREAM_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A7XX_RB_CCU_CNTL, 0, BIT(PIPE_BR) }, + { REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0, BIT(PIPE_BR)}, + { REG_A8XX_RB_CCU_NC_MODE_CNTL, 0, BIT(PIPE_BR) }, + { REG_A8XX_RB_CMP_NC_MODE_CNTL, 0, BIT(PIPE_BR) }, + { REG_A6XX_RB_RBP_CNTL, 0, BIT(PIPE_BR) }, + { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0, BIT(PIPE_BR) }, + { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0, BIT(PIPE_BR) }, + { REG_A7XX_VFD_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BV_THRESHOLD, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BR_THRESHOLD, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_LP_REQ_CNT, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_CP_HW_FAULT_STATUS_MASK_PIPE, 0, BIT(PIPE_BR) | + BIT(PIPE_BV) | BIT(PIPE_LPAC) | BIT(PIPE_AQE0) | + BIT(PIPE_AQE1) | BIT(PIPE_DDE_BR) | BIT(PIPE_DDE_BV) }, + { REG_A8XX_CP_INTERRUPT_STATUS_MASK_PIPE, 0, BIT(PIPE_BR) | + BIT(PIPE_BV) | BIT(PIPE_LPAC) | BIT(PIPE_AQE0) | + BIT(PIPE_AQE1) | BIT(PIPE_DDE_BR) | BIT(PIPE_DDE_BV) }, + { REG_A8XX_CP_PROTECT_CNTL_PIPE, 0, BIT(PIPE_BR) | BIT(PIPE_BV) | BIT(PIPE_LPAC)}, + { REG_A8XX_CP_PROTECT_PIPE(15), 0, BIT(PIPE_BR) | BIT(PIPE_BV) | BIT(PIPE_LPAC) }, + { REG_A8XX_RB_GC_GMEM_PROTECT, 0, BIT(PIPE_BR) }, + { REG_A8XX_RB_LPAC_GMEM_PROTECT, 0, BIT(PIPE_BR) }, + { REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE, 0, BIT(PIPE_BR) }, +}; +DECLARE_ADRENO_REGLIST_PIPE_LIST(x285_dyn_pwrup_reglist); + +static const struct adreno_reglist_pipe a810_nonctxt_regs[] = { + { REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) }, + { REG_A8XX_GRAS_DBG_ECO_CNTL, 0x00f80800, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_VIS_STREAM_CNTL, 0x10010000, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0x00000002, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_1, 0x00000003, BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_1, 0x00000023, BIT(PIPE_BV) }, /* Avoid partial waves at VFD */ + { REG_A8XX_PC_CHICKEN_BITS_2, 0x00000200, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_3, 0x00500000, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_4, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A7XX_RB_CCU_CNTL, 0x00000068, BIT(PIPE_BR) }, + /* Partially enable perf clear, Disable DINT to c/z be data forwarding */ + { REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0x00002200, BIT(PIPE_BR) }, + { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0x00000007, BIT(PIPE_BR) }, + { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0x00004000, BIT(PIPE_BR) }, + { REG_A8XX_RBBM_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_SLICE_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL, 0x00000030, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL2, 0x00000030, BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_GBIF_GX_CONFIG, 0x010240e0, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x22122212, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_CGC_P2S_CNTL, 0x00000040, BIT(PIPE_NONE) }, + /* + * BIT(22): Disable PS out of order retire + * BIT(23): Enable half wave mode and MM instruction src&dst is half precision + */ + { REG_A7XX_SP_CHICKEN_BITS_2, BIT(22) | BIT(23), BIT(PIPE_NONE) }, + { REG_A7XX_SP_CHICKEN_BITS_3, 0x00300000, BIT(PIPE_NONE) }, + { REG_A6XX_SP_PERFCTR_SHADER_MASK, 0x0000003f, BIT(PIPE_NONE) }, + { REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, 0x00000080, BIT(PIPE_NONE) }, + { REG_A6XX_TPL1_DBG_ECO_CNTL, 0x10100000, BIT(PIPE_NONE) }, + { REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x04000724, BIT(PIPE_NONE) }, + { REG_A6XX_UCHE_MODE_CNTL, 0x00020000, BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_CCHE_MODE_CNTL, 0x00001000, BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_CCHE_CACHE_WAYS, 0x00000800, BIT(PIPE_NONE) }, + /* Disable write slow pointer in data phase queue */ + { REG_A8XX_UCHE_HW_DBG_CNTL, BIT(8), BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_VARB_IDLE_TIMEOUT, 0x00000020, BIT(PIPE_NONE) }, + { REG_A7XX_VFD_DBG_ECO_CNTL, 0x00008000, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BV_THRESHOLD, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BR_THRESHOLD, 0x00600060, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0x00200020, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_LP_REQ_CNT, 0x00100020, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_RB_GC_GMEM_PROTECT, 0x00900000, BIT(PIPE_BR) }, + { }, +}; + +static const u32 a810_protect_regs[] = { + A6XX_PROTECT_RDONLY(0x00000, 0x03a3), + A6XX_PROTECT_RDONLY(0x003b4, 0x008b), + A6XX_PROTECT_NORDWR(0x00440, 0x001f), + A6XX_PROTECT_RDONLY(0x00580, 0x005f), + A6XX_PROTECT_NORDWR(0x005e0, 0x011f), + A6XX_PROTECT_RDONLY(0x0074a, 0x0005), + A6XX_PROTECT_RDONLY(0x00759, 0x0026), + A6XX_PROTECT_RDONLY(0x00789, 0x0000), + A6XX_PROTECT_RDONLY(0x0078c, 0x0013), + A6XX_PROTECT_NORDWR(0x00800, 0x0029), + A6XX_PROTECT_NORDWR(0x00837, 0x00af), + A6XX_PROTECT_RDONLY(0x008e7, 0x00c9), + A6XX_PROTECT_NORDWR(0x008ec, 0x00c3), + A6XX_PROTECT_NORDWR(0x009b1, 0x0250), + A6XX_PROTECT_RDONLY(0x00ce0, 0x0001), + A6XX_PROTECT_RDONLY(0x00df0, 0x0000), + A6XX_PROTECT_NORDWR(0x00df1, 0x0000), + A6XX_PROTECT_NORDWR(0x00e01, 0x0000), + A6XX_PROTECT_NORDWR(0x00e03, 0x1fff), + A6XX_PROTECT_NORDWR(0x03c00, 0x00c5), + A6XX_PROTECT_RDONLY(0x03cc6, 0x1fff), + A6XX_PROTECT_NORDWR(0x08600, 0x01ff), + A6XX_PROTECT_NORDWR(0x08e00, 0x00ff), + A6XX_PROTECT_RDONLY(0x08f00, 0x0000), + A6XX_PROTECT_NORDWR(0x08f01, 0x01be), + A6XX_PROTECT_NORDWR(0x09600, 0x01ff), + A6XX_PROTECT_RDONLY(0x0981a, 0x02e5), + A6XX_PROTECT_NORDWR(0x09e00, 0x01ff), + A6XX_PROTECT_NORDWR(0x0a600, 0x01ff), + A6XX_PROTECT_NORDWR(0x0ae00, 0x0006), + A6XX_PROTECT_NORDWR(0x0ae08, 0x0006), + A6XX_PROTECT_NORDWR(0x0ae10, 0x036f), + A6XX_PROTECT_NORDWR(0x0b600, 0x1fff), + A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff), + A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), + A6XX_PROTECT_NORDWR(0x18400, 0x003f), + A6XX_PROTECT_RDONLY(0x18440, 0x013f), + A6XX_PROTECT_NORDWR(0x18580, 0x1fff), + A6XX_PROTECT_NORDWR(0x1b400, 0x1fff), + A6XX_PROTECT_NORDWR(0x1f400, 0x0477), + A6XX_PROTECT_RDONLY(0x1f878, 0x0787), + A6XX_PROTECT_NORDWR(0x1f930, 0x0329), + A6XX_PROTECT_NORDWR(0x20000, 0x1fff), + A6XX_PROTECT_NORDWR(0x27800, 0x007f), + A6XX_PROTECT_RDONLY(0x27880, 0x0381), + A6XX_PROTECT_NORDWR(0x27882, 0x0001), + A6XX_PROTECT_NORDWR(0x27c02, 0x0000), +}; +DECLARE_ADRENO_PROTECT(a810_protect, 64); + +static const uint32_t a810_pwrup_reglist_regs[] = { + REG_A6XX_UCHE_MODE_CNTL, + REG_A8XX_UCHE_VARB_IDLE_TIMEOUT, + REG_A8XX_UCHE_GBIF_GX_CONFIG, + REG_A8XX_UCHE_CACHE_WAYS, + REG_A8XX_UCHE_CCHE_MODE_CNTL, + REG_A8XX_UCHE_CCHE_CACHE_WAYS, + REG_A8XX_UCHE_CCHE_GC_GMEM_RANGE_MIN, + REG_A8XX_UCHE_CCHE_GC_GMEM_RANGE_MIN + 1, + REG_A8XX_UCHE_CCHE_TRAP_BASE, + REG_A8XX_UCHE_CCHE_TRAP_BASE + 1, + REG_A8XX_UCHE_CCHE_WRITE_THRU_BASE, + REG_A8XX_UCHE_CCHE_WRITE_THRU_BASE + 1, + REG_A8XX_UCHE_HW_DBG_CNTL, + REG_A8XX_UCHE_WRITE_THRU_BASE, + REG_A8XX_UCHE_WRITE_THRU_BASE + 1, + REG_A8XX_UCHE_TRAP_BASE, + REG_A8XX_UCHE_TRAP_BASE + 1, + REG_A8XX_UCHE_CLIENT_PF, + REG_A8XX_RB_CMP_NC_MODE_CNTL, + REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, + REG_A8XX_SP_HLSQ_GC_GMEM_RANGE_MIN, + REG_A8XX_SP_HLSQ_GC_GMEM_RANGE_MIN + 1, + REG_A7XX_SP_READ_SEL, + REG_A6XX_TPL1_NC_MODE_CNTL, + REG_A6XX_TPL1_DBG_ECO_CNTL, + REG_A6XX_TPL1_DBG_ECO_CNTL1, + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(1), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(2), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(3), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(4), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(5), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(6), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(7), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(8), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(9), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(10), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(11), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(12), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(13), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(14), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(15), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(16), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(17), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(18), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(19), +}; +DECLARE_ADRENO_REGLIST_LIST(a810_pwrup_reglist); + +static const u32 a810_ifpc_reglist_regs[] = { + REG_A8XX_RBBM_NC_MODE_CNTL, + REG_A8XX_RBBM_PERFCTR_CNTL, + REG_A8XX_RBBM_SLICE_INTERFACE_HANG_INT_CNTL, + REG_A8XX_RBBM_SLICE_NC_MODE_CNTL, + REG_A6XX_SP_NC_MODE_CNTL, + REG_A7XX_SP_CHICKEN_BITS_2, + REG_A7XX_SP_CHICKEN_BITS_3, + REG_A6XX_SP_PERFCTR_SHADER_MASK, + REG_A8XX_CP_PROTECT_GLOBAL(0), + REG_A8XX_CP_PROTECT_GLOBAL(1), + REG_A8XX_CP_PROTECT_GLOBAL(2), + REG_A8XX_CP_PROTECT_GLOBAL(3), + REG_A8XX_CP_PROTECT_GLOBAL(4), + REG_A8XX_CP_PROTECT_GLOBAL(5), + REG_A8XX_CP_PROTECT_GLOBAL(6), + REG_A8XX_CP_PROTECT_GLOBAL(7), + REG_A8XX_CP_PROTECT_GLOBAL(8), + REG_A8XX_CP_PROTECT_GLOBAL(9), + REG_A8XX_CP_PROTECT_GLOBAL(10), + REG_A8XX_CP_PROTECT_GLOBAL(11), + REG_A8XX_CP_PROTECT_GLOBAL(12), + REG_A8XX_CP_PROTECT_GLOBAL(13), + REG_A8XX_CP_PROTECT_GLOBAL(14), + REG_A8XX_CP_PROTECT_GLOBAL(15), + REG_A8XX_CP_PROTECT_GLOBAL(16), + REG_A8XX_CP_PROTECT_GLOBAL(17), + REG_A8XX_CP_PROTECT_GLOBAL(18), + REG_A8XX_CP_PROTECT_GLOBAL(19), + REG_A8XX_CP_PROTECT_GLOBAL(20), + REG_A8XX_CP_PROTECT_GLOBAL(21), + REG_A8XX_CP_PROTECT_GLOBAL(22), + REG_A8XX_CP_PROTECT_GLOBAL(23), + REG_A8XX_CP_PROTECT_GLOBAL(24), + REG_A8XX_CP_PROTECT_GLOBAL(25), + REG_A8XX_CP_PROTECT_GLOBAL(26), + REG_A8XX_CP_PROTECT_GLOBAL(27), + REG_A8XX_CP_PROTECT_GLOBAL(28), + REG_A8XX_CP_PROTECT_GLOBAL(29), + REG_A8XX_CP_PROTECT_GLOBAL(30), + REG_A8XX_CP_PROTECT_GLOBAL(31), + REG_A8XX_CP_PROTECT_GLOBAL(32), + REG_A8XX_CP_PROTECT_GLOBAL(33), + REG_A8XX_CP_PROTECT_GLOBAL(34), + REG_A8XX_CP_PROTECT_GLOBAL(35), + REG_A8XX_CP_PROTECT_GLOBAL(36), + REG_A8XX_CP_PROTECT_GLOBAL(37), + REG_A8XX_CP_PROTECT_GLOBAL(38), + REG_A8XX_CP_PROTECT_GLOBAL(39), + REG_A8XX_CP_PROTECT_GLOBAL(40), + REG_A8XX_CP_PROTECT_GLOBAL(41), + REG_A8XX_CP_PROTECT_GLOBAL(42), + REG_A8XX_CP_PROTECT_GLOBAL(43), + REG_A8XX_CP_PROTECT_GLOBAL(44), + REG_A8XX_CP_PROTECT_GLOBAL(45), + REG_A8XX_CP_PROTECT_GLOBAL(46), + REG_A8XX_CP_PROTECT_GLOBAL(47), + REG_A8XX_CP_PROTECT_GLOBAL(48), + REG_A8XX_CP_PROTECT_GLOBAL(49), + REG_A8XX_CP_PROTECT_GLOBAL(50), + REG_A8XX_CP_PROTECT_GLOBAL(51), + REG_A8XX_CP_PROTECT_GLOBAL(52), + REG_A8XX_CP_PROTECT_GLOBAL(53), + REG_A8XX_CP_PROTECT_GLOBAL(54), + REG_A8XX_CP_PROTECT_GLOBAL(55), + REG_A8XX_CP_PROTECT_GLOBAL(56), + REG_A8XX_CP_PROTECT_GLOBAL(57), + REG_A8XX_CP_PROTECT_GLOBAL(58), + REG_A8XX_CP_PROTECT_GLOBAL(59), + REG_A8XX_CP_PROTECT_GLOBAL(60), + REG_A8XX_CP_PROTECT_GLOBAL(61), + REG_A8XX_CP_PROTECT_GLOBAL(62), + REG_A8XX_CP_PROTECT_GLOBAL(63), +}; +DECLARE_ADRENO_REGLIST_LIST(a810_ifpc_reglist); + +static const struct adreno_reglist_pipe a810_dyn_pwrup_reglist_regs[] = { + { REG_A8XX_CP_PROTECT_CNTL_PIPE, 0, BIT(PIPE_BR) | BIT(PIPE_BV) }, + { REG_A8XX_CP_PROTECT_PIPE(15), 0, BIT(PIPE_BR) | BIT(PIPE_BV) }, + { REG_A8XX_GRAS_TSEFE_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_GRAS_NC_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_GRAS_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A7XX_RB_CCU_CNTL, 0, BIT(PIPE_BR) }, + { REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0, BIT(PIPE_BR) }, + { REG_A8XX_RB_CCU_NC_MODE_CNTL, 0, BIT(PIPE_BR) }, + { REG_A8XX_RB_CMP_NC_MODE_CNTL, 0, BIT(PIPE_BR) }, + { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0, BIT(PIPE_BR) }, + { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0, BIT(PIPE_BR) }, + { REG_A8XX_RB_GC_GMEM_PROTECT, 0, BIT(PIPE_BR) }, + { REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE, 0, BIT(PIPE_BR) }, + { REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_1, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_2, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_3, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_4, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0, BIT(PIPE_BR) | BIT(PIPE_BV) }, + { REG_A8XX_PC_VIS_STREAM_CNTL, 0, BIT(PIPE_BR) | BIT(PIPE_BV) }, + { REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0, BIT(PIPE_BR) | BIT(PIPE_BV) }, + { REG_A8XX_VFD_CB_BV_THRESHOLD, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BR_THRESHOLD, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_LP_REQ_CNT, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A7XX_VFD_DBG_ECO_CNTL, 0, BIT(PIPE_BR) | BIT(PIPE_BV) }, +}; +DECLARE_ADRENO_REGLIST_PIPE_LIST(a810_dyn_pwrup_reglist); + +static const struct a6xx_hfi_clx_table_v2_cmd x285_clx_tbl = { + .version = (2 << 16) | 1, + .domain = { + /* GX DOMAIN */ + { + .data = CLX_DATA(60, 11, 0, 1), + .clxt = 0, + .clxh = 0, + .urg_mode = 1, + .lkg_en = 0, + .curr_budget = 100, + }, + /* MXG DOMAIN */ + { + .data = CLX_DATA(60, 3, 1, 1), + .clxt = 0, + .clxh = 0, + .urg_mode = 1, + .lkg_en = 0, + .curr_budget = 100, + }, + }, +}; + +struct a6xx_hfi_limits_tbl x285_limits_tbl[] = { + { + .feature_id = GMU_MIT_IFF, + .domain = GMU_GX_DOMAIN, + .feature_rev = 0, + .cfg = { + .enable = 1, + .msg_path = 0, + .lkg_en = 0, + .mode = 0, + .sid = 12, + .mit_time = 5, + .curr_limit = 18000, + }, + }, + { + .feature_id = GMU_MIT_IFF, + .domain = GMU_MX_DOMAIN, + .feature_rev = 0, + .cfg = { + .enable = 1, + .msg_path = 0, + .lkg_en = 0, + .mode = 0, + .sid = 18, + .mit_time = 2000, + .curr_limit = 6000, + }, + }, + { + .feature_id = GMU_MIT_PCLX, + .domain = GMU_GX_DOMAIN, + .feature_rev = 0, + .cfg = { + .enable = 1, + .msg_path = 0, + .lkg_en = 0, + .mode = 0, + .sid = 6, + .mit_time = 3, + .curr_limit = 66000, + }, + }, + { + .feature_id = GMU_MIT_PCLX, + .domain = GMU_MX_DOMAIN, + .feature_rev = 0, + .cfg = { + .enable = 0, + .msg_path = 0, + .lkg_en = 0, + .mode = 0, + .sid = 6, + .mit_time = 3, + .curr_limit = 18000, + }, + }, +}; +DECLARE_ADRENO_LIMITS_TABLE(x285_limits); + +static const struct adreno_reglist_pipe a840_nonctxt_regs[] = { + { REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) }, + { REG_A8XX_GRAS_DBG_ECO_CNTL, 0x00000800, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_GRAS_TSEFE_DBG_ECO_CNTL, 0x00200000, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_VIS_STREAM_CNTL, 0x10010000, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0x00000002, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_1, 0x00000003, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_2, 0x00000200, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_3, 0x00500000, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_4, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) }, + /* Disable Dead Draw Merge scheme on RB-HLSQ */ + { REG_A6XX_RB_RBP_CNTL, BIT(5), BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A7XX_RB_CCU_CNTL, 0x00000068, BIT(PIPE_BR) }, + /* Partially enable perf clear, Disable DINT to c/z be data forwarding */ + { REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0x00002200, BIT(PIPE_BR) }, + { REG_A8XX_RB_GC_GMEM_PROTECT, 0x12000000, BIT(PIPE_BR) }, + { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0x00000007, BIT(PIPE_BR) }, + { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0x00004000, BIT(PIPE_BR) }, + { REG_A8XX_RBBM_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_SLICE_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_POWER_UP_RESET_SW_OVERRIDE, 0x70809060, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_POWER_UP_RESET_SW_BV_OVERRIDE, 0x30000000, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL, 0x00000030, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL2, 0x00000030, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_INTERFACE_HANG_INT_CNTL, 0x0fffffff, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x22122212, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_CGC_P2S_CNTL, 0x00000040, BIT(PIPE_NONE) }, + /* Disable mode_switch optimization in UMAS */ + { REG_A6XX_SP_CHICKEN_BITS, BIT(24) | BIT(26), BIT(PIPE_NONE) }, + /* Disable LPAC large-LM mode */ + { REG_A8XX_SP_SS_CHICKEN_BITS_0, BIT(3), BIT(PIPE_NONE) }, + /* Disable PS out of order retire */ + { REG_A7XX_SP_CHICKEN_BITS_2, 0x00c21800, BIT(PIPE_NONE) }, + { REG_A7XX_SP_CHICKEN_BITS_3, 0x00300000, BIT(PIPE_NONE) }, + /* Disable SP2TP info attribute */ + { REG_A8XX_SP_CHICKEN_BITS_4, 0x00000002, BIT(PIPE_NONE) }, + { REG_A6XX_SP_PERFCTR_SHADER_MASK, 0x0000003f, BIT(PIPE_NONE) }, + { REG_A7XX_SP_HLSQ_DBG_ECO_CNTL, BIT(14), BIT(PIPE_NONE) }, + /* Ignore HLSQ shared constant feedback from SP */ + { REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_1, BIT(17), BIT(PIPE_NONE) }, + /* Disable CS dead batch merge */ + { REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_2, BIT(24), BIT(PIPE_NONE) }, + { REG_A8XX_SP_HLSQ_DBG_ECO_CNTL_3, BIT(7), BIT(PIPE_NONE) }, + { REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, 0x00000080, BIT(PIPE_NONE) }, + { REG_A7XX_SP_READ_SEL, 0x0001ff00, BIT(PIPE_NONE) }, + { REG_A6XX_TPL1_DBG_ECO_CNTL, 0x10100000, BIT(PIPE_NONE) }, + /* BIT(26): Disable final clamp for bicubic filtering */ + { REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x04000720, BIT(PIPE_NONE) }, + { REG_A6XX_UCHE_MODE_CNTL, 0x80080000, BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_CCHE_MODE_CNTL, 0x00001000, BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_CCHE_CACHE_WAYS, 0x00000800, BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_GBIF_GX_CONFIG, 0x010240e0, BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_VARB_IDLE_TIMEOUT, 0x00000020, BIT(PIPE_NONE) }, + { REG_A7XX_VFD_DBG_ECO_CNTL, 0x00008000, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BV_THRESHOLD, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BR_THRESHOLD, 0x00600060, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0x00200020, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_LP_REQ_CNT, 0x00000020, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { }, +}; + +static const u32 a840_protect_regs[] = { + A6XX_PROTECT_RDONLY(0x00008, 0x039b), + A6XX_PROTECT_RDONLY(0x003b4, 0x008b), + A6XX_PROTECT_NORDWR(0x00440, 0x001f), + A6XX_PROTECT_RDONLY(0x00580, 0x005f), + A6XX_PROTECT_NORDWR(0x005e0, 0x011f), + A6XX_PROTECT_RDONLY(0x0074a, 0x0005), + A6XX_PROTECT_RDONLY(0x00759, 0x001b), + A6XX_PROTECT_NORDWR(0x00775, 0x000a), + A6XX_PROTECT_RDONLY(0x00789, 0x0000), + A6XX_PROTECT_RDONLY(0x0078c, 0x0013), + A6XX_PROTECT_NORDWR(0x00800, 0x0029), + A6XX_PROTECT_NORDWR(0x00837, 0x00af), + A6XX_PROTECT_RDONLY(0x008e7, 0x00c9), + A6XX_PROTECT_NORDWR(0x008ec, 0x00c3), + A6XX_PROTECT_NORDWR(0x009b1, 0x0250), + A6XX_PROTECT_NORDWR(0x00c07, 0x0008), + A6XX_PROTECT_RDONLY(0x00ce0, 0x0001), + A6XX_PROTECT_RDONLY(0x00df0, 0x0000), + A6XX_PROTECT_NORDWR(0x00df1, 0x0000), + A6XX_PROTECT_NORDWR(0x00e01, 0x0000), + A6XX_PROTECT_NORDWR(0x00e03, 0x1fff), + A6XX_PROTECT_NORDWR(0x03c00, 0x00c5), + A6XX_PROTECT_RDONLY(0x03cc6, 0x0039), + A6XX_PROTECT_NORDWR(0x03d00, 0x1fff), + A6XX_PROTECT_NORDWR(0x08600, 0x01ff), + A6XX_PROTECT_NORDWR(0x08e00, 0x00ff), + A6XX_PROTECT_RDONLY(0x08f00, 0x0000), + A6XX_PROTECT_NORDWR(0x08f01, 0x01be), + A6XX_PROTECT_NORDWR(0x09600, 0x01ff), + A6XX_PROTECT_RDONLY(0x0981a, 0x02e5), + A6XX_PROTECT_NORDWR(0x09e00, 0x01ff), + A6XX_PROTECT_NORDWR(0x0a600, 0x01ff), + A6XX_PROTECT_NORDWR(0x0a82e, 0x0000), + A6XX_PROTECT_NORDWR(0x0ae00, 0x0000), + A6XX_PROTECT_NORDWR(0x0ae02, 0x0004), + A6XX_PROTECT_NORDWR(0x0ae08, 0x0006), + A6XX_PROTECT_NORDWR(0x0ae10, 0x00bf), + A6XX_PROTECT_RDONLY(0x0aed0, 0x002f), + A6XX_PROTECT_NORDWR(0x0af00, 0x027f), + A6XX_PROTECT_NORDWR(0x0b600, 0x1fff), + A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff), + A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), + A6XX_PROTECT_NORDWR(0x18400, 0x003f), + A6XX_PROTECT_RDONLY(0x18440, 0x013f), + A6XX_PROTECT_NORDWR(0x18580, 0x1fff), + A6XX_PROTECT_NORDWR(0x1b400, 0x1fff), + A6XX_PROTECT_NORDWR(0x1f400, 0x0477), + A6XX_PROTECT_RDONLY(0x1f878, 0x0507), + A6XX_PROTECT_NORDWR(0x1f930, 0x0329), + A6XX_PROTECT_NORDWR(0x1fd80, 0x1fff), + A6XX_PROTECT_NORDWR(0x27800, 0x007f), + A6XX_PROTECT_RDONLY(0x27880, 0x0385), + A6XX_PROTECT_NORDWR(0x27882, 0x0009), + A6XX_PROTECT_NORDWR(0x27c06, 0x0000), +}; +DECLARE_ADRENO_PROTECT(a840_protect, 15); + +static const struct adreno_reglist a840_gbif[] = { + { REG_A6XX_GBIF_QSB_SIDE0, 0x00071e20 }, + { REG_A6XX_GBIF_QSB_SIDE1, 0x00071e20 }, + { REG_A6XX_GBIF_QSB_SIDE2, 0x00071e20 }, + { REG_A6XX_GBIF_QSB_SIDE3, 0x00071e20 }, + { REG_A6XX_GBIF_CX_CONFIG, 0x20023000 }, + { }, +}; + +static const uint32_t a840_pwrup_reglist_regs[] = { + REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, + REG_A7XX_SP_READ_SEL, + REG_A6XX_UCHE_MODE_CNTL, + REG_A8XX_UCHE_VARB_IDLE_TIMEOUT, + REG_A8XX_UCHE_GBIF_GX_CONFIG, + REG_A8XX_UCHE_CCHE_MODE_CNTL, + REG_A8XX_UCHE_CCHE_CACHE_WAYS, + REG_A8XX_UCHE_CACHE_WAYS, + REG_A8XX_UCHE_CCHE_GC_GMEM_RANGE_MIN, + REG_A8XX_UCHE_CCHE_GC_GMEM_RANGE_MIN + 1, + REG_A8XX_UCHE_CCHE_LPAC_GMEM_RANGE_MIN, + REG_A8XX_UCHE_CCHE_LPAC_GMEM_RANGE_MIN + 1, + REG_A8XX_UCHE_CCHE_TRAP_BASE, + REG_A8XX_UCHE_CCHE_TRAP_BASE + 1, + REG_A8XX_UCHE_CCHE_WRITE_THRU_BASE, + REG_A8XX_UCHE_CCHE_WRITE_THRU_BASE + 1, + REG_A8XX_UCHE_HW_DBG_CNTL, + REG_A8XX_UCHE_WRITE_THRU_BASE, + REG_A8XX_UCHE_WRITE_THRU_BASE + 1, + REG_A8XX_UCHE_TRAP_BASE, + REG_A8XX_UCHE_TRAP_BASE + 1, + REG_A8XX_UCHE_CLIENT_PF, + REG_A8XX_RB_CMP_NC_MODE_CNTL, + REG_A8XX_SP_HLSQ_GC_GMEM_RANGE_MIN, + REG_A8XX_SP_HLSQ_GC_GMEM_RANGE_MIN + 1, + REG_A6XX_TPL1_NC_MODE_CNTL, + REG_A6XX_TPL1_DBG_ECO_CNTL, + REG_A6XX_TPL1_DBG_ECO_CNTL1, + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(0), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(1), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(2), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(3), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(4), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(5), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(6), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(7), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(8), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(9), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(10), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(11), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(12), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(13), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(14), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(15), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(16), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(17), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(18), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(19), +}; +DECLARE_ADRENO_REGLIST_LIST(a840_pwrup_reglist); + +static const u32 a840_ifpc_reglist_regs[] = { + REG_A8XX_RBBM_NC_MODE_CNTL, + REG_A8XX_RBBM_SLICE_NC_MODE_CNTL, + REG_A6XX_SP_NC_MODE_CNTL, + REG_A6XX_SP_CHICKEN_BITS, + REG_A8XX_SP_SS_CHICKEN_BITS_0, + REG_A7XX_SP_CHICKEN_BITS_1, + REG_A7XX_SP_CHICKEN_BITS_2, + REG_A7XX_SP_CHICKEN_BITS_3, + REG_A8XX_SP_CHICKEN_BITS_4, + REG_A6XX_SP_PERFCTR_SHADER_MASK, + REG_A8XX_RBBM_SLICE_PERFCTR_CNTL, + REG_A8XX_RBBM_SLICE_INTERFACE_HANG_INT_CNTL, + REG_A7XX_SP_HLSQ_DBG_ECO_CNTL, + REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_1, + REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_2, + REG_A8XX_SP_HLSQ_DBG_ECO_CNTL_3, + REG_A8XX_SP_HLSQ_LPAC_GMEM_RANGE_MIN, + REG_A8XX_SP_HLSQ_LPAC_GMEM_RANGE_MIN + 1, + REG_A8XX_CP_INTERRUPT_STATUS_MASK_GLOBAL, + REG_A8XX_RBBM_PERFCTR_CNTL, + REG_A8XX_CP_PROTECT_GLOBAL(0), + REG_A8XX_CP_PROTECT_GLOBAL(1), + REG_A8XX_CP_PROTECT_GLOBAL(2), + REG_A8XX_CP_PROTECT_GLOBAL(3), + REG_A8XX_CP_PROTECT_GLOBAL(4), + REG_A8XX_CP_PROTECT_GLOBAL(5), + REG_A8XX_CP_PROTECT_GLOBAL(6), + REG_A8XX_CP_PROTECT_GLOBAL(7), + REG_A8XX_CP_PROTECT_GLOBAL(8), + REG_A8XX_CP_PROTECT_GLOBAL(9), + REG_A8XX_CP_PROTECT_GLOBAL(10), + REG_A8XX_CP_PROTECT_GLOBAL(11), + REG_A8XX_CP_PROTECT_GLOBAL(12), + REG_A8XX_CP_PROTECT_GLOBAL(13), + REG_A8XX_CP_PROTECT_GLOBAL(14), + REG_A8XX_CP_PROTECT_GLOBAL(15), + REG_A8XX_CP_PROTECT_GLOBAL(16), + REG_A8XX_CP_PROTECT_GLOBAL(17), + REG_A8XX_CP_PROTECT_GLOBAL(18), + REG_A8XX_CP_PROTECT_GLOBAL(19), + REG_A8XX_CP_PROTECT_GLOBAL(20), + REG_A8XX_CP_PROTECT_GLOBAL(21), + REG_A8XX_CP_PROTECT_GLOBAL(22), + REG_A8XX_CP_PROTECT_GLOBAL(23), + REG_A8XX_CP_PROTECT_GLOBAL(24), + REG_A8XX_CP_PROTECT_GLOBAL(25), + REG_A8XX_CP_PROTECT_GLOBAL(26), + REG_A8XX_CP_PROTECT_GLOBAL(27), + REG_A8XX_CP_PROTECT_GLOBAL(28), + REG_A8XX_CP_PROTECT_GLOBAL(29), + REG_A8XX_CP_PROTECT_GLOBAL(30), + REG_A8XX_CP_PROTECT_GLOBAL(31), + REG_A8XX_CP_PROTECT_GLOBAL(32), + REG_A8XX_CP_PROTECT_GLOBAL(33), + REG_A8XX_CP_PROTECT_GLOBAL(34), + REG_A8XX_CP_PROTECT_GLOBAL(35), + REG_A8XX_CP_PROTECT_GLOBAL(36), + REG_A8XX_CP_PROTECT_GLOBAL(37), + REG_A8XX_CP_PROTECT_GLOBAL(38), + REG_A8XX_CP_PROTECT_GLOBAL(39), + REG_A8XX_CP_PROTECT_GLOBAL(40), + REG_A8XX_CP_PROTECT_GLOBAL(41), + REG_A8XX_CP_PROTECT_GLOBAL(42), + REG_A8XX_CP_PROTECT_GLOBAL(43), + REG_A8XX_CP_PROTECT_GLOBAL(44), + REG_A8XX_CP_PROTECT_GLOBAL(45), + REG_A8XX_CP_PROTECT_GLOBAL(46), + REG_A8XX_CP_PROTECT_GLOBAL(47), + REG_A8XX_CP_PROTECT_GLOBAL(48), + REG_A8XX_CP_PROTECT_GLOBAL(49), + REG_A8XX_CP_PROTECT_GLOBAL(50), + REG_A8XX_CP_PROTECT_GLOBAL(51), + REG_A8XX_CP_PROTECT_GLOBAL(52), + REG_A8XX_CP_PROTECT_GLOBAL(53), + REG_A8XX_CP_PROTECT_GLOBAL(54), + REG_A8XX_CP_PROTECT_GLOBAL(55), + REG_A8XX_CP_PROTECT_GLOBAL(56), + REG_A8XX_CP_PROTECT_GLOBAL(57), + REG_A8XX_CP_PROTECT_GLOBAL(58), + REG_A8XX_CP_PROTECT_GLOBAL(59), + REG_A8XX_CP_PROTECT_GLOBAL(60), + REG_A8XX_CP_PROTECT_GLOBAL(61), + REG_A8XX_CP_PROTECT_GLOBAL(62), + REG_A8XX_CP_PROTECT_GLOBAL(63), +}; +DECLARE_ADRENO_REGLIST_LIST(a840_ifpc_reglist); + +static const struct adreno_reglist_pipe a840_dyn_pwrup_reglist_regs[] = { + { REG_A8XX_GRAS_TSEFE_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_GRAS_NC_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_GRAS_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_1, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_2, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_3, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_4, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_VIS_STREAM_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A7XX_RB_CCU_CNTL, 0, BIT(PIPE_BR) }, + { REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0, BIT(PIPE_BR)}, + { REG_A8XX_RB_CCU_NC_MODE_CNTL, 0, BIT(PIPE_BR) }, + { REG_A8XX_RB_CMP_NC_MODE_CNTL, 0, BIT(PIPE_BR) }, + { REG_A6XX_RB_RBP_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0, BIT(PIPE_BR) }, + { REG_A6XX_RB_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0, BIT(PIPE_BR) }, + { REG_A7XX_VFD_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BV_THRESHOLD, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BR_THRESHOLD, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_LP_REQ_CNT, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_CP_HW_FAULT_STATUS_MASK_PIPE, 0, BIT(PIPE_BR) | + BIT(PIPE_BV) | BIT(PIPE_LPAC) | BIT(PIPE_AQE0) | + BIT(PIPE_AQE1) | BIT(PIPE_DDE_BR) | BIT(PIPE_DDE_BV) }, + { REG_A8XX_CP_INTERRUPT_STATUS_MASK_PIPE, 0, BIT(PIPE_BR) | + BIT(PIPE_BV) | BIT(PIPE_LPAC) | BIT(PIPE_AQE0) | + BIT(PIPE_AQE1) | BIT(PIPE_DDE_BR) | BIT(PIPE_DDE_BV) }, + { REG_A8XX_CP_PROTECT_CNTL_PIPE, 0, BIT(PIPE_BR) | BIT(PIPE_BV) | BIT(PIPE_LPAC)}, + { REG_A8XX_CP_PROTECT_PIPE(15), 0, BIT(PIPE_BR) | BIT(PIPE_BV) | BIT(PIPE_LPAC) }, + { REG_A8XX_RB_GC_GMEM_PROTECT, 0, BIT(PIPE_BR) }, + { REG_A8XX_RB_LPAC_GMEM_PROTECT, 0, BIT(PIPE_BR) }, + { REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE, 0, BIT(PIPE_BR) }, +}; +DECLARE_ADRENO_REGLIST_PIPE_LIST(a840_dyn_pwrup_reglist); + +static const struct a6xx_hfi_clx_table_v2_cmd a840_clx_tbl = { + .version = (2 << 16) | 1, + .domain = { + /* GX DOMAIN */ + { + .data = CLX_DATA(60, 5, 1, 1), + .clxt = 0, + .clxh = 0, + .urg_mode = 1, + .lkg_en = 0, + .curr_budget = 100, + }, + /* MXG DOMAIN */ + { + .data = CLX_DATA(60, 1, 1, 1), + .clxt = 0, + .clxh = 0, + .urg_mode = 1, + .lkg_en = 0, + .curr_budget = 50, + }, + }, +}; + +struct a6xx_hfi_limits_tbl a840_limits_tbl[] = { + { + .feature_id = GMU_MIT_IFF, + .domain = GMU_GX_DOMAIN, + .feature_rev = 0, + .cfg = { + .enable = 1, + .msg_path = 0, + .lkg_en = 0, + .mode = 0, + .sid = 12, + .mit_time = 5, + .curr_limit = 6000, + }, + }, + { + .feature_id = GMU_MIT_IFF, + .domain = GMU_MX_DOMAIN, + .feature_rev = 0, + .cfg = { + .enable = 1, + .msg_path = 0, + .lkg_en = 0, + .mode = 0, + .sid = 9, + .mit_time = 2000, + .curr_limit = 6000, + }, + }, + { + .feature_id = GMU_MIT_PCLX, + .domain = GMU_GX_DOMAIN, + .feature_rev = 0, + .cfg = { + .enable = 1, + .msg_path = 0, + .lkg_en = 0, + .mode = 0, + .sid = 7, + .mit_time = 3, + .curr_limit = 30000, + }, + }, + { + .feature_id = GMU_MIT_PCLX, + .domain = GMU_MX_DOMAIN, + .feature_rev = 0, + .cfg = { + .enable = 0, + .msg_path = 0, + .lkg_en = 0, + .mode = 0, + .sid = 7, + .mit_time = 3, + .curr_limit = 6000, + }, + }, +}; +DECLARE_ADRENO_LIMITS_TABLE(a840_limits); + +static const struct adreno_reglist_pipe a845_nonctxt_regs[] = { + { REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) }, + { REG_A8XX_CP_MULTIDRAW_CNTL, 0x00000001, BIT(PIPE_NONE) }, + { REG_A8XX_GRAS_DBG_ECO_CNTL, 0x01000800, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_GRAS_TSEFE_DBG_ECO_CNTL, 0x00200000, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_VIS_STREAM_CNTL, 0x10010000, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0x00000002, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_1, 0x00000803, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_2, 0x00000200, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_3, 0x00400000, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_4, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_5, BIT(28) | BIT(30), BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A7XX_RB_CCU_CNTL, 0x00000068, BIT(PIPE_BR) }, + { REG_A7XX_RB_CCU_DBG_ECO_CNTL, BIT(10) | BIT(9), BIT(PIPE_BR) }, + { REG_A6XX_RB_DBG_ECO_CNTL, BIT(17), BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_RB_GC_GMEM_PROTECT, 0x0C000000, BIT(PIPE_BR) }, + { REG_A6XX_RB_RBP_CNTL, BIT(5) | BIT(6), BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0x00000007, BIT(PIPE_BR) }, + { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0x00004000, BIT(PIPE_BR) }, + { REG_A8XX_RBBM_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_SLICE_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_SLICE_PERFCTR_CNTL, BIT(0), BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_POWER_UP_RESET_SW_OVERRIDE, 0x70809060, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_POWER_UP_RESET_SW_BV_OVERRIDE, 0x30000000, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL, 0x00000030, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL2, 0x00000030, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x22122212, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_CGC_P2S_CNTL, 0x00000040, BIT(PIPE_NONE) }, + { REG_A6XX_SP_CHICKEN_BITS, BIT(24), BIT(PIPE_NONE) }, + { REG_A7XX_SP_CHICKEN_BITS_2, 0x00820800, BIT(PIPE_NONE) }, + { REG_A7XX_SP_CHICKEN_BITS_3, 0x00300000, BIT(PIPE_NONE) }, + { REG_A8XX_SP_CHICKEN_BITS_5, BIT(3), BIT(PIPE_NONE) }, + { REG_A6XX_SP_PERFCTR_SHADER_MASK, 0x0000003f, BIT(PIPE_NONE) }, + { REG_A7XX_SP_HLSQ_DBG_ECO_CNTL, 0x04000000, BIT(PIPE_NONE) }, + { REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_1, BIT(17), BIT(PIPE_NONE) }, + { REG_A8XX_SP_HLSQ_DBG_ECO_CNTL_3, BIT(1), BIT(PIPE_NONE) }, + { REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, 0x00000080, BIT(PIPE_NONE) }, + { REG_A7XX_SP_READ_SEL, 0x0001ff00, BIT(PIPE_NONE) }, + { REG_A8XX_SP_L0_PERF_TUNE, 0x00000024, BIT(PIPE_NONE) }, + { REG_A6XX_TPL1_DBG_ECO_CNTL, 0x10100000, BIT(PIPE_NONE) }, + { REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x00000720, BIT(PIPE_NONE) }, + { REG_A6XX_UCHE_MODE_CNTL, 0x80080000, BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_CCHE_MODE_CNTL, 0x00001000, BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_DBG_ECO_CNTL_0, BIT(31), BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_HW_DBG_CNTL, 0x01410000, BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_CCHE_CACHE_WAYS, 0x00000800, BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_GBIF_GX_CONFIG, 0x010240e0, BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_VARB_IDLE_TIMEOUT, 0x00000020, BIT(PIPE_NONE) }, + { REG_A7XX_VFD_DBG_ECO_CNTL, 0x00008000, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BV_THRESHOLD, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BR_THRESHOLD, 0x00600060, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0x00200020, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_LP_REQ_CNT, 0x00080020, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VSC_VISIBILITY_FLUSH_CNTL, 0x00080004, BIT(PIPE_NONE) }, + { }, +}; + +static const struct adreno_reglist_pipe a850_nonctxt_regs[] = { + { REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) }, + { REG_A8XX_CP_MULTIDRAW_CNTL, 0x00000001, BIT(PIPE_NONE) }, + { REG_A8XX_GRAS_DBG_ECO_CNTL, 0x01000800, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_GRAS_TSEFE_DBG_ECO_CNTL, 0x00200000, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_VIS_STREAM_CNTL, 0x10010000, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0x00000002, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_1, 0x00000003, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_2, 0x00000200, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_3, 0x00400000, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_4, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_5, BIT(28), BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A7XX_RB_CCU_CNTL, 0x00000068, BIT(PIPE_BR) }, + { REG_A7XX_RB_CCU_DBG_ECO_CNTL, BIT(10) | BIT(9), BIT(PIPE_BR) }, + { REG_A6XX_RB_DBG_ECO_CNTL, BIT(17), BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_RB_GC_GMEM_PROTECT, 0x12000000, BIT(PIPE_BR) }, + { REG_A6XX_RB_RBP_CNTL, BIT(5) | BIT(6), BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0x00000007, BIT(PIPE_BR) }, + { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0x00004000, BIT(PIPE_BR) }, + { REG_A8XX_RBBM_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_SLICE_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_SLICE_PERFCTR_CNTL, BIT(0), BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_POWER_UP_RESET_SW_OVERRIDE, 0x70809060, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_POWER_UP_RESET_SW_BV_OVERRIDE, 0x30000000, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL, 0x00000030, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL2, 0x00000030, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x22122212, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_CGC_P2S_CNTL, 0x00000040, BIT(PIPE_NONE) }, + { REG_A6XX_SP_CHICKEN_BITS, BIT(24), BIT(PIPE_NONE) }, + { REG_A7XX_SP_CHICKEN_BITS_2, 0x00820800, BIT(PIPE_NONE) }, + { REG_A7XX_SP_CHICKEN_BITS_3, 0x00300000, BIT(PIPE_NONE) }, + { REG_A8XX_SP_CHICKEN_BITS_5, BIT(3), BIT(PIPE_NONE) }, + { REG_A6XX_SP_PERFCTR_SHADER_MASK, 0x0000003f, BIT(PIPE_NONE) }, + { REG_A7XX_SP_HLSQ_DBG_ECO_CNTL, 0x04000000, BIT(PIPE_NONE) }, + { REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_1, BIT(17), BIT(PIPE_NONE) }, + { REG_A8XX_SP_HLSQ_DBG_ECO_CNTL_3, BIT(1), BIT(PIPE_NONE) }, + { REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, 0x00000080, BIT(PIPE_NONE) }, + { REG_A7XX_SP_READ_SEL, 0x0001ff00, BIT(PIPE_NONE) }, + { REG_A8XX_SP_L0_PERF_TUNE, 0x00000024, BIT(PIPE_NONE) }, + { REG_A6XX_TPL1_DBG_ECO_CNTL, 0x10100000, BIT(PIPE_NONE) }, + { REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x00000720, BIT(PIPE_NONE) }, + { REG_A6XX_UCHE_MODE_CNTL, 0x80080000, BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_CCHE_MODE_CNTL, 0x00001000, BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_DBG_ECO_CNTL_0, BIT(31), BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_HW_DBG_CNTL, 0x01410000, BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_CCHE_CACHE_WAYS, 0x00000800, BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_GBIF_GX_CONFIG, 0x010240e0, BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_VARB_IDLE_TIMEOUT, 0x00000020, BIT(PIPE_NONE) }, + { REG_A7XX_VFD_DBG_ECO_CNTL, 0x00008000, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BV_THRESHOLD, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BR_THRESHOLD, 0x00600060, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0x00200020, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_LP_REQ_CNT, 0x00080020, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VSC_VISIBILITY_FLUSH_CNTL, 0x00080004, BIT(PIPE_NONE) }, + { }, +}; + +static const u32 a850_protect_regs[] = { + A6XX_PROTECT_RDONLY(0x00008, 0x039b), + A6XX_PROTECT_RDONLY(0x003b4, 0x008b), + A6XX_PROTECT_NORDWR(0x00440, 0x001f), + A6XX_PROTECT_RDONLY(0x00580, 0x005f), + A6XX_PROTECT_NORDWR(0x005e0, 0x011f), + A6XX_PROTECT_RDONLY(0x0074a, 0x0005), + A6XX_PROTECT_RDONLY(0x00759, 0x001b), + A6XX_PROTECT_NORDWR(0x00775, 0x000a), + A6XX_PROTECT_RDONLY(0x00789, 0x0000), + A6XX_PROTECT_RDONLY(0x0078c, 0x0013), + A6XX_PROTECT_NORDWR(0x00800, 0x0029), + A6XX_PROTECT_NORDWR(0x00837, 0x00af), + A6XX_PROTECT_RDONLY(0x008e7, 0x00c9), + A6XX_PROTECT_NORDWR(0x008ec, 0x00c3), + A6XX_PROTECT_NORDWR(0x009b1, 0x0250), + A6XX_PROTECT_NORDWR(0x00c07, 0x0008), + A6XX_PROTECT_RDONLY(0x00ce0, 0x0001), + A6XX_PROTECT_RDONLY(0x00df0, 0x0000), + A6XX_PROTECT_NORDWR(0x00df1, 0x0000), + A6XX_PROTECT_NORDWR(0x00df5, 0x0003), + A6XX_PROTECT_RDONLY(0x00df9, 0x0007), + A6XX_PROTECT_NORDWR(0x00e01, 0x0000), + A6XX_PROTECT_NORDWR(0x00e03, 0x1fff), + A6XX_PROTECT_NORDWR(0x03c00, 0x00c5), + A6XX_PROTECT_RDONLY(0x03cc6, 0x0039), + A6XX_PROTECT_NORDWR(0x03d00, 0x1fff), + A6XX_PROTECT_NORDWR(0x08600, 0x01ff), + A6XX_PROTECT_NORDWR(0x08e00, 0x00ff), + A6XX_PROTECT_RDONLY(0x08f00, 0x0000), + A6XX_PROTECT_NORDWR(0x08f01, 0x01be), + A6XX_PROTECT_NORDWR(0x09600, 0x01ff), + A6XX_PROTECT_RDONLY(0x0981a, 0x02e5), + A6XX_PROTECT_NORDWR(0x09e00, 0x01ff), + A6XX_PROTECT_NORDWR(0x0a600, 0x01ff), + A6XX_PROTECT_NORDWR(0x0a82e, 0x0000), + A6XX_PROTECT_NORDWR(0x0ae00, 0x0000), + A6XX_PROTECT_NORDWR(0x0ae02, 0x0004), + A6XX_PROTECT_NORDWR(0x0ae08, 0x0006), + A6XX_PROTECT_NORDWR(0x0ae10, 0x00bf), + A6XX_PROTECT_RDONLY(0x0aed0, 0x002f), + A6XX_PROTECT_NORDWR(0x0af00, 0x027f), + A6XX_PROTECT_NORDWR(0x0b600, 0x1fff), + A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff), + A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), + A6XX_PROTECT_NORDWR(0x18400, 0x003f), + A6XX_PROTECT_RDONLY(0x18440, 0x013f), + A6XX_PROTECT_NORDWR(0x18580, 0x1fff), + A6XX_PROTECT_NORDWR(0x1ac00, 0x1fff), + A6XX_PROTECT_NORDWR(0x1cc00, 0x1fff), + A6XX_PROTECT_NORDWR(0x1f400, 0x0477), + A6XX_PROTECT_RDONLY(0x1f878, 0x0507), + A6XX_PROTECT_NORDWR(0x1f930, 0x0329), + A6XX_PROTECT_NORDWR(0x1fd80, 0x1fff), + A6XX_PROTECT_NORDWR(0x27800, 0x007f), + A6XX_PROTECT_RDONLY(0x27880, 0x0385), + A6XX_PROTECT_NORDWR(0x27882, 0x0035), + A6XX_PROTECT_NORDWR(0x27c06, 0x0000), +}; +DECLARE_ADRENO_PROTECT(a850_protect, 15); + +static const u32 a850_pwrup_reglist_regs[] = { + REG_A8XX_RB_CMP_NC_MODE_CNTL, + REG_A8XX_SP_HLSQ_GC_GMEM_RANGE_MIN, + REG_A8XX_SP_HLSQ_GC_GMEM_RANGE_MIN + 1, + REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, + REG_A7XX_SP_READ_SEL, + REG_A8XX_CP_MULTIDRAW_CNTL, + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(0), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(1), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(2), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(3), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(4), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(5), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(6), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(7), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(8), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(9), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(10), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(11), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(12), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(13), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(14), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(15), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(16), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(17), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(18), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(19), + REG_A6XX_TPL1_DBG_ECO_CNTL, + REG_A6XX_TPL1_DBG_ECO_CNTL1, + REG_A6XX_TPL1_NC_MODE_CNTL, + REG_A6XX_UCHE_MODE_CNTL, + REG_A8XX_UCHE_CCHE_MODE_CNTL, + REG_A8XX_UCHE_HW_DBG_CNTL, + REG_A8XX_UCHE_CCHE_CACHE_WAYS, + REG_A8XX_UCHE_CCHE_GC_GMEM_RANGE_MIN, + REG_A8XX_UCHE_CCHE_GC_GMEM_RANGE_MIN + 1, + REG_A8XX_UCHE_CCHE_LPAC_GMEM_RANGE_MIN, + REG_A8XX_UCHE_CCHE_LPAC_GMEM_RANGE_MIN + 1, + REG_A8XX_UCHE_CCHE_TRAP_BASE, + REG_A8XX_UCHE_CCHE_TRAP_BASE + 1, + REG_A8XX_UCHE_CCHE_WRITE_THRU_BASE, + REG_A8XX_UCHE_CCHE_WRITE_THRU_BASE + 1, + REG_A8XX_UCHE_CLIENT_PF, + REG_A8XX_UCHE_DBG_ECO_CNTL_0, + REG_A8XX_UCHE_GBIF_GX_CONFIG, + REG_A8XX_UCHE_TRAP_BASE, + REG_A8XX_UCHE_TRAP_BASE + 1, + REG_A8XX_UCHE_VARB_IDLE_TIMEOUT, + REG_A8XX_UCHE_WRITE_THRU_BASE, + REG_A8XX_UCHE_WRITE_THRU_BASE + 1, + REG_A8XX_VSC_VISIBILITY_FLUSH_CNTL, +}; +DECLARE_ADRENO_REGLIST_LIST(a850_pwrup_reglist); + +static const u32 a850_ifpc_reglist_regs[] = { + REG_A8XX_CP_INTERRUPT_STATUS_MASK_GLOBAL, + REG_A8XX_RBBM_NC_MODE_CNTL, + REG_A8XX_RBBM_SLICE_INTERFACE_HANG_INT_CNTL, + REG_A8XX_RBBM_SLICE_NC_MODE_CNTL, + REG_A8XX_RBBM_SLICE_PERFCTR_CNTL, + REG_A6XX_SP_CHICKEN_BITS, + REG_A7XX_SP_CHICKEN_BITS_2, + REG_A7XX_SP_CHICKEN_BITS_3, + REG_A8XX_SP_CHICKEN_BITS_5, + REG_A7XX_SP_HLSQ_DBG_ECO_CNTL, + REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_1, + REG_A8XX_SP_HLSQ_DBG_ECO_CNTL_3, + REG_A8XX_SP_HLSQ_LPAC_GMEM_RANGE_MIN, + REG_A8XX_SP_HLSQ_LPAC_GMEM_RANGE_MIN + 1, + REG_A6XX_SP_NC_MODE_CNTL, + REG_A6XX_SP_PERFCTR_SHADER_MASK, + REG_A8XX_SP_L0_PERF_TUNE, + REG_A8XX_CP_PROTECT_GLOBAL(0), + REG_A8XX_CP_PROTECT_GLOBAL(1), + REG_A8XX_CP_PROTECT_GLOBAL(2), + REG_A8XX_CP_PROTECT_GLOBAL(3), + REG_A8XX_CP_PROTECT_GLOBAL(4), + REG_A8XX_CP_PROTECT_GLOBAL(5), + REG_A8XX_CP_PROTECT_GLOBAL(6), + REG_A8XX_CP_PROTECT_GLOBAL(7), + REG_A8XX_CP_PROTECT_GLOBAL(8), + REG_A8XX_CP_PROTECT_GLOBAL(9), + REG_A8XX_CP_PROTECT_GLOBAL(10), + REG_A8XX_CP_PROTECT_GLOBAL(11), + REG_A8XX_CP_PROTECT_GLOBAL(12), + REG_A8XX_CP_PROTECT_GLOBAL(13), + REG_A8XX_CP_PROTECT_GLOBAL(14), + REG_A8XX_CP_PROTECT_GLOBAL(15), + REG_A8XX_CP_PROTECT_GLOBAL(16), + REG_A8XX_CP_PROTECT_GLOBAL(17), + REG_A8XX_CP_PROTECT_GLOBAL(18), + REG_A8XX_CP_PROTECT_GLOBAL(19), + REG_A8XX_CP_PROTECT_GLOBAL(20), + REG_A8XX_CP_PROTECT_GLOBAL(21), + REG_A8XX_CP_PROTECT_GLOBAL(22), + REG_A8XX_CP_PROTECT_GLOBAL(23), + REG_A8XX_CP_PROTECT_GLOBAL(24), + REG_A8XX_CP_PROTECT_GLOBAL(25), + REG_A8XX_CP_PROTECT_GLOBAL(26), + REG_A8XX_CP_PROTECT_GLOBAL(27), + REG_A8XX_CP_PROTECT_GLOBAL(28), + REG_A8XX_CP_PROTECT_GLOBAL(29), + REG_A8XX_CP_PROTECT_GLOBAL(30), + REG_A8XX_CP_PROTECT_GLOBAL(31), + REG_A8XX_CP_PROTECT_GLOBAL(32), + REG_A8XX_CP_PROTECT_GLOBAL(33), + REG_A8XX_CP_PROTECT_GLOBAL(34), + REG_A8XX_CP_PROTECT_GLOBAL(35), + REG_A8XX_CP_PROTECT_GLOBAL(36), + REG_A8XX_CP_PROTECT_GLOBAL(37), + REG_A8XX_CP_PROTECT_GLOBAL(38), + REG_A8XX_CP_PROTECT_GLOBAL(39), + REG_A8XX_CP_PROTECT_GLOBAL(40), + REG_A8XX_CP_PROTECT_GLOBAL(41), + REG_A8XX_CP_PROTECT_GLOBAL(42), + REG_A8XX_CP_PROTECT_GLOBAL(43), + REG_A8XX_CP_PROTECT_GLOBAL(44), + REG_A8XX_CP_PROTECT_GLOBAL(45), + REG_A8XX_CP_PROTECT_GLOBAL(46), + REG_A8XX_CP_PROTECT_GLOBAL(47), + REG_A8XX_CP_PROTECT_GLOBAL(48), + REG_A8XX_CP_PROTECT_GLOBAL(49), + REG_A8XX_CP_PROTECT_GLOBAL(50), + REG_A8XX_CP_PROTECT_GLOBAL(51), + REG_A8XX_CP_PROTECT_GLOBAL(52), + REG_A8XX_CP_PROTECT_GLOBAL(53), + REG_A8XX_CP_PROTECT_GLOBAL(54), + REG_A8XX_CP_PROTECT_GLOBAL(55), + REG_A8XX_CP_PROTECT_GLOBAL(63), +}; +DECLARE_ADRENO_REGLIST_LIST(a850_ifpc_reglist); + +static const struct adreno_reglist a850_gbif[] = { + { REG_A6XX_GBIF_QSB_SIDE0, 0x00071e20 }, + { REG_A6XX_GBIF_QSB_SIDE1, 0x00071e20 }, + { REG_A6XX_GBIF_QSB_SIDE2, 0x00071e20 }, + { REG_A6XX_GBIF_QSB_SIDE3, 0x00071e20 }, + { REG_A6XX_GBIF_CX_CONFIG, 0x20023020 }, + { }, +}; + +static const struct adreno_reglist_pipe a850_dyn_pwrup_reglist_regs[] = { + { REG_A8XX_GRAS_TSEFE_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_GRAS_NC_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_GRAS_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_1, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_2, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_3, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_4, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_5, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_VIS_STREAM_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A7XX_RB_CCU_CNTL, 0, BIT(PIPE_BR) }, + { REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0, BIT(PIPE_BR)}, + { REG_A8XX_RB_CCU_NC_MODE_CNTL, 0, BIT(PIPE_BR) }, + { REG_A8XX_RB_CMP_NC_MODE_CNTL, 0, BIT(PIPE_BR) }, + { REG_A6XX_RB_RBP_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0, BIT(PIPE_BR) }, + { REG_A6XX_RB_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0, BIT(PIPE_BR) }, + { REG_A7XX_VFD_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BV_THRESHOLD, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BR_THRESHOLD, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_LP_REQ_CNT, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_CP_HW_FAULT_STATUS_MASK_PIPE, 0, BIT(PIPE_BR) | + BIT(PIPE_BV) | BIT(PIPE_LPAC) | BIT(PIPE_AQE0) | + BIT(PIPE_AQE1) | BIT(PIPE_DDE_BR) | BIT(PIPE_DDE_BV) }, + { REG_A8XX_CP_INTERRUPT_STATUS_MASK_PIPE, 0, BIT(PIPE_BR) | + BIT(PIPE_BV) | BIT(PIPE_LPAC) | BIT(PIPE_AQE0) | + BIT(PIPE_AQE1) | BIT(PIPE_DDE_BR) | BIT(PIPE_DDE_BV) }, + { REG_A8XX_CP_PROTECT_CNTL_PIPE, 0, BIT(PIPE_BR) | BIT(PIPE_BV) | BIT(PIPE_LPAC) }, + { REG_A8XX_CP_PROTECT_PIPE(15), 0, BIT(PIPE_BR) | BIT(PIPE_BV) | BIT(PIPE_LPAC) }, + { REG_A8XX_RB_GC_GMEM_PROTECT, 0, BIT(PIPE_BR) }, + { REG_A8XX_RB_LPAC_GMEM_PROTECT, 0, BIT(PIPE_BR) }, + { REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE, 0, BIT(PIPE_BR) }, +}; +DECLARE_ADRENO_REGLIST_PIPE_LIST(a850_dyn_pwrup_reglist); + +static const struct adreno_info a8xx_gpus[] = { + { + .chip_ids = ADRENO_CHIP_IDS(0x44050001), + .family = ADRENO_8XX_GEN1, + .fw = { + [ADRENO_FW_SQE] = "gen80000_sqe.fw", + [ADRENO_FW_GMU] = "gen80000_gmu.bin", + [ADRENO_FW_AQE] = "gen80000_aqe.fw", + }, + .gmem = 12 * SZ_1M, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV | + ADRENO_QUIRK_PREEMPTION | + ADRENO_QUIRK_IFPC, + .funcs = &a8xx_gpu_funcs, + .a6xx = &(const struct a6xx_info) { + .protect = &a830_protect, + .nonctxt_reglist = a830_nonctxt_regs, + .pwrup_reglist = &a830_pwrup_reglist, + .dyn_pwrup_reglist = &a830_dyn_pwrup_reglist, + .ifpc_reglist = &a830_ifpc_reglist, + .gbif_cx = a840_gbif, + .max_slices = 3, + .gmu_chipid = 0x8000100, + .bcms = (const struct a6xx_bcm[]) { + { .name = "SH0", .buswidth = 16 }, + { .name = "MC0", .buswidth = 4 }, + { + .name = "ACV", + .fixed = true, + .perfmode = BIT(2), + .perfmode_bw = 10687500, + }, + { /* sentinel */ }, + }, + }, + .preempt_record_size = 13536 * SZ_1K, + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 252, 0 }, + { 242, 1 }, + { 232, 2 }, + { 221, 3 }, + { 190, 4 }, + ), + }, { + .chip_ids = ADRENO_CHIP_IDS(0x44070001), + .family = ADRENO_8XX_GEN2, + .fw = { + [ADRENO_FW_SQE] = "gen80100_sqe.fw", + [ADRENO_FW_GMU] = "gen80100_gmu.bin", + }, + .gmem = 21 * SZ_1M, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV | + ADRENO_QUIRK_PREEMPTION | + ADRENO_QUIRK_SOFTFUSE, + .funcs = &a8xx_gpu_funcs, + .a6xx = &(const struct a6xx_info) { + .protect = &x285_protect, + .nonctxt_reglist = x285_nonctxt_regs, + .pwrup_reglist = &a840_pwrup_reglist, + .dyn_pwrup_reglist = &x285_dyn_pwrup_reglist, + .ifpc_reglist = &a840_ifpc_reglist, + .gbif_cx = a840_gbif, + .max_slices = 4, + .gmu_chipid = 0x8010100, + .bcms = (const struct a6xx_bcm[]) { + { .name = "SH0", .buswidth = 16 }, + { .name = "MC0", .buswidth = 4 }, + { + .name = "ACV", + .fixed = true, + .perfmode = BIT(2), + .perfmode_bw = 16500000, + }, + { /* sentinel */ }, + }, + .clx_tbl = &x285_clx_tbl, + .limits_tbl = &x285_limits, + }, + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 388, 1 }, + { 357, 2 }, + { 284, 3 }, + ), + }, { + .chip_ids = ADRENO_CHIP_IDS(0x44050a01), + .family = ADRENO_8XX_GEN2, + .fw = { + [ADRENO_FW_SQE] = "gen80200_sqe.fw", + [ADRENO_FW_GMU] = "gen80200_gmu.bin", + [ADRENO_FW_AQE] = "gen80200_aqe.fw", + }, + .gmem = 18 * SZ_1M, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV | + ADRENO_QUIRK_PREEMPTION | + ADRENO_QUIRK_IFPC, + .funcs = &a8xx_gpu_funcs, + .a6xx = &(const struct a6xx_info) { + .protect = &a840_protect, + .nonctxt_reglist = a840_nonctxt_regs, + .pwrup_reglist = &a840_pwrup_reglist, + .dyn_pwrup_reglist = &a840_dyn_pwrup_reglist, + .ifpc_reglist = &a840_ifpc_reglist, + .gbif_cx = a840_gbif, + .max_slices = 3, + .gmu_chipid = 0x8020100, + .bcms = (const struct a6xx_bcm[]) { + { .name = "SH0", .buswidth = 16 }, + { .name = "MC0", .buswidth = 4 }, + { + .name = "ACV", + .fixed = true, + .perfmode = BIT(2), + .perfmode_bw = 10687500, + }, + { /* sentinel */ }, + }, + .clx_tbl = &a840_clx_tbl, + .limits_tbl = &a840_limits, + }, + .preempt_record_size = 19708 * SZ_1K, + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 273, 1 }, + { 252, 2 }, + { 221, 3 }, + ), + }, { + .chip_ids = ADRENO_CHIP_IDS(0x44010000), + .family = ADRENO_8XX_GEN1, + .fw = { + [ADRENO_FW_SQE] = "gen80300_sqe.fw", + [ADRENO_FW_GMU] = "gen80300_gmu.bin", + }, + .gmem = SZ_512K + SZ_64K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV | + ADRENO_QUIRK_PREEMPTION | + ADRENO_QUIRK_IFPC, + .funcs = &a8xx_gpu_funcs, + .zapfw = "gen80300_zap.mbn", + .a6xx = &(const struct a6xx_info) { + .protect = &a810_protect, + .nonctxt_reglist = a810_nonctxt_regs, + .pwrup_reglist = &a810_pwrup_reglist, + .dyn_pwrup_reglist = &a810_dyn_pwrup_reglist, + .ifpc_reglist = &a810_ifpc_reglist, + .gbif_cx = a840_gbif, + .max_slices = 1, + .gmu_chipid = 0x8030000, + .bcms = (const struct a6xx_bcm[]) { + { .name = "SH0", .buswidth = 16 }, + { .name = "MC0", .buswidth = 4 }, + { + .name = "ACV", + .fixed = true, + .perfmode = BIT(2), + .perfmode_bw = 10687500, + }, + { /* sentinel */ }, + }, + }, + .preempt_record_size = 4558 * SZ_1K, + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 242, 1 }, + { 221, 2 }, + ), + }, { + .chip_ids = ADRENO_CHIP_IDS(0x44060000), + .family = ADRENO_8XX_GEN2, + .fw = { + [ADRENO_FW_SQE] = "gen80100_sqe.fw", + [ADRENO_FW_GMU] = "gen80100_gmu.bin", + [ADRENO_FW_AQE] = "gen80100_aqe.fw", + }, + .gmem = 15 * SZ_1M + SZ_512K + SZ_256K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV | + ADRENO_QUIRK_PREEMPTION | + ADRENO_QUIRK_SOFTFUSE, + .funcs = &a8xx_gpu_funcs, + .a6xx = &(const struct a6xx_info) { + .protect = &x285_protect, + .nonctxt_reglist = x285_nonctxt_regs, + .pwrup_reglist = &a840_pwrup_reglist, + .dyn_pwrup_reglist = &x285_dyn_pwrup_reglist, + .ifpc_reglist = &a840_ifpc_reglist, + .gbif_cx = a840_gbif, + .max_slices = 3, + .gmu_chipid = 0x80a0000, + .bcms = (const struct a6xx_bcm[]) { + { .name = "SH0", .buswidth = 16 }, + { .name = "MC0", .buswidth = 4 }, + { + .name = "ACV", + .fixed = true, + .perfmode = BIT(2), + .perfmode_bw = 16500000, + }, + { /* sentinel */ }, + }, + }, + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 388, 1 }, + { 357, 2 }, + { 284, 3 }, + ), + }, { + .chip_ids = ADRENO_CHIP_IDS(0x44041400), + .family = ADRENO_8XX_GEN2, + .fw = { + [ADRENO_FW_SQE] = "gen81100_sqe.fw", + [ADRENO_FW_GMU] = "gen81400_gmu.bin", + [ADRENO_FW_AQE] = "gen81100_aqe.fw", + }, + .gmem = 12 * SZ_1M, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV | + ADRENO_QUIRK_PREEMPTION | + ADRENO_QUIRK_IFPC, + .funcs = &a8xx_gpu_funcs, + .a6xx = &(const struct a6xx_info) { + .protect = &a850_protect, + .nonctxt_reglist = a845_nonctxt_regs, + .pwrup_reglist = &a850_pwrup_reglist, + .dyn_pwrup_reglist = &a850_dyn_pwrup_reglist, + .ifpc_reglist = &a850_ifpc_reglist, + .gbif_cx = a850_gbif, + .max_slices = 3, + .gmu_chipid = 0x80e0000, + .thinmem_config = 14, + .bcms = (const struct a6xx_bcm[]) { + { .name = "SH0", .buswidth = 32 }, + { .name = "MC0", .buswidth = 4 }, + { + .name = "ACV", + .fixed = true, + .perfmode = BIT(2), + .perfmode_bw = 16500000, + }, + { /* sentinel */ }, + }, + }, + .preempt_record_size = 13564 * SZ_1K, + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 0xd8, 0 }, + { 0x11c, 1 }, + ), + }, { + .chip_ids = ADRENO_CHIP_IDS(0x44051401), + .family = ADRENO_8XX_GEN2, + .fw = { + [ADRENO_FW_SQE] = "gen81100_sqe.fw", + [ADRENO_FW_GMU] = "gen81100_gmu.bin", + [ADRENO_FW_AQE] = "gen81100_aqe.fw", + }, + .gmem = 18 * SZ_1M, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV | + ADRENO_QUIRK_PREEMPTION | + ADRENO_QUIRK_IFPC, + .funcs = &a8xx_gpu_funcs, + .a6xx = &(const struct a6xx_info) { + .protect = &a850_protect, + .nonctxt_reglist = a850_nonctxt_regs, + .pwrup_reglist = &a850_pwrup_reglist, + .dyn_pwrup_reglist = &a850_dyn_pwrup_reglist, + .ifpc_reglist = &a850_ifpc_reglist, + .gbif_cx = a850_gbif, + .max_slices = 3, + .gmu_chipid = 0x80b0100, + .thinmem_config = 14, + .bcms = (const struct a6xx_bcm[]) { + { .name = "SH0", .buswidth = 32 }, + { .name = "MC0", .buswidth = 4 }, + { + .name = "ACV", + .fixed = true, + .perfmode = BIT(2), + .perfmode_bw = 16500000, + }, + { /* sentinel */ }, + }, + }, + .preempt_record_size = 19708 * SZ_1K, + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 284, 2 }, + { 216, 3 }, + ), + } +}; + +DECLARE_ADRENO_GPULIST(a8xx); + +static inline __always_unused void __build_asserts(void) +{ + BUILD_BUG_ON(a810_protect.count > a810_protect.count_max); + BUILD_BUG_ON(a830_protect.count > a830_protect.count_max); +} diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c index add93c1fa039..f892731cd3d3 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c @@ -112,6 +112,9 @@ void a8xx_gpu_get_slice_info(struct msm_gpu *gpu) /* Chip ID depends on the number of slices available. So update it */ adreno_gpu->chip_id |= FIELD_PREP(GENMASK(7, 4), hweight32(slice_mask)); + /* GMEM is split evenly between slices: report the active share */ + adreno_gpu->gmem = (adreno_gpu->info->gmem / info->max_slices) * hweight32(slice_mask); + /* Update the gpu-name to reflect the slice config: */ const char *name = devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT, @@ -200,7 +203,7 @@ static void a8xx_set_hwcg(struct msm_gpu *gpu, bool state) struct a6xx_gmu *gmu = &a6xx_gpu->gmu; u32 val; - if (adreno_is_x285(adreno_gpu) && state) + if ((adreno_is_x285_family(adreno_gpu) || adreno_is_a830(adreno_gpu)) && state) gpu_write(gpu, REG_A8XX_RBBM_CGC_0_PC, 0x00000702); gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, @@ -286,10 +289,11 @@ static void a8xx_set_ubwc_config(struct msm_gpu *gpu) u32 hbb, hbb_hi, hbb_lo, mode; u8 uavflagprd_inv = 2; - if (ubwc_version > UBWC_6_0) + if (ubwc_version > UBWC_7_0) dev_err(&gpu->pdev->dev, "Unknown UBWC version: 0x%x\n", ubwc_version); - if (ubwc_version == UBWC_6_0) + if (ubwc_version == UBWC_6_0 || + ubwc_version == UBWC_7_0) yuvnotcomptofc = true; if (ubwc_version < UBWC_5_0 && @@ -726,6 +730,7 @@ static int hw_init(struct msm_gpu *gpu) for (pipe_id = PIPE_BR; pipe_id <= PIPE_DDE_BV; pipe_id++) { u32 apriv_mask = A8XX_APRIV_MASK; + u32 int_mask = A8XX_CP_INTERRUPT_STATUS_MASK_PIPE; unsigned long flags; if (pipe_id == PIPE_LPAC) @@ -734,10 +739,16 @@ static int hw_init(struct msm_gpu *gpu) if (pipe_id == PIPE_BR) apriv_mask = A8XX_BR_APRIV_MASK; + /* + * A845/A850's BV pipe raises a spurious RTWROVF fault interrupt; + * mask it off to avoid false fault recovery. + */ + if (adreno_is_a850_family(adreno_gpu) && pipe_id == PIPE_BV) + int_mask &= ~A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_RTWROVF; + a8xx_aperture_acquire(gpu, pipe_id, &flags); gpu_write(gpu, REG_A8XX_CP_APRIV_CNTL_PIPE, apriv_mask); - gpu_write(gpu, REG_A8XX_CP_INTERRUPT_STATUS_MASK_PIPE, - A8XX_CP_INTERRUPT_STATUS_MASK_PIPE); + gpu_write(gpu, REG_A8XX_CP_INTERRUPT_STATUS_MASK_PIPE, int_mask); gpu_write(gpu, REG_A8XX_CP_HW_FAULT_STATUS_MASK_PIPE, A8XX_CP_HW_FAULT_STATUS_MASK_PIPE); a8xx_aperture_release(gpu, flags); diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 05c77fe27e62..7108d4aa59b5 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -271,8 +271,10 @@ static const struct component_ops a3xx_ops = { static int adreno_probe(struct platform_device *pdev) { - if (of_device_is_compatible(pdev->dev.of_node, "amd,imageon") || - msm_gpu_no_components()) + struct device_node *node = pdev->dev.of_node; + + if (of_device_is_compatible(node, "amd,imageon") || + (msm_separate_gpu_kms_components() && adreno_has_gpu(node))) return msm_gpu_probe(pdev, &a3xx_ops); return component_add(&pdev->dev, &a3xx_ops); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 5832dc25d6bf..dadfe4c69438 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -379,7 +379,7 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_context *ctx, *value = adreno_gpu->info->revn; return 0; case MSM_PARAM_GMEM_SIZE: - *value = adreno_gpu->info->gmem; + *value = adreno_gpu->gmem; return 0; case MSM_PARAM_GMEM_BASE: if (adreno_gpu->info->family >= ADRENO_6XX_GEN3) @@ -1205,6 +1205,7 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, adreno_gpu->funcs = funcs; adreno_gpu->info = config->info; adreno_gpu->chip_id = config->chip_id; + adreno_gpu->gmem = config->info->gmem; gpu->allow_relocs = config->info->family < ADRENO_6XX_GEN1; gpu->pdev = pdev; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 114a40f79ef3..4b2156825bdf 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -204,6 +204,8 @@ struct adreno_gpu { struct msm_gpu base; const struct adreno_info *info; uint32_t chip_id; + /* GMEM size available to userspace, see a8xx_gpu_get_slice_info(): */ + uint32_t gmem; uint16_t speedbin; const struct adreno_gpu_funcs *funcs; @@ -580,6 +582,11 @@ static inline int adreno_is_a750_family(struct adreno_gpu *gpu) return gpu->info->family == ADRENO_7XX_GEN3; } +static inline int adreno_is_a6xx(struct adreno_gpu *gpu) +{ + return (gpu->info->family >= ADRENO_6XX_GEN1) && (gpu->info->family < ADRENO_7XX_GEN1); +} + static inline int adreno_is_a7xx(struct adreno_gpu *gpu) { /* Update with non-fake (i.e. non-A702) Gen 7 GPUs */ @@ -597,9 +604,17 @@ static inline int adreno_is_a810(struct adreno_gpu *gpu) return gpu->info->chip_ids[0] == 0x44010000; } -static inline int adreno_is_x285(struct adreno_gpu *gpu) +static inline int adreno_is_x285_family(const struct adreno_gpu *gpu) +{ + if (WARN_ON_ONCE(!gpu->info)) + return false; + return gpu->info->chip_ids[0] == 0x44060000 || + gpu->info->chip_ids[0] == 0x44070001; +} + +static inline int adreno_is_a830(struct adreno_gpu *gpu) { - return gpu->info->chip_ids[0] == 0x44070001; + return gpu->info->chip_ids[0] == 0x44050001; } static inline int adreno_is_a840(struct adreno_gpu *gpu) @@ -607,6 +622,22 @@ static inline int adreno_is_a840(struct adreno_gpu *gpu) return gpu->info->chip_ids[0] == 0x44050a01; } +static inline int adreno_is_a845(struct adreno_gpu *gpu) +{ + return gpu->info->chip_ids[0] == 0x44041400; +} + +static inline int adreno_is_a850(struct adreno_gpu *gpu) +{ + return gpu->info->chip_ids[0] == 0x44051401; +} + +static inline int adreno_is_a850_family(struct adreno_gpu *gpu) +{ + return adreno_is_a845(gpu) || + adreno_is_a850(gpu); +} + /* Put vm_start above 32b to catch issues with not setting xyz_BASE_HI */ #define ADRENO_VM_START 0x100000000ULL u64 adreno_private_vm_size(struct msm_gpu *gpu); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c index fea173e37464..9fa55904dba1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c @@ -54,24 +54,19 @@ u64 dpu_core_perf_adjusted_mode_clk(u64 mode_clk_rate, /** * _dpu_core_perf_calc_bw() - to calculate BW per crtc * @perf_cfg: performance configuration - * @crtc: pointer to a crtc + * @state: the CRTC state * Return: returns aggregated BW for all planes in crtc. */ static u64 _dpu_core_perf_calc_bw(const struct dpu_perf_cfg *perf_cfg, - struct drm_crtc *crtc) + struct drm_crtc_state *state) { struct drm_plane *plane; - struct dpu_plane_state *pstate; + const struct drm_plane_state *plane_state; u64 crtc_plane_bw = 0; u32 bw_factor; - drm_atomic_crtc_for_each_plane(plane, crtc) { - pstate = to_dpu_plane_state(plane->state); - if (!pstate) - continue; - - crtc_plane_bw += pstate->plane_fetch_bw; - } + drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, state) + crtc_plane_bw += to_dpu_plane_state(plane_state)->plane_fetch_bw; bw_factor = perf_cfg->bw_inefficiency_factor; if (bw_factor) { @@ -131,7 +126,7 @@ static void _dpu_core_perf_calc_crtc(const struct dpu_core_perf *core_perf, return; } - perf->bw_ctl = _dpu_core_perf_calc_bw(perf_cfg, crtc); + perf->bw_ctl = _dpu_core_perf_calc_bw(perf_cfg, state); perf->max_per_pipe_ib = perf_cfg->min_dram_ib; perf->core_clk_rate = _dpu_core_perf_calc_clk(perf_cfg, crtc, state); DRM_DEBUG_ATOMIC( diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 1f20695f81e3..0a6be69a3e83 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -1386,7 +1386,6 @@ static void dpu_encoder_virt_atomic_disable(struct drm_encoder *drm_enc, struct dpu_encoder_virt *dpu_enc = NULL; struct drm_crtc *crtc; struct drm_crtc_state *old_state = NULL; - int i = 0; dpu_enc = to_dpu_encoder_virt(drm_enc); DPU_DEBUG_ENC(dpu_enc, "\n"); @@ -1412,12 +1411,11 @@ static void dpu_encoder_virt_atomic_disable(struct drm_encoder *drm_enc, dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_PRE_STOP); - for (i = 0; i < dpu_enc->num_phys_encs; i++) { - struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; + if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.disable) + dpu_enc->cur_slave->ops.disable(dpu_enc->cur_slave); - if (phys->ops.disable) - phys->ops.disable(phys); - } + if (dpu_enc->cur_master && dpu_enc->cur_master->ops.disable) + dpu_enc->cur_master->ops.disable(dpu_enc->cur_master); /* after phys waits for frame-done, should be no more frames pending */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index ba810f26ea30..2ac517db50fc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -134,8 +134,8 @@ static void drm_mode_to_intf_timing_params( * TODO: replace drm_dsc_get_bpp_int with logic to handle * fractional part if there is fraction */ - timing->width = timing->width * drm_dsc_get_bpp_int(dsc) / - (dsc->bits_per_component * 3); + timing->width = DIV_ROUND_UP(timing->width * drm_dsc_get_bpp_int(dsc), + dsc->bits_per_component * 3); timing->xres = timing->width; timing->dce_bytes_per_line = msm_dsc_get_bytes_per_line(dsc); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 9a993cdfab85..107150a8553f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -428,6 +428,8 @@ static const struct dpu_dspp_sub_blks sdm845_dspp_sblk = { static const struct dpu_dspp_sub_blks sm8750_dspp_sblk = { .pcc = {.name = "pcc", .base = 0x1700, .len = 0x90, .version = 0x60000}, + .gc = {.name = "gc", .base = 0x17c0, + .len = 0x40, .version = 0x10008}, }; /************************************************************* diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c index 9b1d1982e683..c299fef1a400 100644 --- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c +++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c @@ -15,6 +15,20 @@ #include "msm_mmu.h" #include "mdp4_kms.h" +static const struct of_device_id mdp4_dt_match[]; +int msm_count_mdp4(void) +{ + struct device_node *np; + int count = 0; + + for_each_matching_node(np, mdp4_dt_match) { + if (of_device_is_available(np)) + count++; + } + + return count; +} + static int mdp4_hw_init(struct msm_kms *kms) { struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c index 7c91fc1915f3..c54aaab2f5bd 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c @@ -698,15 +698,6 @@ static const struct mdp5_cfg_hw msm8x76_config = { MDP_PIPE_CAP_SW_PIX_EXT | 0, }, - .pipe_cursor = { - .count = 1, - .base = { 0x440DC }, - .caps = MDP_PIPE_CAP_HFLIP | - MDP_PIPE_CAP_VFLIP | - MDP_PIPE_CAP_SW_PIX_EXT | - MDP_PIPE_CAP_CURSOR | - 0, - }, .lm = { .count = 2, .base = { 0x44000, 0x45000 }, @@ -744,6 +735,77 @@ static const struct mdp5_cfg_hw msm8x76_config = { .max_clk = 360000000, }; +static const struct mdp5_cfg_hw msm8952_config = { + .name = "msm8952", + .mdp = { + .count = 1, + .base = { 0x0 }, + .caps = MDP_CAP_SMP | + 0, + }, + .smp = { + .mmb_count = 8, + .mmb_size = 8192, + .clients = { + [SSPP_VIG0] = 1, [SSPP_DMA0] = 4, + [SSPP_RGB0] = 7, [SSPP_RGB1] = 8, + }, + }, + .ctl = { + .count = 3, + .base = { 0x01000, 0x01200, 0x01400 }, + .flush_hw_mask = 0xffffffff, + }, + .pipe_vig = { + .count = 1, + .base = { 0x04000 }, + .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP | + MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC | + MDP_PIPE_CAP_DECIMATION, + }, + .pipe_rgb = { + .count = 2, + .base = { 0x14000, 0x16000 }, + .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP | + MDP_PIPE_CAP_DECIMATION, + }, + .pipe_dma = { + .count = 1, + .base = { 0x24000 }, + .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP, + }, + .lm = { + .count = 2, + .base = { 0x44000, 0x47000 }, + .instances = { + { .id = 0, .pp = 0, .dspp = 0, + .caps = MDP_LM_CAP_DISPLAY, }, + { .id = 3, .pp = -1, .dspp = -1, + .caps = MDP_LM_CAP_WB }, + }, + .nb_stages = 8, + .max_width = 2048, + .max_height = 0xFFFF, + }, + .dspp = { + .count = 1, + .base = { 0x54000 }, + + }, + .pp = { + .count = 3, + .base = { 0x70000, 0x70800, 0x72000 }, + }, + .intf = { + .base = { 0x00000, 0x6a800 }, + .connect = { + [0] = INTF_DISABLED, + [1] = INTF_DSI, + }, + }, + .max_clk = 320000000, +}; + static const struct mdp5_cfg_hw msm8x53_config = { .name = "msm8x53", .mdp = { @@ -1017,6 +1079,7 @@ static const struct mdp5_cfg_handler cfg_handlers_v1[] = { { .revision = 9, .config = { .hw = &msm8x94_config } }, { .revision = 7, .config = { .hw = &msm8x96_config } }, { .revision = 11, .config = { .hw = &msm8x76_config } }, + { .revision = 12, .config = { .hw = &msm8952_config } }, { .revision = 14, .config = { .hw = &msm8937_config } }, { .revision = 15, .config = { .hw = &msm8917_config } }, { .revision = 16, .config = { .hw = &msm8x53_config } }, diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index 59070f399e2d..abd3dcdad03c 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -117,6 +117,8 @@ struct msm_dp_ctrl_private { struct msm_dp_link *link; void __iomem *ahb_base; void __iomem *link_base; + void __iomem *mst2link_base; + void __iomem *mst3link_base; struct phy *phy; @@ -126,7 +128,8 @@ struct msm_dp_ctrl_private { unsigned int num_link_clks; struct clk_bulk_data *link_clks; - struct clk *pixel_clk; + struct clk *pixel_clk[DP_STREAM_MAX]; + unsigned int num_pixel_clks; union phy_configure_opts phy_opts; @@ -138,7 +141,7 @@ struct msm_dp_ctrl_private { bool core_clks_on; bool link_clks_on; - bool stream_clks_on; + bool stream_clks_on[DP_STREAM_MAX]; }; static inline u32 msm_dp_read_ahb(const struct msm_dp_ctrl_private *ctrl, u32 offset) @@ -171,6 +174,49 @@ static inline void msm_dp_write_link(struct msm_dp_ctrl_private *ctrl, writel(data, ctrl->link_base + offset); } +static inline u32 msm_dp_read_stream_link(struct msm_dp_ctrl_private *ctrl, + enum msm_dp_stream_id stream_id, u32 offset) +{ + offset = msm_dp_stream_reg(stream_id, offset); + switch (stream_id) { + case DP_STREAM_0: + case DP_STREAM_1: + return readl_relaxed(ctrl->link_base + offset); + case DP_STREAM_2: + return readl_relaxed(ctrl->mst2link_base + offset); + case DP_STREAM_3: + return readl_relaxed(ctrl->mst3link_base + offset); + default: + DRM_ERROR("error stream_id\n"); + return 0; + } +} + +static inline void msm_dp_write_stream_link(struct msm_dp_ctrl_private *ctrl, + enum msm_dp_stream_id stream_id, u32 offset, u32 data) +{ + /* + * To make sure link reg writes happens before any other operation, + * this function uses writel() instread of writel_relaxed() + */ + offset = msm_dp_stream_reg(stream_id, offset); + switch (stream_id) { + case DP_STREAM_0: + case DP_STREAM_1: + writel(data, ctrl->link_base + offset); + break; + case DP_STREAM_2: + writel(data, ctrl->mst2link_base + offset); + break; + case DP_STREAM_3: + writel(data, ctrl->mst3link_base + offset); + break; + default: + DRM_ERROR("error stream_id\n"); + break; + } +} + static int msm_dp_aux_link_configure(struct drm_dp_aux *aux, struct msm_dp_link_info *link) { @@ -396,7 +442,8 @@ static void msm_dp_ctrl_config_ctrl_streams(struct msm_dp_ctrl_private *ctrl, * RMW: called from atomic_enable(), serialized by the DRM atomic framework. * Clear stream-specific fields before OR-ing to avoid bit accumulation. */ - config = msm_dp_read_link(ctrl, REG_DP_CONFIGURATION_CTRL); + config = msm_dp_read_stream_link(ctrl, msm_dp_panel->stream_id, + REG_DP_CONFIGURATION_CTRL); config &= ~(DP_CONFIGURATION_CTRL_RGB_YUV_MASK | DP_CONFIGURATION_CTRL_BPC_MASK | DP_CONFIGURATION_CTRL_SEND_VSC); @@ -414,7 +461,7 @@ static void msm_dp_ctrl_config_ctrl_streams(struct msm_dp_ctrl_private *ctrl, drm_dbg_dp(ctrl->drm_dev, "stream DP_CONFIGURATION_CTRL=0x%x\n", config); - msm_dp_write_link(ctrl, REG_DP_CONFIGURATION_CTRL, config); + msm_dp_write_stream_link(ctrl, msm_dp_panel->stream_id, REG_DP_CONFIGURATION_CTRL, config); } static void msm_dp_ctrl_config_ctrl_link(struct msm_dp_ctrl_private *ctrl, @@ -471,7 +518,7 @@ static void msm_dp_ctrl_config_misc1_misc0(struct msm_dp_ctrl_private *ctrl, msm_dp_panel->msm_dp_mode.bpp); colorimetry_cfg = msm_dp_link_get_colorimetry_config(ctrl->link); - misc_val = msm_dp_read_link(ctrl, REG_DP_MISC1_MISC0); + misc_val = msm_dp_read_stream_link(ctrl, msm_dp_panel->stream_id, REG_DP_MISC1_MISC0); /* clear bpp bits */ misc_val &= ~(0x07 << DP_MISC0_TEST_BITS_DEPTH_SHIFT); @@ -481,7 +528,7 @@ static void msm_dp_ctrl_config_misc1_misc0(struct msm_dp_ctrl_private *ctrl, misc_val |= DP_MISC0_SYNCHRONOUS_CLK; drm_dbg_dp(ctrl->drm_dev, "misc settings = 0x%x\n", misc_val); - msm_dp_write_link(ctrl, REG_DP_MISC1_MISC0, misc_val); + msm_dp_write_stream_link(ctrl, msm_dp_panel->stream_id, REG_DP_MISC1_MISC0, misc_val); } static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private *ctrl, @@ -1750,7 +1797,7 @@ int msm_dp_ctrl_core_clk_enable(struct msm_dp_ctrl *msm_dp_ctrl) drm_dbg_dp(ctrl->drm_dev, "enable core clocks \n"); drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n", - str_on_off(ctrl->stream_clks_on), + str_on_off(ctrl->stream_clks_on[DP_STREAM_0]), str_on_off(ctrl->link_clks_on), str_on_off(ctrl->core_clks_on)); @@ -1769,7 +1816,7 @@ void msm_dp_ctrl_core_clk_disable(struct msm_dp_ctrl *msm_dp_ctrl) drm_dbg_dp(ctrl->drm_dev, "disable core clocks \n"); drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n", - str_on_off(ctrl->stream_clks_on), + str_on_off(ctrl->stream_clks_on[DP_STREAM_0]), str_on_off(ctrl->link_clks_on), str_on_off(ctrl->core_clks_on)); } @@ -1800,7 +1847,7 @@ static int msm_dp_ctrl_link_clk_enable(struct msm_dp_ctrl *msm_dp_ctrl) drm_dbg_dp(ctrl->drm_dev, "enable link clocks\n"); drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n", - str_on_off(ctrl->stream_clks_on), + str_on_off(ctrl->stream_clks_on[DP_STREAM_0]), str_on_off(ctrl->link_clks_on), str_on_off(ctrl->core_clks_on)); @@ -1819,7 +1866,7 @@ static void msm_dp_ctrl_link_clk_disable(struct msm_dp_ctrl *msm_dp_ctrl) drm_dbg_dp(ctrl->drm_dev, "disabled link clocks\n"); drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n", - str_on_off(ctrl->stream_clks_on), + str_on_off(ctrl->stream_clks_on[DP_STREAM_0]), str_on_off(ctrl->link_clks_on), str_on_off(ctrl->core_clks_on)); } @@ -2190,38 +2237,39 @@ static bool msm_dp_ctrl_send_phy_test_pattern(struct msm_dp_ctrl_private *ctrl) return success; } -static int msm_dp_ctrl_on_pixel_clk(struct msm_dp_ctrl_private *ctrl, unsigned long pixel_rate) +static int msm_dp_ctrl_on_pixel_clk(struct msm_dp_ctrl_private *ctrl, unsigned long pixel_rate, + enum msm_dp_stream_id stream_id) { int ret; - ret = clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); + ret = clk_set_rate(ctrl->pixel_clk[stream_id], pixel_rate * 1000); if (ret) { DRM_ERROR("Failed to set pixel clock rate. ret=%d\n", ret); return ret; } - if (WARN_ON_ONCE(ctrl->stream_clks_on)) - return 0; + if (WARN_ON_ONCE(ctrl->stream_clks_on[stream_id])) + return -EINVAL; - ret = clk_prepare_enable(ctrl->pixel_clk); + ret = clk_prepare_enable(ctrl->pixel_clk[stream_id]); if (ret) { DRM_ERROR("Failed to start pixel clocks. ret=%d\n", ret); return ret; } - ctrl->stream_clks_on = true; + ctrl->stream_clks_on[stream_id] = true; return ret; } -void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl) +void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl, enum msm_dp_stream_id stream_id) { struct msm_dp_ctrl_private *ctrl; ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); - if (ctrl->stream_clks_on) { - clk_disable_unprepare(ctrl->pixel_clk); - ctrl->stream_clks_on = false; + if (ctrl->stream_clks_on[stream_id]) { + clk_disable_unprepare(ctrl->pixel_clk[stream_id]); + ctrl->stream_clks_on[stream_id] = false; } } @@ -2242,7 +2290,7 @@ static int msm_dp_ctrl_process_phy_test_request(struct msm_dp_ctrl_private *ctrl * running. Add the global reset just before disabling the * link clocks and core clocks. */ - msm_dp_ctrl_off_pixel_clk(&ctrl->msm_dp_ctrl); + msm_dp_ctrl_off_pixel_clk(&ctrl->msm_dp_ctrl, panel->stream_id); msm_dp_ctrl_off_link(&ctrl->msm_dp_ctrl, panel); ret = msm_dp_ctrl_on_link(&ctrl->msm_dp_ctrl, panel); @@ -2252,7 +2300,7 @@ static int msm_dp_ctrl_process_phy_test_request(struct msm_dp_ctrl_private *ctrl } pixel_rate = panel->msm_dp_mode.drm_mode.clock; - ret = msm_dp_ctrl_on_pixel_clk(ctrl, pixel_rate); + ret = msm_dp_ctrl_on_pixel_clk(ctrl, pixel_rate, panel->stream_id); if (ret) return ret; @@ -2434,6 +2482,9 @@ int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl, if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) return rc; + if (!link_train_max_retries) + rc = -ETIMEDOUT; + if (rc == 0) { /* link train successfully */ /* * do not stop train pattern here @@ -2463,14 +2514,14 @@ static int msm_dp_ctrl_link_retrain(struct msm_dp_ctrl_private *ctrl, } static void msm_dp_ctrl_config_msa(struct msm_dp_ctrl_private *ctrl, - u32 rate, u32 stream_rate_khz, - bool is_ycbcr_420) + struct msm_dp_panel *panel, u32 rate) { u32 pixel_m, pixel_n; u32 mvid, nvid, pixel_div, dispcc_input_rate; u32 const nvid_fixed = DP_LINK_CONSTANT_N_VALUE; u32 const link_rate_hbr2 = 540000; u32 const link_rate_hbr3 = 810000; + u32 stream_rate_khz = panel->msm_dp_mode.drm_mode.clock; unsigned long den, num; switch (rate) { @@ -2516,7 +2567,7 @@ static void msm_dp_ctrl_config_msa(struct msm_dp_ctrl_private *ctrl, nvid = temp; } - if (is_ycbcr_420) + if (panel->msm_dp_mode.out_fmt_is_yuv_420) mvid /= 2; if (link_rate_hbr2 == rate) @@ -2526,8 +2577,8 @@ static void msm_dp_ctrl_config_msa(struct msm_dp_ctrl_private *ctrl, nvid *= 3; drm_dbg_dp(ctrl->drm_dev, "mvid=0x%x, nvid=0x%x\n", mvid, nvid); - msm_dp_write_link(ctrl, REG_DP_SOFTWARE_MVID, mvid); - msm_dp_write_link(ctrl, REG_DP_SOFTWARE_NVID, nvid); + msm_dp_write_stream_link(ctrl, panel->stream_id, REG_DP_SOFTWARE_MVID, mvid); + msm_dp_write_stream_link(ctrl, panel->stream_id, REG_DP_SOFTWARE_NVID, nvid); } int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, @@ -2546,9 +2597,8 @@ int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, ctrl->link->link_params.rate, ctrl->link->link_params.num_lanes); - drm_dbg_dp(ctrl->drm_dev, - "core_clk_on=%d link_clk_on=%d stream_clk_on=%d\n", - ctrl->core_clks_on, ctrl->link_clks_on, ctrl->stream_clks_on); + drm_dbg_dp(ctrl->drm_dev, "core_clk_on=%d link_clk_on=%d\n", + ctrl->core_clks_on, ctrl->link_clks_on); if (!ctrl->link_clks_on) { /* link clk is off */ ret = msm_dp_ctrl_enable_mainlink_clocks(ctrl, panel); @@ -2573,22 +2623,20 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel * bool mainlink_ready = false; struct msm_dp_ctrl_private *ctrl; unsigned long pixel_rate; - unsigned long pixel_rate_orig; if (!msm_dp_ctrl) return -EINVAL; ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); - pixel_rate_orig = panel->msm_dp_mode.drm_mode.clock; - pixel_rate = pixel_rate_orig; + pixel_rate = panel->msm_dp_mode.drm_mode.clock; if (msm_dp_ctrl->wide_bus_en || panel->msm_dp_mode.out_fmt_is_yuv_420) pixel_rate >>= 1; drm_dbg_dp(ctrl->drm_dev, "pixel_rate=%lu\n", pixel_rate); - ret = msm_dp_ctrl_on_pixel_clk(ctrl, pixel_rate); + ret = msm_dp_ctrl_on_pixel_clk(ctrl, pixel_rate, panel->stream_id); if (ret) return ret; @@ -2600,14 +2648,11 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel * msm_dp_ctrl_lane_mapping(ctrl); msm_dp_setup_peripheral_flush(ctrl); - msm_dp_ctrl_config_ctrl_link(ctrl, panel); msm_dp_ctrl_configure_source_params(ctrl, panel); - msm_dp_ctrl_config_msa(ctrl, - ctrl->link->link_params.rate, - pixel_rate_orig, - panel->msm_dp_mode.out_fmt_is_yuv_420); + msm_dp_ctrl_config_msa(ctrl, panel, + ctrl->link->link_params.rate); msm_dp_panel_clear_dsc_dto(panel); @@ -2648,8 +2693,6 @@ void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_ctrl, ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); phy = ctrl->phy; - msm_dp_panel_disable_vsc_sdp(panel); - msm_dp_ctrl_mainlink_disable(ctrl); msm_dp_ctrl_reset(&ctrl->msm_dp_ctrl, panel); @@ -2719,6 +2762,13 @@ static const char *ctrl_clks[] = { "ctrl_link_iface", }; +static const char * const pixel_clks[] = { + "stream_pixel", + "stream_1_pixel", + "stream_2_pixel", + "stream_3_pixel", +}; + static int msm_dp_ctrl_clk_init(struct msm_dp_ctrl *msm_dp_ctrl) { struct msm_dp_ctrl_private *ctrl; @@ -2752,18 +2802,40 @@ static int msm_dp_ctrl_clk_init(struct msm_dp_ctrl *msm_dp_ctrl) if (rc) return rc; - ctrl->pixel_clk = devm_clk_get(dev, "stream_pixel"); - if (IS_ERR(ctrl->pixel_clk)) - return PTR_ERR(ctrl->pixel_clk); + ctrl->pixel_clk[0] = devm_clk_get(dev, pixel_clks[0]); + if (IS_ERR(ctrl->pixel_clk[0])) + return PTR_ERR(ctrl->pixel_clk[0]); + ctrl->num_pixel_clks = 1; + + for (i = DP_STREAM_1; i < DP_STREAM_MAX; i++) { + ctrl->pixel_clk[i] = devm_clk_get_optional(dev, pixel_clks[i]); + if (IS_ERR(ctrl->pixel_clk[i])) + return PTR_ERR(ctrl->pixel_clk[i]); + if (!ctrl->pixel_clk[i]) + break; + ctrl->num_pixel_clks++; + } return 0; } +bool msm_dp_ctrl_stream_clks_on(struct msm_dp_ctrl *msm_dp_ctrl, + enum msm_dp_stream_id stream_id) +{ + struct msm_dp_ctrl_private *ctrl; + + ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); + + return ctrl->stream_clks_on[stream_id]; +} + struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, struct msm_dp_link *link, struct drm_dp_aux *aux, struct phy *phy, void __iomem *ahb_base, - void __iomem *link_base) + void __iomem *link_base, + void __iomem *mst2link_base, + void __iomem *mst3link_base) { struct msm_dp_ctrl_private *ctrl; int ret; @@ -2802,6 +2874,8 @@ struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, struct msm_dp_link *link ctrl->phy = phy; ctrl->ahb_base = ahb_base; ctrl->link_base = link_base; + ctrl->mst2link_base = mst2link_base; + ctrl->mst3link_base = mst3link_base; ret = msm_dp_ctrl_clk_init(&ctrl->msm_dp_ctrl); if (ret) { diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_ctrl.h index 5902cf7e746a..80d9258501b4 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -24,7 +24,7 @@ int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool force_link_train); void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel *panel); -void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl); +void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl, enum msm_dp_stream_id stream_id); void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl); irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel *panel); @@ -35,7 +35,9 @@ struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, struct drm_dp_aux *aux, struct phy *phy, void __iomem *ahb_base, - void __iomem *link_base); + void __iomem *link_base, + void __iomem *mst2link_base, + void __iomem *mst3link_base); void msm_dp_ctrl_reset(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel *panel); @@ -55,4 +57,6 @@ void msm_dp_ctrl_enable_irq(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_disable_irq(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_reinit_phy(struct msm_dp_ctrl *msm_dp_ctrl); +bool msm_dp_ctrl_stream_clks_on(struct msm_dp_ctrl *dp_ctrl, + enum msm_dp_stream_id stream_id); #endif /* _DP_CTRL_H_ */ diff --git a/drivers/gpu/drm/msm/dp/dp_debug.c b/drivers/gpu/drm/msm/dp/dp_debug.c index cf3838fcd154..00fb1a7ba40e 100644 --- a/drivers/gpu/drm/msm/dp/dp_debug.c +++ b/drivers/gpu/drm/msm/dp/dp_debug.c @@ -216,6 +216,7 @@ int msm_dp_debug_init(struct device *dev, struct msm_dp_panel *panel, debug->link = link; debug->panel = panel; + debug->connector = connector; debugfs_create_file("dp_debug", 0444, root, debug, &msm_dp_debug_fops); diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index 6abe30bdff12..9299ce616fdb 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -86,8 +86,14 @@ struct msm_dp_display_private { void __iomem *link_base; size_t link_len; - void __iomem *p0_base; - size_t p0_len; + void __iomem *mst2link_base; + size_t mst2link_len; + + void __iomem *mst3link_base; + size_t mst3link_len; + + void __iomem *pixel_base[DP_STREAM_MAX]; + size_t pixel_len[DP_STREAM_MAX]; }; struct msm_dp_desc { @@ -451,6 +457,8 @@ static int msm_dp_hpd_unplug_handle(struct msm_dp_display_private *dp) { struct platform_device *pdev = dp->msm_dp_display.pdev; + guard(mutex)(&dp->plugged_lock); + dp->panel->video_test = false; msm_dp_aux_enable_xfers(dp->aux, false); @@ -459,7 +467,6 @@ static int msm_dp_hpd_unplug_handle(struct msm_dp_display_private *dp) dp->msm_dp_display.connector_type, dp->link->sink_count); - guard(mutex)(&dp->plugged_lock); if (!dp->plugged) return 0; @@ -501,6 +508,8 @@ static int msm_dp_irq_hpd_handle(struct msm_dp_display_private *dp) u32 sink_request; int rc = 0; + guard(mutex)(&dp->plugged_lock); + /* irq_hpd can happen at either connected or disconnected state */ drm_dbg_dp(dp->drm_dev, "Before, type=%d, sink_count=%d\n", dp->msm_dp_display.connector_type, @@ -563,7 +572,8 @@ static int msm_dp_init_sub_modules(struct msm_dp_display_private *dp) goto error_link; } - dp->panel = msm_dp_panel_get(dev, dp->aux, dp->link, dp->link_base, dp->p0_base); + dp->panel = msm_dp_panel_get(dev, dp->aux, dp->link, dp->link_base, + dp->mst2link_base, dp->mst3link_base, dp->pixel_base[0]); if (IS_ERR(dp->panel)) { rc = PTR_ERR(dp->panel); DRM_ERROR("failed to initialize panel, rc = %d\n", rc); @@ -572,7 +582,8 @@ static int msm_dp_init_sub_modules(struct msm_dp_display_private *dp) } dp->ctrl = msm_dp_ctrl_get(dev, dp->link, dp->aux, - phy, dp->ahb_base, dp->link_base); + phy, dp->ahb_base, dp->link_base, + dp->mst2link_base, dp->mst3link_base); if (IS_ERR(dp->ctrl)) { rc = PTR_ERR(dp->ctrl); DRM_ERROR("failed to initialize ctrl, rc = %d\n", rc); @@ -721,21 +732,7 @@ static int msm_dp_display_disable(struct msm_dp_display_private *dp, msm_dp_panel_disable_vsc_sdp(msm_dp_panel); - msm_dp_ctrl_off_pixel_clk(dp->ctrl); - - /* dongle is still connected but sinks are disconnected */ - if (dp->link->sink_count == 0) - msm_dp_link_psm_config(dp->link, &msm_dp_panel->link_info, true); - - msm_dp_ctrl_off_link(dp->ctrl, msm_dp_panel); - - if (dp->link->sink_count == 0) - /* re-init the PHY so that we can listen to Dongle disconnect */ - msm_dp_ctrl_reinit_phy(dp->ctrl); - else - msm_dp_display_host_phy_exit(dp); - - msm_dp_display->power_on = false; + msm_dp_ctrl_off_pixel_clk(dp->ctrl, msm_dp_panel->stream_id); drm_dbg_dp(dp->drm_dev, "sink count: %d\n", dp->link->sink_count); return 0; @@ -861,8 +858,19 @@ void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp) msm_dp_display->aux_base, "dp_aux"); msm_disp_snapshot_add_block(disp_state, msm_dp_display->link_len, msm_dp_display->link_base, "dp_link"); - msm_disp_snapshot_add_block(disp_state, msm_dp_display->p0_len, - msm_dp_display->p0_base, "dp_p0"); + if (msm_dp_display->mst2link_base) + msm_disp_snapshot_add_block(disp_state, msm_dp_display->mst2link_len, + msm_dp_display->mst2link_base, "dp_mst2link"); + if (msm_dp_display->mst3link_base) + msm_disp_snapshot_add_block(disp_state, msm_dp_display->mst3link_len, + msm_dp_display->mst3link_base, "dp_mst3link"); + + for (int i = 0; i < DP_STREAM_MAX; i++) { + if (!msm_dp_ctrl_stream_clks_on(msm_dp_display->ctrl, i)) + continue; + msm_disp_snapshot_add_block(disp_state, msm_dp_display->pixel_len[i], + msm_dp_display->pixel_base[i], "dp_p%d", i); + } } void msm_dp_display_set_psr(struct msm_dp *msm_dp_display, bool enter) @@ -1130,6 +1138,26 @@ static void __iomem *msm_dp_ioremap(struct platform_device *pdev, int idx, size_ return base; } +static void __iomem *msm_dp_ioremap_optional(struct platform_device *pdev, + int idx, size_t *len) +{ + struct resource *res; + void __iomem *base; + + if (len) + *len = 0; + + res = platform_get_resource(pdev, IORESOURCE_MEM, idx); + if (!res) + return NULL; + + base = devm_ioremap_resource(&pdev->dev, res); + if (!IS_ERR(base)) + *len = resource_size(res); + + return base; +} + #define DP_DEFAULT_AHB_OFFSET 0x0000 #define DP_DEFAULT_AHB_SIZE 0x0200 #define DP_DEFAULT_AUX_OFFSET 0x0200 @@ -1142,6 +1170,7 @@ static void __iomem *msm_dp_ioremap(struct platform_device *pdev, int idx, size_ static int msm_dp_display_get_io(struct msm_dp_display_private *display) { struct platform_device *pdev = display->msm_dp_display.pdev; + int i; display->ahb_base = msm_dp_ioremap(pdev, 0, &display->ahb_len); if (IS_ERR(display->ahb_base)) @@ -1171,8 +1200,8 @@ static int msm_dp_display_get_io(struct msm_dp_display_private *display) display->aux_len = DP_DEFAULT_AUX_SIZE; display->link_base = display->ahb_base + DP_DEFAULT_LINK_OFFSET; display->link_len = DP_DEFAULT_LINK_SIZE; - display->p0_base = display->ahb_base + DP_DEFAULT_P0_OFFSET; - display->p0_len = DP_DEFAULT_P0_SIZE; + display->pixel_base[0] = display->ahb_base + DP_DEFAULT_P0_OFFSET; + display->pixel_len[DP_STREAM_0] = DP_DEFAULT_P0_SIZE; return 0; } @@ -1183,12 +1212,28 @@ static int msm_dp_display_get_io(struct msm_dp_display_private *display) return PTR_ERR(display->link_base); } - display->p0_base = msm_dp_ioremap(pdev, 3, &display->p0_len); - if (IS_ERR(display->p0_base)) { - DRM_ERROR("unable to remap p0 region: %pe\n", display->p0_base); - return PTR_ERR(display->p0_base); + display->pixel_base[0] = msm_dp_ioremap(pdev, 3, + &display->pixel_len[DP_STREAM_0]); + if (IS_ERR(display->pixel_base[0])) + return PTR_ERR(display->pixel_base[0]); + + for (i = DP_STREAM_1; i < DP_STREAM_MAX; i++) { + display->pixel_base[i] = msm_dp_ioremap_optional(pdev, i + 3, + &display->pixel_len[i]); + if (IS_ERR(display->pixel_base[i])) + return PTR_ERR(display->pixel_base[i]); + if (!display->pixel_base[i]) + break; } + display->mst2link_base = msm_dp_ioremap_optional(pdev, 7, &display->mst2link_len); + if (IS_ERR(display->mst2link_base)) + return PTR_ERR(display->mst2link_base); + + display->mst3link_base = msm_dp_ioremap_optional(pdev, 8, &display->mst3link_len); + if (IS_ERR(display->mst3link_base)) + return PTR_ERR(display->mst3link_base); + return 0; } @@ -1483,6 +1528,20 @@ static void msm_dp_display_unprepare(struct msm_dp_display_private *dp) { struct msm_dp *msm_dp_display = &dp->msm_dp_display; + /* dongle is still connected but sinks are disconnected */ + if (dp->link->sink_count == 0) + msm_dp_link_psm_config(dp->link, &dp->panel->link_info, true); + + msm_dp_ctrl_off_link(dp->ctrl, dp->panel); + + if (dp->link->sink_count == 0) + /* re-init the PHY so that we can listen to Dongle disconnect */ + msm_dp_ctrl_reinit_phy(dp->ctrl); + else + msm_dp_display_host_phy_exit(dp); + + msm_dp_display->power_on = false; + pm_runtime_put_sync(&msm_dp_display->pdev->dev); drm_dbg_dp(dp->drm_dev, "type=%d Done\n", msm_dp_display->connector_type); diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_panel.c index e76dad0f6663..d3468b73fdc3 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -25,13 +25,92 @@ struct msm_dp_panel_private { struct drm_dp_aux *aux; struct msm_dp_link *link; void __iomem *link_base; - void __iomem *p0_base; + void __iomem *mst2link_base; + void __iomem *mst3link_base; + void __iomem *pixel_base; bool panel_on; }; +u32 msm_dp_stream_reg(enum msm_dp_stream_id id, u32 reg) +{ + bool is_s1 = (id == DP_STREAM_1); + + if (id == DP_STREAM_0) + return reg; + + switch (reg) { + case REG_DP_STATE_CTRL: + return is_s1 ? REG_DP_STATE_CTRL : REG_DP_MSTLINK_STATE_CTRL; + case REG_DP_CONFIGURATION_CTRL: + return is_s1 ? REG_DP1_CONFIGURATION_CTRL : REG_DP_MSTLINK_CONFIGURATION_CTRL; + case REG_DP_SOFTWARE_MVID: + return is_s1 ? REG_DP1_SOFTWARE_MVID : REG_DP_MSTLINK_SOFTWARE_MVID; + case REG_DP_SOFTWARE_NVID: + return is_s1 ? REG_DP1_SOFTWARE_NVID : REG_DP_MSTLINK_SOFTWARE_NVID; + case REG_DP_TOTAL_HOR_VER: + return is_s1 ? REG_DP1_TOTAL_HOR_VER : REG_DP_MSTLINK_TOTAL_HOR_VER; + case REG_DP_START_HOR_VER_FROM_SYNC: + return is_s1 ? REG_DP1_START_HOR_VER_FROM_SYNC + : REG_DP_MSTLINK_START_HOR_VER_FROM_SYNC; + case REG_DP_HSYNC_VSYNC_WIDTH_POLARITY: + return is_s1 ? REG_DP1_HSYNC_VSYNC_WIDTH_POLARITY + : REG_DP_MSTLINK_HSYNC_VSYNC_WIDTH_POLARITY; + case REG_DP_ACTIVE_HOR_VER: + return is_s1 ? REG_DP1_ACTIVE_HOR_VER : REG_DP_MSTLINK_ACTIVE_HOR_VER; + case REG_DP_MISC1_MISC0: + return is_s1 ? REG_DP1_MISC1_MISC0 : REG_DP_MSTLINK_MISC1_MISC0; + case REG_DP_DP0_TIMESLOT_1_32: + return is_s1 ? REG_DP_DP1_TIMESLOT_1_32 : REG_DP_MSTLINK_TIMESLOT_1_32; + case REG_DP_DP0_TIMESLOT_33_63: + return is_s1 ? REG_DP_DP1_TIMESLOT_33_63 : REG_DP_MSTLINK_TIMESLOT_33_63; + case REG_DP_DP0_RG: + return is_s1 ? REG_DP_DP1_RG : REG_DP_MSTLINK_DP_RG; + case MMSS_DP_SDP_CFG: + return is_s1 ? MMSS_DP1_SDP_CFG : MMSS_DP_MSTLINK_SDP_CFG; + case MMSS_DP_SDP_CFG2: + return is_s1 ? MMSS_DP1_SDP_CFG2 : MMSS_DP_MSTLINK_SDP_CFG2; + case MMSS_DP_SDP_CFG3: + return is_s1 ? MMSS_DP1_SDP_CFG3 : MMSS_DP_MSTLINK_SDP_CFG3; + case MMSS_DP_GENERIC0_0: + return is_s1 ? MMSS_DP1_GENERIC0_0 : MMSS_DP_MSTLINK_GENERIC0_0; + case MMSS_DP_GENERIC0_1: + return is_s1 ? MMSS_DP1_GENERIC0_1 : MMSS_DP_MSTLINK_GENERIC0_1; + case MMSS_DP_GENERIC0_2: + return is_s1 ? MMSS_DP1_GENERIC0_2 : MMSS_DP_MSTLINK_GENERIC0_2; + case MMSS_DP_GENERIC0_3: + return is_s1 ? MMSS_DP1_GENERIC0_3 : MMSS_DP_MSTLINK_GENERIC0_3; + case MMSS_DP_GENERIC0_4: + return is_s1 ? MMSS_DP1_GENERIC0_4 : MMSS_DP_MSTLINK_GENERIC0_4; + case MMSS_DP_GENERIC0_5: + return is_s1 ? MMSS_DP1_GENERIC0_5 : MMSS_DP_MSTLINK_GENERIC0_5; + case MMSS_DP_GENERIC0_6: + return is_s1 ? MMSS_DP1_GENERIC0_6 : MMSS_DP_MSTLINK_GENERIC0_6; + case MMSS_DP_GENERIC0_7: + return is_s1 ? MMSS_DP1_GENERIC0_7 : MMSS_DP_MSTLINK_GENERIC0_7; + case MMSS_DP_GENERIC0_8: + return is_s1 ? MMSS_DP1_GENERIC0_8 : MMSS_DP_MSTLINK_GENERIC0_8; + case MMSS_DP_GENERIC0_9: + return is_s1 ? MMSS_DP1_GENERIC0_9 : MMSS_DP_MSTLINK_GENERIC0_9; + default: + return reg; + } +} + static inline u32 msm_dp_read_link(struct msm_dp_panel_private *panel, u32 offset) { - return readl_relaxed(panel->link_base + offset); + offset = msm_dp_stream_reg(panel->msm_dp_panel.stream_id, offset); + switch (panel->msm_dp_panel.stream_id) { + case DP_STREAM_0: + case DP_STREAM_1: + return readl_relaxed(panel->link_base + offset); + case DP_STREAM_2: + return readl_relaxed(panel->mst2link_base + offset); + case DP_STREAM_3: + return readl_relaxed(panel->mst3link_base + offset); + default: + DRM_ERROR("error stream_id\n"); + return 0; + } } static inline void msm_dp_write_link(struct msm_dp_panel_private *panel, @@ -41,27 +120,42 @@ static inline void msm_dp_write_link(struct msm_dp_panel_private *panel, * To make sure link reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - writel(data, panel->link_base + offset); + offset = msm_dp_stream_reg(panel->msm_dp_panel.stream_id, offset); + switch (panel->msm_dp_panel.stream_id) { + case DP_STREAM_0: + case DP_STREAM_1: + writel(data, panel->link_base + offset); + break; + case DP_STREAM_2: + writel(data, panel->mst2link_base + offset); + break; + case DP_STREAM_3: + writel(data, panel->mst3link_base + offset); + break; + default: + DRM_ERROR("error stream_id\n"); + break; + } } -static inline void msm_dp_write_p0(struct msm_dp_panel_private *panel, - u32 offset, u32 data) +static inline void msm_dp_write_pn(struct msm_dp_panel_private *panel, + u32 offset, u32 data) { /* - * To make sure interface reg writes happens before any other operation, - * this function uses writel() instread of writel_relaxed() + * Use writel() instead of writel_relaxed() to ensure the interface + * register write reaches the hardware before subsequent operations. */ - writel(data, panel->p0_base + offset); + writel(data, panel->pixel_base + offset); } -static inline u32 msm_dp_read_p0(struct msm_dp_panel_private *panel, - u32 offset) +static inline u32 msm_dp_read_pn(struct msm_dp_panel_private *panel, + u32 offset) { /* - * To make sure interface reg writes happens before any other operation, - * this function uses writel() instread of writel_relaxed() + * Only reads a configuration register: no DMA or memory ordering is + * required, so readl_relaxed() is sufficient. */ - return readl_relaxed(panel->p0_base + offset); + return readl_relaxed(panel->pixel_base + offset); } static void msm_dp_panel_read_psr_cap(struct msm_dp_panel_private *panel) @@ -367,34 +461,34 @@ static void msm_dp_panel_tpg_enable(struct msm_dp_panel *msm_dp_panel, display_hctl = (hsync_end_x << 16) | hsync_start_x; - msm_dp_write_p0(panel, MMSS_DP_INTF_HSYNC_CTL, hsync_ctl); - msm_dp_write_p0(panel, MMSS_DP_INTF_VSYNC_PERIOD_F0, vsync_period * + msm_dp_write_pn(panel, MMSS_DP_INTF_HSYNC_CTL, hsync_ctl); + msm_dp_write_pn(panel, MMSS_DP_INTF_VSYNC_PERIOD_F0, vsync_period * hsync_period); - msm_dp_write_p0(panel, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0, v_sync_width * + msm_dp_write_pn(panel, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0, v_sync_width * hsync_period); - msm_dp_write_p0(panel, MMSS_DP_INTF_VSYNC_PERIOD_F1, 0); - msm_dp_write_p0(panel, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1, 0); - msm_dp_write_p0(panel, MMSS_DP_INTF_DISPLAY_HCTL, display_hctl); - msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_HCTL, 0); - msm_dp_write_p0(panel, MMSS_INTF_DISPLAY_V_START_F0, display_v_start); - msm_dp_write_p0(panel, MMSS_DP_INTF_DISPLAY_V_END_F0, display_v_end); - msm_dp_write_p0(panel, MMSS_INTF_DISPLAY_V_START_F1, 0); - msm_dp_write_p0(panel, MMSS_DP_INTF_DISPLAY_V_END_F1, 0); - msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_V_START_F0, 0); - msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_V_END_F0, 0); - msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_V_START_F1, 0); - msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_V_END_F1, 0); - msm_dp_write_p0(panel, MMSS_DP_INTF_POLARITY_CTL, 0); - - msm_dp_write_p0(panel, MMSS_DP_TPG_MAIN_CONTROL, - DP_TPG_CHECKERED_RECT_PATTERN); - msm_dp_write_p0(panel, MMSS_DP_TPG_VIDEO_CONFIG, - DP_TPG_VIDEO_CONFIG_BPP_8BIT | - DP_TPG_VIDEO_CONFIG_RGB); - msm_dp_write_p0(panel, MMSS_DP_BIST_ENABLE, - DP_BIST_ENABLE_DPBIST_EN); - msm_dp_write_p0(panel, MMSS_DP_TIMING_ENGINE_EN, - DP_TIMING_ENGINE_EN_EN); + msm_dp_write_pn(panel, MMSS_DP_INTF_VSYNC_PERIOD_F1, 0); + msm_dp_write_pn(panel, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1, 0); + msm_dp_write_pn(panel, MMSS_DP_INTF_DISPLAY_HCTL, display_hctl); + msm_dp_write_pn(panel, MMSS_DP_INTF_ACTIVE_HCTL, 0); + msm_dp_write_pn(panel, MMSS_INTF_DISPLAY_V_START_F0, display_v_start); + msm_dp_write_pn(panel, MMSS_DP_INTF_DISPLAY_V_END_F0, display_v_end); + msm_dp_write_pn(panel, MMSS_INTF_DISPLAY_V_START_F1, 0); + msm_dp_write_pn(panel, MMSS_DP_INTF_DISPLAY_V_END_F1, 0); + msm_dp_write_pn(panel, MMSS_DP_INTF_ACTIVE_V_START_F0, 0); + msm_dp_write_pn(panel, MMSS_DP_INTF_ACTIVE_V_END_F0, 0); + msm_dp_write_pn(panel, MMSS_DP_INTF_ACTIVE_V_START_F1, 0); + msm_dp_write_pn(panel, MMSS_DP_INTF_ACTIVE_V_END_F1, 0); + msm_dp_write_pn(panel, MMSS_DP_INTF_POLARITY_CTL, 0); + + msm_dp_write_pn(panel, MMSS_DP_TPG_MAIN_CONTROL, + DP_TPG_CHECKERED_RECT_PATTERN); + msm_dp_write_pn(panel, MMSS_DP_TPG_VIDEO_CONFIG, + DP_TPG_VIDEO_CONFIG_BPP_8BIT | + DP_TPG_VIDEO_CONFIG_RGB); + msm_dp_write_pn(panel, MMSS_DP_BIST_ENABLE, + DP_BIST_ENABLE_DPBIST_EN); + msm_dp_write_pn(panel, MMSS_DP_TIMING_ENGINE_EN, + DP_TIMING_ENGINE_EN_EN); drm_dbg_dp(panel->drm_dev, "%s: enabled tpg\n", __func__); } @@ -403,9 +497,9 @@ static void msm_dp_panel_tpg_disable(struct msm_dp_panel *msm_dp_panel) struct msm_dp_panel_private *panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); - msm_dp_write_p0(panel, MMSS_DP_TPG_MAIN_CONTROL, 0x0); - msm_dp_write_p0(panel, MMSS_DP_BIST_ENABLE, 0x0); - msm_dp_write_p0(panel, MMSS_DP_TIMING_ENGINE_EN, 0x0); + msm_dp_write_pn(panel, MMSS_DP_TPG_MAIN_CONTROL, 0x0); + msm_dp_write_pn(panel, MMSS_DP_BIST_ENABLE, 0x0); + msm_dp_write_pn(panel, MMSS_DP_TIMING_ENGINE_EN, 0x0); } void msm_dp_panel_tpg_config(struct msm_dp_panel *msm_dp_panel, bool enable) @@ -439,7 +533,7 @@ void msm_dp_panel_clear_dsc_dto(struct msm_dp_panel *msm_dp_panel) struct msm_dp_panel_private *panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); - msm_dp_write_p0(panel, MMSS_DP_DSC_DTO, 0x0); + msm_dp_write_pn(panel, MMSS_DP_DSC_DTO, 0x0); } static void msm_dp_panel_send_vsc_sdp(struct msm_dp_panel_private *panel, struct dp_sdp *vsc_sdp) @@ -629,7 +723,7 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel, bool wide_bus_en) msm_dp_write_link(panel, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY, width_blanking); msm_dp_write_link(panel, REG_DP_ACTIVE_HOR_VER, msm_dp_active); - reg = msm_dp_read_p0(panel, MMSS_DP_INTF_CONFIG); + reg = msm_dp_read_pn(panel, MMSS_DP_INTF_CONFIG); if (wide_bus_en) reg |= DP_INTF_CONFIG_DATABUS_WIDEN; else @@ -637,7 +731,7 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel, bool wide_bus_en) drm_dbg_dp(panel->drm_dev, "wide_bus_en=%d reg=%#x\n", wide_bus_en, reg); - msm_dp_write_p0(panel, MMSS_DP_INTF_CONFIG, reg); + msm_dp_write_pn(panel, MMSS_DP_INTF_CONFIG, reg); if (msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420) msm_dp_panel_setup_vsc_sdp_yuv_420(msm_dp_panel); @@ -701,7 +795,9 @@ int msm_dp_panel_init_panel_info(struct msm_dp_panel *msm_dp_panel, struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_aux *aux, struct msm_dp_link *link, void __iomem *link_base, - void __iomem *p0_base) + void __iomem *mst2link_base, + void __iomem *mst3link_base, + void __iomem *pixel_base) { struct msm_dp_panel_private *panel; struct msm_dp_panel *msm_dp_panel; @@ -719,10 +815,13 @@ struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_aux *aux panel->aux = aux; panel->link = link; panel->link_base = link_base; - panel->p0_base = p0_base; + panel->pixel_base = pixel_base; + panel->mst2link_base = mst2link_base; + panel->mst3link_base = mst3link_base; msm_dp_panel = &panel->msm_dp_panel; msm_dp_panel->max_bw_code = DP_LINK_BW_8_1; + msm_dp_panel->stream_id = DP_STREAM_0; return msm_dp_panel; } diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_panel.h index 4519ac374220..dc046fec24fc 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -27,6 +27,15 @@ struct msm_dp_panel_psr { u8 capabilities; }; +/* stream id */ +enum msm_dp_stream_id { + DP_STREAM_0, + DP_STREAM_1, + DP_STREAM_2, + DP_STREAM_3, + DP_STREAM_MAX, +}; + struct msm_dp_panel { /* dpcd raw data */ u8 dpcd[DP_RECEIVER_CAP_SIZE]; @@ -40,6 +49,8 @@ struct msm_dp_panel { bool vsc_sdp_supported; u32 hw_revision; + enum msm_dp_stream_id stream_id; + u32 max_bw_code; }; @@ -88,8 +99,12 @@ static inline bool is_lane_count_valid(u32 lane_count) lane_count == 4); } +u32 msm_dp_stream_reg(enum msm_dp_stream_id id, u32 reg); + struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_aux *aux, struct msm_dp_link *link, void __iomem *link_base, - void __iomem *p0_base); + void __iomem *mst2link_base, + void __iomem *mst3link_base, + void __iomem *pixel_base); #endif /* _DP_PANEL_H_ */ diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_reg.h index dda4b642c81b..265da58e064c 100644 --- a/drivers/gpu/drm/msm/dp/dp_reg.h +++ b/drivers/gpu/drm/msm/dp/dp_reg.h @@ -302,6 +302,35 @@ #define MMSS_DP_VSCEXT_8 (0x000002F0) #define MMSS_DP_VSCEXT_9 (0x000002F4) +/* Stream 1 (DP1) registers, relative to link_base. */ +#define REG_DP1_CONFIGURATION_CTRL (0x00000400) +#define REG_DP_DP0_TIMESLOT_1_32 (0x00000404) +#define REG_DP_DP0_TIMESLOT_33_63 (0x00000408) +#define REG_DP_DP1_TIMESLOT_1_32 (0x0000040C) +#define REG_DP_DP1_TIMESLOT_33_63 (0x00000410) +#define REG_DP1_SOFTWARE_MVID (0x00000414) +#define REG_DP1_SOFTWARE_NVID (0x00000418) +#define REG_DP1_TOTAL_HOR_VER (0x0000041c) +#define REG_DP1_START_HOR_VER_FROM_SYNC (0x00000420) +#define REG_DP1_HSYNC_VSYNC_WIDTH_POLARITY (0x00000424) +#define REG_DP1_ACTIVE_HOR_VER (0x00000428) +#define REG_DP1_MISC1_MISC0 (0x0000042c) +#define MMSS_DP1_GENERIC0_0 (0x00000490) +#define MMSS_DP1_GENERIC0_1 (0x00000494) +#define MMSS_DP1_GENERIC0_2 (0x00000498) +#define MMSS_DP1_GENERIC0_3 (0x0000049c) +#define MMSS_DP1_GENERIC0_4 (0x000004a0) +#define MMSS_DP1_GENERIC0_5 (0x000004a4) +#define MMSS_DP1_GENERIC0_6 (0x000004a8) +#define MMSS_DP1_GENERIC0_7 (0x000004ac) +#define MMSS_DP1_GENERIC0_8 (0x000004b0) +#define MMSS_DP1_GENERIC0_9 (0x000004b4) +#define MMSS_DP1_SDP_CFG (0x000004e0) +#define MMSS_DP1_SDP_CFG2 (0x000004e4) +#define MMSS_DP1_SDP_CFG3 (0x000004e8) +#define REG_DP_DP0_RG (0x000004f8) +#define REG_DP_DP1_RG (0x000004fc) + #define MMSS_DP_BIST_ENABLE (0x00000000) #define DP_BIST_ENABLE_DPBIST_EN (0x00000001) @@ -334,6 +363,33 @@ #define DP_TPG_VIDEO_CONFIG_BPP_8BIT (0x00000001) #define DP_TPG_VIDEO_CONFIG_RGB (0x00000004) +/* Streams 2/3 registers, relative to mst2link_base / mst3link_base. */ +#define REG_DP_MSTLINK_STATE_CTRL (0x00000000) +#define REG_DP_MSTLINK_CONFIGURATION_CTRL (0x00000034) +#define REG_DP_MSTLINK_TIMESLOT_1_32 (0x00000038) +#define REG_DP_MSTLINK_TIMESLOT_33_63 (0x0000003c) +#define REG_DP_MSTLINK_SOFTWARE_MVID (0x00000040) +#define REG_DP_MSTLINK_SOFTWARE_NVID (0x00000044) +#define REG_DP_MSTLINK_TOTAL_HOR_VER (0x00000048) +#define REG_DP_MSTLINK_START_HOR_VER_FROM_SYNC (0x0000004c) +#define REG_DP_MSTLINK_HSYNC_VSYNC_WIDTH_POLARITY (0x00000050) +#define REG_DP_MSTLINK_ACTIVE_HOR_VER (0x00000054) +#define REG_DP_MSTLINK_MISC1_MISC0 (0x00000058) +#define MMSS_DP_MSTLINK_GENERIC0_0 (0x000000bc) +#define MMSS_DP_MSTLINK_GENERIC0_1 (0x000000c0) +#define MMSS_DP_MSTLINK_GENERIC0_2 (0x000000c4) +#define MMSS_DP_MSTLINK_GENERIC0_3 (0x000000c8) +#define MMSS_DP_MSTLINK_GENERIC0_4 (0x000000cc) +#define MMSS_DP_MSTLINK_GENERIC0_5 (0x000000d0) +#define MMSS_DP_MSTLINK_GENERIC0_6 (0x000000d4) +#define MMSS_DP_MSTLINK_GENERIC0_7 (0x000000d8) +#define MMSS_DP_MSTLINK_GENERIC0_8 (0x000000dc) +#define MMSS_DP_MSTLINK_GENERIC0_9 (0x000000e0) +#define MMSS_DP_MSTLINK_SDP_CFG (0x0000010c) +#define MMSS_DP_MSTLINK_SDP_CFG2 (0x00000110) +#define MMSS_DP_MSTLINK_SDP_CFG3 (0x00000114) +#define REG_DP_MSTLINK_DP_RG (0x0000011C) + #define MMSS_DP_ASYNC_FIFO_CONFIG (0x00000088) #define REG_DP_PHY_AUX_INTERRUPT_CLEAR (0x0000004C) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index b292dfd266d1..d92659d80f17 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -1254,6 +1254,8 @@ int dsi_tx_buf_alloc_6g(struct msm_dsi_host *msm_host, int size) if (IS_ERR(data)) { msm_host->tx_gem_obj = NULL; + drm_gpuvm_put(msm_host->vm); + msm_host->vm = NULL; return PTR_ERR(data); } diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c b/drivers/gpu/drm/msm/dsi/dsi_manager.c index 959daa88b1d0..531d4ff78f56 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_manager.c +++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c @@ -429,7 +429,7 @@ static enum drm_mode_status dsi_mgr_bridge_mode_valid(struct drm_bridge *bridge, if (dev_pm_opp_get_opp_count(&pdev->dev) != 0) return MODE_CLOCK_RANGE; } else { - return MODE_ERROR; + return MODE_ERROR; } return msm_dsi_host_check_dsc(host, mode); diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c index 157f19bd90b4..49587927e8a5 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c @@ -13,14 +13,16 @@ #include "msm_kms.h" #include "hdmi.h" -static void msm_hdmi_power_on(struct drm_bridge *bridge) +static int msm_hdmi_power_on(struct drm_bridge *bridge) { struct drm_device *dev = bridge->dev; struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); struct hdmi *hdmi = hdmi_bridge->hdmi; int ret; - pm_runtime_resume_and_get(&hdmi->pdev->dev); + ret = pm_runtime_resume_and_get(&hdmi->pdev->dev); + if (ret) + return ret; if (hdmi->extp_clk) { DBG("pixclock: %lu", hdmi->pixclock); @@ -29,9 +31,14 @@ static void msm_hdmi_power_on(struct drm_bridge *bridge) DRM_DEV_ERROR(dev->dev, "failed to set extp clk rate: %d\n", ret); ret = clk_prepare_enable(hdmi->extp_clk); - if (ret) + if (ret) { DRM_DEV_ERROR(dev->dev, "failed to enable extp clk: %d\n", ret); + pm_runtime_put(&hdmi->pdev->dev); + return ret; + } } + + return 0; } static void power_off(struct drm_bridge *bridge) @@ -287,13 +294,18 @@ static void msm_hdmi_bridge_atomic_pre_enable(struct drm_bridge *bridge, msm_hdmi_set_timings(hdmi, &crtc_state->adjusted_mode); - mutex_lock(&hdmi->state_mutex); - if (!hdmi->power_on) { - msm_hdmi_phy_resource_enable(phy); - msm_hdmi_power_on(bridge); - hdmi->power_on = true; + scoped_guard(mutex, &hdmi->state_mutex) { + if (!hdmi->power_on) { + if (msm_hdmi_phy_resource_enable(phy)) + return; + + if (msm_hdmi_power_on(bridge)) { + msm_hdmi_phy_resource_disable(phy); + return; + } + hdmi->power_on = true; + } } - mutex_unlock(&hdmi->state_mutex); if (connector->display_info.is_hdmi) msm_hdmi_audio_update(hdmi); @@ -327,10 +339,10 @@ static void msm_hdmi_bridge_atomic_post_disable(struct drm_bridge *bridge, msm_hdmi_phy_powerdown(phy); if (hdmi->power_on) { - power_off(bridge); hdmi->power_on = false; if (hdmi->connector->display_info.is_hdmi) msm_hdmi_audio_update(hdmi); + power_off(bridge); msm_hdmi_phy_resource_disable(phy); } mutex_unlock(&hdmi->state_mutex); @@ -472,7 +484,7 @@ msm_hdmi_hotplug_work(struct work_struct *work) /* initialize bridge */ int msm_hdmi_bridge_init(struct hdmi *hdmi) { - struct drm_bridge *bridge = NULL; + struct drm_bridge *bridge; struct hdmi_bridge *hdmi_bridge; int ret; diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_phy.c b/drivers/gpu/drm/msm/hdmi/hdmi_phy.c index 77dce35cd45e..ebb600d77cd8 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi_phy.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi_phy.c @@ -67,16 +67,28 @@ int msm_hdmi_phy_resource_enable(struct hdmi_phy *phy) ret = regulator_bulk_enable(cfg->num_regs, phy->regs); if (ret) { DRM_DEV_ERROR(dev, "failed to enable regulators: (%d)\n", ret); - return ret; + goto err_pm_put; } for (i = 0; i < cfg->num_clks; i++) { ret = clk_prepare_enable(phy->clks[i]); - if (ret) + if (ret) { DRM_DEV_ERROR(dev, "failed to enable clock: %s (%d)\n", cfg->clk_names[i], ret); + goto err_clk_unprepare; + } } + return 0; + +err_clk_unprepare: + for (; i > 0; i--) + clk_disable_unprepare(phy->clks[i - 1]); + regulator_bulk_disable(cfg->num_regs, phy->regs); + +err_pm_put: + pm_runtime_put_sync(dev); + return ret; } diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index f3d2eaa04f14..5e8f3ce26b32 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -54,16 +54,87 @@ static bool modeset = true; MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)"); module_param(modeset, bool, 0600); -static bool separate_gpu_kms; -MODULE_PARM_DESC(separate_gpu_kms, "Use separate DRM device for the GPU (0=single DRM device for both GPU and display (default), 1=two DRM devices)"); -module_param(separate_gpu_kms, bool, 0400); +/* + * separate_gpu_kms (tristate): + * -1 (default): decide automatically based on hardware topology. Split devices + * if there is more than one GPU or more than one display master. + * 0: force single DRM device (bind display + GPU) + * 1: force separate DRM devices + */ +static int separate_gpu_kms = -1; +MODULE_PARM_DESC(separate_gpu_kms, + "Use separate DRM device for the GPU (-1=auto (default), 0=single DRM device, 1=separate DRM devices)"); +module_param(separate_gpu_kms, int, 0400); + +#ifdef CONFIG_TRANSPARENT_HUGEPAGE +static bool transparent_hugepage = true; +module_param(transparent_hugepage, bool, 0400); +MODULE_PARM_DESC(transparent_hugepage, "Use a dedicated tmpfs mount point with Transparent Hugepage enabled (true = default)"); +#else +#define transparent_hugepage false +#endif DECLARE_FAULT_ATTR(fail_gem_alloc); DECLARE_FAULT_ATTR(fail_gem_iova); -bool msm_gpu_no_components(void) +static void msm_gem_thp_init(struct drm_device *dev) +{ + int err; + + if (!transparent_hugepage) + return; + + err = drm_gem_huge_mnt_create(dev, "within_size"); + if (drm_gem_get_huge_mnt(dev)) + drm_info(dev, "Using Transparent Hugepage\n"); + else if (err) + drm_warn(dev, "Can't use Transparent Hugepage (%d)\n", err); +} + +static const struct of_device_id msm_gpu_match[]; +static inline bool msm_gpu_node_present(struct device_node *np) +{ + return np && of_device_is_available(np) && adreno_has_gpu(np); +} + +static int msm_count_gpus(void) +{ + struct device_node *np; + int count = 0; + + for_each_matching_node(np, msm_gpu_match) { + if (msm_gpu_node_present(np)) + count++; + } + + return count; +} + +static bool msm_separate_gpu_kms_auto(void) +{ + int gpus = msm_count_gpus(); + int display_subsystems = msm_count_mdss() + msm_count_mdp4(); + + if (gpus <= 0 || display_subsystems <= 0) + return false; + + /* Single card if there is exactly one GPU and one display subsystem */ + return gpus > 1 || display_subsystems > 1; +} + +bool msm_separate_gpu_kms_components(void) { - return separate_gpu_kms; + if (msm_count_gpus() == 0) + return true; + + switch (separate_gpu_kms) { + case 0: + return false; + case 1: + return true; + default: + return msm_separate_gpu_kms_auto(); + } } static int msm_drm_uninit(struct device *dev, const struct component_ops *gpu_ops) @@ -161,6 +232,8 @@ static int msm_drm_init(struct device *dev, const struct drm_driver *drv, if (ret) goto err_msm_uninit; + msm_gem_thp_init(ddev); + if (priv->kms_init) { ret = msm_drm_kms_init(dev, drv); if (ret) @@ -1029,7 +1102,7 @@ static int add_gpu_components(struct device *dev, if (!np) return 0; - if (of_device_is_available(np) && adreno_has_gpu(np)) + if (msm_gpu_node_present(np)) drm_of_component_match_add(dev, matchptr, component_compare_of, np); of_node_put(np); @@ -1040,7 +1113,7 @@ static int add_gpu_components(struct device *dev, static int msm_drm_bind(struct device *dev) { return msm_drm_init(dev, - msm_gpu_no_components() ? + msm_separate_gpu_kms_components() ? &msm_kms_driver : &msm_driver, NULL); @@ -1079,7 +1152,7 @@ int msm_drv_probe(struct device *master_dev, return ret; } - if (!msm_gpu_no_components()) { + if (!msm_separate_gpu_kms_components()) { ret = add_gpu_components(master_dev, &match); if (ret) return ret; diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index eb4bbae8557b..2840e8a5052d 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -394,9 +394,11 @@ static inline bool msm_dp_wide_bus_available(const struct msm_dp *dp_display) #ifdef CONFIG_DRM_MSM_MDP4 void msm_mdp4_register(void); void msm_mdp4_unregister(void); +int msm_count_mdp4(void); #else static inline void msm_mdp4_register(void) {} static inline void msm_mdp4_unregister(void) {} +static inline int msm_count_mdp4(void) { return 0; } #endif #ifdef CONFIG_DRM_MSM_MDP5 @@ -418,9 +420,11 @@ static inline void msm_dpu_unregister(void) {} #ifdef CONFIG_DRM_MSM_MDSS void msm_mdss_register(void); void msm_mdss_unregister(void); +int msm_count_mdss(void); #else static inline void msm_mdss_register(void) {} static inline void msm_mdss_unregister(void) {} +static inline int msm_count_mdss(void) { return 0; } #endif #ifdef CONFIG_DEBUG_FS @@ -534,6 +538,6 @@ void msm_kms_shutdown(struct platform_device *pdev); bool msm_disp_drv_should_bind(struct device *dev, bool dpu_driver); -bool msm_gpu_no_components(void); +bool msm_separate_gpu_kms_components(void); #endif /* __MSM_DRV_H__ */ diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c index c4cff3d53d81..130ae27ee00b 100644 --- a/drivers/gpu/drm/msm/msm_gem.c +++ b/drivers/gpu/drm/msm/msm_gem.c @@ -23,6 +23,8 @@ #include "msm_gpu.h" #include "msm_kms.h" +MODULE_IMPORT_NS("DMA_BUF"); + static void update_device_mem(struct msm_drm_private *priv, ssize_t size) { uint64_t total_mem = atomic64_add_return(size, &priv->total_mem); @@ -147,7 +149,7 @@ static void update_lru_active(struct drm_gem_object *obj) struct msm_drm_private *priv = obj->dev->dev_private; struct msm_gem_object *msm_obj = to_msm_bo(obj); - GEM_WARN_ON(!msm_obj->pages); + GEM_WARN_ON(!is_resident(msm_obj)); if (msm_obj->pin_count) { drm_gem_lru_move_tail_locked(&priv->lru.pinned, obj); @@ -167,7 +169,7 @@ static void update_lru_locked(struct drm_gem_object *obj) msm_gem_assert_locked(&msm_obj->base); - if (!msm_obj->pages) { + if (!is_resident(msm_obj)) { GEM_WARN_ON(msm_obj->pin_count); drm_gem_lru_move_tail_locked(&priv->lru.unbacked, obj); @@ -191,6 +193,9 @@ static struct page **get_pages(struct drm_gem_object *obj) msm_gem_assert_locked(obj); + if (drm_WARN_ON_ONCE(obj->dev, drm_gem_is_imported(obj))) + return ERR_PTR(-EINVAL); + if (!msm_obj->pages) { struct drm_device *dev = obj->dev; struct page **p; @@ -263,7 +268,7 @@ static void put_pages(struct drm_gem_object *obj) } } -struct page **msm_gem_get_pages_locked(struct drm_gem_object *obj, unsigned madv) +static int check_madv_locked(struct drm_gem_object *obj, unsigned madv) { struct msm_gem_object *msm_obj = to_msm_bo(obj); @@ -272,10 +277,25 @@ struct page **msm_gem_get_pages_locked(struct drm_gem_object *obj, unsigned madv if (msm_obj->madv > madv) { DRM_DEV_DEBUG_DRIVER(obj->dev->dev, "Invalid madv state: %u vs %u\n", msm_obj->madv, madv); - return ERR_PTR(-EBUSY); + return -EBUSY; } - return get_pages(obj); + return 0; +} + +int msm_gem_make_resident_locked(struct drm_gem_object *obj, unsigned madv) +{ + int err = check_madv_locked(obj, madv); + if (err) + return err; + + if (is_resident(to_msm_bo(obj))) + return 0; + + struct page **pages = get_pages(obj); + if (IS_ERR(pages)) + return PTR_ERR(pages); + return 0; } /* @@ -300,17 +320,17 @@ static void pin_obj_locked(struct drm_gem_object *obj) mutex_unlock(&dev->gem_lru_mutex); } -struct page **msm_gem_pin_pages_locked(struct drm_gem_object *obj) +int msm_gem_pin_pages_locked(struct drm_gem_object *obj) { - struct page **p; + int ret; msm_gem_assert_locked(obj); - p = msm_gem_get_pages_locked(obj, MSM_MADV_WILLNEED); - if (!IS_ERR(p)) + ret = msm_gem_make_resident_locked(obj, MSM_MADV_WILLNEED); + if (!ret) pin_obj_locked(obj); - return p; + return ret; } void msm_gem_unpin_pages_locked(struct drm_gem_object *obj) @@ -338,6 +358,9 @@ static vm_fault_t msm_gem_fault(struct vm_fault *vmf) int err; vm_fault_t ret; + if (drm_WARN_ON_ONCE(obj->dev, drm_gem_is_imported(obj))) + return VM_FAULT_SIGBUS; + /* * vm_ops.open/drm_gem_mmap_obj and close get and put * a reference on obj. So, we dont need to hold one here. @@ -474,14 +497,14 @@ int msm_gem_prot(struct drm_gem_object *obj) int msm_gem_pin_vma_locked(struct drm_gem_object *obj, struct drm_gpuva *vma) { struct msm_gem_object *msm_obj = to_msm_bo(obj); - struct page **pages; int prot = msm_gem_prot(obj); + int ret; msm_gem_assert_locked(obj); - pages = msm_gem_get_pages_locked(obj, MSM_MADV_WILLNEED); - if (IS_ERR(pages)) - return PTR_ERR(pages); + ret = msm_gem_make_resident_locked(obj, MSM_MADV_WILLNEED); + if (ret) + return ret; return msm_gem_vma_map(vma, prot, msm_obj->sgt); } @@ -717,7 +740,11 @@ static void *get_vaddr(struct drm_gem_object *obj, unsigned madv) if (drm_gem_is_imported(obj)) return ERR_PTR(-ENODEV); - pages = msm_gem_get_pages_locked(obj, madv); + int err = check_madv_locked(obj, madv); + if (err) + return ERR_PTR(err); + + pages = get_pages(obj); if (IS_ERR(pages)) return ERR_CAST(pages); @@ -949,7 +976,7 @@ void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m, stats->active.size += obj->size; } - if (msm_obj->pages) { + if (is_resident(msm_obj)) { stats->resident.count++; stats->resident.size += obj->size; } @@ -1089,11 +1116,6 @@ static void msm_gem_free_object(struct drm_gem_object *obj) if (drm_gem_is_imported(obj)) { GEM_WARN_ON(msm_obj->vaddr); - /* Don't drop the pages for imported dmabuf, as they are not - * ours, just free the array we allocated: - */ - kvfree(msm_obj->pages); - /* In msm_gem_import() error path, sgt won't be set yet: */ if (msm_obj->sgt) drm_prime_gem_destroy(obj, msm_obj->sgt); @@ -1126,6 +1148,25 @@ static int msm_gem_object_mmap(struct drm_gem_object *obj, struct vm_area_struct { struct msm_gem_object *msm_obj = to_msm_bo(obj); + if (drm_gem_is_imported(obj)) { + int ret; + + /* Reset both vm_ops and vm_private_data, so we don't end up with + * vm_ops pointing to our implementation if the dma-buf backend + * doesn't set those fields. + */ + vma->vm_private_data = NULL; + vma->vm_ops = NULL; + + ret = dma_buf_mmap(obj->dma_buf, vma, 0); + + /* Drop the reference drm_gem_mmap_obj() acquired.*/ + if (!ret) + drm_gem_object_put(obj); + + return ret; + } + vm_flags_set(vma, VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP); vma->vm_page_prot = msm_gem_pgprot(msm_obj, vma_get_page_prot(vma)); @@ -1172,7 +1213,7 @@ static enum drm_gem_object_status msm_gem_status(struct drm_gem_object *obj) struct msm_gem_object *msm_obj = to_msm_bo(obj); enum drm_gem_object_status status = 0; - if (msm_obj->pages) + if (is_resident(msm_obj)) status |= DRM_GEM_OBJECT_RESIDENT; if (msm_obj->madv == MSM_MADV_DONTNEED) @@ -1304,14 +1345,10 @@ struct drm_gem_object *msm_gem_import(struct drm_device *dev, struct dma_buf_attachment *attach, struct sg_table *sgt) { - struct msm_gem_object *msm_obj; struct drm_gem_object *obj; struct dma_buf *dmabuf = attach->dmabuf; - size_t size, npages; int ret; - size = PAGE_ALIGN(dmabuf->size); - ret = msm_gem_new_impl(dev, MSM_BO_WC, &obj); if (ret) return ERR_PTR(ret); @@ -1322,28 +1359,14 @@ struct drm_gem_object *msm_gem_import(struct drm_device *dev, */ obj->import_attach = attach; obj->resv = dmabuf->resv; - drm_gem_private_object_init(dev, obj, size); - - npages = size / PAGE_SIZE; - - msm_obj = to_msm_bo(obj); - msm_obj->pages = kvmalloc_objs(struct page *, npages); - if (!msm_obj->pages) { - ret = -ENOMEM; - goto fail; - } - - ret = drm_prime_sg_to_page_array(sgt, msm_obj->pages, npages); - if (ret) { - goto fail; - } + drm_gem_private_object_init(dev, obj, PAGE_ALIGN(dmabuf->size)); ret = msm_gem_init_bookkeeping(obj); if (ret) goto fail; /* Now that we are past potential failure points, set sgt: */ - msm_obj->sgt = sgt; + to_msm_bo(obj)->sgt = sgt; return obj; diff --git a/drivers/gpu/drm/msm/msm_gem.h b/drivers/gpu/drm/msm/msm_gem.h index 7c6a8c01f910..d8ec696d89d7 100644 --- a/drivers/gpu/drm/msm/msm_gem.h +++ b/drivers/gpu/drm/msm/msm_gem.h @@ -282,8 +282,8 @@ int msm_gem_get_and_pin_iova(struct drm_gem_object *obj, struct drm_gpuvm *vm, uint64_t *iova); void msm_gem_unpin_iova(struct drm_gem_object *obj, struct drm_gpuvm *vm); void msm_gem_pin_obj_locked(struct drm_gem_object *obj); -struct page **msm_gem_get_pages_locked(struct drm_gem_object *obj, unsigned madv); -struct page **msm_gem_pin_pages_locked(struct drm_gem_object *obj); +int msm_gem_make_resident_locked(struct drm_gem_object *obj, unsigned madv); +int msm_gem_pin_pages_locked(struct drm_gem_object *obj); void msm_gem_unpin_pages_locked(struct drm_gem_object *obj); int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev, struct drm_mode_create_dumb *args); @@ -422,6 +422,12 @@ static inline bool is_unevictable(struct msm_gem_object *msm_obj) return is_unpurgeable(msm_obj) || msm_obj->vaddr; } +/* Are backing pages/sgt allocated? */ +static inline bool is_resident(struct msm_gem_object *msm_obj) +{ + return !!msm_obj->sgt; +} + void msm_gem_purge(struct drm_gem_object *obj); void msm_gem_evict(struct drm_gem_object *obj); void msm_gem_vunmap(struct drm_gem_object *obj); diff --git a/drivers/gpu/drm/msm/msm_gem_prime.c b/drivers/gpu/drm/msm/msm_gem_prime.c index beb7f22fd694..e1e74e9b7e6a 100644 --- a/drivers/gpu/drm/msm/msm_gem_prime.c +++ b/drivers/gpu/drm/msm/msm_gem_prime.c @@ -109,20 +109,13 @@ struct dma_buf *msm_gem_prime_export(struct drm_gem_object *obj, int flags) int msm_gem_prime_pin(struct drm_gem_object *obj) { - struct page **pages; - int ret = 0; - if (drm_gem_is_imported(obj)) return 0; if (to_msm_bo(obj)->flags & MSM_BO_NO_SHARE) return -EINVAL; - pages = msm_gem_pin_pages_locked(obj); - if (IS_ERR(pages)) - ret = PTR_ERR(pages); - - return ret; + return msm_gem_pin_pages_locked(obj); } void msm_gem_prime_unpin(struct drm_gem_object *obj) diff --git a/drivers/gpu/drm/msm/msm_gem_shrinker.c b/drivers/gpu/drm/msm/msm_gem_shrinker.c index 3514d5c84989..52a8f5faeb87 100644 --- a/drivers/gpu/drm/msm/msm_gem_shrinker.c +++ b/drivers/gpu/drm/msm/msm_gem_shrinker.c @@ -19,6 +19,10 @@ static bool enable_eviction = true; MODULE_PARM_DESC(enable_eviction, "Enable swappable GEM buffers"); module_param(enable_eviction, bool, 0600); +static bool eviction_can_block = true; +MODULE_PARM_DESC(eviction_can_block, "Enable blocking for GEM buffer to become idle for eviction"); +module_param(eviction_can_block, bool, 0600); + static bool can_swap(void) { return enable_eviction && get_nr_swap_pages() > 0; @@ -26,6 +30,8 @@ static bool can_swap(void) static bool can_block(struct shrink_control *sc) { + if (!eviction_can_block) + return false; return (sc->gfp_mask & __GFP_DIRECT_RECLAIM) || (current_is_kswapd() && (sc->gfp_mask & __GFP_KSWAPD_RECLAIM)); } @@ -51,6 +57,7 @@ with_vm_locks(void (*fn)(struct drm_gem_object *obj), * success paths */ struct drm_gpuvm_bo *vm_bo, *last_locked = NULL; + struct drm_gpuvm_bo *next; bool locked = true; drm_gem_for_each_gpuvm_bo (vm_bo, obj) { @@ -82,7 +89,7 @@ with_vm_locks(void (*fn)(struct drm_gem_object *obj), out_unlock: if (last_locked) { - drm_gem_for_each_gpuvm_bo (vm_bo, obj) { + drm_gem_for_each_gpuvm_bo_safe(vm_bo, next, obj) { struct dma_resv *resv = drm_gpuvm_resv(vm_bo->vm); if (resv == obj->resv) diff --git a/drivers/gpu/drm/msm/msm_gem_vma.c b/drivers/gpu/drm/msm/msm_gem_vma.c index 1badec3caa7b..f687a629629d 100644 --- a/drivers/gpu/drm/msm/msm_gem_vma.c +++ b/drivers/gpu/drm/msm/msm_gem_vma.c @@ -1300,11 +1300,11 @@ vm_bind_job_pin_objects(struct msm_vm_bind_job *job) * trigger get_pages()) */ job_foreach_bo (obj, job) { - struct page **pages; + int ret; - pages = msm_gem_get_pages_locked(obj, MSM_MADV_WILLNEED); - if (IS_ERR(pages)) - return PTR_ERR(pages); + ret = msm_gem_make_resident_locked(obj, MSM_MADV_WILLNEED); + if (ret) + return ret; } struct drm_device *dev = job->vm->drm; diff --git a/drivers/gpu/drm/msm/msm_io_utils.c b/drivers/gpu/drm/msm/msm_io_utils.c index a6efe1eac271..99221b0d7e3f 100644 --- a/drivers/gpu/drm/msm/msm_io_utils.c +++ b/drivers/gpu/drm/msm/msm_io_utils.c @@ -77,7 +77,8 @@ static void __iomem *_msm_ioremap(struct platform_device *pdev, const char *name if (!res) { if (!quiet) - DRM_DEV_ERROR(&pdev->dev, "failed to get memory resource: %s\n", name); + DRM_DEV_ERROR(&pdev->dev, "failed to get memory resource: %s\n", + (name ?: "#0")); return ERR_PTR(-EINVAL); } @@ -86,7 +87,8 @@ static void __iomem *_msm_ioremap(struct platform_device *pdev, const char *name ptr = devm_ioremap(&pdev->dev, res->start, size); if (!ptr) { if (!quiet) - DRM_DEV_ERROR(&pdev->dev, "failed to ioremap: %s\n", name); + DRM_DEV_ERROR(&pdev->dev, "failed to ioremap: %s\n", + (name ?: "#0")); return ERR_PTR(-ENOMEM); } diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index 9087c4b290db..e69b122f2687 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -73,6 +73,21 @@ static int msm_mdss_parse_data_bus_icc_path(struct device *dev, return 0; } +static const struct of_device_id mdss_dt_match[]; + +int msm_count_mdss(void) +{ + struct device_node *np; + int count = 0; + + for_each_matching_node(np, mdss_dt_match) { + if (of_device_is_available(np)) + count++; + } + + return count; +} + static void msm_mdss_irq(struct irq_desc *desc) { struct msm_mdss *msm_mdss = irq_desc_get_handler_data(desc); diff --git a/drivers/gpu/drm/msm/registers/adreno/a2xx.xml b/drivers/gpu/drm/msm/registers/adreno/a2xx.xml index 22caddaa0db9..66a9ad75131c 100644 --- a/drivers/gpu/drm/msm/registers/adreno/a2xx.xml +++ b/drivers/gpu/drm/msm/registers/adreno/a2xx.xml @@ -1228,10 +1228,15 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> <reg32 offset="0x0c86" name="PA_SU_FACE_DATA"> <bitfield name="BASE_ADDR" low="5" high="31" type="uint"/> </reg32> + <reg32 offset="0x0d03" name="SQ_RESOURCE_MANAGMENT"> + <bitfield name="VTX_THREAD_BUF_ENTRIES" low="0" high="7" type="uint"/> + <bitfield name="PIX_THREAD_BUF_ENTRIES" low="8" high="15" type="uint"/> + <bitfield name="EXPORT_BUF_ENTRIES" low="16" high="24" type="uint"/> + </reg32> <reg32 offset="0x0d00" name="SQ_GPR_MANAGEMENT"> <bitfield name="REG_DYNAMIC" pos="0" type="boolean"/> - <bitfield name="REG_SIZE_PIX" low="4" high="11" type="uint"/> - <bitfield name="REG_SIZE_VTX" low="12" high="19" type="uint"/> + <bitfield name="REG_SIZE_PIX" low="4" high="10" type="uint"/> + <bitfield name="REG_SIZE_VTX" low="12" high="18" type="uint"/> </reg32> <reg32 offset="0x0d01" name="SQ_FLOW_CONTROL"/> <reg32 offset="0x0d02" name="SQ_INST_STORE_MANAGMENT"> @@ -1527,12 +1532,12 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> </reg32> <reg32 offset="0x2293" name="PA_SC_VIZ_QUERY"> <bitfield name="VIZ_QUERY_ENA" pos="0" type="boolean"/> - <bitfield name="VIZ_QUERY_ID" low="1" high="6" type="uint"/> - <bitfield name="KILL_PIX_POST_EARLY_Z" pos="8" type="boolean"/> + <bitfield name="VIZ_QUERY_ID" low="1" high="5" type="uint"/> + <bitfield name="KILL_PIX_POST_EARLY_Z" pos="7" type="boolean"/> </reg32> <reg32 offset="0x2294" name="VGT_ENHANCE"/> <reg32 offset="0x2300" name="PA_SC_LINE_CNTL"> - <bitfield name="BRES_CNTL" low="0" high="15" type="uint"/> + <bitfield name="BRES_CNTL" low="0" high="7" type="uint"/> <bitfield name="USE_BRES_CNTL" pos="8" type="boolean"/> <bitfield name="EXPAND_LINE_WIDTH" pos="9" type="boolean"/> <bitfield name="LAST_PIXEL" pos="10" type="boolean"/> @@ -1544,7 +1549,7 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> <reg32 offset="0x2302" name="PA_SU_VTX_CNTL"> <bitfield name="PIX_CENTER" pos="0" type="a2xx_pa_pixcenter"/> <bitfield name="ROUND_MODE" low="1" high="2" type="a2xx_pa_roundmode"/> - <bitfield name="QUANT_MODE" low="7" high="9" type="a2xx_pa_quantmode"/> + <bitfield name="QUANT_MODE" low="3" high="5" type="a2xx_pa_quantmode"/> </reg32> <reg32 offset="0x2303" name="PA_CL_GB_VERT_CLIP_ADJ" type="float"/> <reg32 offset="0x2304" name="PA_CL_GB_VERT_DISC_ADJ" type="float"/> @@ -1796,10 +1801,10 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> <value name="SQ_TEX_NUM_FORMAT_INT" value="1"/> </enum> <enum name="sq_tex_type"> - <value name="SQ_TEX_TYPE_0" value="0"/> - <value name="SQ_TEX_TYPE_1" value="1"/> - <value name="SQ_TEX_TYPE_2" value="2"/> - <value name="SQ_TEX_TYPE_3" value="3"/> + <value name="SQ_TEX_TYPE_INVALID_TEXTURE" value="0"/> + <value name="SQ_TEX_TYPE_INVALID_BUFFER" value="1"/> + <value name="SQ_TEX_TYPE_VALID_TEXTURE" value="2"/> + <value name="SQ_TEX_TYPE_VALID_BUFFER" value="3"/> </enum> <reg32 offset="0" name="0"> <bitfield name="TYPE" low="0" high="1" type="sq_tex_type"/> diff --git a/drivers/gpu/drm/msm/registers/adreno/a5xx.xml b/drivers/gpu/drm/msm/registers/adreno/a5xx.xml index 4af76b3750f7..e928ad4e518c 100644 --- a/drivers/gpu/drm/msm/registers/adreno/a5xx.xml +++ b/drivers/gpu/drm/msm/registers/adreno/a5xx.xml @@ -1804,6 +1804,9 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> <reg32 offset="0xe000" name="GRAS_CL_CNTL"> + <bitfield name="ZNEAR_CLIP_DISABLE" pos="1" type="boolean"/> + <bitfield name="ZFAR_CLIP_DISABLE" pos="2" type="boolean"/> + <bitfield name="Z_CLAMP_ENABLE" pos="5" type="boolean"/> <bitfield name="ZERO_GB_SCALE_Z" pos="6" type="boolean"/> </reg32> <bitset name="a5xx_gras_xs_cl_cntl" inline="yes"> @@ -1832,6 +1835,13 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> <reg32 offset="0xe013" name="GRAS_CL_VPORT_YSCALE_0" type="float"/> <reg32 offset="0xe014" name="GRAS_CL_VPORT_ZOFFSET_0" type="float"/> <reg32 offset="0xe015" name="GRAS_CL_VPORT_ZSCALE_0" type="float"/> + <doc> + The range GRAS_CL_CNTL.Z_CLAMP_ENABLE clamps to. Near and far, not + sorted as the a6xx equivalents are: a reversed depth range is written + reversed. + </doc> + <reg32 offset="0xe070" name="GRAS_CL_VIEWPORT_ZCLAMP_NEAR_0" type="float"/> + <reg32 offset="0xe071" name="GRAS_CL_VIEWPORT_ZCLAMP_FAR_0" type="float"/> <reg32 offset="0xe090" name="GRAS_SU_CNTL"> <bitfield name="CULL_FRONT" pos="0" type="boolean"/> <bitfield name="CULL_BACK" pos="1" type="boolean"/> @@ -1976,6 +1986,7 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32? not set <reg32 offset="0xe146" name="RB_FS_OUTPUT_CNTL"> <!-- bit0 set except for binning pass.. --> <bitfield name="MRT" low="0" high="3" type="uint"/> + <bitfield name="DUAL_COLOR_IN_ENABLE" pos="4" type="boolean"/> <bitfield name="FRAG_WRITES_Z" pos="5" type="boolean"/> </reg32> <reg32 offset="0xe147" name="RB_RENDER_COMPONENTS"> @@ -2058,6 +2069,7 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32? not set <!-- per-mrt enable bit --> <bitfield name="ENABLE_BLEND" low="0" high="7"/> <bitfield name="INDEPENDENT_BLEND" pos="8" type="boolean"/> + <bitfield name="DUAL_COLOR_IN_ENABLE" pos="9" type="boolean"/> <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/> <!-- a guess? --> <bitfield name="SAMPLE_MASK" low="16" high="31"/> @@ -2070,6 +2082,7 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32? not set <bitfield name="Z_TEST_ENABLE" pos="0" type="boolean"/> <bitfield name="Z_WRITE_ENABLE" pos="1" type="boolean"/> <bitfield name="ZFUNC" low="2" high="4" type="adreno_compare_func"/> + <bitfield name="Z_CLAMP_ENABLE" pos="5" type="boolean"/> <doc>Z_READ_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER</doc> <bitfield name="Z_READ_ENABLE" pos="6" type="boolean"/> </reg32> @@ -2114,6 +2127,8 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32? not set <reg32 offset="0xe1d1" name="RB_SAMPLE_COUNT_CONTROL"> <bitfield name="COPY" pos="1" type="boolean"/> </reg32> + <reg32 offset="0xe200" name="RB_VIEWPORT_ZCLAMP_NEAR" type="float"/> + <reg32 offset="0xe201" name="RB_VIEWPORT_ZCLAMP_FAR" type="float"/> <doc> Blits: @@ -2523,10 +2538,12 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32? not set <!-- per-mrt enable bit --> <bitfield name="ENABLE_BLEND" low="0" high="7"/> <bitfield name="UNK8" pos="8" type="boolean"/> + <bitfield name="DUAL_COLOR_IN_ENABLE" pos="9" type="boolean"/> <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/> </reg32> <reg32 offset="0xe5ca" name="SP_FS_OUTPUT_CNTL"> <bitfield name="MRT" low="0" high="3" type="uint"/> + <bitfield name="DUAL_COLOR_IN_ENABLE" pos="4" type="boolean"/> <bitfield name="DEPTH_REGID" low="5" high="12" type="a3xx_regid"/> <bitfield name="SAMPLEMASK_REGID" low="13" high="20" type="a3xx_regid"/> </reg32> diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml index 69dd0446f8d2..cf2fb20203b7 100644 --- a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml +++ b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml @@ -269,6 +269,7 @@ by a particular renderpass/blit. <reg32 offset="0x08b2" name="CP_CHICKEN_DBG_PIPE" variants="A8XX-"/> <reg32 offset="0x0842" name="CP_ADDR_MODE_CNTL" type="a5xx_address_mode" variants="A6XX"/> <reg32 offset="0x0843" name="CP_DBG_ECO_CNTL" variants="A6XX-A7XX"/> + <reg32 offset="0x084a" name="CP_MULTIDRAW_CNTL" variants="A8XX-"/> <reg32 offset="0x084b" name="CP_DBG_ECO_CNTL" variants="A8XX-"/> <bitset name="a6xx_cp_protect_cntl" inline="yes"> @@ -1326,6 +1327,7 @@ by a particular renderpass/blit. <reg32 offset="0x0c00" name="VSC_DBG_ECO_CNTL"/> <reg32 offset="0x0df0" name="VSC_KMD_DBG_ECO_CNTL" variants="A8XX-"/> + <reg32 offset="0x0df8" name="VSC_VISIBILITY_FLUSH_CNTL" variants="A8XX-"/> <reg32 offset="0x0c02" name="VSC_BIN_SIZE" usage="cmd" variants="A6XX-A7XX"> <bitfield name="BINW" low="0" high="7" shr="5" type="uint"/> <bitfield name="BINH" low="8" high="16" shr="4" type="uint"/> @@ -1386,7 +1388,7 @@ by a particular renderpass/blit. <reg32 offset="0x0" name="REG"/> </array> - <array offset="0x0c58" name="VSC_PIPE_DATA_PRIM_SIZE" stride="1" length="32" variants="A6XX" usage="cmd"> + <array offset="0x0c58" name="VSC_PIPE_DATA_PRIM_SIZE" stride="1" length="32" usage="cmd"> <doc> Has the size of data written to corresponding VSC_PRIM_STRM buffer. @@ -1394,7 +1396,7 @@ by a particular renderpass/blit. <reg32 offset="0x0" name="REG"/> </array> - <array offset="0x0c78" name="VSC_PIPE_DATA_DRAW_SIZE" stride="1" length="32" variants="A6XX" usage="cmd"> + <array offset="0x0c78" name="VSC_PIPE_DATA_DRAW_SIZE" stride="1" length="32" usage="cmd"> <doc> Has the size of data written to corresponding VSC pipe, ie. same thing that is written out to VSC_SIZE_BASE @@ -1459,8 +1461,10 @@ by a particular renderpass/blit. <bitfield name="IJ_LINEAR_CENTROID" pos="4" type="boolean"/> <bitfield name="IJ_LINEAR_SAMPLE" pos="5" type="boolean"/> <bitfield name="COORD_MASK" low="6" high="9" type="hex"/> - <bitfield name="UNK10" pos="10" type="boolean" variants="A7XX-"/> - <bitfield name="UNK11" pos="11" type="boolean" variants="A7XX-"/> + <!-- A740+ field, Must match RB_PS_INPUT_CNTL --> + <bitfield name="FACENESS" pos="10" type="boolean" variants="A7XX-"/> + <!-- A740+ field, Must match RB_PS_INPUT_CNTL --> + <bitfield name="CENTERRHW" pos="11" type="boolean" variants="A7XX-"/> </bitset> <reg32 offset="0x8005" name="GRAS_CL_INTERP_CNTL" type="a6xx_gras_cl_interp_cntl" variants="A6XX-A7XX" usage="draw"/> @@ -2168,12 +2172,12 @@ by a particular renderpass/blit. <bitfield name="SCISSOR" pos="16" type="boolean"/> <bitfield name="UNK17" low="17" high="18"/> <!-- required when blitting D24S8/D24X8 --> - <bitfield name="D24S8" pos="19" type="boolean"/> + <bitfield name="IS_SRC_YUV" pos="19" type="boolean"/> <!-- some sort of channel mask, disabled channels are set to zero ? --> <bitfield name="MASK" low="20" high="23"/> <bitfield name="IFMT" low="24" high="26" type="a6xx_2d_ifmt"/> - <bitfield name="UNK27" pos="27" type="boolean"/> - <bitfield name="UNK28" pos="28" type="boolean"/> + <bitfield name="FULL_RANGE_YUV" pos="27" type="boolean"/> + <bitfield name="LINEAR_YUV" pos="28" type="boolean"/> <bitfield name="RASTER_MODE" pos="29" type="a6xx_raster_mode"/> <bitfield name="COPY" pos="30" type="boolean" variants="A7XX-"/> </bitset> @@ -2559,10 +2563,8 @@ by a particular renderpass/blit. <reg32 offset="0" name="REG" type="float"/> </array> - <!-- 0x88c2-0x88cf invalid--> <reg32 offset="0x88d0" name="RB_RESOLVE_CNTL_0" usage="resolve"> - <bitfield name="UNK0" low="0" high="12"/> - <bitfield name="UNK16" low="16" high="26"/> + <bitfield name="YUV_PLANE_ID" low="0" high="1"/> </reg32> <reg32 offset="0x88d1" name="RB_RESOLVE_CNTL_1" type="a6xx_reg_xy" usage="resolve"/> <reg32 offset="0x88d2" name="RB_RESOLVE_CNTL_2" type="a6xx_reg_xy" usage="resolve"/> @@ -2759,7 +2761,22 @@ by a particular renderpass/blit. <reg32 offset="0x8a30" name="RB_UNKNOWN_8A30" variants="A6XX" usage="draw"/> <reg32 offset="0x8c00" name="RB_A2D_BLT_CNTL" type="a6xx_a2d_blt_cntl" usage="blit"/> - <reg32 offset="0x8c01" name="RB_A2D_PIXEL_CNTL" low="0" high="31" usage="blit"/> + + <enum name="a6xx_a2d_pixel_op"> + <value value="0" name="PIXEL_OP_DISABLED"/> + <value value="1" name="PIXEL_OP_BLENDING"/> + <value value="3" name="PIXEL_OP_ROP"/> + </enum> + + <reg32 offset="0x8c01" name="RB_A2D_PIXEL_CNTL" low="0" high="31" usage="blit"> + <bitfield name="PIXEL_OP" low="0" high="1" type="a6xx_a2d_pixel_op"/> + <bitfield name="COLOR_SRC_FACTOR" low="6" high="10" type="adreno_rb_blend_factor"/> + <bitfield name="COLOR_BLEND_OP" low="11" high="13" type="a3xx_rb_blend_opcode"/> + <bitfield name="COLOR_DST_FACTOR" low="14" high="18" type="adreno_rb_blend_factor"/> + <bitfield name="ALPHA_SRC_FACTOR" low="19" high="23" type="adreno_rb_blend_factor"/> + <bitfield name="ALPHA_BLEND_OP" low="24" high="26" type="a3xx_rb_blend_opcode"/> + <bitfield name="ALPHA_DST_FACTOR" low="27" high="31" type="adreno_rb_blend_factor"/> + </reg32> <bitset name="a6xx_a2d_src_texture_info" inline="yes"> <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/> @@ -2812,7 +2829,7 @@ by a particular renderpass/blit. <reg32 offset="0x8c2e" name="RB_A2D_CLEAR_COLOR_DW2" usage="blit"/> <reg32 offset="0x8c2f" name="RB_A2D_CLEAR_COLOR_DW3" usage="blit"/> - <reg32 offset="0x8c34" name="RB_A2D_UNKNOWN_8C34" variants="A7XX-" usage="blit"/> + <reg32 offset="0x8c34" name="RB_A2D_DEST_BUFFER_ARRAY_PITCH" variants="A7XX-" usage="blit"/> <!-- 0x8c35-0x8dff invalid --> @@ -2957,17 +2974,10 @@ by a particular renderpass/blit. <bitfield name="DISCARD" pos="2" type="boolean"/> </bitset> - <reg32 offset="0x9980" name="VPC_RAST_STREAM_CNTL" type="a6xx_vpc_rast_stream_cntl" variants="A6XX" usage="draw"/> - <reg32 offset="0x9107" name="VPC_RAST_STREAM_CNTL" type="a6xx_vpc_rast_stream_cntl" variants="A7XX" usage="draw"/> + <reg32 offset="0x9107" name="VPC_RAST_STREAM_CNTL" type="a6xx_vpc_rast_stream_cntl" variants="A6XX-A7XX" usage="draw"/> <reg32 offset="0x930d" name="VPC_RAST_STREAM_CNTL" type="a6xx_vpc_rast_stream_cntl" variants="A8XX-" usage="draw"/> <reg32 offset="0x9317" name="VPC_RAST_STREAM_CNTL_V2" type="a6xx_vpc_rast_stream_cntl" variants="A7XX" usage="draw"/> - <reg32 offset="0x9107" name="VPC_UNKNOWN_9107" variants="A6XX" usage="draw"> - <!-- this mirrors VPC_RAST_STREAM_CNTL::DISCARD, although it seems it's unused --> - <bitfield name="RASTER_DISCARD" pos="0" type="boolean"/> - <bitfield name="UNK2" pos="2" type="boolean"/> - </reg32> - <reg32 offset="0x9108" name="VPC_RAST_CNTL" type="a6xx_rast_cntl" variants="A6XX-A7XX" usage="draw"/> <reg32 offset="0x930e" name="VPC_RAST_CNTL" type="a6xx_rast_cntl" variants="A8XX-" usage="draw"/> <bitset name="a6xx_pc_cntl" inline="yes"> @@ -3286,7 +3296,29 @@ by a particular renderpass/blit. <reg32 offset="0x9803" name="PC_RESTART_INDEX" low="0" high="31" type="uint" variants="A6XX-A7XX" usage="draw"/> <reg32 offset="0x9b15" name="PC_RESTART_INDEX" low="0" high="31" type="uint" variants="A8XX-" usage="draw"/> - <reg32 offset="0x9804" name="PC_MODE_CNTL" low="0" high="7" variants="A6XX-A7XX" usage="draw"/> + <reg32 offset="0x9804" name="PC_MODE_CNTL" low="0" high="7" variants="A6XX-A7XX" usage="draw"> + <!-- + The higher this is set, the faster primitive processing performance + ends up being. It is likely the amount of entries to process/fetch. + --> + <bitfield name="COUNT1" low="0" high="4" type="uint"/> + <!-- + Setting this slows down primitive processing substantially, but it + was noted to fix some vertex corruption issues in the past. Likely + serves as a workaround to serialize the primitive pipeline? + --> + <bitfield name="UNK5" pos="5" type="boolean"/> + <!-- Never set by the blob, removed in A7XX. Unclear impact. --> + <bitfield name="UNK6" pos="6" type="boolean" variants="A6XX"/> + <!-- Never set by the blob. Unclear impact. --> + <bitfield name="UNK7" pos="7" type="boolean"/> + <!-- + Same as COUNT1 but one bit larger, this replaces COUNT1 mid-A7XX but + the proprietary driver tends to set it to the same or larger value + (by using the extra bit) as COUNT1. + --> + <bitfield name="COUNT2" low="8" high="13" type="uint" variants="A7XX-"/> + </reg32> <reg32 offset="0x9b00" name="PC_MODE_CNTL" low="0" high="14" variants="A8XX" usage="draw"/> <reg32 offset="0x9805" name="PC_POWER_CNTL" low="0" high="2" variants="A6XX" usage="draw"/> @@ -3365,6 +3397,8 @@ by a particular renderpass/blit. <reg32 offset="0x9886" name="PC_TF_BUFFER_SIZE" variants="A7XX" usage="cmd"/> <reg32 offset="0x9815" name="PC_TF_BUFFER_SIZE" variants="A8XX-" usage="cmd"/> + <reg32 offset="0x9980" name="PC_RAST_STREAM_CNTL" type="a6xx_vpc_rast_stream_cntl" variants="A6XX" usage="draw"/> + <!-- 0x9982-0x9aff invalid --> <reg32 offset="0x9b00" name="PC_CNTL" type="a6xx_pc_cntl" variants="A6XX-A7XX" usage="draw"/> @@ -3464,7 +3498,7 @@ by a particular renderpass/blit. <reg64 offset="0x9e12" name="PC_PVIS_STREAM_BIN_BASE" type="waddress" align="32" variants="A6XX-A7XX"/> <reg64 offset="0x9e14" name="PC_DVIS_STREAM_BIN_BASE" type="waddress" align="32" variants="A6XX-A7XX"/> - <reg32 offset="0x9e0a" name="PC_AUTO_VERTEX_STRIDE"/> + <reg32 offset="0x9e0a" name="PC_AUTO_VERTEX_STRIDE" low="0" high="9" type="uint"/> <reg32 offset="0x9e0d" name="PC_VIS_STREAM_CNTL" type="a6xx_pc_vis_stream_cntl" variants="A8XX-"/> <reg64 offset="0x9e0e" name="PC_PVIS_STREAM_BIN_BASE" type="waddress" align="32" variants="A8XX-"/> <reg64 offset="0x9e10" name="PC_DVIS_STREAM_BIN_BASE" type="waddress" align="32" variants="A8XX-"/> @@ -4075,8 +4109,8 @@ by a particular renderpass/blit. <bitfield name="THREADSIZE" pos="20" type="a6xx_threadsize"/> <!-- seems to make SP use less concurrent threads when possible? --> <bitfield name="UNK21" pos="21" type="boolean"/> - <!-- has a small impact on performance, not clear what it does --> - <bitfield name="UNK22" pos="22" type="boolean"/> + <!-- Enables round-robin mode, which guarantees fair scheduling --> + <bitfield name="COMPUTERRMODEEN" pos="22" type="boolean"/> <bitfield name="EARLYPREAMBLE" pos="23" type="boolean"/> <bitfield name="MERGEDREGS" pos="31" type="boolean"/> </reg32> @@ -4340,6 +4374,7 @@ by a particular renderpass/blit. </doc> <bitfield name="EOLM_ENABLE" pos="1" type="boolean"/> </reg32> + <reg32 offset="0xaf81" name="SP_LPAC_CHICKEN_BITS" variants="A7XX" usage="init"/> <reg32 offset="0xae04" name="SP_NC_MODE_CNTL_2" usage="init"> <bitfield name="F16_NO_INF" pos="3" type="boolean"/> </reg32> @@ -4352,6 +4387,7 @@ by a particular renderpass/blit. <reg32 offset="0xae0a" name="SP_CHICKEN_BITS_3" variants="A7XX-" usage="init"/> <reg32 offset="0xae0b" name="SP_CHICKEN_BITS_4" variants="A8XX-"/> <reg32 offset="0xae0c" name="SP_STATUS"/> + <reg32 offset="0xae0e" name="SP_L0_PERF_TUNE" variants="A8XX-"/> <reg32 offset="0xae0f" name="SP_PERFCTR_SHADER_MASK" usage="init"> <!-- some perfcntrs are affected by a per-stage enable bit @@ -4389,6 +4425,7 @@ by a particular renderpass/blit. <reg64 offset="0xae10" name="SP_HLSQ_GC_GMEM_RANGE_MIN" variants="A8XX-"/> <reg64 offset="0xae12" name="SP_HLSQ_LPAC_GMEM_RANGE_MIN" variants="A8XX-"/> + <reg32 offset="0xae14" name="SP_CHICKEN_BITS_5" variants="A8XX-"/> <reg32 offset="0xae15" name="SP_LPAC_CPI_STATUS" variants="A8XX-"/> <reg32 offset="0xae16" name="SP_LPAC_DBG_STATUS" variants="A8XX-"/> <reg32 offset="0xae17" name="SP_LPAC_ISDB_BATCH_COUNT" variants="A8XX-"/> @@ -5094,6 +5131,10 @@ by a particular renderpass/blit. <reg32 offset="0x0001" name="SYSTEM_CACHE_CNTL_0"/> <reg32 offset="0x0002" name="SYSTEM_CACHE_CNTL_1"/> <reg32 offset="0x0039" name="CX_MISC_TCM_RET_CNTL" variants="A7XX-"/> + <reg32 offset="0x0083" name="CX_MISC_GFX_PWR_CLK_STATUS" variants="A8XX-"> + <bitfield name="GX_GDSC_POWER_OFF" pos="3" type="boolean"/> + <bitfield name="GX_CLK_OFF" pos="4" type="boolean"/> + </reg32> <reg32 offset="0x0087" name="CX_MISC_SLICE_ENABLE_FINAL" variants="A8XX"/> <reg32 offset="0x0400" name="CX_MISC_SW_FUSE_VALUE" variants="A7XX-"> <bitfield pos="0" name="FASTBLEND" type="boolean"/> diff --git a/drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml b/drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml index f185b541aa70..2723da19cf5b 100644 --- a/drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml +++ b/drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml @@ -646,10 +646,10 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> <value name="CP_NON_CONTEXT_REG_BUNCH" value="0x5d" variants="A7XX-"/> <doc> Write to a scratch memory that is read by CP_REG_TEST with - SOURCE_SCRATCH_MEM set. It's not the same scratch as scratch registers. + SOURCE_OC_MEM set. It's not the same scratch as scratch registers. However it uses the same memory space. </doc> - <value name="CP_MEM_TO_SCRATCH_MEM" value="0x49" variants="A7XX-"/> + <value name="CP_MEM_TO_OC_MEM" value="0x49" variants="A7XX-"/> <doc> Executes an array of fixed-size command buffers where each @@ -1039,6 +1039,11 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) </domain> <domain name="CP_DRAW_AUTO" width="32"> + <doc> + Draws (counter - NUM_VERTICES_OFFSET / 4) / STRIDE vertices, counter + read from NUM_VERTICES_BASE. a7xx divides the counter by four too, + earlier gens use it as-is. + </doc> <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/> <reg32 offset="1" name="1"> <bitfield name="NUM_INSTANCES" low="0" high="31" type="uint"/> @@ -1048,7 +1053,8 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) <bitfield name="NUM_VERTICES_OFFSET" low="0" high="31" type="uint"/> </reg32> <reg32 offset="5" name="5"> - <bitfield name="STRIDE" low="0" high="31" type="uint"/> + <!-- the CP masks the stride to 11 bits before forwarding it --> + <bitfield name="STRIDE" low="0" high="10" type="uint"/> </reg32> </domain> @@ -1255,6 +1261,11 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) $dst = (($dst & $src0) rot $rotate) | $src1 Here "rot" means rotate left. + If SRCn_IS_REG, the corresponding src is a register offset, + otherwise it is an immediate. + + If DST_SCRATCH is set then the value modified is a scratch + ram address, instead of a register. </doc> <reg32 offset="0" name="0"> <bitfield name="DST_REG" low="0" high="17" type="hex"/> @@ -1286,7 +1297,7 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) Treat things as 64B, allowing for a 64B atomic read of registers. --> - <bitfield name="64B" pos="30" type="boolean"/> + <bitfield name="IS_64B" pos="30" type="boolean"/> <bitfield name="ACCUMULATE" pos="31" type="boolean"/> </reg32> <stripe varset="chip" variants="A2XX-A4XX"> @@ -1307,7 +1318,7 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) <bitfield name="REG" low="0" high="17" type="hex"/> <!-- number of registers/dwords copied is max(CNT, 1). --> <bitfield name="CNT" low="18" high="29" type="uint"/> - <bitfield name="64B" pos="30" type="boolean"/> + <bitfield name="IS_64B" pos="30" type="boolean"/> <bitfield name="ACCUMULATE" pos="31" type="boolean"/> </reg32> <reg64 offset="1" name="DEST" type="waddress"/> @@ -1327,7 +1338,7 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) <bitfield name="REG" low="0" high="17" type="hex"/> <!-- number of registers/dwords copied is max(CNT, 1). --> <bitfield name="CNT" low="18" high="29" type="uint"/> - <bitfield name="64B" pos="30" type="boolean"/> + <bitfield name="IS_64B" pos="30" type="boolean"/> <bitfield name="ACCUMULATE" pos="31" type="boolean"/> </reg32> <reg64 offset="1" name="DEST" type="waddress"/> @@ -1337,12 +1348,13 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) <domain name="CP_MEM_TO_REG" width="32"> <reg32 offset="0" name="0"> <bitfield name="REG" low="0" high="17" type="hex"/> + <!-- if set, all writes are to the same reg --> + <bitfield name="ONE_REG_WR" pos="18" type="boolean"/> <!-- number of registers/dwords copied is max(CNT, 1). --> <bitfield name="CNT" low="19" high="29" type="uint"/> <!-- shift each DWORD left by 2 while copying --> <bitfield name="SHIFT_BY_2" pos="30" type="boolean"/> - <!-- does the same thing as CP_MEM_TO_MEM::UNK31 --> - <bitfield name="UNK31" pos="31" type="boolean"/> + <bitfield name="WAIT_CACHE_FLUSH" pos="31" type="boolean"/> </reg32> <stripe varset="chip" variants="A2XX-A4XX"> <reg32 offset="1" name="SRC" type="address"/> @@ -1366,8 +1378,7 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) <bitfield name="DOUBLE" pos="29" type="boolean"/> <!-- execute CP_WAIT_FOR_MEM_WRITES beforehand --> <bitfield name="WAIT_FOR_MEM_WRITES" pos="30" type="boolean"/> - <!-- some other kind of wait --> - <bitfield name="UNK31" pos="31" type="boolean"/> + <bitfield name="WAIT_CACHE_FLUSH" pos="31" type="boolean"/> </reg32> <reg64 offset="1" name="DST" type="waddress"/> <reg64 offset="3" name="SRC_A" type="address"/> @@ -1954,13 +1965,13 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) <enum name="source_type"> <value value="0" name="SOURCE_REG"/> <!-- Don't confuse with scratch registers, this is a separate memory - written into by CP_MEM_TO_SCRATCH_MEM. --> - <value value="1" name="SOURCE_SCRATCH_MEM" varset="chip" variants="A7XX-"/> + written into by CP_MEM_TO_OC_MEM. --> + <value value="1" name="SOURCE_OC_MEM" varset="chip" variants="A7XX-"/> </enum> <reg32 offset="0" name="0"> <!-- the register to test --> <bitfield name="REG" low="0" high="17" varset="source_type" variants="SOURCE_REG"/> - <bitfield name="SCRATCH_MEM_OFFSET" low="0" high="17" varset="source_type" variants="SOURCE_SCRATCH_MEM"/> + <bitfield name="OC_MEM_OFFSET" low="0" high="17" varset="source_type" variants="SOURCE_OC_MEM"/> <bitfield name="SOURCE" pos="18" type="source_type" addvariant="yes"/> <!-- the bit to test --> <bitfield name="BIT" low="20" high="24" type="uint"/> @@ -2277,10 +2288,10 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) </reg32> </domain> -<domain name="CP_MEM_TO_SCRATCH_MEM" width="32"> +<domain name="CP_MEM_TO_OC_MEM" width="32"> <doc> Best guess is that it is a faster way to fetch all the VSC_CHANNEL_VISIBILITY registers - and keep them in a local scratch memory instead of fetching every time + and keep them in a local on-chip memory instead of fetching every time when skipping IBs. </doc> <reg32 offset="0" name="0"> diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index 2b524154d9fb..9f703261d7ac 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -39,7 +39,6 @@ config QCOM_COMMAND_DB config QCOM_GENI_SE tristate "Qualcomm GENI Serial Engine Driver" - depends on ARM64 || COMPILE_TEST default ARCH_QCOM help This driver is used to manage Generic Interface (GENI) firmware based diff --git a/drivers/soc/qcom/apr.c b/drivers/soc/qcom/apr.c index ea7f83916d8d..2d5645ff9919 100644 --- a/drivers/soc/qcom/apr.c +++ b/drivers/soc/qcom/apr.c @@ -338,29 +338,6 @@ static void apr_rxwq(struct work_struct *work) } } -static int apr_device_match(struct device *dev, const struct device_driver *drv) -{ - struct apr_device *adev = to_apr_device(dev); - const struct apr_driver *adrv = to_apr_driver(drv); - const struct apr_device_id *id = adrv->id_table; - - /* Attempt an OF style match first */ - if (of_driver_match_device(dev, drv)) - return 1; - - if (!id) - return 0; - - while (id->domain_id != 0 || id->svc_id != 0) { - if (id->domain_id == adev->domain_id && - id->svc_id == adev->svc.id) - return 1; - id++; - } - - return 0; -} - static int apr_device_probe(struct device *dev) { struct apr_device *adev = to_apr_device(dev); @@ -401,7 +378,7 @@ static int apr_uevent(const struct device *dev, struct kobj_uevent_env *env) const struct bus_type aprbus = { .name = "aprbus", - .match = apr_device_match, + .match = of_driver_match_device, .probe = apr_device_probe, .uevent = apr_uevent, .remove = apr_device_remove, @@ -434,31 +411,35 @@ static int apr_add_device(struct device *dev, struct device_node *np, if (np) snprintf(adev->name, APR_NAME_SIZE, "%pOFn", np); + adev->dev.bus = &aprbus; + adev->dev.parent = dev; + adev->dev.of_node = np; + adev->dev.release = apr_dev_release; + adev->dev.driver = NULL; + device_initialize(&adev->dev); + switch (apr->type) { case PR_TYPE_APR: - dev_set_name(&adev->dev, "aprsvc:%s:%x:%x", adev->name, - domain_id, svc_id); + ret = dev_set_name(&adev->dev, "aprsvc:%s:%x:%x", adev->name, + domain_id, svc_id); break; case PR_TYPE_GPR: - dev_set_name(&adev->dev, "gprsvc:%s:%x:%x", adev->name, - domain_id, svc_id); + ret = dev_set_name(&adev->dev, "gprsvc:%s:%x:%x", adev->name, + domain_id, svc_id); break; default: + ret = -EINVAL; break; } - - adev->dev.bus = &aprbus; - adev->dev.parent = dev; - adev->dev.of_node = np; - adev->dev.release = apr_dev_release; - adev->dev.driver = NULL; + if (ret) + goto out_put_device; spin_lock(&apr->svcs_lock); ret = idr_alloc(&apr->svcs_idr, svc, svc_id, svc_id + 1, GFP_ATOMIC); spin_unlock(&apr->svcs_lock); if (ret < 0) { dev_err(dev, "idr_alloc failed: %d\n", ret); - goto out; + goto out_put_device; } /* Protection domain is optional, it does not exist on older platforms */ @@ -466,18 +447,26 @@ static int apr_add_device(struct device *dev, struct device_node *np, 1, &adev->service_path); if (ret < 0 && ret != -EINVAL) { dev_err(dev, "Failed to read second value of qcom,protection-domain\n"); - goto out; + goto out_remove_idr; } dev_info(dev, "Adding APR/GPR dev: %s\n", dev_name(&adev->dev)); - ret = device_register(&adev->dev); + ret = device_add(&adev->dev); if (ret) { - dev_err(dev, "device_register failed: %d\n", ret); - put_device(&adev->dev); + dev_err(dev, "device_add failed: %d\n", ret); + goto out_remove_idr; } -out: + return 0; + +out_remove_idr: + spin_lock(&apr->svcs_lock); + idr_remove(&apr->svcs_idr, svc_id); + spin_unlock(&apr->svcs_lock); + flush_workqueue(apr->rxwq); +out_put_device: + put_device(&adev->dev); return ret; } diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 733999867bbf..5e45a10663c4 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -626,11 +626,11 @@ static const struct llcc_slice_config glymur_data[] = { static const struct llcc_slice_config ipq5424_data[] = { { - .usecase_id = LLCC_CPUSS, + .usecase_id = LLCC_PPE_RXDESC, .slice_id = 1, - .max_cap = 768, - .priority = 1, - .bonus_ways = 0xFFFF, + .max_cap = 128, + .priority = 3, + .bonus_ways = 0x0FFF, .retain_on_pc = true, .activate_on_init = true, .write_scid_cacheable_en = true, @@ -642,12 +642,52 @@ static const struct llcc_slice_config ipq5424_data[] = { .vict_prio = true, }, { - .usecase_id = LLCC_VIDSC0, + .usecase_id = LLCC_CPUSS, .slice_id = 2, - .max_cap = 256, - .priority = 2, + .max_cap = 768, + .priority = 1, .fixed_size = true, - .bonus_ways = 0xF000, + .bonus_ways = 0x0FFF, + .retain_on_pc = true, + .activate_on_init = true, + .write_scid_cacheable_en = true, + .stale_en = true, + .stale_cap_en = true, + }, + { + .usecase_id = LLCC_PPE_RXFILL, + .slice_id = 5, + .max_cap = 128, + .priority = 3, + .bonus_ways = 0x0FFF, + .retain_on_pc = true, + .activate_on_init = true, + .write_scid_cacheable_en = true, + .stale_en = true, + .stale_cap_en = true, + .alloc_oneway_en = true, + .ovcap_en = true, + .ovcap_prio = true, + .vict_prio = true, + }, + { + .usecase_id = LLCC_WLAN_5G, + .slice_id = 6, + .max_cap = 128, + .priority = 3, + .bonus_ways = 0xC000, + .retain_on_pc = true, + .activate_on_init = true, + .write_scid_cacheable_en = true, + .stale_en = true, + .stale_cap_en = true, + }, + { + .usecase_id = LLCC_WLAN_6G, + .slice_id = 7, + .max_cap = 128, + .priority = 3, + .bonus_ways = 0x3000, .retain_on_pc = true, .activate_on_init = true, .write_scid_cacheable_en = true, @@ -5617,6 +5657,10 @@ static int qcom_llcc_probe(struct platform_device *pdev) } drv_data->ecc_irq = platform_get_irq_optional(pdev, 0); + if (drv_data->ecc_irq < 0 && drv_data->ecc_irq != -ENXIO) + return dev_err_probe(&pdev->dev, drv_data->ecc_irq, + "failed to get IRQ resource\n"); + drv_data->edac_reg_offset = cfg->edac_reg_offset; drv_data->ecc_irq_configured = cfg->irq_configured; drv_data->dev = dev; diff --git a/drivers/soc/qcom/pmic_glink_altmode.c b/drivers/soc/qcom/pmic_glink_altmode.c index 13c434f8d03a..465e5d2316a0 100644 --- a/drivers/soc/qcom/pmic_glink_altmode.c +++ b/drivers/soc/qcom/pmic_glink_altmode.c @@ -451,7 +451,7 @@ static void pmic_glink_altmode_sc8180xp_notify(struct pmic_glink_altmode *altmod alt_port->mode = mode; alt_port->hpd_state = hpd_state; alt_port->hpd_irq = hpd_irq; - schedule_work(&alt_port->work); + queue_work(system_freezable_wq, &alt_port->work); } #define SC8280XP_DPAM_MASK 0x3f @@ -502,7 +502,7 @@ static void pmic_glink_altmode_sc8280xp_notify(struct pmic_glink_altmode *altmod alt_port->tbt_data = *tbt; } - schedule_work(&alt_port->work); + queue_work(system_freezable_wq, &alt_port->work); } static void pmic_glink_altmode_callback(const void *data, size_t len, void *priv) diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c index 873bfbd6b2b7..6ac2bdc16984 100644 --- a/drivers/soc/qcom/qcom-geni-se.c +++ b/drivers/soc/qcom/qcom-geni-se.c @@ -1230,25 +1230,28 @@ EXPORT_SYMBOL_GPL(geni_se_resources_init); * @se: Pointer to the serial engine structure. * @fw: Pointer to the firmware image. * @protocol: Expected serial engine protocol type. + * @fw_size_out: Non-NULL output parameter; receives the rounded, validated + * firmware word count on success. * * Identifies the appropriate firmware image or configuration required for a * specific communication protocol instance running on a Qualcomm GENI * controller. Validates the firmware size against the hardware PROG_RAM_DEPTH * read from SE_HW_PARAM_2. * - * Return: pointer to a valid 'struct se_fw_hdr' if found, or NULL otherwise. + * Return: pointer to a valid 'const struct se_fw_hdr' if found, or NULL otherwise. */ -static struct se_fw_hdr *geni_find_protocol_fw(struct geni_se *se, const struct firmware *fw, - enum geni_se_protocol_type protocol) +static const struct se_fw_hdr *geni_find_protocol_fw(struct geni_se *se, const struct firmware *fw, + enum geni_se_protocol_type protocol, + u32 *fw_size_out) { struct device *dev = se->dev; const struct elf32_hdr *ehdr; const struct elf32_phdr *phdrs; const struct elf32_phdr *phdr; - struct se_fw_hdr *sefw; + const struct se_fw_hdr *sefw; u32 fw_end, cfg_idx_end, cfg_val_end; u32 prog_ram_depth; - u16 fw_size; + u32 fw_size; int i; if (!fw || fw->size < sizeof(struct elf32_hdr)) @@ -1287,24 +1290,23 @@ static struct se_fw_hdr *geni_find_protocol_fw(struct geni_se *se, const struct if (phdr->p_filesz < sizeof(struct se_fw_hdr)) continue; - sefw = (struct se_fw_hdr *)(fw->data + phdr->p_offset); + sefw = (const struct se_fw_hdr *)(fw->data + phdr->p_offset); fw_size = le16_to_cpu(sefw->fw_size_in_items); - fw_end = le16_to_cpu(sefw->fw_offset) + fw_size * sizeof(u32); - cfg_idx_end = le16_to_cpu(sefw->cfg_idx_offset) + - le16_to_cpu(sefw->cfg_size_in_items) * sizeof(u8); - cfg_val_end = le16_to_cpu(sefw->cfg_val_offset) + - le16_to_cpu(sefw->cfg_size_in_items) * sizeof(u32); if (le32_to_cpu(sefw->magic) != SE_MAGIC_NUM || le32_to_cpu(sefw->version) != 1) continue; - if (le32_to_cpu(sefw->serial_protocol) != protocol) + if (le16_to_cpu(sefw->serial_protocol) != protocol) continue; - if (fw_size % 2 != 0) { + if (fw_size % 2 != 0) fw_size++; - sefw->fw_size_in_items = cpu_to_le16(fw_size); - } + + fw_end = le16_to_cpu(sefw->fw_offset) + fw_size * sizeof(u32); + cfg_idx_end = le16_to_cpu(sefw->cfg_idx_offset) + + le16_to_cpu(sefw->cfg_size_in_items) * sizeof(u8); + cfg_val_end = le16_to_cpu(sefw->cfg_val_offset) + + le16_to_cpu(sefw->cfg_size_in_items) * sizeof(u32); prog_ram_depth = FIELD_GET(PROG_RAM_DEPTH_MSK, readl_relaxed(se->base + SE_HW_PARAM_2)); @@ -1320,6 +1322,7 @@ static struct se_fw_hdr *geni_find_protocol_fw(struct geni_se *se, const struct continue; } + *fw_size_out = fw_size; return sefw; } @@ -1430,17 +1433,17 @@ static int geni_load_se_fw(struct geni_se *se, const struct firmware *fw, { const u32 *fw_data, *cfg_val_arr; const u8 *cfg_idx_arr; - u32 i, reg_value; + u32 i, reg_value, fw_size_in_items; int ret; - struct se_fw_hdr *hdr; + const struct se_fw_hdr *hdr; - hdr = geni_find_protocol_fw(se, fw, protocol); + hdr = geni_find_protocol_fw(se, fw, protocol, &fw_size_in_items); if (!hdr) return -EINVAL; - fw_data = (const u32 *)((u8 *)hdr + le16_to_cpu(hdr->fw_offset)); + fw_data = (const u32 *)((const u8 *)hdr + le16_to_cpu(hdr->fw_offset)); cfg_idx_arr = (const u8 *)hdr + le16_to_cpu(hdr->cfg_idx_offset); - cfg_val_arr = (const u32 *)((u8 *)hdr + le16_to_cpu(hdr->cfg_val_offset)); + cfg_val_arr = (const u32 *)((const u8 *)hdr + le16_to_cpu(hdr->cfg_val_offset)); ret = geni_icc_set_bw(se); if (ret) @@ -1511,7 +1514,7 @@ static int geni_load_se_fw(struct geni_se *se, const struct firmware *fw, /* Program RAM address space. */ memcpy_toio(se->base + SE_GENI_CFG_RAMN, fw_data, - le16_to_cpu(hdr->fw_size_in_items) * sizeof(u32)); + fw_size_in_items * sizeof(u32)); /* Put default values on GENI's output pads. */ writel_relaxed(0x1, se->base + GENI_FORCE_DEFAULT_REG); diff --git a/drivers/soc/qcom/qcom_aoss.c b/drivers/soc/qcom/qcom_aoss.c index 259c41f0c34e..a6b673cd7678 100644 --- a/drivers/soc/qcom/qcom_aoss.c +++ b/drivers/soc/qcom/qcom_aoss.c @@ -602,10 +602,8 @@ static int qmp_probe(struct platform_device *pdev) irq = platform_get_irq(pdev, 0); ret = devm_request_irq(&pdev->dev, irq, qmp_intr, 0, "aoss-qmp", qmp); - if (ret < 0) { - dev_err(&pdev->dev, "failed to request interrupt\n"); + if (ret < 0) goto err_free_mbox; - } ret = qmp_open(qmp); if (ret < 0) diff --git a/drivers/soc/qcom/rpmh-internal.h b/drivers/soc/qcom/rpmh-internal.h index e3cf1beff803..39441a25af9b 100644 --- a/drivers/soc/qcom/rpmh-internal.h +++ b/drivers/soc/qcom/rpmh-internal.h @@ -20,7 +20,7 @@ struct rsc_drv; /** - * struct tcs_group: group of Trigger Command Sets (TCS) to send state requests + * struct tcs_group - group of Trigger Command Sets (TCS) to send state requests * to the controller * * @drv: The controller. @@ -53,7 +53,7 @@ struct tcs_group { }; /** - * struct rpmh_request: the message to be sent to rpmh-rsc + * struct rpmh_request - the message to be sent to rpmh-rsc * * @msg: the request * @cmd: the payload that will be part of the @msg @@ -70,7 +70,7 @@ struct rpmh_request { }; /** - * struct rpmh_ctrlr: our representation of the controller + * struct rpmh_ctrlr - our representation of the controller * * @cache: the list of cached requests * @cache_lock: synchronize access to the cache data @@ -84,13 +84,19 @@ struct rpmh_ctrlr { struct list_head batch_cache; }; +/** + * struct rsc_ver - Hardware version of the RSC controller. + * + * @major: Major version number. + * @minor: Minor version number. + */ struct rsc_ver { u32 major; u32 minor; }; /** - * struct rsc_drv: the Direct Resource Voter (DRV) of the + * struct rsc_drv - the Direct Resource Voter (DRV) of the * Resource State Coordinator controller (RSC) * * @name: Controller identifier. @@ -116,6 +122,8 @@ struct rsc_ver { * slot * @client: Handle to the DRV's client. * @dev: RSC device. + * @ver: HW version of the RSC controller. + * @regs: Pointer to the register offset table for this version. */ struct rsc_drv { const char *name; diff --git a/drivers/soc/qcom/rpmh-rsc.c b/drivers/soc/qcom/rpmh-rsc.c index f881af35ecfc..c4542318eac4 100644 --- a/drivers/soc/qcom/rpmh-rsc.c +++ b/drivers/soc/qcom/rpmh-rsc.c @@ -842,7 +842,7 @@ exit: } /** - * rpmh_rsc_cpu_pm_callback() - Check if any of the AMCs are busy. + * rpmh_rsc_cpu_pm_callback() - CPU PM notifier to flush sleep/wake TCS data. * @nfb: Pointer to the notifier block in struct rsc_drv. * @action: CPU_PM_ENTER, CPU_PM_ENTER_FAILED, or CPU_PM_EXIT. * @v: Unused @@ -923,7 +923,7 @@ static int rpmh_rsc_cpu_pm_callback(struct notifier_block *nfb, } /** - * rpmh_rsc_pd_callback() - Check if any of the AMCs are busy. + * rpmh_rsc_pd_callback() - PM domain callback to flush sleep/wake TCS data. * @nfb: Pointer to the genpd notifier block in struct rsc_drv. * @action: GENPD_NOTIFY_PRE_OFF, GENPD_NOTIFY_OFF, GENPD_NOTIFY_PRE_ON or GENPD_NOTIFY_ON. * @v: Unused diff --git a/drivers/soc/qcom/rpmh.c b/drivers/soc/qcom/rpmh.c index f881c4c757ec..360242a315e3 100644 --- a/drivers/soc/qcom/rpmh.c +++ b/drivers/soc/qcom/rpmh.c @@ -41,7 +41,7 @@ #define ctrlr_to_drv(ctrlr) container_of(ctrlr, struct rsc_drv, client) /** - * struct cache_req: the request object for caching + * struct cache_req - the request object for caching * * @addr: the address of the resource * @sleep_val: the sleep vote @@ -56,7 +56,7 @@ struct cache_req { }; /** - * struct batch_cache_req - An entry in our batch catch + * struct batch_cache_req - An entry in our batch cache * * @list: linked list obj * @count: number of messages @@ -76,6 +76,14 @@ static struct rpmh_ctrlr *get_rpmh_ctrlr(const struct device *dev) return &drv->client; } +/** + * rpmh_tx_done() - Signal the completion of a RPMH transfer. + * @msg: The request that was previously sent. + * + * Called by the RSC driver when an active-only transfer is complete. + * Signals any blocking waiter and frees the message if it was dynamically + * allocated. + */ void rpmh_tx_done(const struct tcs_request *msg) { struct rpmh_request *rpm_msg = container_of(msg, struct rpmh_request, @@ -157,7 +165,7 @@ unlock: } /** - * __rpmh_write: Cache and send the RPMH request + * __rpmh_write() - Cache and send the RPMH request. * * @dev: The device making the request * @state: Active/Sleep request type @@ -166,6 +174,8 @@ unlock: * Cache the RPMH request and send if the state is ACTIVE_ONLY. * SLEEP/WAKE_ONLY requests are not sent to the controller at * this time. Use rpmh_flush() to send them to the controller. + * + * Return: 0 on success, negative error code on failure. */ static int __rpmh_write(const struct device *dev, enum rpmh_state state, struct rpmh_request *rpm_msg) @@ -248,7 +258,7 @@ int rpmh_read(const struct device *dev, struct tcs_cmd *cmd) EXPORT_SYMBOL_GPL(rpmh_read); /** - * rpmh_write_async: Write a set of RPMH commands + * rpmh_write_async() - Write a set of RPMH commands. * * @dev: The device making the request * @state: Active/sleep set @@ -257,6 +267,8 @@ EXPORT_SYMBOL_GPL(rpmh_read); * * Write a set of RPMH commands, the order of commands is maintained * and will be sent as a single shot. + * + * Return: 0 on success, negative error code on failure. */ int rpmh_write_async(const struct device *dev, enum rpmh_state state, const struct tcs_cmd *cmd, u32 n) @@ -280,7 +292,7 @@ int rpmh_write_async(const struct device *dev, enum rpmh_state state, EXPORT_SYMBOL_GPL(rpmh_write_async); /** - * rpmh_write: Write a set of RPMH commands and block until response + * rpmh_write() - Write a set of RPMH commands and block until response * * @dev: The device making the request * @state: Active/sleep set @@ -288,6 +300,8 @@ EXPORT_SYMBOL_GPL(rpmh_write_async); * @n: The number of elements in @cmd * * May sleep. Do not call from atomic contexts. + * + * Return: 0 on success, negative error code on failure. */ int rpmh_write(const struct device *dev, enum rpmh_state state, const struct tcs_cmd *cmd, u32 n) @@ -342,7 +356,7 @@ static int flush_batch(struct rpmh_ctrlr *ctrlr) } /** - * rpmh_write_batch: Write multiple sets of RPMH commands and wait for the + * rpmh_write_batch() - Write multiple sets of RPMH commands and wait for the * batch to finish. * * @dev: the device making the request @@ -350,13 +364,15 @@ static int flush_batch(struct rpmh_ctrlr *ctrlr) * @cmd: The payload data * @n: The array of count of elements in each batch, 0 terminated. * - * Write a request to the RSC controller without caching. If the request - * state is ACTIVE, then the requests are treated as completion request - * and sent to the controller immediately. The function waits until all the - * commands are complete. If the request was to SLEEP or WAKE_ONLY, then the - * request is sent as fire-n-forget and no ack is expected. + * If the request state is ACTIVE_ONLY, the requests are sent to the + * controller immediately and the function waits until all commands are + * complete. If the state is SLEEP or WAKE_ONLY, the requests are cached + * and the function returns immediately; they are sent to the controller + * later by rpmh_flush(). * * May sleep. Do not call from atomic contexts for ACTIVE_ONLY requests. + * + * Return: 0 on success, negative error code on failure. */ int rpmh_write_batch(const struct device *dev, enum rpmh_state state, const struct tcs_cmd *cmd, u32 *n) @@ -519,7 +535,7 @@ exit: } /** - * rpmh_invalidate: Invalidate sleep and wake sets in batch_cache + * rpmh_invalidate() - Invalidate sleep and wake sets in batch_cache * * @dev: The device making the request * diff --git a/drivers/soc/qcom/smem_dramc.c b/drivers/soc/qcom/smem_dramc.c index 63ebe7f6db59..497513c95308 100644 --- a/drivers/soc/qcom/smem_dramc.c +++ b/drivers/soc/qcom/smem_dramc.c @@ -20,12 +20,22 @@ #define MAX_DDR_FREQ_NUM_V5 14 #define MAX_CHAN_NUM 8 +#define MAX_CHAN_NUM_V7_GLYMUR 16 #define MAX_RANK_NUM 2 #define DDR_HBB_MIN 13 #define DDR_HBB_MAX 19 #define MAX_SHUB_ENTRIES 8 +#define MAX_SHUB_ENTRIES_V7_GLYMUR 10 +#define MAX_DDR_REGIONS_V7_GLYMUR 4 + +/* + * Glymur's DRAM information entry has 256 bytes of trailing zeroes + * after its DDR details, four region slots, 10-entry SHUB frequency + * plan, and v6 misc information. + */ +#define DDR_V7_GLYMUR_RESERVED_SIZE 256 static struct smem_dram *__dram; @@ -39,6 +49,7 @@ enum ddr_info_version { INFO_V6, /* INFO_V6 seems to only have shipped with 6 DDR regions, unlike V7 */ INFO_V7, INFO_V7_WITH_6_REGIONS, + INFO_V7_GLYMUR, }; struct smem_dram { @@ -188,6 +199,37 @@ struct ddr_details_v7 { struct ddr_regions_v5 ddr_regions; }; +struct ddr_regions_v7_glymur { + __le32 ddr_region_num; + __le64 ddr_rank0_size; + __le64 ddr_rank1_size; + __le64 ddr_cs0_start_addr; + __le64 ddr_cs1_start_addr; + __le32 highest_bank_addr_bit; + struct ddr_region_v5 ddr_region[MAX_DDR_REGIONS_V7_GLYMUR]; +}; + +struct ddr_details_v7_glymur { + u8 manufacturer_id; + u8 device_type; + struct ddr_part_details ddr_params[MAX_CHAN_NUM_V7_GLYMUR]; + struct ddr_freq_plan_v5 ddr_freq_tbl; + u8 num_channels; + u8 sct_config; + struct ddr_regions_v7_glymur ddr_regions; +}; + +struct shub_freq_plan_entry_v7_glymur { + u8 num_shub_freqs; + struct shub_freq_table shub_freq[MAX_SHUB_ENTRIES_V7_GLYMUR]; +}; + +struct ddr_v7_glymur_tail { + struct shub_freq_plan_entry_v7_glymur shub_freq_plan; + struct ddr_misc_info_v6 misc_info; + u8 reserved[DDR_V7_GLYMUR_RESERVED_SIZE]; +}; + /** * qcom_smem_dram_get_hbb(): Get the Highest bank address bit * @@ -219,7 +261,7 @@ static void smem_dram_parse_v3_data(struct smem_dram *dram, void *data) if (freq_entry->freq_khz && freq_entry->enabled) { u32 freq_khz = le32_to_cpu(freq_entry->freq_khz); - dram->frequencies[dram->num_frequencies++] = 1000 * freq_khz; + dram->frequencies[dram->num_frequencies++] = 1000UL * freq_khz; } } } @@ -231,8 +273,11 @@ static void smem_dram_parse_v3_14freqs_data(struct smem_dram *dram, void *data) for (int i = 0; i < MAX_DDR_FREQ_NUM_V3 + 1; i++) { struct ddr_freq_table *freq_entry = &details->ddr_freq_tbl.ddr_freq[i]; - if (freq_entry->freq_khz && freq_entry->enabled) - dram->frequencies[dram->num_frequencies++] = 1000 * freq_entry->freq_khz; + if (freq_entry->freq_khz && freq_entry->enabled) { + u32 freq_khz = le32_to_cpu(freq_entry->freq_khz); + + dram->frequencies[dram->num_frequencies++] = 1000UL * freq_khz; + } } } @@ -248,7 +293,7 @@ static void smem_dram_parse_v4_data(struct smem_dram *dram, void *data) if (freq_entry->freq_khz && freq_entry->enabled) { u32 freq_khz = le32_to_cpu(freq_entry->freq_khz); - dram->frequencies[dram->num_frequencies++] = 1000 * freq_khz; + dram->frequencies[dram->num_frequencies++] = 1000UL * freq_khz; } } } @@ -265,7 +310,7 @@ static void smem_dram_parse_v5_data(struct smem_dram *dram, void *data) if (freq_entry->freq_khz && freq_entry->enabled) { u32 freq_khz = le32_to_cpu(freq_entry->freq_khz); - dram->frequencies[dram->num_frequencies++] = 1000 * freq_khz; + dram->frequencies[dram->num_frequencies++] = 1000UL * freq_khz; } } } @@ -282,6 +327,23 @@ static void smem_dram_parse_v7_data(struct smem_dram *dram, void *data) if (freq_entry->freq_khz && freq_entry->enabled) { u32 freq_khz = le32_to_cpu(freq_entry->freq_khz); + dram->frequencies[dram->num_frequencies++] = 1000UL * freq_khz; + } + } +} + +static void smem_dram_parse_v7_glymur_data(struct smem_dram *dram, void *data) +{ + struct ddr_details_v7_glymur *details = data; + + dram->hbb = le32_to_cpu(details->ddr_regions.highest_bank_addr_bit); + + for (int i = 0; i < MAX_DDR_FREQ_NUM_V5; i++) { + struct ddr_freq_table *freq_entry = &details->ddr_freq_tbl.ddr_freq[i]; + + if (freq_entry->freq_khz && freq_entry->enabled) { + u32 freq_khz = le32_to_cpu(freq_entry->freq_khz); + dram->frequencies[dram->num_frequencies++] = 1000 * freq_khz; } } @@ -341,6 +403,10 @@ static int smem_dram_infer_struct_version(size_t size) sizeof(struct shub_freq_plan_entry)) return INFO_V7_WITH_6_REGIONS; + if (size == sizeof(struct ddr_details_v7_glymur) + + sizeof(struct ddr_v7_glymur_tail)) + return INFO_V7_GLYMUR; + return INFO_UNKNOWN; } @@ -382,7 +448,7 @@ struct dentry *smem_dram_parse(struct qcom_smem *smem, struct device *dev) return ERR_PTR(-ENODATA); ver = smem_dram_infer_struct_version(actual_size); - if (ver < 0) { + if ((int)ver < 0) { /* Some SoCs don't provide data that's useful for us */ return ERR_PTR(-ENODATA); } else if (ver == INFO_UNKNOWN) { @@ -415,6 +481,9 @@ struct dentry *smem_dram_parse(struct qcom_smem *smem, struct device *dev) case INFO_V7_WITH_6_REGIONS: smem_dram_parse_v7_data(dram, data); break; + case INFO_V7_GLYMUR: + smem_dram_parse_v7_glymur_data(dram, data); + break; default: return ERR_PTR(-EINVAL); } diff --git a/drivers/soc/qcom/smp2p.c b/drivers/soc/qcom/smp2p.c index af0ceeaf6e07..3104e31f91c9 100644 --- a/drivers/soc/qcom/smp2p.c +++ b/drivers/soc/qcom/smp2p.c @@ -102,7 +102,7 @@ struct smp2p_entry { struct qcom_smp2p *smp2p; const char *name; - u32 *value; + u32 __iomem *value; u32 last_value; struct irq_domain *domain; @@ -276,7 +276,7 @@ static void qcom_smp2p_start_in(struct qcom_smp2p *smp2p) list_for_each_entry(entry, &smp2p->inbound, node) { memcpy(buf, in->entries[i].name, sizeof(buf)); if (!strcmp(buf, entry->name)) { - entry->value = &in->entries[i].value; + entry->value = (u32 __iomem *)&in->entries[i].value; entry->last_value = readl(entry->value); break; } @@ -302,7 +302,7 @@ static void qcom_smp2p_notify_in(struct qcom_smp2p *smp2p) list_for_each_entry(entry, &smp2p->inbound, node) { memcpy(buf, in->entries[i].name, sizeof(buf)); if (!strcmp(buf, entry->name)) { - entry->value = &in->entries[i].value; + entry->value = (u32 __iomem *)&in->entries[i].value; break; } } @@ -528,7 +528,7 @@ static int qcom_smp2p_outbound_entry(struct qcom_smp2p *smp2p, memcpy(out->entries[out->valid_entries].name, buf, SMP2P_MAX_ENTRY_NAME); /* Make the logical entry reference the physical value */ - entry->value = &out->entries[out->valid_entries].value; + entry->value = (u32 __iomem *)&out->entries[out->valid_entries].value; out->valid_entries++; @@ -720,10 +720,8 @@ static int qcom_smp2p_probe(struct platform_device *pdev) NULL, qcom_smp2p_intr, IRQF_ONESHOT, NULL, (void *)smp2p); - if (ret) { - dev_err(&pdev->dev, "failed to request interrupt\n"); + if (ret) goto unwind_interfaces; - } /* * Treat smp2p interrupt as wakeup source, but keep it disabled diff --git a/drivers/soc/qcom/smsm.c b/drivers/soc/qcom/smsm.c index 021e9d1f61dc..ac3c85a2597a 100644 --- a/drivers/soc/qcom/smsm.c +++ b/drivers/soc/qcom/smsm.c @@ -82,8 +82,8 @@ struct qcom_smsm { u32 num_hosts; u32 num_entries; - u32 *local_state; - u32 *subscription; + u32 __iomem *local_state; + u32 __iomem *subscription; struct qcom_smem_state *state; spinlock_t lock; @@ -115,8 +115,8 @@ struct smsm_entry { DECLARE_BITMAP(irq_falling, 32); unsigned long last_value; - u32 *remote_state; - u32 *subscription; + u32 __iomem *remote_state; + u32 __iomem *subscription; }; /** @@ -451,10 +451,8 @@ static int smsm_inbound_entry(struct qcom_smsm *smsm, NULL, smsm_intr, IRQF_ONESHOT, "smsm", (void *)entry); - if (ret) { - dev_err(smsm->dev, "failed to request interrupt\n"); + if (ret) return ret; - } entry->domain = irq_domain_create_linear(of_fwnode_handle(node), 32, &smsm_irq_ops, entry); if (!entry->domain) { @@ -513,9 +511,9 @@ static int qcom_smsm_probe(struct platform_device *pdev) struct device_node *node; struct smsm_entry *entry; struct qcom_smsm *smsm; - u32 *intr_mask; + u32 __iomem *intr_mask; size_t size; - u32 *states; + u32 __iomem *states; u32 id; int ret; @@ -579,7 +577,7 @@ static int qcom_smsm_probe(struct platform_device *pdev) goto out_put; } - states = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_SMSM_SHARED_STATE, NULL); + states = (u32 __iomem *)qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_SMSM_SHARED_STATE, NULL); if (IS_ERR(states)) { dev_err(&pdev->dev, "Unable to acquire shared state entry\n"); ret = PTR_ERR(states); @@ -594,7 +592,7 @@ static int qcom_smsm_probe(struct platform_device *pdev) goto out_put; } - intr_mask = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_SMSM_CPU_INTR_MASK, NULL); + intr_mask = (u32 __iomem *)qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_SMSM_CPU_INTR_MASK, NULL); if (IS_ERR(intr_mask)) { dev_err(&pdev->dev, "unable to acquire shared memory interrupt mask\n"); ret = PTR_ERR(intr_mask); diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 1836e226a294..63ee5cd561a2 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -450,6 +450,7 @@ static const struct soc_id soc_id[] = { { qcom_board_id(IPQ8172) }, { qcom_board_id(IPQ8173) }, { qcom_board_id(IPQ8174) }, + { qcom_board_id(SM7250) }, { qcom_board_id(IPQ6018) }, { qcom_board_id(IPQ6028) }, { qcom_board_id(SDM429W) }, diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c index 23901a4c51f7..36c90f72943f 100644 --- a/drivers/soc/qcom/ubwc_config.c +++ b/drivers/soc/qcom/ubwc_config.c @@ -105,6 +105,13 @@ static const struct qcom_ubwc_cfg_data milos_data = { .highest_bank_bit = 15, }; +static const struct qcom_ubwc_cfg_data ubwc_7_0_hbb16 = { + .ubwc_enc_version = UBWC_7_0, + .flags = UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, + .highest_bank_bit = 16, +}; + static const struct of_device_id qcom_ubwc_configs[] __maybe_unused = { { .compatible = "qcom,apq8016", .data = &no_ubwc_data }, { .compatible = "qcom,apq8026", .data = &no_ubwc_data }, @@ -112,8 +119,10 @@ static const struct of_device_id qcom_ubwc_configs[] __maybe_unused = { { .compatible = "qcom,apq8096", .data = &ubwc_1_0_hbb15 }, { .compatible = "qcom,eliza", .data = &ubwc_5_0_hbb15 }, { .compatible = "qcom,glymur", .data = &glymur_data}, + { .compatible = "qcom,hawi", .data = &ubwc_7_0_hbb16 }, { .compatible = "qcom,kaanapali", .data = &ubwc_6_0_hbb16 }, { .compatible = "qcom,mahua", .data = &glymur_data }, + { .compatible = "qcom,maili", .data = &ubwc_7_0_hbb16, }, { .compatible = "qcom,milos", .data = &milos_data }, { .compatible = "qcom,msm8226", .data = &no_ubwc_data }, { .compatible = "qcom,msm8916", .data = &no_ubwc_data }, @@ -127,6 +136,7 @@ static const struct of_device_id qcom_ubwc_configs[] __maybe_unused = { { .compatible = "qcom,msm8976", .data = &no_ubwc_data }, { .compatible = "qcom,msm8996", .data = &ubwc_1_0_hbb15 }, { .compatible = "qcom,msm8998", .data = &ubwc_1_0_hbb15 }, + { .compatible = "qcom,nord", .data = &glymur_data }, { .compatible = "qcom,qcm2290", .data = &ubwc_0_0_hbb15, }, { .compatible = "qcom,qcm6490", .data = &ubwc_3_1_hbb14, }, { .compatible = "qcom,qcs8300", .data = &ubwc_4_0_hbb16, }, diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h index 2cf433f61d5e..b63e4a0b8e54 100644 --- a/include/dt-bindings/arm/qcom,ids.h +++ b/include/dt-bindings/arm/qcom,ids.h @@ -209,6 +209,7 @@ #define QCOM_ID_IPQ8172 397 #define QCOM_ID_IPQ8173 398 #define QCOM_ID_IPQ8174 399 +#define QCOM_ID_SM7250 400 #define QCOM_ID_IPQ6018 402 #define QCOM_ID_IPQ6028 403 #define QCOM_ID_SDM429W 416 diff --git a/include/dt-bindings/clock/qcom,eliza-cambistmclkcc.h b/include/dt-bindings/clock/qcom,eliza-cambistmclkcc.h new file mode 100644 index 000000000000..7b8b285f18d2 --- /dev/null +++ b/include/dt-bindings/clock/qcom,eliza-cambistmclkcc.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_CAM_BIST_MCLK_CC_ELIZA_H +#define _DT_BINDINGS_CLK_QCOM_CAM_BIST_MCLK_CC_ELIZA_H + +/* CAM_BIST_MCLK_CC clocks */ +#define CAM_BIST_MCLK_CC_MCLK0_CLK 0 +#define CAM_BIST_MCLK_CC_MCLK0_CLK_SRC 1 +#define CAM_BIST_MCLK_CC_MCLK1_CLK 2 +#define CAM_BIST_MCLK_CC_MCLK1_CLK_SRC 3 +#define CAM_BIST_MCLK_CC_MCLK2_CLK 4 +#define CAM_BIST_MCLK_CC_MCLK2_CLK_SRC 5 +#define CAM_BIST_MCLK_CC_MCLK3_CLK 6 +#define CAM_BIST_MCLK_CC_MCLK3_CLK_SRC 7 +#define CAM_BIST_MCLK_CC_MCLK4_CLK 8 +#define CAM_BIST_MCLK_CC_MCLK4_CLK_SRC 9 +#define CAM_BIST_MCLK_CC_MCLK5_CLK 10 +#define CAM_BIST_MCLK_CC_MCLK5_CLK_SRC 11 +#define CAM_BIST_MCLK_CC_MCLK6_CLK 12 +#define CAM_BIST_MCLK_CC_MCLK6_CLK_SRC 13 +#define CAM_BIST_MCLK_CC_MCLK7_CLK 14 +#define CAM_BIST_MCLK_CC_MCLK7_CLK_SRC 15 +#define CAM_BIST_MCLK_CC_PLL0 16 +#define CAM_BIST_MCLK_CC_PLL_TEST_CLK 17 +#define CAM_BIST_MCLK_CC_PLL_TEST_DIV_CLK_SRC 18 +#define CAM_BIST_MCLK_CC_SLEEP_CLK 19 +#define CAM_BIST_MCLK_CC_SLEEP_CLK_SRC 20 + +#endif diff --git a/include/dt-bindings/clock/qcom,eliza-camcc.h b/include/dt-bindings/clock/qcom,eliza-camcc.h new file mode 100644 index 000000000000..d85ef9777d08 --- /dev/null +++ b/include/dt-bindings/clock/qcom,eliza-camcc.h @@ -0,0 +1,151 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_ELIZA_H +#define _DT_BINDINGS_CLK_QCOM_CAM_CC_ELIZA_H + +/* CAM_CC clocks */ +#define CAM_CC_CAM_TOP_AHB_CLK 0 +#define CAM_CC_CAM_TOP_FAST_AHB_CLK 1 +#define CAM_CC_CAMNOC_DCD_XO_CLK 2 +#define CAM_CC_CAMNOC_NRT_AXI_CLK 3 +#define CAM_CC_CAMNOC_NRT_CRE_CLK 4 +#define CAM_CC_CAMNOC_NRT_IPE_NPS_CLK 5 +#define CAM_CC_CAMNOC_NRT_OFE_ANCHOR_CLK 6 +#define CAM_CC_CAMNOC_NRT_OFE_HDR_CLK 7 +#define CAM_CC_CAMNOC_NRT_OFE_MAIN_CLK 8 +#define CAM_CC_CAMNOC_RT_AXI_CLK 9 +#define CAM_CC_CAMNOC_RT_AXI_CLK_SRC 10 +#define CAM_CC_CAMNOC_RT_IFE_LITE_CLK 11 +#define CAM_CC_CAMNOC_RT_TFE_0_BAYER_CLK 12 +#define CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK 13 +#define CAM_CC_CAMNOC_RT_TFE_1_BAYER_CLK 14 +#define CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK 15 +#define CAM_CC_CAMNOC_RT_TFE_2_BAYER_CLK 16 +#define CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK 17 +#define CAM_CC_CAMNOC_XO_CLK 18 +#define CAM_CC_CCI_0_CLK 19 +#define CAM_CC_CCI_0_CLK_SRC 20 +#define CAM_CC_CCI_1_CLK 21 +#define CAM_CC_CCI_1_CLK_SRC 22 +#define CAM_CC_CCI_2_CLK 23 +#define CAM_CC_CCI_2_CLK_SRC 24 +#define CAM_CC_CORE_AHB_CLK 25 +#define CAM_CC_CPHY_RX_CLK_SRC 26 +#define CAM_CC_CRE_AHB_CLK 27 +#define CAM_CC_CRE_CLK 28 +#define CAM_CC_CRE_CLK_SRC 29 +#define CAM_CC_CSI0PHYTIMER_CLK 30 +#define CAM_CC_CSI0PHYTIMER_CLK_SRC 31 +#define CAM_CC_CSI1PHYTIMER_CLK 32 +#define CAM_CC_CSI1PHYTIMER_CLK_SRC 33 +#define CAM_CC_CSI2PHYTIMER_CLK 34 +#define CAM_CC_CSI2PHYTIMER_CLK_SRC 35 +#define CAM_CC_CSI3PHYTIMER_CLK 36 +#define CAM_CC_CSI3PHYTIMER_CLK_SRC 37 +#define CAM_CC_CSI4PHYTIMER_CLK 38 +#define CAM_CC_CSI4PHYTIMER_CLK_SRC 39 +#define CAM_CC_CSI5PHYTIMER_CLK 40 +#define CAM_CC_CSI5PHYTIMER_CLK_SRC 41 +#define CAM_CC_CSID_CLK 42 +#define CAM_CC_CSID_CLK_SRC 43 +#define CAM_CC_CSID_CSIPHY_RX_CLK 44 +#define CAM_CC_CSIPHY0_CLK 45 +#define CAM_CC_CSIPHY1_CLK 46 +#define CAM_CC_CSIPHY2_CLK 47 +#define CAM_CC_CSIPHY3_CLK 48 +#define CAM_CC_CSIPHY4_CLK 49 +#define CAM_CC_CSIPHY5_CLK 50 +#define CAM_CC_DRV_AHB_CLK 51 +#define CAM_CC_DRV_XO_CLK 52 +#define CAM_CC_FAST_AHB_CLK_SRC 53 +#define CAM_CC_GDSC_CLK 54 +#define CAM_CC_ICP_0_AHB_CLK 55 +#define CAM_CC_ICP_0_CLK 56 +#define CAM_CC_ICP_0_CLK_SRC 57 +#define CAM_CC_ICP_1_AHB_CLK 58 +#define CAM_CC_ICP_1_CLK 59 +#define CAM_CC_ICP_1_CLK_SRC 60 +#define CAM_CC_IFE_LITE_AHB_CLK 61 +#define CAM_CC_IFE_LITE_CLK 62 +#define CAM_CC_IFE_LITE_CLK_SRC 63 +#define CAM_CC_IFE_LITE_CPHY_RX_CLK 64 +#define CAM_CC_IFE_LITE_CSID_CLK 65 +#define CAM_CC_IFE_LITE_CSID_CLK_SRC 66 +#define CAM_CC_IPE_NPS_AHB_CLK 67 +#define CAM_CC_IPE_NPS_CLK 68 +#define CAM_CC_IPE_NPS_CLK_SRC 69 +#define CAM_CC_IPE_NPS_FAST_AHB_CLK 70 +#define CAM_CC_IPE_PPS_CLK 71 +#define CAM_CC_IPE_PPS_FAST_AHB_CLK 72 +#define CAM_CC_JPEG_0_CLK 73 +#define CAM_CC_JPEG_1_CLK 74 +#define CAM_CC_JPEG_CLK_SRC 75 +#define CAM_CC_OFE_AHB_CLK 76 +#define CAM_CC_OFE_ANCHOR_CLK 77 +#define CAM_CC_OFE_ANCHOR_FAST_AHB_CLK 78 +#define CAM_CC_OFE_CLK_SRC 79 +#define CAM_CC_OFE_HDR_CLK 80 +#define CAM_CC_OFE_HDR_FAST_AHB_CLK 81 +#define CAM_CC_OFE_MAIN_CLK 82 +#define CAM_CC_OFE_MAIN_FAST_AHB_CLK 83 +#define CAM_CC_PLL0 84 +#define CAM_CC_PLL0_OUT_EVEN 85 +#define CAM_CC_PLL0_OUT_ODD 86 +#define CAM_CC_PLL1 87 +#define CAM_CC_PLL1_OUT_EVEN 88 +#define CAM_CC_PLL2 89 +#define CAM_CC_PLL2_OUT_EVEN 90 +#define CAM_CC_PLL3 91 +#define CAM_CC_PLL3_OUT_EVEN 92 +#define CAM_CC_PLL4 93 +#define CAM_CC_PLL4_OUT_EVEN 94 +#define CAM_CC_PLL5 95 +#define CAM_CC_PLL5_OUT_EVEN 96 +#define CAM_CC_PLL6 97 +#define CAM_CC_PLL6_OUT_EVEN 98 +#define CAM_CC_PLL6_OUT_ODD 99 +#define CAM_CC_QDSS_DEBUG_CLK 100 +#define CAM_CC_QDSS_DEBUG_CLK_SRC 101 +#define CAM_CC_QDSS_DEBUG_XO_CLK 102 +#define CAM_CC_SLEEP_CLK 103 +#define CAM_CC_SLEEP_CLK_SRC 104 +#define CAM_CC_SLOW_AHB_CLK_SRC 105 +#define CAM_CC_TFE_0_BAYER_CLK 106 +#define CAM_CC_TFE_0_BAYER_FAST_AHB_CLK 107 +#define CAM_CC_TFE_0_CLK_SRC 108 +#define CAM_CC_TFE_0_MAIN_CLK 109 +#define CAM_CC_TFE_0_MAIN_FAST_AHB_CLK 110 +#define CAM_CC_TFE_1_BAYER_CLK 111 +#define CAM_CC_TFE_1_BAYER_FAST_AHB_CLK 112 +#define CAM_CC_TFE_1_CLK_SRC 113 +#define CAM_CC_TFE_1_MAIN_CLK 114 +#define CAM_CC_TFE_1_MAIN_FAST_AHB_CLK 115 +#define CAM_CC_TFE_2_BAYER_CLK 116 +#define CAM_CC_TFE_2_BAYER_FAST_AHB_CLK 117 +#define CAM_CC_TFE_2_CLK_SRC 118 +#define CAM_CC_TFE_2_MAIN_CLK 119 +#define CAM_CC_TFE_2_MAIN_FAST_AHB_CLK 120 +#define CAM_CC_XO_CLK_SRC 121 + +/* CAM_CC power domains */ +#define CAM_CC_IPE_0_GDSC 0 +#define CAM_CC_OFE_GDSC 1 +#define CAM_CC_TFE_0_GDSC 2 +#define CAM_CC_TFE_1_GDSC 3 +#define CAM_CC_TFE_2_GDSC 4 +#define CAM_CC_TITAN_TOP_GDSC 5 + +/* CAM_CC resets */ +#define CAM_CC_DRV_BCR 0 +#define CAM_CC_ICP_BCR 1 +#define CAM_CC_IPE_0_BCR 2 +#define CAM_CC_OFE_BCR 3 +#define CAM_CC_QDSS_DEBUG_BCR 4 +#define CAM_CC_TFE_0_BCR 5 +#define CAM_CC_TFE_1_BCR 6 +#define CAM_CC_TFE_2_BCR 7 + +#endif diff --git a/include/dt-bindings/clock/qcom,eliza-gpucc.h b/include/dt-bindings/clock/qcom,eliza-gpucc.h new file mode 100644 index 000000000000..c3d9b7827325 --- /dev/null +++ b/include/dt-bindings/clock/qcom,eliza-gpucc.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_ELIZA_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_ELIZA_H + +/* GPU_CC clocks */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CRC_AHB_CLK 1 +#define GPU_CC_CX_ACCU_SHIFT_CLK 2 +#define GPU_CC_CX_FF_CLK 3 +#define GPU_CC_CX_GMU_CLK 4 +#define GPU_CC_CXO_AON_CLK 5 +#define GPU_CC_CXO_CLK 6 +#define GPU_CC_DEMET_CLK 7 +#define GPU_CC_DEMET_DIV_CLK_SRC 8 +#define GPU_CC_FF_CLK_SRC 9 +#define GPU_CC_FREQ_MEASURE_CLK 10 +#define GPU_CC_GMU_CLK_SRC 11 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 12 +#define GPU_CC_HUB_AON_CLK 13 +#define GPU_CC_HUB_CLK_SRC 14 +#define GPU_CC_HUB_CX_INT_CLK 15 +#define GPU_CC_MEMNOC_GFX_CLK 16 +#define GPU_CC_MND1X_0_GFX3D_CLK 17 +#define GPU_CC_MND1X_1_GFX3D_CLK 18 +#define GPU_CC_PLL0 19 +#define GPU_CC_PLL1 20 +#define GPU_CC_SLEEP_CLK 21 +#define GPU_CC_XO_CLK_SRC 22 +#define GPU_CC_XO_DIV_CLK_SRC 23 + +/* GPU_CC power domains */ +#define GPU_CC_CX_GDSC 0 +#define GPU_CC_GX_GDSC 1 + +/* GPU_CC resets */ +#define GPU_CC_ACD_BCR 0 +#define GPU_CC_CB_BCR 1 +#define GPU_CC_CX_BCR 2 +#define GPU_CC_FAST_HUB_BCR 3 +#define GPU_CC_FF_BCR 4 +#define GPU_CC_GFX3D_AON_BCR 5 +#define GPU_CC_GMU_BCR 6 +#define GPU_CC_GX_BCR 7 +#define GPU_CC_RBCPR_BCR 8 +#define GPU_CC_XO_BCR 9 + +#endif diff --git a/include/dt-bindings/clock/qcom,eliza-videocc.h b/include/dt-bindings/clock/qcom,eliza-videocc.h new file mode 100644 index 000000000000..1e922250a7fa --- /dev/null +++ b/include/dt-bindings/clock/qcom,eliza-videocc.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_ELIZA_H +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_ELIZA_H + +/* VIDEO_CC clocks */ +#define VIDEO_CC_AHB_CLK 0 +#define VIDEO_CC_AHB_CLK_SRC 1 +#define VIDEO_CC_MVS0_CLK 2 +#define VIDEO_CC_MVS0_CLK_SRC 3 +#define VIDEO_CC_MVS0_DIV_CLK_SRC 4 +#define VIDEO_CC_MVS0_SHIFT_CLK 5 +#define VIDEO_CC_MVS0C_CLK 6 +#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 7 +#define VIDEO_CC_MVS0C_SHIFT_CLK 8 +#define VIDEO_CC_PLL0 9 +#define VIDEO_CC_SLEEP_CLK 10 +#define VIDEO_CC_SLEEP_CLK_SRC 11 +#define VIDEO_CC_XO_CLK 12 +#define VIDEO_CC_XO_CLK_SRC 13 + +/* VIDEO_CC power domains */ +#define VIDEO_CC_MVS0_GDSC 0 +#define VIDEO_CC_MVS0C_GDSC 1 + +/* VIDEO_CC resets */ +#define VIDEO_CC_INTERFACE_BCR 0 +#define VIDEO_CC_MVS0_CLK_ARES 1 +#define VIDEO_CC_MVS0_BCR 2 +#define VIDEO_CC_MVS0C_CLK_ARES 3 +#define VIDEO_CC_MVS0C_BCR 4 +#define VIDEO_CC_XO_CLK_ARES 5 + +#endif diff --git a/include/linux/device-id/apr.h b/include/linux/device-id/apr.h deleted file mode 100644 index f282608ea018..000000000000 --- a/include/linux/device-id/apr.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef LINUX_DEVICE_ID_APR_H -#define LINUX_DEVICE_ID_APR_H - -#ifdef __KERNEL__ -#include <linux/types.h> -typedef unsigned long kernel_ulong_t; -#endif - -#define APR_NAME_SIZE 32 -#define APR_MODULE_PREFIX "apr:" - -struct apr_device_id { - char name[APR_NAME_SIZE]; - __u32 domain_id; - __u32 svc_id; - __u32 svc_version; - kernel_ulong_t driver_data; /* Data private to the driver */ -}; - -#endif /* ifndef LINUX_DEVICE_ID_APR_H */ diff --git a/include/linux/mod_devicetable.h b/include/linux/mod_devicetable.h index a397213bedac..4fe1cd64292f 100644 --- a/include/linux/mod_devicetable.h +++ b/include/linux/mod_devicetable.h @@ -15,7 +15,6 @@ #include "device-id/acpi.h" #include "device-id/amba.h" #include "device-id/ap.h" -#include "device-id/apr.h" #include "device-id/auxiliary.h" #include "device-id/bcma.h" #include "device-id/ccw.h" diff --git a/include/linux/soc/qcom/apr.h b/include/linux/soc/qcom/apr.h index 909e84f84e0c..2e4231092088 100644 --- a/include/linux/soc/qcom/apr.h +++ b/include/linux/soc/qcom/apr.h @@ -5,7 +5,6 @@ #include <linux/spinlock.h> #include <linux/device.h> -#include <linux/device-id/apr.h> #include <dt-bindings/soc/qcom,apr.h> #include <dt-bindings/soc/qcom,gpr.h> @@ -135,6 +134,8 @@ struct pkt_router_svc { typedef struct pkt_router_svc gpr_port_t; +#define APR_NAME_SIZE 32 + struct apr_device { struct device dev; uint16_t svc_id; @@ -158,7 +159,6 @@ struct apr_driver { const struct apr_resp_pkt *d); gpr_port_cb gpr_callback; struct device_driver driver; - const struct apr_device_id *id_table; }; typedef struct apr_driver gpr_driver_t; diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h index f3ed63e475ab..1ccc429401e8 100644 --- a/include/linux/soc/qcom/llcc-qcom.h +++ b/include/linux/soc/qcom/llcc-qcom.h @@ -86,6 +86,10 @@ #define LLCC_CPUSS_HEU 94 #define LLCC_PCIE_TCU 97 #define LLCC_MDM_PNG_FIXED 100 +#define LLCC_PPE_RXDESC 101 +#define LLCC_PPE_RXFILL 102 +#define LLCC_WLAN_5G 103 +#define LLCC_WLAN_6G 104 /** * struct llcc_slice_desc - Cache slice descriptor diff --git a/include/linux/soc/qcom/ubwc.h b/include/linux/soc/qcom/ubwc.h index f3a70360b177..b09ae05cbeae 100644 --- a/include/linux/soc/qcom/ubwc.h +++ b/include/linux/soc/qcom/ubwc.h @@ -36,6 +36,7 @@ struct qcom_ubwc_cfg_data { #define UBWC_4_3 0x40030000 #define UBWC_5_0 0x50000000 #define UBWC_6_0 0x60000000 +#define UBWC_7_0 0x70000000 #if IS_ENABLED(CONFIG_QCOM_UBWC_CONFIG) const struct qcom_ubwc_cfg_data *qcom_ubwc_config_get_data(void); @@ -108,6 +109,8 @@ static inline u32 qcom_ubwc_swizzle(const struct qcom_ubwc_cfg_data *cfg) static inline u32 qcom_ubwc_version_tag(const struct qcom_ubwc_cfg_data *cfg) { + if (cfg->ubwc_enc_version >= UBWC_7_0) + return 6; if (cfg->ubwc_enc_version >= UBWC_6_0) return 5; if (cfg->ubwc_enc_version >= UBWC_5_0) |