diff options
| author | Mukul Joshi <mukul.joshi@amd.com> | 2025-09-15 10:48:04 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2026-01-05 16:59:56 -0500 |
| commit | 3af6302d8c2ee37b9a791222947052ee2dfdea5b (patch) | |
| tree | 4f1d2fde688c27445de1b6c7de5faded107f0d58 | |
| parent | 258cc2b687bf67f7872707061158aefddbc449e1 (diff) | |
drm/amdgpu: Update TCP Control register on GFX 12.1
Update TCP CNTL register to disable some features not supported
on GFX 12.1.
Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: Alex Sierra <alex.sierra@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c index 7d4b241fc3a4..59bbb9a5d298 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c @@ -2668,6 +2668,17 @@ static void gfx_v12_1_xcc_disable_early_write_ack(struct amdgpu_device *adev, WREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_CNTL3, data); } +static void gfx_v12_1_xcc_disable_tcp_spill_cache(struct amdgpu_device *adev, + int xcc_id) +{ + uint32_t data; + + data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_CNTL); + data = REG_SET_FIELD(data, TCP_CNTL, TCP_SPILL_CACHE_DISABLE, 0x1); + + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_CNTL, data); +} + static void gfx_v12_1_init_golden_registers(struct amdgpu_device *adev) { int i; @@ -2677,6 +2688,7 @@ static void gfx_v12_1_init_golden_registers(struct amdgpu_device *adev) gfx_v12_1_xcc_enable_atomics(adev, i); gfx_v12_1_xcc_setup_tcp_thrashing_ctrl(adev, i); gfx_v12_1_xcc_disable_early_write_ack(adev, i); + gfx_v12_1_xcc_disable_tcp_spill_cache(adev, i); } } |