diff options
| author | Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> | 2026-09-17 17:24:25 +0530 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2026-09-27 21:26:29 -0500 |
| commit | 450a0bfdb1b66da50ef98eefe1ff45b7be21e9a7 (patch) | |
| tree | 2bd99cea25b3384c6adb05fc5db1ab9c462042c6 | |
| parent | e622c5d6553b8a83af04115c87f006406baf2675 (diff) | |
arm64: dts: qcom: sa8540p-ride: Fix PCIe WAKE# GPIO polarity
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Link: https://patch.msgid.link/20260917-root_port-v2-17-0d627d0856d5@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts index c72faaa0ae7a..e85d78ecac2e 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts @@ -374,7 +374,7 @@ &pcie2a_port0 { reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 145 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; }; &pcie2a_phy { @@ -397,7 +397,7 @@ &pcie3a_port0 { reset-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 56 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 56 GPIO_ACTIVE_LOW>; }; &pcie3a_phy { |