diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2026-04-23 08:57:24 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2026-04-23 08:57:24 -0700 |
| commit | 507bd4b66c85d5b65696150cc16d31ac0b2ab151 (patch) | |
| tree | 115dd98721d30768168d3c7515d57a8fe8d67a11 | |
| parent | 8841842cc9be68e0f670323e697c9b3214831d6a (diff) | |
| parent | dd5dc1917473f398949b95f6b77c60d4d8eb1d97 (diff) | |
Merge tag 'soc-late-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull more SoC updates from Arnd Bergmann:
"These are the contents that arrived during the easter vacation and
didn't make it into the last 7.0 bugfixes or the first set of branches
for the merge window. Aside from a reset controller bugfix and an
update to the MAINTAINERS entry, this is all devicetree changes.
The Marvell devicetree updates contain the usual minor updates and
bugfixes, along with a two larger but trivial patches to drop unused
dtsi files, the single broadcom fix addresses a build time warning
introduced during the merge window.
The freescale, amlogic, and apple changes missed the last fixes branch
for 7.0"
* tag 'soc-late-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (38 commits)
arm64: dts: meson-gxl-p230: fix ethernet PHY interrupt number
arm64: dts: amlogic: meson-axg: Add missing cache information to cpu0
arm64: dts: amlogic: t7: khadas-vim4: fix board model name
arm64: dts: amlogic: Fix GIC register ranges for Amlogic T7
arm64: dts: amlogic: t7: khadas-vim4: fix memory layout for 8GB RAM
arm64: dts: amlogic: s6: Drop CPU masks from GICv3 PPI interrupts
Documentation/process: maintainer-soc: Document purpose of defconfigs
Documentation/process: maintainer-soc: Trim from trivial ask-DT
ARM: dts: bcm4709: fix bus range assignment
arm64: dts: apple: Fix spelling error
dt-bindings: Update Sasha Finkelstein's email address
mailmap: Update Sasha Finkelstein's email address
arm64: dts: marvell: armada-37xx: swap PHYs' order in USB3 controller node
arm64: dts: marvell: armada-37xx: use 'usb2-phy' in USB3 controller's phy-names
arm64: dts: imx8mm-tqma8mqml: Correct PAD settings for PMIC_nINT
arm64: dts: imx8mn-tqma8mqnl: Correct PAD settings for PMIC_nINT
arm64: dts: imx8mm-emtop-som: Correct PAD settings for PMIC_nINT
reset: amlogic: t7: Fix null reset ops
arm64: dts: imx8mp-data-modul-edm-sbc: Correct PAD settings for PMIC_nINT
arm64: dts: imx8mp-dhcom-som: Correct PAD settings for PMIC_nINT
...
43 files changed, 81 insertions, 314 deletions
@@ -743,6 +743,7 @@ Sarangdhar Joshi <spjoshi@codeaurora.org> Saravana Kannan <saravanak@kernel.org> <skannan@codeaurora.org> Saravana Kannan <saravanak@kernel.org> <saravanak@google.com> Sascha Hauer <s.hauer@pengutronix.de> +Sasha Finkelstein <k@chaosmail.tech> <fnkl.kernel@gmail.com> Sahitya Tummala <quic_stummala@quicinc.com> <stummala@codeaurora.org> Sathishkumar Muruganandam <quic_murugana@quicinc.com> <murugana@codeaurora.org> Satya Priya <quic_skakitap@quicinc.com> <quic_c_skakit@quicinc.com> <skakit@codeaurora.org> diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml b/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml index 4bc7454a5d3a..7e77310da626 100644 --- a/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml +++ b/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml @@ -21,6 +21,17 @@ properties: - const: marvell,armada-ap806-dual - const: marvell,armada-ap806 + - description: + Falcon (DB-98CX85x0) Development board COM Express Carrier plus + Armada 7020 SoC COM Express CPU module + items: + - const: marvell,armada7020-falcon-carrier + - const: marvell,db-falcon-carrier + - const: marvell,armada7020-cpu-module + - const: marvell,armada7020 + - const: marvell,armada-ap806-dual + - const: marvell,armada-ap806 + - description: Armada 7040 SoC items: - enum: diff --git a/Documentation/devicetree/bindings/display/apple,h7-display-pipe-mipi.yaml b/Documentation/devicetree/bindings/display/apple,h7-display-pipe-mipi.yaml index 5e6da66499a5..d7c822df8a94 100644 --- a/Documentation/devicetree/bindings/display/apple,h7-display-pipe-mipi.yaml +++ b/Documentation/devicetree/bindings/display/apple,h7-display-pipe-mipi.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Apple pre-DCP display controller MIPI interface maintainers: - - Sasha Finkelstein <fnkl.kernel@gmail.com> + - Sasha Finkelstein <k@chaosmail.tech> description: The MIPI controller part of the pre-DCP Apple display controller diff --git a/Documentation/devicetree/bindings/display/apple,h7-display-pipe.yaml b/Documentation/devicetree/bindings/display/apple,h7-display-pipe.yaml index 102fb1804c0c..571fa32db2cf 100644 --- a/Documentation/devicetree/bindings/display/apple,h7-display-pipe.yaml +++ b/Documentation/devicetree/bindings/display/apple,h7-display-pipe.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Apple pre-DCP display controller maintainers: - - Sasha Finkelstein <fnkl.kernel@gmail.com> + - Sasha Finkelstein <k@chaosmail.tech> description: A secondary display controller used to drive the "touchbar" on diff --git a/Documentation/devicetree/bindings/display/panel/apple,summit.yaml b/Documentation/devicetree/bindings/display/panel/apple,summit.yaml index f081755325e9..1c1ba59467f3 100644 --- a/Documentation/devicetree/bindings/display/panel/apple,summit.yaml +++ b/Documentation/devicetree/bindings/display/panel/apple,summit.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Apple "Summit" display panel maintainers: - - Sasha Finkelstein <fnkl.kernel@gmail.com> + - Sasha Finkelstein <k@chaosmail.tech> description: An OLED panel used as a touchbar on certain Apple laptops. diff --git a/Documentation/devicetree/bindings/gpu/apple,agx.yaml b/Documentation/devicetree/bindings/gpu/apple,agx.yaml index 05af942ad174..59989d8bd1cb 100644 --- a/Documentation/devicetree/bindings/gpu/apple,agx.yaml +++ b/Documentation/devicetree/bindings/gpu/apple,agx.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Apple SoC GPU maintainers: - - Sasha Finkelstein <fnkl.kernel@gmail.com> + - Sasha Finkelstein <k@chaosmail.tech> properties: compatible: diff --git a/Documentation/devicetree/bindings/input/touchscreen/apple,z2-multitouch.yaml b/Documentation/devicetree/bindings/input/touchscreen/apple,z2-multitouch.yaml index 402ca6bffd34..44158e89e818 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/apple,z2-multitouch.yaml +++ b/Documentation/devicetree/bindings/input/touchscreen/apple,z2-multitouch.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Apple touchscreens attached using the Z2 protocol maintainers: - - Sasha Finkelstein <fnkl.kernel@gmail.com> + - Sasha Finkelstein <k@chaosmail.tech> description: A series of touschscreen controllers used in Apple products diff --git a/Documentation/devicetree/bindings/nvmem/apple,spmi-nvmem.yaml b/Documentation/devicetree/bindings/nvmem/apple,spmi-nvmem.yaml index 80b5a6cdcec9..4ca75ed07a54 100644 --- a/Documentation/devicetree/bindings/nvmem/apple,spmi-nvmem.yaml +++ b/Documentation/devicetree/bindings/nvmem/apple,spmi-nvmem.yaml @@ -9,7 +9,7 @@ title: Apple SPMI NVMEM description: Exports a series of SPMI registers as NVMEM cells maintainers: - - Sasha Finkelstein <fnkl.kernel@gmail.com> + - Sasha Finkelstein <k@chaosmail.tech> allOf: - $ref: nvmem.yaml# diff --git a/Documentation/devicetree/bindings/pwm/apple,s5l-fpwm.yaml b/Documentation/devicetree/bindings/pwm/apple,s5l-fpwm.yaml index 04519b0c581d..d8f4f9ffe884 100644 --- a/Documentation/devicetree/bindings/pwm/apple,s5l-fpwm.yaml +++ b/Documentation/devicetree/bindings/pwm/apple,s5l-fpwm.yaml @@ -8,7 +8,7 @@ title: Apple FPWM controller maintainers: - asahi@lists.linux.dev - - Sasha Finkelstein <fnkl.kernel@gmail.com> + - Sasha Finkelstein <k@chaosmail.tech> description: PWM controller used for keyboard backlight on ARM Macs diff --git a/Documentation/devicetree/bindings/spmi/apple,spmi.yaml b/Documentation/devicetree/bindings/spmi/apple,spmi.yaml index ba524f1eb704..3e5b14bc8c31 100644 --- a/Documentation/devicetree/bindings/spmi/apple,spmi.yaml +++ b/Documentation/devicetree/bindings/spmi/apple,spmi.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Apple SPMI controller maintainers: - - Sasha Finkelstein <fnkl.kernel@gmail.com> + - Sasha Finkelstein <k@chaosmail.tech> description: A SPMI controller present on most Apple SoCs diff --git a/Documentation/process/maintainer-soc.rst b/Documentation/process/maintainer-soc.rst index 7d6bad989ad8..a3a90a7d4c68 100644 --- a/Documentation/process/maintainer-soc.rst +++ b/Documentation/process/maintainer-soc.rst @@ -169,8 +169,6 @@ more information on the validation of devicetrees. For new platforms, or additions to existing ones, ``make dtbs_check`` should not add any new warnings. For RISC-V and Samsung SoC, ``make dtbs_check W=1`` is required to not add any new warnings. -If in any doubt about a devicetree change, reach out to the devicetree -maintainers. Branches and Pull Requests ~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -209,3 +207,13 @@ The subject line of a pull request should begin with "[GIT PULL]" and made using a signed tag, rather than a branch. This tag should contain a short description summarising the changes in the pull request. For more detail on sending pull requests, please see Documentation/maintainer/pull-requests.rst. + +Defconfigs purpose +~~~~~~~~~~~~~~~~~~ + +Defconfigs are primarily used by the kernel developers, because distros have +their own configs. A change adding new CONFIG options to a defconfig should +explain why the kernel developers in general would want such option, e.g. by +providing a name of an upstream-supported machine/board using that new option. +This implies that enabling options in defconfig for non-upstream machines shall +not be accepted. diff --git a/MAINTAINERS b/MAINTAINERS index 3ad4d0a132c9..d885cf5ccc34 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -8706,7 +8706,7 @@ F: include/linux/host1x.h F: include/uapi/drm/tegra_drm.h DRM DRIVERS FOR PRE-DCP APPLE DISPLAY OUTPUT -M: Sasha Finkelstein <fnkl.kernel@gmail.com> +M: Sasha Finkelstein <k@chaosmail.tech> R: Janne Grunau <j@jannau.net> L: dri-devel@lists.freedesktop.org L: asahi@lists.linux.dev diff --git a/arch/arm/boot/dts/broadcom/bcm4709-netgear-r8000.dts b/arch/arm/boot/dts/broadcom/bcm4709-netgear-r8000.dts index d170c71cbd76..e85693fba16a 100644 --- a/arch/arm/boot/dts/broadcom/bcm4709-netgear-r8000.dts +++ b/arch/arm/boot/dts/broadcom/bcm4709-netgear-r8000.dts @@ -139,7 +139,6 @@ pcie@0,0 { device_type = "pci"; reg = <0x0000 0 0 0 0>; - bus-range = <0x01 0xff>; #address-cells = <3>; #size-cells = <2>; diff --git a/arch/arm/boot/dts/marvell/armada-380.dtsi b/arch/arm/boot/dts/marvell/armada-380.dtsi deleted file mode 100644 index e94f22b0e9b5..000000000000 --- a/arch/arm/boot/dts/marvell/armada-380.dtsi +++ /dev/null @@ -1,148 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Marvell Armada 380 SoC. - * - * Copyright (C) 2014 Marvell - * - * Lior Amsalem <alior@marvell.com> - * Gregory CLEMENT <gregory.clement@free-electrons.com> - * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> - */ - -#include "armada-38x.dtsi" - -/ { - model = "Marvell Armada 380 family SoC"; - compatible = "marvell,armada380"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "marvell,armada-380-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - }; - }; - - soc { - internal-regs { - pinctrl@18000 { - compatible = "marvell,mv88f6810-pinctrl"; - }; - }; - - pcie { - compatible = "marvell,armada-370-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - msi-parent = <&mpic>; - bus-range = <0x00 0xff>; - - ranges = - <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 - 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 - 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 - 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 - 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ - 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */ - 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */ - 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */ - 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */>; - - /* x1 port */ - pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie1_intc 0>, - <0 0 0 2 &pcie1_intc 1>, - <0 0 0 3 &pcie1_intc 2>, - <0 0 0 4 &pcie1_intc 3>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 8>; - status = "disabled"; - - pcie1_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - /* x1 port */ - pcie@2,0 { - device_type = "pci"; - assigned-addresses = <0x82001000 0 0x40000 0 0x2000>; - reg = <0x1000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 - 0x81000000 0 0 0x81000000 0x2 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie2_intc 0>, - <0 0 0 2 &pcie2_intc 1>, - <0 0 0 3 &pcie2_intc 2>, - <0 0 0 4 &pcie2_intc 3>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 5>; - status = "disabled"; - - pcie2_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - /* x1 port */ - pcie@3,0 { - device_type = "pci"; - assigned-addresses = <0x82001800 0 0x44000 0 0x2000>; - reg = <0x1800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 - 0x81000000 0 0 0x81000000 0x3 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie3_intc 0>, - <0 0 0 2 &pcie3_intc 1>, - <0 0 0 3 &pcie3_intc 2>, - <0 0 0 4 &pcie3_intc 3>; - marvell,pcie-port = <2>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 6>; - status = "disabled"; - - pcie3_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi index 8ef631939033..ab3acef2b147 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi @@ -53,10 +53,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; }; psci { @@ -84,7 +84,7 @@ interrupt-controller; reg = <0x0 0xff200000 0 0x10000>, <0x0 0xff240000 0 0x80000>; - interrupts = <GIC_PPI 9 0xf04>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; }; apb: bus@fe000000 { diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts b/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts index fffdab96b12e..f4c953034be3 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts @@ -8,7 +8,7 @@ #include "amlogic-t7.dtsi" / { - model = "Khadas vim4"; + model = "Khadas VIM4"; compatible = "khadas,vim4", "amlogic,a311d2", "amlogic,t7"; aliases { @@ -17,7 +17,9 @@ memory@0 { device_type = "memory"; - reg = <0x0 0x0 0x2 0x0>; /* 8 GB */ + reg = <0x0 0x0 0x0 0xE0000000 + 0x1 0x0 0x0 0xE0000000 + 0x2 0x0 0x0 0x40000000>; /* 8 GB */ }; reserved-memory { diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi index 6510068bcff9..d523cbc0ed22 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi @@ -213,7 +213,9 @@ #address-cells = <0>; interrupt-controller; reg = <0x0 0xfff01000 0 0x1000>, - <0x0 0xfff02000 0 0x0100>; + <0x0 0xfff02000 0 0x2000>, + <0x0 0xfff04000 0 0x2000>, + <0x0 0xfff06000 0 0x2000>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index cc72491eaf6f..f1f53fd98ae2 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -72,6 +72,12 @@ compatible = "arm,cortex-a53"; reg = <0x0 0x0>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; clocks = <&scpi_dvfs 0>; dynamic-power-coefficient = <140>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts index 7dffeb5931c9..701de57ff0f3 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts @@ -84,7 +84,8 @@ reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; interrupt-parent = <&gpio_intc>; - interrupts = <29 IRQ_TYPE_LEVEL_LOW>; + /* MAC_INTR on GPIOZ_15 */ + interrupts = <25 IRQ_TYPE_LEVEL_LOW>; eee-broken-1000t; }; }; diff --git a/arch/arm64/boot/dts/apple/spi1-nvram.dtsi b/arch/arm64/boot/dts/apple/spi1-nvram.dtsi index 9740fbf200f0..d2720b307774 100644 --- a/arch/arm64/boot/dts/apple/spi1-nvram.dtsi +++ b/arch/arm64/boot/dts/apple/spi1-nvram.dtsi @@ -2,7 +2,7 @@ // // Devicetree include for common spi-nor nvram flash. // -// Apple uses a consistent configiguration for the nvram on all known M1* and +// Apple uses a consistent configuration for the nvram on all known M1* and // M2* devices. // // Copyright The Asahi Linux Contributors diff --git a/arch/arm64/boot/dts/freescale/imx8mm-emtop-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-emtop-som.dtsi index 67d22d3768aa..507d1824d99d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-emtop-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-emtop-som.dtsi @@ -60,7 +60,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pmic>; interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_EDGE_RISING>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; regulators { buck1: BUCK1 { @@ -194,7 +194,7 @@ pinctrl_pmic: emtop-pmic-grp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi index 29b298af0d73..1b5ba3c47164 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi @@ -292,7 +292,7 @@ }; pinctrl_pmic: pmicgrp { - fsl,pins = <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x94>; + fsl,pins = <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x1d4>; }; pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { diff --git a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi index 31a3ca137e63..48a687926aa1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi @@ -283,7 +283,7 @@ }; pinctrl_pmic: pmicgrp { - fsl,pins = <MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x84>; + fsl,pins = <MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x1c4>; }; pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { diff --git a/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3a-som-v1.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3a-som-v1.dtsi index f654d866e58c..e7666e54310b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3a-som-v1.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3a-som-v1.dtsi @@ -903,7 +903,7 @@ pinctrl_pmic: aristainetos3-pmic-grp { fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts index 7e46537a22a0..cb28cf1cdd23 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts @@ -1001,7 +1001,7 @@ pinctrl_pmic: pmic-grp { fsl,pins = < /* PMIC_nINT */ - MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x40000090 + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts b/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts index 9422beee30b2..201cf7f5eb0e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts @@ -440,7 +440,7 @@ pinctrl_pmic: pmicirqgrp { fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts b/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts index 04619a722906..1471ff361b54 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts @@ -499,7 +499,7 @@ pinctrl_pmic: pmicgrp { fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a.dtsi index 91094c227744..b31e8fe95ca7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a.dtsi @@ -241,7 +241,7 @@ pinctrl_pmic: pmicgrp { fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi index f8303b7e2bd2..0a6a60670f76 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi @@ -989,7 +989,7 @@ pinctrl_pmic: dhcom-pmic-grp { fsl,pins = < /* PMIC_nINT */ - MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x40000090 + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-edm-g.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-edm-g.dtsi index 3f1e0837f349..91b87a7248dd 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-edm-g.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-edm-g.dtsi @@ -563,7 +563,7 @@ pinctrl_pmic: pmicirqgrp { fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi index a6319824ea2e..69558ffefa9a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi @@ -132,7 +132,7 @@ pinctrl_pmic: pmicgrp { fsl,pins = < - MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x41 + MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x1c0 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-navqp.dts b/arch/arm64/boot/dts/freescale/imx8mp-navqp.dts index 4a4f7c1adc23..9dedb9f11145 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-navqp.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-navqp.dts @@ -356,7 +356,7 @@ pinctrl_pmic: pmicgrp { fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-som.dtsi index f658309612ef..8465b36d440a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-som.dtsi @@ -296,7 +296,7 @@ pinctrl_pmic: pmicirqgrp { fsl,pins = < - MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x41 + MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x1c0 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi index 3cdb0bc0ab72..c3f7daa773ea 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi @@ -174,7 +174,7 @@ pinctrl-0 = <&pmic_pins>; pinctrl-names = "default"; interrupt-parent = <&gpio1>; - interrupts = <3 GPIO_ACTIVE_LOW>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; nxp,i2c-lt-enable; regulators { @@ -417,7 +417,7 @@ pmic_pins: pinctrl-pmic-grp { fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-ultra-mach-sbc.dts b/arch/arm64/boot/dts/freescale/imx8mp-ultra-mach-sbc.dts index 9ecec1a41878..3e6f9c88cc20 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-ultra-mach-sbc.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-ultra-mach-sbc.dts @@ -275,7 +275,7 @@ reg = <0x25>; pinctrl-0 = <&pinctrl_pmic>; interrupt-parent = <&gpio1>; - interrupts = <3 GPIO_ACTIVE_LOW>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; /* * i.MX 8M Plus Data Sheet for Consumer Products @@ -739,7 +739,7 @@ pinctrl_pmic: pmic-grp { fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x40 /* #PMIC_INT */ + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 /* #PMIC_INT */ >; }; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-atlas-v5.dts b/arch/arm64/boot/dts/marvell/armada-3720-atlas-v5.dts index 070d10a705bb..a313d5687789 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-atlas-v5.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-atlas-v5.dts @@ -82,7 +82,6 @@ mmc-ddr-1_8v; mmc-hs400-1_8v; sd-uhs-sdr104; - marvell,xenon-emmc; marvell,xenon-tun-count = <9>; marvell,pad-type = "fixed-1-8v"; vqmmc-supply = <&vsdc_reg>; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi index fed2dcecb323..37e16fb3a383 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi @@ -78,7 +78,6 @@ bus-width = <8>; mmc-ddr-1_8v; mmc-hs400-1_8v; - marvell,xenon-emmc; marvell,xenon-tun-count = <9>; marvell,pad-type = "fixed-1-8v"; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dtsi b/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dtsi index 242820845707..12deacb741cc 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dtsi @@ -15,6 +15,11 @@ #include "armada-372x.dtsi" / { + aliases { + ethernet0 = ð0; + ethernet1 = ð1; + }; + chosen { stdout-path = "serial0:115200n8"; }; @@ -156,7 +161,7 @@ &usb3 { status = "okay"; phys = <&usb2_utmi_otg_phy>; - phy-names = "usb2-utmi-otg-phy"; + phy-names = "usb2-phy"; }; &uart0 { diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index 87f9367aec12..360fc24fdde2 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -369,11 +369,10 @@ compatible = "marvell,armada3700-xhci", "generic-xhci"; reg = <0x58000 0x4000>; - marvell,usb-misc-reg = <&usb32_syscon>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; clocks = <&sb_periph_clk 12>; - phys = <&comphy0 0>, <&usb2_utmi_otg_phy>; - phy-names = "usb3-phy", "usb2-utmi-otg-phy"; + phys = <&usb2_utmi_otg_phy>, <&comphy0 0>; + phy-names = "usb2-phy", "usb3-phy"; status = "disabled"; }; @@ -393,10 +392,9 @@ usb2: usb@5e000 { compatible = "marvell,armada-3700-ehci"; reg = <0x5e000 0x1000>; - marvell,usb-misc-reg = <&usb2_syscon>; interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; phys = <&usb2_utmi_host_phy>; - phy-names = "usb2-utmi-host-phy"; + phy-names = "usb"; status = "disabled"; }; @@ -534,7 +532,6 @@ armada-3700-rwtm { compatible = "marvell,armada-3700-rwtm-firmware"; mboxes = <&rwtm 0>; - status = "okay"; }; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-7020-comexpress.dtsi b/arch/arm64/boot/dts/marvell/armada-7020-comexpress.dtsi index 2b5ec4a451e3..0cfcf5f6bde1 100644 --- a/arch/arm64/boot/dts/marvell/armada-7020-comexpress.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-7020-comexpress.dtsi @@ -70,7 +70,7 @@ &cp0_eth1 { status = "okay"; - phy = <&phy0>; + phy-handle = <&phy0>; phy-mode = "rgmii-id"; }; diff --git a/arch/arm64/boot/dts/marvell/armada-8020.dtsi b/arch/arm64/boot/dts/marvell/armada-8020.dtsi deleted file mode 100644 index b6fc18876093..000000000000 --- a/arch/arm64/boot/dts/marvell/armada-8020.dtsi +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for the Armada 8020 SoC, made of an AP806 Dual and - * two CP110. - */ - -#include "armada-ap806-dual.dtsi" -#include "armada-80x0.dtsi" - -/* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock - * in CP master is not connected (by package) to the oscillator. So - * disable it. However, the RTC clock in CP slave is connected to the - * oscillator so this one is let enabled. - */ - -&cp0_rtc { - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi b/arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi deleted file mode 100644 index 028496ebc473..000000000000 --- a/arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi +++ /dev/null @@ -1,96 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2023 Marvell International Ltd. - * - * Device tree for the CN9130-DB Com Express CPU module board. - */ - -#include "cn9130-db.dtsi" - -/ { - model = "Marvell Armada CN9130-DB COM EXPRESS type 7 CPU module board"; - compatible = "marvell,cn9130-cpu-module", "marvell,cn9130", - "marvell,armada-ap807-quad", "marvell,armada-ap807"; - -}; - -&ap0_reg_sd_vccq { - regulator-max-microvolt = <1800000>; - states = <1800000 0x1 1800000 0x0>; - /delete-property/ gpios; -}; - -&cp0_reg_usb3_vbus0 { - /delete-property/ gpio; -}; - -&cp0_reg_usb3_vbus1 { - /delete-property/ gpio; -}; - -&cp0_reg_sd_vcc { - status = "disabled"; -}; - -&cp0_reg_sd_vccq { - status = "disabled"; -}; - -&cp0_sdhci0 { - status = "disabled"; -}; - -&cp0_eth0 { - status = "disabled"; -}; - -&cp0_eth1 { - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; -}; - -&cp0_eth2 { - status = "disabled"; -}; - -&cp0_mdio { - status = "okay"; - pinctrl-0 = <&cp0_ge_mdio_pins>; - phy0: ethernet-phy@0 { - status = "okay"; - }; -}; - -&cp0_syscon0 { - cp0_pinctrl: pinctrl { - compatible = "marvell,cp115-standalone-pinctrl"; - - cp0_ge_mdio_pins: ge-mdio-pins { - marvell,pins = "mpp40", "mpp41"; - marvell,function = "ge"; - }; - }; -}; - -&cp0_sdhci0 { - status = "disabled"; -}; - -&cp0_spi1 { - status = "okay"; -}; - -&cp0_usb3_0 { - status = "okay"; - usb-phy = <&cp0_usb3_0_phy0>; - phy-names = "usb"; - /delete-property/ phys; -}; - -&cp0_usb3_1 { - status = "okay"; - usb-phy = <&cp0_usb3_0_phy1>; - phy-names = "usb"; - /delete-property/ phys; -}; diff --git a/drivers/reset/amlogic/reset-meson.c b/drivers/reset/amlogic/reset-meson.c index 84610365a823..c303e8590dd6 100644 --- a/drivers/reset/amlogic/reset-meson.c +++ b/drivers/reset/amlogic/reset-meson.c @@ -42,6 +42,7 @@ static const struct meson_reset_param meson_s4_param = { }; static const struct meson_reset_param t7_param = { + .reset_ops = &meson_reset_ops, .reset_num = 224, .reset_offset = 0x0, .level_offset = 0x40, |