diff options
| author | Aurabindo Pillai <aurabindo.pillai@amd.com> | 2022-07-07 13:53:57 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2022-07-08 18:24:18 -0400 |
| commit | 5531786537e4fcd82a221b0bd01ce375942b3854 (patch) | |
| tree | b3c401a84d365bf270278ec3b355f7b317427594 | |
| parent | c59d73d43fce92e79eddc047e1961054f1284384 (diff) | |
drm/amd/display: Add callback to set dig mode
[Why&How]
Add a missing callback to set DIG FIFO output pixel mode. This is used
when ODM combine is activated.
Fixes: 235c67634230 ("drm/amd/display: add DCN32/321 specific files for Display Core")
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c index da7d2243664f..26648ce772da 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c @@ -391,6 +391,16 @@ static void enc32_stream_encoder_reset_fifo(struct stream_encoder *enc) } } +static void enc32_set_dig_input_mode(struct stream_encoder *enc, unsigned int pix_per_container) +{ + struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); + + /* The naming of this field is confusing, what it means is the output mode of otg, which + * is the input mode of the dig + */ + REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_MODE, pix_per_container == 2 ? 0x1 : 0x0); +} + static const struct stream_encoder_funcs dcn32_str_enc_funcs = { .dp_set_odm_combine = enc32_dp_set_odm_combine, @@ -436,6 +446,8 @@ static const struct stream_encoder_funcs dcn32_str_enc_funcs = { .dp_set_dsc_pps_info_packet = enc3_dp_set_dsc_pps_info_packet, .set_dynamic_metadata = enc2_set_dynamic_metadata, .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute, + + .set_input_mode = enc32_set_dig_input_mode, }; void dcn32_dio_stream_encoder_construct( |