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| author | Drew Fustini <dfustini@oss.tenstorrent.com> | 2025-10-13 20:11:55 -0700 |
|---|---|---|
| committer | Drew Fustini <dfustini@oss.tenstorrent.com> | 2025-10-18 10:44:14 -0700 |
| commit | 571e42a1197c432d6bb78e1feb9586b4feb0a981 (patch) | |
| tree | 83f0e22ca4609146004f5fa99ceab46491a7b0a1 | |
| parent | 4de28f1edcfbd22ade0a69b97a10a43d09f5d4b4 (diff) | |
dt-bindings: riscv: cpus: Add SiFive X280 compatible
Document compatible for the SiFive X280 RISC-V core.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Joel Stanley <jms@oss.tenstorrent.com>
Signed-off-by: Drew Fustini <dfustini@oss.tenstorrent.com>
| -rw-r--r-- | Documentation/devicetree/bindings/riscv/cpus.yaml | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 153d0dac57fb..afb8533f6a08 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -70,6 +70,7 @@ properties: - enum: - sifive,e51 - sifive,u54-mc + - sifive,x280 - const: sifive,rocket0 - const: riscv - const: riscv # Simulator only |