diff options
| author | Nitin Garg <nitin.garg@freescale.com> | 2014-03-29 17:32:22 -0500 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@freescale.com> | 2014-04-16 08:58:10 -0500 |
| commit | 58e78520bcbe01f12be1b4020b3e7650dee875f2 (patch) | |
| tree | aae22a12fd28c684869fcb4b87aa46058ee60719 | |
| parent | 80b8d1939e4b875086ffe4e062070edfed34d2f4 (diff) | |
ENGR00306276: iMX6: Add workaround for ARM errata 761320 and 794072
These are Category B, hence workaround is essential.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
| -rw-r--r-- | arch/arm/Kconfig | 23 | ||||
| -rw-r--r-- | arch/arm/mach-imx/Kconfig | 2 | ||||
| -rw-r--r-- | arch/arm/mm/proc-v7.S | 11 |
3 files changed, 36 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ca88d4aa41b3..ea6ec7eef19b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1261,6 +1261,29 @@ config ARM_ERRATA_751472 operation is received by a CPU before the ICIALLUIS has completed, potentially leading to corrupted entries in the cache or TLB. +config ARM_ERRATA_794072 + bool "ARM errata: A short loop including a DMB instruction might cause a denial of service" + depends on CPU_V7 && SMP + help + This option enables the workaround for the 794072 Cortex-A9 + (all revisions). A processor which continuously executes a short + loop containing a DMB instruction might prevent a CP15 operation + broadcast by another processor making further progress, causing + a denial of service. This erratum can be worked around by setting + bit[4] of the undocumented Diagnostic Control Register to 1. + +config ARM_ERRATA_761320 + bool "Full cache line writes to the same memory region from at least two processors might deadlock processor" + depends on CPU_V7 && SMP + help + This option enables the workaround for the 761320 Cortex-A9 (r0..r3). + Under very rare circumstances, full cache line writes + from (at least) 2 processors on cache lines in hazard with + other requests may cause arbitration issues in the SCU, + leading to processor deadlock. This erratum can be + worked around by setting bit[21] of the undocumented + Diagnostic Control Register to 1. + config PL310_ERRATA_753970 bool "PL310 errata: cache sync operation may be faulty" depends on CACHE_PL310 diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 3c70ffcc443a..7875adb8c7f4 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -800,6 +800,8 @@ config SOC_IMX6Q select ARM_ERRATA_754322 select ARM_ERRATA_764369 if SMP select ARM_ERRATA_775420 + select ARM_ERRATA_794072 if SMP + select ARM_ERRATA_761320 if SMP select ARM_GIC select COMMON_CLK select CPU_V7 diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 5fbccee5f644..7a6141f495e1 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -326,6 +326,17 @@ __v7_setup: mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register 1: #endif +#ifdef CONFIG_ARM_ERRATA_794072 + mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register + orr r10, r10, #1 << 4 @ set bit #4 + mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register +#endif +#ifdef CONFIG_ARM_ERRATA_761320 + cmp r6, #0x40 @ present prior to r4p0 + mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register + orrlt r10, r10, #1 << 21 @ set bit #21 + mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register +#endif 3: mov r10, #0 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate |