diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2026-02-10 21:11:08 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2026-02-10 21:11:08 -0800 |
| commit | 6589b3d76db2d6adbf8f2084c303fb24252a0dc6 (patch) | |
| tree | 41756c314daec1e37b73dcc174c97ed417a484a0 | |
| parent | 60dc45dde44e0b5c433d8db574daf86b59eb6dc3 (diff) | |
| parent | f51d34065de4f29fd237276a49cad06ac7356a55 (diff) | |
Merge tag 'soc-dt-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC devicetree updates from Arnd Bergmann:
"There are a handful of new SoCs this time, all of these are more or
less related to chips in a wider family:
- SpacemiT Key Stone K3 is an 8-core risc-v chip, and the first
widely available RVA23 implementation. Note that this is entirely
unrelated with the similarly named Texas Instruments K3 chip family
that follwed the TI Keystone2 SoC.
- The Realtek Kent family of SoCs contains three chip models
rtd1501s, rtd1861b and rtd1920s, and is related to their earlier
Set-top-box and NAS products such as rtd1619, but is built on newer
Arm Cortex-A78 cores.
- The Qualcomm Milos family includes the Snapdragon 7s Gen 3 (SM7635)
mobile phone SoC built around Armv9 Kryo cores of the Arm
Cortex-A720 generation. This one is used in the Fairphone Gen 6
- Qualcomm Kaanapali is a new SoC based around eight high performance
Oryon CPU cores
- NXP i.MX8QP and i.MX952 are both feature reduced versions of chips
we already support, i.e. the i.MX8QM and i.MX952, with fewer CPU
cores and I/O interfaces.
As part of a cleanup, a number of SoC specific devicetree files got
removed because they did not have a single board using the .dtsi files
and they were never compile tested as a result: Samsung s3c6400, ST
spear320s, ST stm32mp21xc/stm32mp23xc/stm32mp25xc, Renesas
r8a779m0/r8a779m2/r8a779m4/r8a779m6/r8a779m7/r8a779m8/r8a779mb/
r9a07g044c1/r9a07g044l1/r9a07g054l1/r9a09g047e37, and TI
am3703/am3715. All of these could be restored easily if a new board
gets merged.
Broadcom/Cavium/Marvell ThunderX2 gets removed along with its only
machine, as all remaining users are assumed to be using ACPI based
firmware.
A relatively small number of 43 boards get added this time, and almost
all of them for arm64. Aside from the reference boards for the newly
added SoCs, this includes:
- Three server boards use 32-bit ASpeed BMCs
- One more reference board for 32-bit Microchip LAN9668
- 64-bit Arm single-board computers based on Amlogic s905y4, CIX
sky1, NXP ls1028a/imx8mn/imx8mp/imx91/imx93/imx95, Qualcomm
qcs6490/qrb2210 and Rockchip rk3568/rk3588s
- Carrier board for SOMs using Intel agilex5, Marvell Armada 7020,
NXP iMX8QP, Mediatek mt8370/mt8390 and rockchip rk3588
- Two mobile phones using Snapdragon 845
- A gaming device and a NAS box, both based on Rockchips rk356x
On top of the newly added boards and SoCs, there is a lot of
background activity going into cleanups, in particular towards getting
a warning-free dtc build, and the usual work on adding support for
more hardware on the previously added machines"
* tag 'soc-dt-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (757 commits)
dt-bindings: intel: Add Agilex eMMC support
arm64: dts: socfpga: agilex: add emmc support
arm64: dts: intel: agilex5: Add simple-bus node on top of dma controller node
ARM: dts: socfpga: fix dtbs_check warning for fpga-region
ARM: dts: socfpga: add #address-cells and #size-cells for sram node
dt-bindings: altera: document syscon as fallback for sys-mgr
arm64: dts: altera: Use lowercase hex
dt-bindings: arm: altera: combine Intel's SoCFPGA into altera.yaml
arm64: dts: socfpga: agilex5: Add IOMMUS property for ethernet nodes
arm64: dts: socfpga: agilex5: add support for modular board
dt-bindings: intel: Add Agilex5 SoCFPGA modular board
arm64: dts: socfpga: agilex5: Add dma-coherent property
arm64: dts: realtek: Add Kent SoC and EVB device trees
dt-bindings: arm: realtek: Add Kent Soc family compatibles
ARM: dts: samsung: Drop s3c6400.dtsi
ARM: dts: nuvoton: Minor whitespace cleanup
MAINTAINERS: Add Falcon DB
arm64: dts: a7k: add COM Express boards
ARM: dts: microchip: Drop usb_a9g20-dab-mmx.dtsi
arm64: dts: rockchip: Fix rk3588 PCIe range mappings
...
775 files changed, 52023 insertions, 5486 deletions
diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml index db61537b7115..13a3a9696821 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -9,6 +9,9 @@ title: Altera's SoCFPGA platform maintainers: - Dinh Nguyen <dinguyen@kernel.org> +description: + Altera/Intel boards with ARM 32/64 bits cores + properties: $nodename: const: "/" @@ -81,6 +84,30 @@ properties: - altr,socfpga-stratix10-swvp - const: altr,socfpga-stratix10 + - description: AgileX boards + items: + - enum: + - intel,n5x-socdk + - intel,socfpga-agilex-n6000 + - intel,socfpga-agilex-socdk + - intel,socfpga-agilex-socdk-emmc + - const: intel,socfpga-agilex + + - description: Agilex3 boards + items: + - enum: + - intel,socfpga-agilex3-socdk + - const: intel,socfpga-agilex3 + - const: intel,socfpga-agilex5 + + - description: Agilex5 boards + items: + - enum: + - intel,socfpga-agilex5-socdk + - intel,socfpga-agilex5-socdk-013b + - intel,socfpga-agilex5-socdk-nand + - const: intel,socfpga-agilex5 + - description: SoCFPGA VT items: - const: altr,socfpga-vt diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml index 08d9963fe925..a885278bc4e2 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml @@ -245,6 +245,14 @@ properties: items: - enum: - amlogic,aq222 + - const: amlogic,s805x2 + - const: amlogic,s4 + + - description: Boards with the Amlogic Meson S4 S905Y4 SoC + items: + - enum: + - khadas,vim1s + - const: amlogic,s905y4 - const: amlogic,s4 - description: Boards with the Amlogic S6 S905X5 SoC diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml index 9298c1a75dd1..f9925a14680e 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -34,6 +34,7 @@ properties: - amd,ethanolx-bmc - ampere,mtjade-bmc - aspeed,ast2500-evb + - asrock,altrad8-bmc - asrock,e3c246d4i-bmc - asrock,e3c256d4i-bmc - asrock,romed8hm3-bmc @@ -80,6 +81,7 @@ properties: - aspeed,ast2600-evb - aspeed,ast2600-evb-a1 - asus,x4tf-bmc + - facebook,anacapa-bmc - facebook,bletchley-bmc - facebook,catalina-bmc - facebook,clemente-bmc @@ -107,6 +109,7 @@ properties: - inventec,transformer-bmc - jabil,rbp-bmc - nvidia,gb200nvl-bmc + - nvidia,msx4-bmc - qcom,dc-scm-v1-bmc - quanta,s6q-bmc - ufispace,ncplite-bmc diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.yaml b/Documentation/devicetree/bindings/arm/atmel-at91.yaml index 3a34b7a2e8d4..68d306d17c2a 100644 --- a/Documentation/devicetree/bindings/arm/atmel-at91.yaml +++ b/Documentation/devicetree/bindings/arm/atmel-at91.yaml @@ -235,9 +235,11 @@ properties: - const: microchip,lan9662 - const: microchip,lan966 - - description: Microchip LAN9668 PCB8290 Evaluation Board. + - description: Microchip LAN9668 Evaluation Board. items: - - const: microchip,lan9668-pcb8290 + - enum: + - microchip,lan9668-pcb8290 + - microchip,lan9668-pcb8385 - const: microchip,lan9668 - const: microchip,lan966 diff --git a/Documentation/devicetree/bindings/arm/cix.yaml b/Documentation/devicetree/bindings/arm/cix.yaml index 114dab4bc4d2..21e66df7f696 100644 --- a/Documentation/devicetree/bindings/arm/cix.yaml +++ b/Documentation/devicetree/bindings/arm/cix.yaml @@ -16,9 +16,11 @@ properties: compatible: oneOf: - - description: Radxa Orion O6 + - description: Sky1 based boards items: - - const: radxa,orion-o6 + - enum: + - radxa,orion-o6 # Radxa Orion O6 board + - xunlong,orangepi-6-plus # Xunlong orangepi 6 plus board - const: cix,sky1 additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 336669e16d7a..5716d701292c 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1071,6 +1071,15 @@ properties: - gw,imx8mn-gw7902 # i.MX8MM Gateworks Board - const: fsl,imx8mn + - description: ifm i.MX8MN VHIP4 based boards + items: + - enum: + - ifm,imx8mn-vhip4-evalboard-v1 + - ifm,imx8mn-vhip4-evalboard-v2 + - const: ifm,imx8mn-vhip4-evalboard + - const: ifm,imx8mn-vhip4 + - const: fsl,imx8mn + - description: Variscite VAR-SOM-MX8MN based boards items: - enum: @@ -1099,6 +1108,7 @@ properties: - emcraft,imx8mp-navqp # i.MX8MP Emcraft Systems NavQ+ Kit - fsl,imx8mp-evk # i.MX8MP EVK Board - fsl,imx8mp-evk-revb4 # i.MX8MP EVK Rev B4 Board + - fsl,imx8mp-frdm # i.MX8MP Freedom Board - gateworks,imx8mp-gw71xx-2x # i.MX8MP Gateworks Board - gateworks,imx8mp-gw72xx-2x # i.MX8MP Gateworks Board - gateworks,imx8mp-gw73xx-2x # i.MX8MP Gateworks Board @@ -1340,7 +1350,7 @@ properties: - const: toradex,apalis-imx8 - const: fsl,imx8qm - - description: i.MX8QM Boards with Toradex Apalis iMX8 V1.1 Modules + - description: i.MX8QM/i.MX8QP Boards with Toradex Apalis iMX8 V1.1 Modules items: - enum: - toradex,apalis-imx8-v1.1-eval # Apalis iMX8 V1.1 Module on Apalis Eval. V1.0/V1.1 Board @@ -1348,7 +1358,9 @@ properties: - toradex,apalis-imx8-v1.1-ixora-v1.1 # Apalis iMX8 V1.1 Module on Ixora V1.1 C. Board - toradex,apalis-imx8-v1.1-ixora-v1.2 # Apalis iMX8 V1.1 Module on Ixora V1.2 C. Board - const: toradex,apalis-imx8-v1.1 - - const: fsl,imx8qm + - enum: + - fsl,imx8qm + - fsl,imx8qp - description: i.MX8QXP based Boards items: @@ -1419,6 +1431,7 @@ properties: items: - enum: - fsl,imx91-11x11-evk # i.MX91 11x11 EVK Board + - fsl,imx91-11x11-frdm # FRDM i.MX91 Development Board - const: fsl,imx91 - description: i.MX93 based Boards @@ -1426,6 +1439,7 @@ properties: - enum: - fsl,imx93-9x9-qsb # i.MX93 9x9 QSB Board - fsl,imx93-11x11-evk # i.MX93 11x11 EVK Board + - fsl,imx93-11x11-frdm # i.MX93 11x11 FRDM Board - fsl,imx93-14x14-evk # i.MX93 14x14 EVK Board - const: fsl,imx93 @@ -1439,10 +1453,17 @@ properties: items: - enum: - fsl,imx95-15x15-evk # i.MX95 15x15 EVK Board + - fsl,imx95-15x15-frdm # i.MX95 15x15 FRDM Board - fsl,imx95-19x19-evk # i.MX95 19x19 EVK Board - toradex,verdin-imx95-19x19-evk # i.MX95 Verdin Evaluation Kit (EVK) - const: fsl,imx95 + - description: i.MX952 based Boards + items: + - enum: + - fsl,imx952-evk # i.MX952 EVK Board + - const: fsl,imx952 + - description: PHYTEC i.MX 95 FPSC based Boards items: - enum: @@ -1679,6 +1700,15 @@ properties: - const: kontron,sl28 - const: fsl,ls1028a + - description: + TQ-Systems TQMLS1028A SoM on MBLS1028A/MBLS1028A-IND board + items: + - enum: + - tq,ls1028a-tqmls1028a-mbls1028a + - tq,ls1028a-tqmls1028a-mbls1028a-ind + - const: tq,ls1028a-tqmls1028a + - const: fsl,ls1028a + - description: LS1043A based Boards items: - enum: diff --git a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml deleted file mode 100644 index c918837bd41c..000000000000 --- a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml +++ /dev/null @@ -1,40 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/arm/intel,socfpga.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Intel SoCFPGA platform - -maintainers: - - Dinh Nguyen <dinguyen@kernel.org> - -properties: - $nodename: - const: "/" - compatible: - oneOf: - - description: AgileX boards - items: - - enum: - - intel,n5x-socdk - - intel,socfpga-agilex-n6000 - - intel,socfpga-agilex-socdk - - const: intel,socfpga-agilex - - description: Agilex3 boards - items: - - enum: - - intel,socfpga-agilex3-socdk - - const: intel,socfpga-agilex3 - - const: intel,socfpga-agilex5 - - description: Agilex5 boards - items: - - enum: - - intel,socfpga-agilex5-socdk - - intel,socfpga-agilex5-socdk-013b - - intel,socfpga-agilex5-socdk-nand - - const: intel,socfpga-agilex5 - -additionalProperties: true - -... diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 718d732174b9..382d0eb4d0af 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -438,12 +438,14 @@ properties: - const: mediatek,mt8365 - items: - enum: + - ezurio,mt8370-tungsten-smarc - grinn,genio-510-sbc - mediatek,mt8370-evk - const: mediatek,mt8370 - const: mediatek,mt8188 - items: - enum: + - ezurio,mt8390-tungsten-smarc - grinn,genio-700-sbc - mediatek,mt8390-evk - const: mediatek,mt8390 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml index f3a761cbd0fd..09a6c16e7e82 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml @@ -48,19 +48,39 @@ required: - compatible - '#clock-cells' -if: - properties: - compatible: - contains: - const: mediatek,mt8183-audiosys -then: - properties: - audio-controller: - $ref: /schemas/sound/mediatek,mt8183-audio.yaml# -else: - properties: - audio-controller: - $ref: /schemas/sound/mediatek,mt2701-audio.yaml# +allOf: + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt2701-audsys + - mediatek,mt7622-audsys + then: + properties: + audio-controller: + $ref: /schemas/sound/mediatek,mt2701-audio.yaml# + + - if: + properties: + compatible: + contains: + const: mediatek,mt8183-audiosys + then: + properties: + audio-controller: + $ref: /schemas/sound/mediatek,mt8183-audio.yaml# + + - if: + properties: + compatible: + contains: + const: mediatek,mt8192-audsys + then: + properties: + audio-controller: + $ref: /schemas/sound/mt8192-afe-pcm.yaml# + additionalProperties: false diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index d84bd3bca201..d48c625d3fc4 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -63,6 +63,11 @@ properties: - items: - enum: + - fairphone,fp6 + - const: qcom,milos + + - items: + - enum: - microsoft,dempsey - microsoft,makepeace - microsoft,moneypenny @@ -327,6 +332,12 @@ properties: - qcom,ipq9574-ap-al02-c9 - const: qcom,ipq9574 + - items: + - enum: + - qcom,kaanapali-mtp + - qcom,kaanapali-qrd + - const: qcom,kaanapali + - description: Sierra Wireless MangOH Green with WP8548 Module items: - const: swir,mangoh-green-wp8548 @@ -336,6 +347,7 @@ properties: - description: Qualcomm Technologies, Inc. Robotics RB1 items: - enum: + - arduino,imola - qcom,qrb2210-rb1 - const: qcom,qrb2210 - const: qcom,qcm2290 @@ -348,6 +360,7 @@ properties: - qcom,qcs6490-rb3gen2 - radxa,dragon-q6a - shift,otter + - thundercomm,rubikpi3 - const: qcom,qcm6490 - description: Qualcomm Technologies, Inc. Distributed Unit 1000 platform @@ -900,6 +913,8 @@ properties: - items: - enum: + - google,blueline + - google,crosshatch - huawei,planck - lenovo,yoga-c630 - lg,judyln @@ -1069,6 +1084,19 @@ properties: - items: - enum: + - medion,sprchrgd14s1 + - tuxedo,elite14gen1 + - const: qcom,x1e78100 + - const: qcom,x1e80100 + + - items: + - const: microsoft,denali-lcd + - const: microsoft,denali + - const: qcom,x1p64100 + - const: qcom,x1e80100 + + - items: + - enum: - asus,vivobook-s15 - asus,zenbook-a14-ux3407ra - dell,inspiron-14-plus-7441 @@ -1090,6 +1118,11 @@ properties: - const: qcom,x1e80100 - items: + - const: microsoft,denali-oled + - const: microsoft,denali + - const: qcom,x1e80100 + + - items: - enum: - asus,zenbook-a14-ux3407qa-lcd - asus,zenbook-a14-ux3407qa-oled diff --git a/Documentation/devicetree/bindings/arm/realtek.yaml b/Documentation/devicetree/bindings/arm/realtek.yaml index ddd9a85099e9..be529490640c 100644 --- a/Documentation/devicetree/bindings/arm/realtek.yaml +++ b/Documentation/devicetree/bindings/arm/realtek.yaml @@ -14,21 +14,21 @@ properties: const: '/' compatible: oneOf: - # RTD1195 SoC based boards - - items: + - description: RTD1195 SoC based boards + items: - enum: - mele,x1000 # MeLE X1000 - realtek,horseradish # Realtek Horseradish EVB - const: realtek,rtd1195 - # RTD1293 SoC based boards - - items: + - description: RTD1293 SoC based boards + items: - enum: - synology,ds418j # Synology DiskStation DS418j - const: realtek,rtd1293 - # RTD1295 SoC based boards - - items: + - description: RTD1295 SoC based boards + items: - enum: - mele,v9 # MeLE V9 - probox2,ava # ProBox2 AVA @@ -36,25 +36,43 @@ properties: - zidoo,x9s # Zidoo X9S - const: realtek,rtd1295 - # RTD1296 SoC based boards - - items: + - description: RTD1296 SoC based boards + items: - enum: - synology,ds418 # Synology DiskStation DS418 - const: realtek,rtd1296 - # RTD1395 SoC based boards - - items: + - description: RTD1395 SoC based boards + items: - enum: - bananapi,bpi-m4 # Banana Pi BPI-M4 - realtek,lion-skin # Realtek Lion Skin EVB - const: realtek,rtd1395 - # RTD1619 SoC based boards - - items: + - description: RTD1501s SoC based boards + items: + - enum: + - realtek,phantom # Realtek Phantom EVB (8GB) + - const: realtek,rtd1501s + + - description: RTD1619 SoC based boards + items: - enum: - realtek,mjolnir # Realtek Mjolnir EVB - const: realtek,rtd1619 + - description: RTD1861b SoC based boards + items: + - enum: + - realtek,krypton # Realtek Krypton EVB (8GB) + - const: realtek,rtd1861b + + - description: RTD1920s SoC based boards + items: + - enum: + - realtek,smallville # Realtek Smallville EVB (4GB) + - const: realtek,rtd1920s + additionalProperties: true ... diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index d496421dbd87..ae77ded9fe47 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -60,6 +60,12 @@ properties: - anbernic,rg-arc-s - const: rockchip,rk3566 + - description: Anbernic RK3568 Handheld Gaming Console + items: + - enum: + - anbernic,rg-ds + - const: rockchip,rk3568 + - description: Ariaboard Photonicat items: - const: ariaboard,photonicat @@ -894,11 +900,15 @@ properties: - const: rockchip,rk3568 - description: QNAP TS-x33 NAS devices - items: - - enum: - - qnap,ts233 - - qnap,ts433 - - const: rockchip,rk3568 + oneOf: + - items: + - const: qnap,ts133 + - const: rockchip,rk3566 + - items: + - enum: + - qnap,ts233 + - qnap,ts433 + - const: rockchip,rk3568 - description: Radxa Compute Module 3 (CM3) items: @@ -907,13 +917,27 @@ properties: - const: radxa,cm3 - const: rockchip,rk3566 - - description: Radxa CM3 Industrial + - description: Radxa CM3I items: - enum: - radxa,e25 - const: radxa,cm3i - const: rockchip,rk3568 + - description: Radxa CM3J + items: + - enum: + - radxa,cm3j-rpi-cm4 + - const: radxa,cm3j + - const: rockchip,rk3568 + + - description: Radxa CM5 + items: + - enum: + - radxa,cm5-io + - const: radxa,cm5 + - const: rockchip,rk3588s + - description: Radxa E20C items: - const: radxa,e20c @@ -1299,6 +1323,12 @@ properties: - xunlong,orangepi-5b - const: rockchip,rk3588s + - description: Xunlong Orange Pi CM5 + items: + - const: xunlong,orangepi-cm5-base + - const: xunlong,orangepi-cm5 + - const: rockchip,rk3588s + - description: Zkmagic A95X Z2 items: - const: zkmagic,a95x-z2 diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml index be70819020c5..dcd1c5376507 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml @@ -19,15 +19,15 @@ properties: - nvidia,tegra264-pmc reg: - minItems: 4 + minItems: 3 maxItems: 5 reg-names: - minItems: 4 + minItems: 3 items: - const: pmc - const: wake - - const: aotag + - enum: [ aotag, scratch, misc ] - enum: [ scratch, misc ] - const: misc @@ -51,6 +51,7 @@ allOf: then: properties: reg: + minItems: 4 maxItems: 4 reg-names: maxItems: 4 @@ -73,7 +74,9 @@ allOf: properties: compatible: contains: - const: nvidia,tegra234-pmc + enum: + - nvidia,tegra234-pmc + - nvidia,tegra264-pmc then: properties: reg-names: diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml index 31e106ef913d..6193c87511fa 100644 --- a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml +++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml @@ -29,9 +29,10 @@ properties: enum: - google,gs101-cmu-top - google,gs101-cmu-apm - - google,gs101-cmu-misc + - google,gs101-cmu-dpu - google,gs101-cmu-hsi0 - google,gs101-cmu-hsi2 + - google,gs101-cmu-misc - google,gs101-cmu-peric0 - google,gs101-cmu-peric1 @@ -81,6 +82,24 @@ allOf: properties: compatible: contains: + const: google,gs101-cmu-dpu + + then: + properties: + clocks: + items: + - description: External reference clock (24.576 MHz) + - description: DPU bus clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: bus + + - if: + properties: + compatible: + contains: const: google,gs101-cmu-hsi0 then: diff --git a/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml index 1b15b5070954..881a5dd8d06f 100644 --- a/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml @@ -62,6 +62,9 @@ properties: - description: USB4_1 PHY max PIPE clock source - description: USB4_2 PHY PCIE PIPE clock source - description: USB4_2 PHY max PIPE clock source + - description: UFS PHY RX Symbol 0 clock source + - description: UFS PHY RX Symbol 1 clock source + - description: UFS PHY TX Symbol 0 clock source power-domains: description: @@ -121,7 +124,10 @@ examples: <&usb4_1_phy_pcie_pipe_clk>, <&usb4_1_phy_max_pipe_clk>, <&usb4_2_phy_pcie_pipe_clk>, - <&usb4_2_phy_max_pipe_clk>; + <&usb4_2_phy_max_pipe_clk>, + <&ufs_phy_rx_symbol_0>, + <&ufs_phy_rx_symbol_1>, + <&ufs_phy_tx_symbol_0>; power-domains = <&rpmhpd RPMHPD_CX>; #clock-cells = <1>; #reset-cells = <1>; diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.yaml index 193ddb105283..9a500f52f01d 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.yaml @@ -18,6 +18,7 @@ properties: enum: - nvidia,tegra114-mipi - nvidia,tegra124-mipi + - nvidia,tegra132-mipi - nvidia,tegra210-mipi - nvidia,tegra186-mipi diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml index 644f42b942ad..bb138277d5e8 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml @@ -16,16 +16,21 @@ properties: compatible: oneOf: - - const: nvidia,tegra20-vi - - const: nvidia,tegra30-vi - - const: nvidia,tegra114-vi - - const: nvidia,tegra124-vi + - enum: + - nvidia,tegra20-vi + - nvidia,tegra114-vi + - nvidia,tegra124-vi + - nvidia,tegra210-vi + - nvidia,tegra186-vi + - nvidia,tegra194-vi + + - items: + - const: nvidia,tegra30-vi + - const: nvidia,tegra20-vi + - items: - const: nvidia,tegra132-vi - const: nvidia,tegra124-vi - - const: nvidia,tegra210-vi - - const: nvidia,tegra186-vi - - const: nvidia,tegra194-vi reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vip.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vip.yaml index 14294edb8d8c..9104a36e16d9 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vip.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vip.yaml @@ -11,8 +11,13 @@ maintainers: properties: compatible: - enum: - - nvidia,tegra20-vip + oneOf: + - enum: + - nvidia,tegra20-vip + + - items: + - const: nvidia,tegra30-vip + - const: nvidia,tegra20-vip ports: $ref: /schemas/graph.yaml#/properties/ports diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml index da0235e451d6..269a1f7ebdbb 100644 --- a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml @@ -46,7 +46,7 @@ properties: Should contain all of the per-channel DMA interrupts in ascending order with respect to the DMA channel index. minItems: 1 - maxItems: 32 + maxItems: 64 clocks: description: Must contain one entry for the ADMA module clock @@ -86,6 +86,19 @@ allOf: reg: items: - description: Full address space range of DMA registers. + interrupts: + maxItems: 22 + + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra186-adma + then: + properties: + interrupts: + maxItems: 32 - if: properties: diff --git a/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml b/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml index 457bb0702ed9..64aaa0dfa8fa 100644 --- a/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml @@ -127,6 +127,9 @@ properties: wakeup-source: true + power-domains: + maxItems: 1 + access-controllers: minItems: 1 maxItems: 2 diff --git a/Documentation/devicetree/bindings/input/touchscreen/goodix.yaml b/Documentation/devicetree/bindings/input/touchscreen/goodix.yaml index a96137c6f063..a26a54d63a1c 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/goodix.yaml +++ b/Documentation/devicetree/bindings/input/touchscreen/goodix.yaml @@ -42,6 +42,8 @@ properties: address, thus it can be driven by the host during the reset sequence. maxItems: 1 + panel: true + reset-gpios: maxItems: 1 diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml index bef00521d5da..0718071444d2 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml @@ -28,6 +28,7 @@ properties: items: - enum: - qemu,aplic + - spacemit,k3-aplic - const: riscv,aplic reg: diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml index c23b5c09fdb9..feec122bddde 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml @@ -48,6 +48,7 @@ properties: items: - enum: - qemu,imsics + - spacemit,k3-imsics - const: riscv,imsics reg: diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml index 75fcf4cb52d9..82957334bea2 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml @@ -20,7 +20,12 @@ properties: $nodename: pattern: "^iommu@[0-9a-f]*" compatible: - const: arm,smmu-v3 + oneOf: + - const: arm,smmu-v3 + - items: + - enum: + - nvidia,tegra264-smmu + - const: arm,smmu-v3 reg: maxItems: 1 @@ -58,6 +63,15 @@ properties: msi-parent: true + nvidia,cmdqv: + description: | + A phandle to its pairing CMDQV extension for an implementation on NVIDIA + Tegra SoC. + + If this property is absent, CMDQ-Virtualization won't be used and SMMU + will only use its own CMDQ. + $ref: /schemas/types.yaml#/definitions/phandle + hisilicon,broken-prefetch-cmd: type: boolean description: Avoid sending CMD_PREFETCH_* commands to the SMMU. @@ -69,6 +83,17 @@ properties: register access with page 0 offsets. Set for Cavium ThunderX2 silicon that doesn't support SMMU page1 register space. +allOf: + - if: + not: + properties: + compatible: + contains: + const: nvidia,tegra264-smmu + then: + properties: + nvidia,cmdqv: false + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml b/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml new file mode 100644 index 000000000000..3f5006a59805 --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iommu/nvidia,tegra264-cmdqv.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra264 CMDQV + +description: + The CMDQ-Virtualization hardware block is part of the SMMUv3 implementation + on Tegra264 SoCs. It assists in virtualizing the command queue for the SMMU. + +maintainers: + - Nicolin Chen <nicolinc@nvidia.com> + +properties: + compatible: + const: nvidia,tegra264-cmdqv + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + cmdqv@5200000 { + compatible = "nvidia,tegra264-cmdqv"; + reg = <0x5200000 0x830000>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + }; diff --git a/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml index 9122c3d2dc30..90bfde66cc4a 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml @@ -19,6 +19,8 @@ properties: - items: - enum: - qcom,glymur-cpucp-mbox + - qcom,kaanapali-cpucp-mbox + - qcom,sm8750-cpucp-mbox - const: qcom,x1e80100-cpucp-mbox - enum: - qcom,x1e80100-cpucp-mbox diff --git a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml index e5c423130db6..7c4d6170491d 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml @@ -24,6 +24,8 @@ properties: compatible: items: - enum: + - qcom,glymur-ipcc + - qcom,kaanapali-ipcc - qcom,milos-ipcc - qcom,qcs8300-ipcc - qcom,qdu1000-ipcc diff --git a/Documentation/devicetree/bindings/media/st,stm32-dcmipp.yaml b/Documentation/devicetree/bindings/media/st,stm32-dcmipp.yaml index 7b03a77adbce..162a0c526d5d 100644 --- a/Documentation/devicetree/bindings/media/st,stm32-dcmipp.yaml +++ b/Documentation/devicetree/bindings/media/st,stm32-dcmipp.yaml @@ -37,6 +37,9 @@ properties: resets: maxItems: 1 + power-domains: + maxItems: 1 + access-controllers: minItems: 1 maxItems: 2 diff --git a/Documentation/devicetree/bindings/media/st,stm32mp25-csi.yaml b/Documentation/devicetree/bindings/media/st,stm32mp25-csi.yaml index e9fa3cfea5d2..2ac7c9670c62 100644 --- a/Documentation/devicetree/bindings/media/st,stm32mp25-csi.yaml +++ b/Documentation/devicetree/bindings/media/st,stm32mp25-csi.yaml @@ -46,6 +46,9 @@ properties: minItems: 1 maxItems: 2 + power-domains: + maxItems: 1 + ports: $ref: /schemas/graph.yaml#/properties/ports diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml index b901f1b3e0fc..7b03b589168b 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml @@ -92,10 +92,14 @@ patternProperties: clocks: items: - description: external memory clock + - description: data backbone clock + minItems: 1 clock-names: items: - const: emc + - const: dbb + minItems: 1 "#interconnect-cells": const: 0 @@ -115,6 +119,9 @@ patternProperties: reg: maxItems: 1 + clocks: + maxItems: 1 + - if: properties: compatible: @@ -124,6 +131,9 @@ patternProperties: reg: minItems: 2 + clocks: + maxItems: 1 + - if: properties: compatible: @@ -133,6 +143,9 @@ patternProperties: reg: minItems: 2 + clocks: + maxItems: 1 + - if: properties: compatible: diff --git a/Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.yaml b/Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.yaml new file mode 100644 index 000000000000..b417d72fa0de --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/nvidia,tegra20-nand.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra NAND Flash Controller + +maintainers: + - Jonathan Hunter <jonathanh@nvidia.com> + +allOf: + - $ref: nand-controller.yaml + +description: + The NVIDIA NAND controller provides an interface between NVIDIA SoCs + and raw NAND flash devices. It supports standard NAND operations, + hardware-assisted ECC, OOB data access, and DMA transfers, and + integrates with the Linux MTD NAND subsystem for reliable flash management. + +properties: + compatible: + const: nvidia,tegra20-nand + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: nand + + resets: + maxItems: 1 + + reset-names: + items: + - const: nand + + power-domains: + maxItems: 1 + + operating-points-v2: + maxItems: 1 + +patternProperties: + '^nand@': + type: object + description: Individual NAND chip connected to the NAND controller + $ref: raw-nand-chip.yaml# + + properties: + reg: + maximum: 5 + + unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - reset-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/tegra20-car.h> + #include <dt-bindings/gpio/tegra-gpio.h> + + nand-controller@70008000 { + compatible = "nvidia,tegra20-nand"; + reg = <0x70008000 0x100>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA20_CLK_NDFLASH>; + clock-names = "nand"; + resets = <&tegra_car 13>; + reset-names = "nand"; + #address-cells = <1>; + #size-cells = <0>; + + nand@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + nand-bus-width = <8>; + nand-on-flash-bbt; + nand-ecc-algo = "bch"; + nand-ecc-strength = <8>; + wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt b/Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt deleted file mode 100644 index 4a00ec2b2540..000000000000 --- a/Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt +++ /dev/null @@ -1,64 +0,0 @@ -NVIDIA Tegra NAND Flash controller - -Required properties: -- compatible: Must be one of: - - "nvidia,tegra20-nand" -- reg: MMIO address range -- interrupts: interrupt output of the NFC controller -- clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: Must include the following entries: - - nand -- resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names: Must include the following entries: - - nand - -Optional children nodes: -Individual NAND chips are children of the NAND controller node. Currently -only one NAND chip supported. - -Required children node properties: -- reg: An integer ranging from 1 to 6 representing the CS line to use. - -Optional children node properties: -- nand-ecc-mode: String, operation mode of the NAND ecc mode. Currently only - "hw" is supported. -- nand-ecc-algo: string, algorithm of NAND ECC. - Supported values with "hw" ECC mode are: "rs", "bch". -- nand-bus-width : See nand-controller.yaml -- nand-on-flash-bbt: See nand-controller.yaml -- nand-ecc-strength: integer representing the number of bits to correct - per ECC step (always 512). Supported strength using HW ECC - modes are: - - RS: 4, 6, 8 - - BCH: 4, 8, 14, 16 -- nand-ecc-maximize: See nand-controller.yaml -- nand-is-boot-medium: Makes sure only ECC strengths supported by the boot ROM - are chosen. -- wp-gpios: GPIO specifier for the write protect pin. - -Optional child node of NAND chip nodes: -Partitions: see mtd.yaml - - Example: - nand-controller@70008000 { - compatible = "nvidia,tegra20-nand"; - reg = <0x70008000 0x100>; - interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&tegra_car TEGRA20_CLK_NDFLASH>; - clock-names = "nand"; - resets = <&tegra_car 13>; - reset-names = "nand"; - - nand@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - nand-bus-width = <8>; - nand-on-flash-bbt; - nand-ecc-algo = "bch"; - nand-ecc-strength = <8>; - wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>; - }; - }; diff --git a/Documentation/devicetree/bindings/power/fsl,imx-gpc.yaml b/Documentation/devicetree/bindings/power/fsl,imx-gpc.yaml index 9de3fe73c1eb..d49a5130b87c 100644 --- a/Documentation/devicetree/bindings/power/fsl,imx-gpc.yaml +++ b/Documentation/devicetree/bindings/power/fsl,imx-gpc.yaml @@ -38,6 +38,9 @@ properties: reg: maxItems: 1 + "#address-cells": + const: 0 + interrupts: maxItems: 1 diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index d733c0bd534f..5feeb2203050 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -61,6 +61,7 @@ properties: - sifive,u7 - sifive,u74 - sifive,u74-mc + - spacemit,x100 - spacemit,x60 - thead,c906 - thead,c908 diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 5bab356addc8..4ffd61926505 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -24,12 +24,6 @@ description: | ratified states, with the exception of the I, Zicntr & Zihpm extensions. See the "i" property for more information. -select: - properties: - compatible: - contains: - const: riscv - properties: riscv,isa: description: @@ -109,6 +103,13 @@ properties: The standard C extension for compressed instructions, as ratified in the 20191213 version of the unprivileged ISA specification. + - const: b + description: + The standard B extension for bit manipulation instructions, as + ratified in the 20240411 version of the unprivileged ISA + specification. The B standard extension comprises instructions + provided by the Zba, Zbb, and Zbs extensions. + - const: v description: The standard V extension for vector operations, as ratified @@ -117,10 +118,62 @@ properties: - const: h description: - The standard H extension for hypervisors as ratified in the 20191213 - version of the privileged ISA specification. + The standard H extension for hypervisors as ratified in the RISC-V + Instruction Set Manual, Volume II Privileged Architecture, + Document Version 20211203. # multi-letter extensions, sorted alphanumerically + - const: sha + description: | + The standard Sha extension for augmented hypervisor extension as + ratified in RVA23 Profiles Version 1.0, with commit 0273f3c921b6 + ("rva23/rvb23 ratified"). + + Sha captures the full set of features that are mandated to be + supported along with the H extension. Sha comprises the following + extensions: H, Shcounterenw, Shgatpa, Shtvala, Shvsatpa, Shvstvala, + Shvstvecd, and Ssstateen. + + - const: shcounterenw + description: | + The standard Shcounterenw extension for support writable enables + in hcounteren for any supported counter, as ratified in RISC-V + Profiles Version 1.0, with commit b1d806605f87 ("Updated to + ratified state.") + + - const: shgatpa + description: | + The standard Shgatpa extension indicates that for each supported + virtual memory scheme SvNN supported in satp, the corresponding + hgatp SvNNx4 mode must be supported. The hgatp mode Bare must + also be supported. It is ratified in RISC-V Profiles Version 1.0, + with commit b1d806605f87 ("Updated to ratified state.") + + - const: shtvala + description: | + The standard Shtvala extension for htval be written with the + faulting guest physical address in all circumstances permitted by + the ISA. It is ratified in RISC-V Profiles Version 1.0, with + commit b1d806605f87 ("Updated to ratified state.") + + - const: shvsatpa + description: | + The standard Shvsatpa extension for vsatp supporting all translation + modes supported in satp, as ratified in RISC-V Profiles Version 1.0, + with commit b1d806605f87 ("Updated to ratified state.") + + - const: shvstvala + description: | + The standard Shvstvala extension for vstval provides all needed + values as ratified in RISC-V Profiles Version 1.0, with commit + b1d806605f87 ("Updated to ratified state.") + + - const: shvstvecd + description: | + The standard Shvstvecd extension for vstvec supporting Direct mode, + as ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87 + ("Updated to ratified state.") + - const: smaia description: | The standard Smaia supervisor-level extension for the advanced @@ -153,24 +206,62 @@ properties: behavioural changes to interrupts as frozen at commit ccbddab ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia. + - const: ssccptr + description: | + The standard Ssccptr extension for main memory (cacheability and + coherence) hardware page-table reads, as ratified in RISC-V + Profiles Version 1.0, with commit b1d806605f87 ("Updated to + ratified state.") + - const: sscofpmf description: | The standard Sscofpmf supervisor-level extension for count overflow and mode-based filtering as ratified at commit 01d1df0 ("Add ability to manually trigger workflow. (#2)") of riscv-count-overflow. + - const: sscounterenw + description: | + The standard Sscounterenw extension for support writable enables + in scounteren for any supported counter, as ratified in RISC-V + Profiles Version 1.0, with commit b1d806605f87 ("Updated to + ratified state.") + - const: ssnpm description: | The standard Ssnpm extension for next-mode pointer masking as ratified at commit d70011dde6c2 ("Update to ratified state") of riscv-j-extension. + - const: ssstateen + description: | + The standard Ssstateen extension for supervisor-mode view of the + state-enable extension, as ratified in RISC-V Profiles Version 1.0, + with commit b1d806605f87 ("Updated to ratified state.") + - const: sstc description: | The standard Sstc supervisor-level extension for time compare as ratified at commit 3f9ed34 ("Add ability to manually trigger workflow. (#2)") of riscv-time-compare. + - const: sstvala + description: | + The standard Sstvala extension for stval provides all needed values + as ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87 + ("Updated to ratified state.") + + - const: sstvecd + description: | + The standard Sstvecd extension for stvec supports Direct mode as + ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87 + ("Updated to ratified state.") + + - const: ssu64xl + description: | + The standard Ssu64xl extension for UXLEN=64 must be supported, as + ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87 + ("Updated to ratified state.") + - const: svade description: | The standard Svade supervisor-level extension for SW-managed PTE A/D @@ -202,20 +293,22 @@ properties: - const: svinval description: The standard Svinval supervisor-level extension for fine-grained - address-translation cache invalidation as ratified in the 20191213 - version of the privileged ISA specification. + address-translation cache invalidation as ratified in the RISC-V + Instruction Set Manual, Volume II Privileged Architecture, + Document Version 20211203. - const: svnapot description: The standard Svnapot supervisor-level extensions for napot - translation contiguity as ratified in the 20191213 version of the - privileged ISA specification. + translation contiguity as ratified in the RISC-V Instruction Set + Manual, Volume II Privileged Architecture, Document Version + 20211203. - const: svpbmt description: The standard Svpbmt supervisor-level extensions for page-based - memory types as ratified in the 20191213 version of the privileged - ISA specification. + memory types as ratified in the RISC-V Instruction Set Manual, + Volume II Privileged Architecture, Document Version 20211203. - const: svrsw60t59b description: @@ -230,6 +323,12 @@ properties: as ratified at commit 4a69197e5617 ("Update to ratified state") of riscv-svvptc. + - const: za64rs + description: + The standard Za64rs extension for reservation set size of at most + 64 bytes, as ratified in RISC-V Profiles Version 1.0, with commit + b1d806605f87 ("Updated to ratified state.") + - const: zaamo description: | The standard Zaamo extension for atomic memory operations as @@ -371,6 +470,27 @@ properties: in commit 64074bc ("Update version numbers for Zfh/Zfinx") of riscv-isa-manual. + - const: ziccamoa + description: + The standard Ziccamoa extension for main memory (cacheability and + coherence) must support all atomics in A, as ratified in RISC-V + Profiles Version 1.0, with commit b1d806605f87 ("Updated to + ratified state.") + + - const: ziccif + description: + The standard Ziccif extension for main memory (cacheability and + coherence) instruction fetch atomicity, as ratified in RISC-V + Profiles Version 1.0, with commit b1d806605f87 ("Updated to + ratified state.") + + - const: zicclsm + description: + The standard Zicclsm extension for main memory (cacheability and + coherence) must support misaligned loads and stores, as ratified + in RISC-V Profiles Version 1.0, with commit b1d806605f87 ("Updated + to ratified state.") + - const: ziccrse description: The standard Ziccrse extension which provides forward progress @@ -749,6 +869,42 @@ properties: then: contains: const: f + # B comprises Zba, Zbb, and Zbs + - if: + contains: + const: b + then: + allOf: + - contains: + const: zba + - contains: + const: zbb + - contains: + const: zbs + # Zba, Zbb, Zbs together require B + - if: + allOf: + - contains: + const: zba + - contains: + const: zbb + - contains: + const: zbs + then: + contains: + const: b + # Za64rs and Ziccrse depend on Zalrsc or A + - if: + contains: + anyOf: + - const: za64rs + - const: ziccrse + then: + oneOf: + - contains: + const: zalrsc + - contains: + const: a # Zcb depends on Zca - if: contains: @@ -790,6 +946,16 @@ properties: then: contains: const: f + # Ziccamoa depends on Zaamo or A + - if: + contains: + const: ziccamoa + then: + oneOf: + - contains: + const: zaamo + - contains: + const: a # Zvfbfmin depends on V or Zve32f - if: contains: diff --git a/Documentation/devicetree/bindings/riscv/spacemit.yaml b/Documentation/devicetree/bindings/riscv/spacemit.yaml index 9c49482002f7..b958b94a924d 100644 --- a/Documentation/devicetree/bindings/riscv/spacemit.yaml +++ b/Documentation/devicetree/bindings/riscv/spacemit.yaml @@ -7,6 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: SpacemiT SoC-based boards maintainers: + - Guodong Xu <guodong@riscstar.com> - Yangyu Chen <cyy@cyyself.name> - Yixun Lan <dlan@gentoo.org> @@ -26,6 +27,10 @@ properties: - xunlong,orangepi-r2s - xunlong,orangepi-rv2 - const: spacemit,k1 + - items: + - enum: + - spacemit,k3-pico-itx + - const: spacemit,k3 additionalProperties: true diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml index 9253aab21518..8ba0e10b529a 100644 --- a/Documentation/devicetree/bindings/riscv/starfive.yaml +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml @@ -41,6 +41,7 @@ properties: - starfive,visionfive-2-lite - starfive,visionfive-2-lite-emmc - const: starfive,jh7110s + - const: starfive,jh7110 additionalProperties: true diff --git a/Documentation/devicetree/bindings/rng/samsung,exynos5250-trng.yaml b/Documentation/devicetree/bindings/rng/samsung,exynos5250-trng.yaml index 1a71935d8a19..699831927932 100644 --- a/Documentation/devicetree/bindings/rng/samsung,exynos5250-trng.yaml +++ b/Documentation/devicetree/bindings/rng/samsung,exynos5250-trng.yaml @@ -12,9 +12,13 @@ maintainers: properties: compatible: - enum: - - samsung,exynos5250-trng - - samsung,exynos850-trng + oneOf: + - enum: + - samsung,exynos5250-trng + - samsung,exynos850-trng + - items: + - const: google,gs101-trng + - const: samsung,exynos850-trng clocks: minItems: 1 @@ -24,6 +28,9 @@ properties: minItems: 1 maxItems: 2 + power-domains: + maxItems: 1 + reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/soc/altera/altr,sys-mgr.yaml b/Documentation/devicetree/bindings/soc/altera/altr,sys-mgr.yaml index d56ff4c05ae5..2dd3395f3f63 100644 --- a/Documentation/devicetree/bindings/soc/altera/altr,sys-mgr.yaml +++ b/Documentation/devicetree/bindings/soc/altera/altr,sys-mgr.yaml @@ -13,7 +13,9 @@ properties: compatible: oneOf: - description: Cyclone5/Arria5/Arria10 - const: altr,sys-mgr + items: + - const: altr,sys-mgr + - const: syscon - description: Stratix10 SoC items: - const: altr,sys-mgr-s10 @@ -45,7 +47,7 @@ additionalProperties: false examples: - | sysmgr@ffd08000 { - compatible = "altr,sys-mgr"; + compatible = "altr,sys-mgr", "syscon"; reg = <0xffd08000 0x1000>; cpu1-start-addr = <0xffd080c4>; }; diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas,rzn1-gpioirqmux.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas,rzn1-gpioirqmux.yaml new file mode 100644 index 000000000000..1a31c11bc3b4 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,rzn1-gpioirqmux.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/renesas/renesas,rzn1-gpioirqmux.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/N1 SoCs GPIO Interrupt Multiplexer + +description: | + The Renesas RZ/N1 GPIO Interrupt Multiplexer multiplexes GPIO interrupt + lines to the interrupt controller available in the SoC. + + It selects up to 8 of the 96 GPIO interrupt lines available and connect them + to 8 output interrupt lines. + +maintainers: + - Herve Codina <herve.codina@bootlin.com> + +properties: + compatible: + items: + - enum: + - renesas,r9a06g032-gpioirqmux + - const: renesas,rzn1-gpioirqmux + + reg: + maxItems: 1 + + "#address-cells": + const: 0 + + "#interrupt-cells": + const: 1 + + interrupt-map-mask: + items: + - const: 0x7f + + interrupt-map: + description: | + Specifies the mapping from external GPIO interrupt lines to the output + interrupts. The array has up to 8 items defining the mapping related to + the output line 0 (GIC 103) up to the output line 7 (GIC 110). + + The child interrupt number set in arrays items is computed using the + following formula: + gpio_bank * 32 + gpio_number + with: + - gpio_bank: The GPIO bank number + - 0 for GPIO0A, + - 1 for GPIO1A, + - 2 for GPIO2A + - gpio_number: Number of the gpio in the bank (0..31) + minItems: 1 + maxItems: 8 + +required: + - compatible + - reg + - "#address-cells" + - "#interrupt-cells" + - interrupt-map-mask + - interrupt-map + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + gic: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <3>; + }; + + interrupt-controller@51000480 { + compatible = "renesas,r9a06g032-gpioirqmux", "renesas,rzn1-gpioirqmux"; + reg = <0x51000480 0x20>; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0x7f>; + interrupt-map = + <32 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* line 0, GPIO1A.0 */ + <89 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* line 1, GPIO2A.25 */ + <9 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; /* line 3, GPIO0A.9 */ + }; diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml index a6bb3093b10a..76ce7e98c10f 100644 --- a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml @@ -12,9 +12,10 @@ maintainers: properties: compatible: oneOf: + - enum: + - google,gs101-pmu - items: - enum: - - google,gs101-pmu - samsung,exynos3250-pmu - samsung,exynos4210-pmu - samsung,exynos4212-pmu diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index 0d3b8dc362ba..3bab40500df9 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -33,6 +33,7 @@ properties: - eswin,eic7700-clint # ESWIN EIC7700 - sifive,fu540-c000-clint # SiFive FU540 - spacemit,k1-clint # SpacemiT K1 + - spacemit,k3-clint # SpacemiT K3 - starfive,jh7100-clint # StarFive JH7100 - starfive,jh7110-clint # StarFive JH7110 - starfive,jh8100-clint # StarFive JH8100 diff --git a/Documentation/devicetree/bindings/tpm/tcg,tpm-tis-i2c.yaml b/Documentation/devicetree/bindings/tpm/tcg,tpm-tis-i2c.yaml index af7720dc4a12..fdd7fd874e01 100644 --- a/Documentation/devicetree/bindings/tpm/tcg,tpm-tis-i2c.yaml +++ b/Documentation/devicetree/bindings/tpm/tcg,tpm-tis-i2c.yaml @@ -33,6 +33,7 @@ properties: - infineon,slb9673 - nuvoton,npct75x - st,st33ktpm2xi2c + - st,st33tphf2ei2c - const: tcg,tpm-tis-i2c - description: TPM 1.2 and 2.0 chips with vendor-specific I²C interface diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index c7591b2aec2a..baaf826a9d38 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -158,6 +158,8 @@ patternProperties: description: Arctic Sand "^arcx,.*": description: arcx Inc. / Archronix Inc. + "^arduino,.*": + description: Arduino SRL "^argon40,.*": description: Argon 40 Technologies Limited "^ariaboard,.*": @@ -555,6 +557,8 @@ patternProperties: description: Exegin Technologies Limited "^ezchip,.*": description: EZchip Semiconductor + "^ezurio,.*": + description: Ezurio LLC "^facebook,.*": description: Facebook "^fairchild,.*": @@ -755,6 +759,8 @@ patternProperties: description: IEI Integration Corp. "^ifi,.*": description: Ingenieurburo Fur Ic-Technologie (I/F/I) + "^ifm,.*": + description: ifm electronic gmbh "^ilitek,.*": description: ILI Technology Corporation (ILITEK) "^imagis,.*": @@ -995,6 +1001,8 @@ patternProperties: description: Mustek Limited "^mediatek,.*": description: MediaTek Inc. + "^medion,.*": + description: Medion AG "^megachips,.*": description: MegaChips "^mele,.*": @@ -1697,6 +1705,8 @@ patternProperties: description: Theobroma Systems Design und Consulting GmbH "^turing,.*": description: Turing Machines, Inc. + "^tuxedo,.*": + description: TUXEDO Computers GmbH "^tyan,.*": description: Tyan Computer Corporation "^tyhx,.*": diff --git a/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml b/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml index 54f5311ed016..f2c4bc900e5f 100644 --- a/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml @@ -43,6 +43,7 @@ properties: - qcom,apss-wdt-sm6350 - qcom,apss-wdt-sm8150 - qcom,apss-wdt-sm8250 + - qcom,apss-wdt-x1e80100 - const: qcom,kpss-wdt - const: qcom,kpss-wdt deprecated: true diff --git a/Documentation/devicetree/bindings/watchdog/xlnx,versal-wwdt.yaml b/Documentation/devicetree/bindings/watchdog/xlnx,versal-wwdt.yaml index 14b069599740..fccfc785a077 100644 --- a/Documentation/devicetree/bindings/watchdog/xlnx,versal-wwdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/xlnx,versal-wwdt.yaml @@ -32,6 +32,9 @@ properties: clocks: maxItems: 1 + power-domains: + maxItems: 1 + required: - compatible - reg diff --git a/MAINTAINERS b/MAINTAINERS index 92193eacf888..df78ffb94176 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2947,6 +2947,7 @@ S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu.git F: Documentation/devicetree/bindings/arm/marvell/ F: arch/arm/boot/dts/marvell/armada* +F: arch/arm/boot/dts/marvell/db-falcon* F: arch/arm/boot/dts/marvell/kirkwood* F: arch/arm/configs/mvebu_*_defconfig F: arch/arm/mach-mvebu/ @@ -25738,7 +25739,7 @@ TEGRA NAND DRIVER M: Stefan Agner <stefan@agner.ch> M: Lucas Stach <dev@lynxeye.de> S: Maintained -F: Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt +F: Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.yaml F: drivers/mtd/nand/raw/tegra_nand.c TEGRA PWM DRIVER diff --git a/arch/arm/boot/dts/allwinner/sun4i-a10-dserve-dsrv9703c.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-dserve-dsrv9703c.dts index 63e77c05bfda..f2413ba6a858 100644 --- a/arch/arm/boot/dts/allwinner/sun4i-a10-dserve-dsrv9703c.dts +++ b/arch/arm/boot/dts/allwinner/sun4i-a10-dserve-dsrv9703c.dts @@ -112,7 +112,7 @@ &i2c1 { /* pull-ups and devices require AXP209 LDO3 */ - status = "failed"; + status = "fail"; }; &i2c2 { diff --git a/arch/arm/boot/dts/allwinner/sun4i-a10-pov-protab2-ips9.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-pov-protab2-ips9.dts index c32596947647..e0c7099015da 100644 --- a/arch/arm/boot/dts/allwinner/sun4i-a10-pov-protab2-ips9.dts +++ b/arch/arm/boot/dts/allwinner/sun4i-a10-pov-protab2-ips9.dts @@ -96,7 +96,7 @@ &i2c1 { /* pull-ups and devices require AXP209 LDO3 */ - status = "failed"; + status = "fail"; }; &i2c2 { diff --git a/arch/arm/boot/dts/allwinner/sun5i-a13-utoo-p66.dts b/arch/arm/boot/dts/allwinner/sun5i-a13-utoo-p66.dts index be486d28d04f..428cab5a0e90 100644 --- a/arch/arm/boot/dts/allwinner/sun5i-a13-utoo-p66.dts +++ b/arch/arm/boot/dts/allwinner/sun5i-a13-utoo-p66.dts @@ -102,6 +102,7 @@ /* The P66 uses a different EINT then the reference design */ interrupts = <6 9 IRQ_TYPE_EDGE_FALLING>; /* EINT9 (PG9) */ /* The icn8318 binding expects wake-gpios instead of power-gpios */ + /delete-property/ power-gpios; wake-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ touchscreen-size-x = <800>; touchscreen-size-y = <480>; diff --git a/arch/arm/boot/dts/allwinner/sun6i-a31-hummingbird.dts b/arch/arm/boot/dts/allwinner/sun6i-a31-hummingbird.dts index 5bce7a32651e..5dfd36e3a49d 100644 --- a/arch/arm/boot/dts/allwinner/sun6i-a31-hummingbird.dts +++ b/arch/arm/boot/dts/allwinner/sun6i-a31-hummingbird.dts @@ -170,7 +170,7 @@ &i2c0 { /* pull-ups and devices require AXP221 DLDO3 */ - status = "failed"; + status = "fail"; }; &i2c1 { diff --git a/arch/arm/boot/dts/allwinner/sun6i-a31s-primo81.dts b/arch/arm/boot/dts/allwinner/sun6i-a31s-primo81.dts index b32b70ada7fd..fefd887fbc39 100644 --- a/arch/arm/boot/dts/allwinner/sun6i-a31s-primo81.dts +++ b/arch/arm/boot/dts/allwinner/sun6i-a31s-primo81.dts @@ -90,7 +90,7 @@ &i2c0 { /* pull-ups and device VDDIO use AXP221 DLDO3 */ - status = "failed"; + status = "fail"; }; &i2c1 { diff --git a/arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi b/arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi index c7181308ae6f..424f4a2487e2 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi +++ b/arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi @@ -4,6 +4,7 @@ #define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/thermal/thermal.h> #include <riscv/allwinner/sunxi-d1s-t113.dtsi> #include <riscv/allwinner/sunxi-d1-t113.dtsi> @@ -20,6 +21,7 @@ reg = <0>; clocks = <&ccu CLK_CPUX>; clock-names = "cpu"; + #cooling-cells = <2>; }; cpu1: cpu@1 { @@ -28,6 +30,7 @@ reg = <1>; clocks = <&ccu CLK_CPUX>; clock-names = "cpu"; + #cooling-cells = <2>; }; }; @@ -56,4 +59,34 @@ <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; interrupt-affinity = <&cpu0>, <&cpu1>; }; + + thermal-zones { + cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths>; + + cooling-maps { + map0 { + trip = <&cpu_alert>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu_alert: cpu-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-crit { + temperature = <100000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; }; diff --git a/arch/arm/boot/dts/amlogic/meson.dtsi b/arch/arm/boot/dts/amlogic/meson.dtsi index 28ec2c821cdc..6792377b2841 100644 --- a/arch/arm/boot/dts/amlogic/meson.dtsi +++ b/arch/arm/boot/dts/amlogic/meson.dtsi @@ -12,11 +12,6 @@ #size-cells = <1>; interrupt-parent = <&gic>; - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&saradc 8>; - }; - soc { compatible = "simple-bus"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/arm/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/arm/vexpress-v2m-rs1.dtsi index 158b3923eae3..248b8e492d43 100644 --- a/arch/arm/boot/dts/arm/vexpress-v2m-rs1.dtsi +++ b/arch/arm/boot/dts/arm/vexpress-v2m-rs1.dtsi @@ -420,7 +420,7 @@ compatible = "arm,vexpress,config-bus"; arm,vexpress,config-bridge = <&v2m_sysreg>; - oscclk0 { + clock-controller-0 { /* MCC static memory clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 0>; @@ -429,7 +429,7 @@ clock-output-names = "v2m:oscclk0"; }; - v2m_oscclk1: oscclk1 { + v2m_oscclk1: clock-controller-1 { /* CLCD clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 1>; @@ -438,7 +438,7 @@ clock-output-names = "v2m:oscclk1"; }; - v2m_oscclk2: oscclk2 { + v2m_oscclk2: clock-controller-2 { /* IO FPGA peripheral clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 2>; @@ -447,7 +447,7 @@ clock-output-names = "v2m:oscclk2"; }; - volt-vio { + regulator-vio { /* Logic level voltage */ compatible = "arm,vexpress-volt"; arm,vexpress-sysreg,func = <2 0>; diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/Makefile index 9adf9278dc94..20e5b64280a5 100644 --- a/arch/arm/boot/dts/aspeed/Makefile +++ b/arch/arm/boot/dts/aspeed/Makefile @@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-ampere-mtjefferson.dtb \ aspeed-bmc-ampere-mtmitchell.dtb \ aspeed-bmc-arm-stardragon4800-rep2.dtb \ + aspeed-bmc-asrock-altrad8.dtb \ aspeed-bmc-asrock-e3c246d4i.dtb \ aspeed-bmc-asrock-e3c256d4i.dtb \ aspeed-bmc-asrock-romed8hm3.dtb \ @@ -17,6 +18,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-asus-x4tf.dtb \ aspeed-bmc-bytedance-g220a.dtb \ aspeed-bmc-delta-ahe50dc.dtb \ + aspeed-bmc-facebook-anacapa.dtb \ aspeed-bmc-facebook-bletchley.dtb \ aspeed-bmc-facebook-catalina.dtb \ aspeed-bmc-facebook-clemente.dtb \ @@ -58,6 +60,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-lenovo-hr855xg2.dtb \ aspeed-bmc-microsoft-olympus.dtb \ aspeed-bmc-nvidia-gb200nvl-bmc.dtb \ + aspeed-bmc-nvidia-msx4-bmc.dtb \ aspeed-bmc-opp-lanyang.dtb \ aspeed-bmc-opp-mowgli.dtb \ aspeed-bmc-opp-nicole.dtb \ diff --git a/arch/arm/boot/dts/aspeed/aspeed-ast2600-evb.dts b/arch/arm/boot/dts/aspeed/aspeed-ast2600-evb.dts index de83c0eb1d6e..3f2ca9da0be2 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-ast2600-evb.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-ast2600-evb.dts @@ -205,6 +205,7 @@ &uart5 { // Workaround for A0 compatible = "snps,dw-apb-uart"; + /delete-property/ no-loopback-test; }; &i2c0 { @@ -314,9 +315,8 @@ status = "okay"; bus-width = <4>; max-frequency = <100000000>; - sdhci-drive-type = /bits/ 8 <3>; sdhci-caps-mask = <0x7 0x0>; - sdhci,wp-inverted; + wp-inverted; vmmc-supply = <&vcc_sdhci0>; vqmmc-supply = <&vccq_sdhci0>; clk-phase-sd-hs = <7>, <200>; @@ -326,9 +326,8 @@ status = "okay"; bus-width = <4>; max-frequency = <100000000>; - sdhci-drive-type = /bits/ 8 <3>; sdhci-caps-mask = <0x7 0x0>; - sdhci,wp-inverted; + wp-inverted; vmmc-supply = <&vcc_sdhci1>; vqmmc-supply = <&vccq_sdhci1>; clk-phase-sd-hs = <7>, <200>; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-altrad8.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-altrad8.dts new file mode 100644 index 000000000000..d4028312bdf2 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-altrad8.dts @@ -0,0 +1,637 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; + +#include "aspeed-g5.dtsi" +#include <dt-bindings/gpio/aspeed-gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/i2c/i2c.h> + +/ { + model = "ASRock ALTRAD8 BMC"; + compatible = "asrock,altrad8-bmc", "aspeed,ast2500"; + + aliases { + serial4 = &uart5; + i2c50 = &nvme1; + i2c51 = &pcie4; + i2c52 = &pcie5; + i2c53 = &pcie6; + i2c54 = &pcie7; + i2c55 = &nvme3; + i2c56 = &nvme2; + i2c57 = &nvme0; + i2c58 = &nvme4; + i2c59 = &nvme5; + i2c60 = &nvme6; + i2c61 = &nvme7; + i2c62 = &nvme8; + i2c63 = &nvme9; + i2c64 = &nvme10; + i2c65 = &nvme11; + }; + + chosen { + stdout-path = "uart5:115200n8"; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4> ,<&adc 5>, <&adc 6>, <&adc 7>, + <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>, + <&adc 12>, <&adc 13>, <&adc 14>, <&adc 15>; + }; + + leds { + compatible = "gpio-leds"; + + led-system-fault { + gpios = <&gpio ASPEED_GPIO(G,3) GPIO_ACTIVE_LOW>; + label = "platform:red:fault"; + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_FAULT; + }; + + led-heartbeat { + gpios = <&gpio ASPEED_GPIO(G,0) GPIO_ACTIVE_LOW>; + label = "platform:green:heartbeat"; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_INDICATOR; + linux,default-trigger = "timer"; + }; + + led-fan1-fault { + retain-state-shutdown; + default-state = "off"; + gpios = <&io_expander0 0 GPIO_ACTIVE_LOW>; + label = "fan1:red:fault"; + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_FAULT; + }; + + led-fan2-fault { + retain-state-shutdown; + default-state = "off"; + gpios = <&io_expander0 1 GPIO_ACTIVE_LOW>; + label = "fan2:red:fault"; + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_FAULT; + }; + + led-fan3-fault { + retain-state-shutdown; + default-state = "off"; + gpios = <&io_expander0 2 GPIO_ACTIVE_LOW>; + label = "fan3:red:fault"; + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_FAULT; + }; + + led-fan4-fault { + retain-state-shutdown; + default-state = "off"; + gpios = <&io_expander0 3 GPIO_ACTIVE_LOW>; + label = "fan4:red:fault"; + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_FAULT; + }; + + led-fan5-fault { + retain-state-shutdown; + default-state = "off"; + gpios = <&io_expander0 4 GPIO_ACTIVE_LOW>; + label = "fan5:red:fault"; + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_FAULT; + }; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gfx_memory: framebuffer { + compatible = "shared-dma-pool"; + size = <0x01000000>; + alignment = <0x01000000>; + reusable; + }; + + vga_memory: framebuffer@9f000000 { + no-map; + reg = <0x9f000000 0x01000000>; /* 16M */ + }; + + video_engine_memory: jpegbuffer { + compatible = "shared-dma-pool"; + size = <0x02000000>; /* 32M */ + alignment = <0x01000000>; + reusable; + }; + }; +}; + +&adc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default + &pinctrl_adc1_default + &pinctrl_adc2_default + &pinctrl_adc3_default + &pinctrl_adc4_default + &pinctrl_adc5_default + &pinctrl_adc6_default + &pinctrl_adc7_default + &pinctrl_adc8_default + &pinctrl_adc9_default + &pinctrl_adc10_default + &pinctrl_adc11_default + &pinctrl_adc12_default + &pinctrl_adc13_default + &pinctrl_adc14_default + &pinctrl_adc15_default>; +}; + +&fmc { + status = "okay"; + + flash@0 { + label = "bmc"; + m25p,fast-read; + spi-max-frequency = <50000000>; + status = "okay"; +#include "openbmc-flash-layout-64.dtsi" + }; +}; + +&gfx { + memory-region = <&gfx_memory>; + status = "okay"; +}; + +&gpio { + gpio-line-names = + /*A0-A7*/ "","","","bmc-ready","","","","", + /*B0-B7*/ "i2c-backup-sel","","","","","","","host0-shd-ack-n", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "button-power-n","control-power-n","button-reset-n", + "host0-sysreset-n","","","power-chassis-good","", + /*E0-E7*/ "","s0-vrd1-vddq0123-fault-n", + "s0-vrd1-vddq4567-fault-n","s0-vrd0-vddc-fault-n", + "s0-vrd3-p0v75-fault-n","","","", + /*F0-F7*/ "","","ps-atx-on-n","","","","","", + /*G0-G7*/ "led-bmc-heartbeat-n","button-identify-n","", + "led-system-fault-n","uboot-ready","bmc-salt2-n","","", + /*H0-H7*/ "ps-pwr-ok","","","","","","","", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "s0-hightemp-n","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "cpld-disable-bmc-n","","","","","s0-spi-auth-fail-n","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "","","","","","","","", + /*Q0-Q7*/ "","","","","","","led-identify-n", + "chassis-intrusion-n", + /*R0-R7*/ "","","ext-hightemp-n","spi0-program-sel","", + "output-hwm-bat-en","","", + /*S0-S7*/ "s0-vr-hot-n","","input-salt2-n","bmc-sysreset-n","","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "","","","s0-rtc-lock","","","","", + /*AA0-AA7*/ "s0-rtc-int-n","","","","","pmbus-sel-n","","", + /*AB0-AB7*/ "host0-reboot-ack-n","s0-sys-auth-failure-n", + "","","","","","", + /*AC0-AC7*/ "s0-fault-alert","host0-ready","s0-overtemp-n", + "","bmc-ok","host0-special-boot","presence-cpu0", + "host0-shd-req-n"; + + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + ipmb@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; + +}; + +&i2c1 { + status = "okay"; + + i2c-mux1@73 { + compatible = "nxp,pca9548"; + reg = <0x73>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + nvme1: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + pcie4: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + pcie5: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + pcie6: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + pcie7: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + nvme3: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + nvme2: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + nvme0: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + + i2c-mux2@75 { + compatible = "nxp,pca9548"; + reg = <0x75>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + nvme4: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + nvme5: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + nvme6: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + nvme7: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + nvme8: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + nvme9: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + nvme10: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + nvme11: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; +}; + +&i2c2 { + status = "okay"; + + smpro@4f { + compatible = "ampere,smpro"; + reg = <0x4f>; + }; +}; + +&i2c3 { + status = "okay"; + + // PSU FRU + eeprom@38 { + compatible = "atmel,24c02"; + reg = <0x38>; + }; +}; + +&i2c4 { + status = "okay"; + + temperature-sensor@29 { + compatible = "nuvoton,nct7802"; + reg = <0x29>; + + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { /* LTD */ + reg = <0>; + status = "okay"; + }; + + channel@1 { /* RTD1 */ + reg = <1>; + sensor-type = "temperature"; + temperature-mode = "thermistor"; + }; + + channel@2 { /* RTD2 */ + reg = <2>; + sensor-type = "temperature"; + temperature-mode = "thermal-diode"; + }; + }; + + temperature-sensor@4c { + compatible = "nuvoton,w83773g"; + reg = <0x4c>; + }; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; + + rtc@6f { + compatible = "isil,isl1208"; + reg = <0x6f>; + }; +}; + +&i2c7 { + status = "okay"; + + // BMC FRU + eeprom@57 { + compatible = "atmel,24c128"; + reg = <0x57>; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eth1_macaddress: macaddress@3f80 { + reg = <0x3f80 6>; + }; + + // The offset for eth0 really is at 0x3f88. + // eth0 and eth1 are swapped from what might be + // expected. + eth0_macaddress: macaddress@3f88 { + reg = <0x3f88 6>; + }; + }; + }; +}; + +&i2c8 { + status = "okay"; + + io_expander0: gpio@1c { + compatible = "nxp,pca9557"; + reg = <0x1c>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c9 { + status = "okay"; +}; + +&i2c10 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; +}; + +// Bus for accessing the SCP EEPROM +&i2c12 { + status = "okay"; +}; + +&i2c13 { + status = "okay"; + + ssif-bmc@10 { + compatible = "ssif-bmc"; + reg = <0x10>; + }; +}; + +// Connected to host Intel X550 (ALTRAD8UD-1L2T) or +// Broadcom BCM57414 (ALTRAD8UD2-1L2Q) interface. +// Unconnected on ALTRAD8UD-1L +&mac0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; + use-ncsi; + nvmem-cells = <ð0_macaddress>; + nvmem-cell-names = "mac-address"; + + status = "okay"; +}; + +// Connected to Realtek RTL8211E +&mac1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; + + nvmem-cells = <ð1_macaddress>; + nvmem-cell-names = "mac-address"; + + status = "okay"; +}; + +&pwm_tacho { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default + &pinctrl_pwm1_default + &pinctrl_pwm2_default + &pinctrl_pwm3_default + &pinctrl_pwm4_default + &pinctrl_pwm5_default + &pinctrl_pwm6_default + &pinctrl_pwm7_default>; + + status = "okay"; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00 0x08>; + }; + + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x01 0x09>; + }; + + fan@2 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x02 0x0a>; + }; + + fan@3 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x03 0x0b>; + }; + + fan@4 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x04 0x0c>; + }; + + fan@5 { + reg = <0x05>; + aspeed,fan-tach-ch = /bits/ 8 <0x05 0x0d>; + }; + + fan@6 { + reg = <0x06>; + aspeed,fan-tach-ch = /bits/ 8 <0x06 0x0e>; + }; + + fan@7 { + reg = <0x07>; + aspeed,fan-tach-ch = /bits/ 8 <0x07 0x0f>; + }; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + status = "okay"; + + // Host BIOS/UEFI EEPROM + flash@0 { + m25p,fast-read; + label = "pnor"; + spi-max-frequency = <100000000>; + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + tfa@400000 { + reg = <0x400000 0x200000>; + label = "pnor-tfa"; + }; + + uefi@600000 { + reg = <0x600000 0x1A00000>; + label = "pnor-uefi"; + }; + }; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default + &pinctrl_ncts1_default + &pinctrl_nrts1_default>; + + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd2_default + &pinctrl_rxd2_default>; + + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd3_default + &pinctrl_rxd3_default>; + + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd4_default + &pinctrl_rxd4_default>; + + status = "okay"; +}; + +// The BMC's uart +&uart5 { + status = "okay"; +}; + +&vhub { + status = "okay"; +}; + +&video { + memory-region = <&video_engine_memory>; + + status = "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts new file mode 100644 index 000000000000..221af858cb6b --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts @@ -0,0 +1,1045 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/dts-v1/; +#include "aspeed-g6.dtsi" +#include <dt-bindings/gpio/aspeed-gpio.h> +#include <dt-bindings/i2c/i2c.h> + +/ { + model = "Facebook Anacapa BMC"; + compatible = "facebook,anacapa-bmc", "aspeed,ast2600"; + + aliases { + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + i2c16 = &i2c0mux0ch0; + i2c17 = &i2c0mux0ch1; + i2c18 = &i2c0mux0ch2; + i2c19 = &i2c0mux0ch3; + i2c20 = &i2c1mux0ch0; + i2c21 = &i2c1mux0ch1; + i2c22 = &i2c1mux0ch2; + i2c23 = &i2c1mux0ch3; + i2c24 = &i2c4mux0ch0; + i2c25 = &i2c4mux0ch1; + i2c26 = &i2c4mux0ch2; + i2c27 = &i2c4mux0ch3; + i2c28 = &i2c4mux0ch4; + i2c29 = &i2c4mux0ch5; + i2c30 = &i2c4mux0ch6; + i2c31 = &i2c4mux0ch7; + i2c32 = &i2c8mux0ch0; + i2c33 = &i2c8mux0ch1; + i2c34 = &i2c8mux0ch2; + i2c35 = &i2c8mux0ch3; + i2c36 = &i2c10mux0ch0; + i2c37 = &i2c10mux0ch1; + i2c38 = &i2c10mux0ch2; + i2c39 = &i2c10mux0ch3; + i2c40 = &i2c10mux0ch4; + i2c41 = &i2c10mux0ch5; + i2c42 = &i2c10mux0ch6; + i2c43 = &i2c10mux0ch7; + i2c44 = &i2c11mux0ch0; + i2c45 = &i2c11mux0ch1; + i2c46 = &i2c11mux0ch2; + i2c47 = &i2c11mux0ch3; + i2c48 = &i2c11mux0ch4; + i2c49 = &i2c11mux0ch5; + i2c50 = &i2c11mux0ch6; + i2c51 = &i2c11mux0ch7; + i2c52 = &i2c13mux0ch0; + i2c53 = &i2c13mux0ch1; + i2c54 = &i2c13mux0ch2; + i2c55 = &i2c13mux0ch3; + i2c56 = &i2c13mux0ch4; + i2c57 = &i2c13mux0ch5; + i2c58 = &i2c13mux0ch6; + i2c59 = &i2c13mux0ch7; + }; + + chosen { + stdout-path = "serial4:57600n8"; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>, + <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>, + <&adc1 2>; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + label = "bmc_heartbeat_amber"; + gpios = <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + + led-1 { + label = "fp_id_amber"; + default-state = "off"; + gpios = <&gpio0 ASPEED_GPIO(B, 5) GPIO_ACTIVE_HIGH>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + video_engine_memory: video { + size = <0x02c00000>; + alignment = <0x00100000>; + compatible = "shared-dma-pool"; + reusable; + }; + + gfx_memory: framebuffer { + size = <0x01000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + }; + + p3v3_bmc_aux: regulator-p3v3-bmc-aux { + compatible = "regulator-fixed"; + regulator-name = "p3v3_bmc_aux"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + spi_gpio: spi { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + sck-gpios = <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio0 ASPEED_GPIO(Z, 5) GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>; + num-chipselects = <1>; + status = "okay"; + + tpm@0 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + spi-max-frequency = <33000000>; + reg = <0>; + }; + }; +}; + +&adc0 { + aspeed,int-vref-microvolt = <2500000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default + &pinctrl_adc2_default &pinctrl_adc3_default + &pinctrl_adc4_default &pinctrl_adc5_default + &pinctrl_adc6_default &pinctrl_adc7_default>; + status = "okay"; +}; + +&adc1 { + aspeed,int-vref-microvolt = <2500000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc10_default>; + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&fmc { + status = "okay"; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout-128.dtsi" + }; + + flash@1 { + status = "okay"; + m25p,fast-read; + label = "alt-bmc"; + spi-max-frequency = <50000000>; + }; +}; + +&gfx { + status = "okay"; + memory-region = <&gfx_memory>; +}; + +&gpio0 { + gpio-line-names = + + /*A0-A7*/ + "","","","","","","","", + + /*B0-B7*/ + "BATTERY_DETECT", "", "", "BMC_READY", + "", "FM_ID_LED", "", "", + + /*C0-C7*/ + "","","","","","","","", + + /*D0-D7*/ + "","","","","","","","", + + /*E0-E7*/ + "","","","","","","","", + + /*F0-F7*/ + "","","","","","","","", + + /*G0-G7*/ + "FM_MUX1_SEL", "", "", "", + "", "", "FM_DEBUG_PORT_PRSNT_N", "FM_BMC_DBP_PRESENT_N", + + /*H0-H7*/ + "","","","","","","","", + + /*I0-I7*/ + "", "", "", "", + "", "FLASH_WP_STATUS", "BMC_JTAG_MUX_SEL", "", + + /*J0-J7*/ + "","","","","","","","", + + /*K0-K7*/ + "","","","","","","","", + + /*L0-L7*/ + "","","","","","","","", + + /*M0-M7*/ + "", "BMC_FRU_WP", "", "", + "", "", "", "", + + /*N0-N7*/ + "LED_POSTCODE_0", "LED_POSTCODE_1", "LED_POSTCODE_2", "LED_POSTCODE_3", + "LED_POSTCODE_4", "LED_POSTCODE_5", "LED_POSTCODE_6", "LED_POSTCODE_7", + + /*O0-O7*/ + "","","","","","","","", + + /*P0-P7*/ + "PWR_BTN_BMC_BUF_N", "", "ID_RST_BTN_BMC_N", "", + "PWR_LED", "", "", "BMC_HEARTBEAT_N", + + /*Q0-Q7*/ + "","","","","","","","", + + /*R0-R7*/ + "","","","","","","","", + + /*S0-S7*/ + "", "", "SYS_BMC_PWRBTN_N", "", + "", "", "", "RUN_POWER_FAULT", + + /*T0-T7*/ + "","","","","","","","", + + /*U0-U7*/ + "","","","","","","","", + + /*V0-V7*/ + "","","","","","","","", + + /*W0-W7*/ + "","","","","","","","", + + /*X0-X7*/ + "","","","","","","","", + + /*Y0-Y7*/ + "","","","","","","","", + + /*Z0-Z7*/ + "SPI_BMC_TPM_CS2_N", "", "", "SPI_BMC_TPM_CLK", + "SPI_BMC_TPM_MOSI", "SPI_BMC_TPM_MISO", "", ""; +}; + +&gpio1 { + gpio-line-names = + /*18A0-18A7*/ + "","","","","","","","", + + /*18B0-18B7*/ + "","","","", + "FM_BOARD_BMC_REV_ID0", "FM_BOARD_BMC_REV_ID1", + "FM_BOARD_BMC_REV_ID2", "", + + /*18C0-18C7*/ + "","","","","","","","", + + /*18D0-18D7*/ + "","","","","","","","", + + /*18E0-18E3*/ + "FM_BMC_PROT_LS_EN", "AC_PWR_BMC_BTN_N", "", ""; +}; + +// L Bridge Board +&i2c0 { + status = "okay"; + + i2c-mux@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c0mux0ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c0mux0ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c0mux0ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c0mux0ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +// R Bridge Board +&i2c1 { + status = "okay"; + + i2c-mux@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c1mux0ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c1mux0ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c1mux0ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c1mux0ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +// MB - E1.S +&i2c4 { + status = "okay"; + + i2c-mux@70 { + compatible = "nxp,pca9548"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c4mux0ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c4mux0ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c4mux0ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c4mux0ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c4mux0ch4: i2c@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c4mux0ch5: i2c@5 { + reg = <5>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c4mux0ch6: i2c@6 { + reg = <6>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c4mux0ch7: i2c@7 { + reg = <7>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +// AMC +&i2c5 { + status = "okay"; +}; + +// MB +&i2c6 { + status = "okay"; + + // HPM FRU + eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + }; +}; + +// SCM +&i2c7 { + status = "okay"; + + +}; + +// MB - PDB +&i2c8 { + status = "okay"; + + i2c-mux@72 { + compatible = "nxp,pca9546"; + reg = <0x72>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c8mux0ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + adc@1f { + compatible = "ti,adc128d818"; + reg = <0x1f>; + ti,mode = /bits/ 8 <1>; + }; + + gpio@22 { + compatible = "nxp,pca9555"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "RPDB_FAN_FULL_SPEED_R_N", "RPDB_I2C_TEMP75_U8_ALERT_R_N", + "RPDB_I2C_TMP432_U29_ALERT_R_N", "RPDB_GLOBAL_WP", + "RPDB_FAN_CT_FAN_FAIL_R_N", "", + "", "", + "RPDB_ALERT_P50V_HSC2_R_N", "RPDB_ALERT_P50V_HSC3_R_N", + "RPDB_ALERT_P50V_HSC4_R_N", "RPDB_ALERT_P50V_STBY_R_N", + "RPDB_I2C_P12V_MB_VRM_ALERT_R_N", + "RPDB_I2C_P12V_STBY_VRM_ALERT_R_N", + "RPDB_PGD_P3V3_STBY_PWRGD_R", + "RPDB_P12V_STBY_VRM_PWRGD_BUF_R"; + }; + + gpio@24 { + compatible = "nxp,pca9555"; + reg = <0x24>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "RPDB_EAM2_PRSNT_MOS_N_R", "RPDB_EAM3_PRSNT_MOS_N_R", + "RPDB_PWRGD_P50V_HSC4_SYS_R", + "RPDB_PWRGD_P50V_STBY_SYS_BUF_R", + "RPDB_P50V_FAN1_R2_PG", "RPDB_P50V_FAN2_R2_PG", + "RPDB_P50V_FAN3_R2_PG", "RPDB_P50V_FAN4_R2_PG", + "", "RPDB_FAN1_PRSNT_N_R", + "", "RPDB_FAN2_PRSNT_N_R", + "RPDB_FAN3_PRSNT_N_R", "RPDB_FAN4_PRSNT_N_R", + "", ""; + }; + + // R-PDB FRU + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; + }; + i2c8mux0ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + gpio@22 { + compatible = "nxp,pca9555"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "LPDB_FAN_FULL_SPEED_R_N","LPDB_I2C_TEMP75_U8_ALERT_R_N", + "LPDB_I2C_TMP432_U29_ALERT_R_N","LPDB_GLOBAL_WP", + "LPDB_FAN_CT_FAN_FAIL_R_N","", + "","", + "LPDB_ALERT_P50V_HSC0_R_N","LPDB_ALERT_P50V_HSC1_R_N", + "LPDB_ALERT_P50V_HSC5_R_N","LPDB_I2C_P12V_SW_VRM_ALERT_R_N", + "LPDB_EAM0_PRSNT_MOS_N_R","LPDB_EAM1_PRSNT_MOS_N_R", + "LPDB_PWRGD_P50V_HSC5_SYS_R",""; + }; + + gpio@24 { + compatible = "nxp,pca9555"; + reg = <0x24>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "LPDB_P50V_FAN1_R2_PG","LPDB_P50V_FAN2_R2_PG", + "LPDB_P50V_FAN3_R2_PG","LPDB_P50V_FAN4_R2_PG", + "LPDB_P50V_FAN5_R2_PG","LPDB_FAN1_PRSNT_N_R", + "LPDB_FAN2_PRSNT_N_R","LPDB_FAN3_PRSNT_N_R", + "LPDB_FAN4_PRSNT_N_R","LPDB_FAN5_PRSNT_N_R", + "","", + "","", + "",""; + }; + + // L-PDB FRU + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; + }; + i2c8mux0ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c8mux0ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +// SCM +&i2c9 { + status = "okay"; + + // SCM FRU + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; + + // BSM FRU + eeprom@56 { + compatible = "atmel,24c64"; + reg = <0x56>; + }; +}; + +// R Bridge Board +&i2c10 { + status = "okay"; + + i2c-mux@71 { + compatible = "nxp,pca9548"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c10mux0ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c10mux0ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c10mux0ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c10mux0ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c10mux0ch4: i2c@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c10mux0ch5: i2c@5 { + reg = <5>; + #address-cells = <1>; + #size-cells = <0>; + + gpio@22 { + compatible = "nxp,pca9555"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "","", + "","RBB_CPLD_REFRESH_IN_PRGRS_R_L", + "RBB_EAM0_NIC_CBL_PRSNT_R_L","RBB_EAM1_NIC_CBL_PRSNT_R_L", + "RBB_AINIC_JTAG_MUX_R2_SEL","RBB_SPI_MUX0_R2_SEL", + "RBB_AINIC_PRSNT_R_L","RBB_AINIC_OE_R_N", + "RBB_AINIC_BOARD_R2_ID","RBB_RST_USB2_HUB_R_N", + "RBB_RST_FT4222_R_N","RBB_RST_MCP2210_R_N", + "",""; + }; + + // R Bridge Board FRU + eeprom@52 { + compatible = "atmel,24c256"; + reg = <0x52>; + }; + }; + i2c10mux0ch6: i2c@6 { + reg = <6>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c10mux0ch7: i2c@7 { + reg = <7>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +// L Bridge Board +&i2c11 { + status = "okay"; + + i2c-mux@71 { + compatible = "nxp,pca9548"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c11mux0ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c11mux0ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c11mux0ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c11mux0ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c11mux0ch4: i2c@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c11mux0ch5: i2c@5 { + reg = <5>; + #address-cells = <1>; + #size-cells = <0>; + + gpio@22 { + compatible = "nxp,pca9555"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "","", + "","LBB_CPLD_REFRESH_IN_PRGRS_R_L", + "LBB_EAM0_NIC_CBL_PRSNT_R_L","LBB_EAM1_NIC_CBL_PRSNT_R_L", + "LBB_AINIC_JTAG_MUX_R2_SEL","LBB_SPI_MUX0_R2_SEL", + "LBB_AINIC_PRSNT_R_L","LBB_AINIC_OE_R_N", + "LBB_AINIC_BOARD_R2_ID","LBB_RST_USB2_HUB_R_N", + "LBB_RST_FT4222_R_N","LBB_RST_MCP2210_R_N", + "",""; + }; + + // L Bridge Board FRU + eeprom@52 { + compatible = "atmel,24c256"; + reg = <0x52>; + }; + }; + i2c11mux0ch6: i2c@6 { + reg = <6>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c11mux0ch7: i2c@7 { + reg = <7>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +// Debug Card +&i2c12 { + status = "okay"; +}; + +// MB +&i2c13 { + status = "okay"; + + i2c-mux@70 { + compatible = "nxp,pca9548"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c13mux0ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c13mux0ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c13mux0ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c13mux0ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + adc@1f { + compatible = "ti,adc128d818"; + reg = <0x1f>; + ti,mode = /bits/ 8 <1>; + }; + }; + i2c13mux0ch4: i2c@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + + // HPM BRD ID FRU + eeprom@51 { + compatible = "atmel,24c256"; + reg = <0x51>; + }; + }; + i2c13mux0ch5: i2c@5 { + reg = <5>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c13mux0ch6: i2c@6 { + reg = <6>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c13mux0ch7: i2c@7 { + reg = <7>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +// SCM +&i2c14 { + status = "okay"; +}; + +&i2c15 { + status = "okay"; +}; + +&kcs2 { + aspeed,lpc-io-reg = <0xca8>; + status = "okay"; +}; + +&kcs3 { + aspeed,lpc-io-reg = <0xca2>; + status = "okay"; +}; + +&lpc_ctrl { + status = "okay"; +}; + +&mac2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ncsi3_default>; + use-ncsi; +}; + +&sgpiom0 { + ngpios = <128>; + bus-frequency = <2000000>; + gpio-line-names = + /*in - out - in - out */ + /* A0-A7 line 0-15 */ + "", "FM_CPU0_SYS_RESET_N", "", "CPU0_KBRST_N", + "", "FM_CPU0_PROCHOT_trigger_N", "", "FM_CLR_CMOS_R_P0", + "", "Force_I3C_SEL", "", "SYSTEM_Force_Run_AC_Cycle", + "", "", "", "", + + /* B0-B7 line 16-31 */ + "Channel0_leakage_EAM3", "FM_CPU_FPGA_JTAG_MUX_SEL", + "Channel1_leakage_EAM0", "FM_SCM_JTAG_MUX_SEL", + "Channel2_leakage_Manifold1", "FM_BRIDGE_JTAG_MUX_SEL", + "Channel3_leakage", "FM_CPU0_NMI_SYNC_FLOOD_N", + "Channel4_leakage_Manifold2", "", + "Channel5_leakage_EAM1", "", + "Channel6_leakage_CPU_DIMM", "", + "Channel7_leakage_EAM2", "", + + /* C0-C7 line 32-47 */ + "RSVD_RMC_GPIO3", "", "", "", + "", "", "", "", + "LEAK_DETECT_RMC_N", "", "", "", + "", "", "", "", + + /* D0-D7 line 48-63 */ + "PWRGD_PDB_EAMHSC0_CPLD_PG_R", "", + "PWRGD_PDB_EAMHSC1_CPLD_PG_R", "", + "PWRGD_PDB_EAMHSC2_CPLD_PG_R", "", + "PWRGD_PDB_EAMHSC3_CPLD_PG_R", "", + "AMC_BRD_PRSNT_CPLD_L", "", "", "", + "", "", "", "", + + /* E0-E7 line 64-79 */ + "AMC_PDB_EAMHSC0_CPLD_EN_R", "", + "AMC_PDB_EAMHSC1_CPLD_EN_R", "", + "AMC_PDB_EAMHSC2_CPLD_EN_R", "", + "AMC_PDB_EAMHSC3_CPLD_EN_R", "", + "", "", "", "", + "", "", "", "", + + /* F0-F7 line 80-95 */ + "PWRGD_PVDDCR_CPU1_P0", "SGPIO_READY", + "PWRGD_PVDDCR_CPU0_P0", "", + "", "", "", "", + "", "", "", "", + + /* G0-G7 line 96-111 */ + "PWRGD_PVDDCR_SOC_P0", "", + "PWRGD_PVDDIO_P0", "", + "PWRGD_PVDDIO_MEM_S3_P0", "", + "PWRGD_CHMP_CPU0_FPGA", "", + "PWRGD_CHIL_CPU0_FPGA", "", + "PWRGD_CHEH_CPU0_FPGA", "", + "PWRGD_CHAD_CPU0_FPGA", "FM_BMC_READY_PLD", + "", "", + + /* H0-H7 line 112-127 */ + "PWRGD_P3V3", "", + "P12V_DDR_IP_PWRGD_R", "", + "P12V_DDR_AH_PWRGD_R", "", + "PWRGD_P12V_VRM1_CPLD_PG_R", "", + "PWRGD_P12V_VRM0_CPLD_PG_R", "", + "PWRGD_PDB_HSC4_CPLD_PG_R", "", + "PWRGD_PVDD18_S5_P0_PG", "", + "PWRGD_PVDD33_S5_P0_PG", "", + + /* I0-I7 line 128-143 */ + "EAM0_BRD_PRSNT_R_L", "", + "EAM1_BRD_PRSNT_R_L", "", + "EAM2_BRD_PRSNT_R_L", "", + "EAM3_BRD_PRSNT_R_L", "", + "EAM0_CPU_MOD_PWR_GD_R", "", + "EAM1_CPU_MOD_PWR_GD_R", "", + "EAM2_CPU_MOD_PWR_GD_R", "", + "EAM3_CPU_MOD_PWR_GD_R", "", + + /* J0-J7 line 144-159 */ + "PRSNT_L_BIRDGE_R", "", + "PRSNT_R_BIRDGE_R", "", + "BRIDGE_L_MAIN_PG_R", "", + "BRIDGE_R_MAIN_PG_R", "", + "BRIDGE_L_STBY_PG_R", "", + "BRIDGE_R_STBY_PG_R", "", + "", "", "", "", + + /* K0-K7 line 160-175 */ + "ADC_I2C_ALERT_N", "", + "TEMP_I2C_ALERT_R_L", "", + "CPU0_VR_SMB_ALERT_CPLD_N", "", + "COVER_INTRUDER_R_N", "", + "HANDLE_INTRUDER_CPLD_N", "", + "IRQ_MCIO_CPLD_WAKE_R_N", "", + "APML_CPU0_ALERT_R_N", "", + "PDB_ALERT_R_N", "", + + /* L0-L7 line 176-191 */ + "CPU0_SP7R1", "", "CPU0_SP7R2", "", + "CPU0_SP7R3", "", "CPU0_SP7R4", "", + "CPU0_CORETYPE0", "", "CPU0_CORETYPE1", "", + "CPU0_CORETYPE2", "", "FM_BIOS_POST_CMPLT_R_N", "", + + /* M0-M7 line 192-207 */ + "EAM0_SMERR_CPLD_R_L", "", + "EAM1_SMERR_CPLD_R_L", "", + "EAM2_SMERR_CPLD_R_L", "", + "EAM3_SMERR_CPLD_R_L", "", + "CPU0_SMERR_N_R", "", + "CPU0_NV_SAVE_N_R", "", + "PDB_PWR_LOSS_CPLD_N", "", + "IRQ_BMC_SMI_ACTIVE_R_N", "", + + /* N0-N7 line 208-223 */ + "AMCROT_BMC_S5_RDY_R", "", + "AMC_RDY_R", "", + "AMC_STBY_PGOOD_R", "", + "CPU_AMC_SLP_S5_R_L", "", + "AMC_CPU_EAMPG_R", "", + "", "", "", "", + + /* O0-O7 line 224-239 */ + "HPM_PWR_FAIL", "Port80_b0", + "FM_DIMM_IP_FAIL", "Port80_b1", + "FM_DIMM_AH_FAIL", "Port80_b2", + "HPM_AMC_THERMTRIP_R_L", "Port80_b3", + "FM_CPU0_THERMTRIP_N", "Port80_b4", + "PVDDCR_SOC_P0_OCP_L", "Port80_b5", + "CPLD_SGPIO_RDY", "Port80_b6", + "", "Port80_b7", + + /* P0-P7 line 240-255 */ + "CPU0_SLP_S5_N_R", "NFC_VEN", + "CPU0_SLP_S3_N_R", "", + "FM_CPU0_PWRGD", "", + "PWRGD_RMC", "", + "FM_RST_CPU0_RESET_N", "", + "FM_PWRGD_CPU0_PWROK", "", + "wS5_PWR_Ready", "", + "wS0_ON_N", "PWRGD_P1V0_AUX"; + status = "okay"; +}; + +// BIOS Flash +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2_default>; + status = "okay"; + reg = <0x1e631000 0xc4>, <0x50000000 0x8000000>; + + flash@0 { + compatible = "jedec,spi-nor"; + label = "pnor"; + spi-max-frequency = <12000000>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; + status = "okay"; + }; +}; + +// HOST BIOS Debug +&uart1 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +// BMC Debug Console +&uart5 { + status = "okay"; +}; + +&uart_routing { + status = "okay"; +}; + +&uhci { + status = "okay"; +}; + +&vhub { + status = "okay"; + pinctrl-names = "default"; +}; + +&video { + status = "okay"; + memory-region = <&video_engine_memory>; +}; + +&wdt1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdtrst1_default>; + aspeed,reset-type = "soc"; + aspeed,external-signal; + aspeed,ext-push-pull; + aspeed,ext-active-high; + aspeed,ext-pulse-duration = <256>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts index 24969c82d05e..d1a04b63df9e 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts @@ -34,14 +34,14 @@ <&adc1 4>, <&adc1 5>, <&adc1 6>, <&adc1 7>; }; - spi1_gpio: spi1-gpio { + spi1_gpio: spi { compatible = "spi-gpio"; #address-cells = <1>; #size-cells = <0>; - gpio-sck = <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; - gpio-mosi = <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; - gpio-miso = <&gpio0 ASPEED_GPIO(Z, 5) GPIO_ACTIVE_HIGH>; + sck-gpios = <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio0 ASPEED_GPIO(Z, 5) GPIO_ACTIVE_HIGH>; num-chipselects = <1>; cs-gpios = <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>; @@ -54,7 +54,8 @@ front_gpio_leds { compatible = "gpio-leds"; - sys_log_id { + led-0 { + label = "sys_log_id"; default-state = "off"; gpios = <&front_leds 0 GPIO_ACTIVE_LOW>; }; @@ -62,42 +63,50 @@ fan_gpio_leds { compatible = "gpio-leds"; - fan0_blue { + led-0 { + label = "fan0_blue"; retain-state-shutdown; default-state = "on"; gpios = <&fan_leds 8 GPIO_ACTIVE_HIGH>; }; - fan1_blue { + led-1 { + label = "fan1_blue"; retain-state-shutdown; default-state = "on"; gpios = <&fan_leds 9 GPIO_ACTIVE_HIGH>; }; - fan2_blue { + led-2 { + label = "fan2_blue"; retain-state-shutdown; default-state = "on"; gpios = <&fan_leds 10 GPIO_ACTIVE_HIGH>; }; - fan3_blue { + led-3 { + label = "fan3_blue"; retain-state-shutdown; default-state = "on"; gpios = <&fan_leds 11 GPIO_ACTIVE_HIGH>; }; - fan0_amber { + led-4 { + label = "fan0_amber"; retain-state-shutdown; default-state = "off"; gpios = <&fan_leds 12 GPIO_ACTIVE_HIGH>; }; - fan1_amber { + led-5 { + label = "fan1_amber"; retain-state-shutdown; default-state = "off"; gpios = <&fan_leds 13 GPIO_ACTIVE_HIGH>; }; - fan2_amber { + led-6 { + label = "fan2_amber"; retain-state-shutdown; default-state = "off"; gpios = <&fan_leds 14 GPIO_ACTIVE_HIGH>; }; - fan3_amber { + led-7 { + label = "fan3_amber"; retain-state-shutdown; default-state = "off"; gpios = <&fan_leds 15 GPIO_ACTIVE_HIGH>; @@ -106,12 +115,14 @@ sled1_gpio_leds { compatible = "gpio-leds"; - sled1_amber { + led-0 { + label = "sled1_amber"; retain-state-shutdown; default-state = "keep"; gpios = <&sled1_leds 0 GPIO_ACTIVE_LOW>; }; - sled1_blue { + led-1 { + label = "sled1_blue"; retain-state-shutdown; default-state = "keep"; gpios = <&sled1_leds 1 GPIO_ACTIVE_LOW>; @@ -120,12 +131,14 @@ sled2_gpio_leds { compatible = "gpio-leds"; - sled2_amber { + led-0 { + label = "sled2_amber"; retain-state-shutdown; default-state = "keep"; gpios = <&sled2_leds 0 GPIO_ACTIVE_LOW>; }; - sled2_blue { + led-1 { + label = "sled2_blue"; retain-state-shutdown; default-state = "keep"; gpios = <&sled2_leds 1 GPIO_ACTIVE_LOW>; @@ -134,12 +147,14 @@ sled3_gpio_leds { compatible = "gpio-leds"; - sled3_amber { + led-0 { + label = "sled3_amber"; retain-state-shutdown; default-state = "keep"; gpios = <&sled3_leds 0 GPIO_ACTIVE_LOW>; }; - sled3_blue { + led-1 { + label = "sled3_blue"; retain-state-shutdown; default-state = "keep"; gpios = <&sled3_leds 1 GPIO_ACTIVE_LOW>; @@ -148,12 +163,14 @@ sled4_gpio_leds { compatible = "gpio-leds"; - sled4_amber { + led-0 { + label = "sled4_amber"; retain-state-shutdown; default-state = "keep"; gpios = <&sled4_leds 0 GPIO_ACTIVE_LOW>; }; - sled4_blue { + led-1 { + label = "sled4_blue"; retain-state-shutdown; default-state = "keep"; gpios = <&sled4_leds 1 GPIO_ACTIVE_LOW>; @@ -162,12 +179,14 @@ sled5_gpio_leds { compatible = "gpio-leds"; - sled5_amber { + led-0 { + label = "sled5_amber"; retain-state-shutdown; default-state = "keep"; gpios = <&sled5_leds 0 GPIO_ACTIVE_LOW>; }; - sled5_blue { + led-1 { + label = "sled5_blue"; retain-state-shutdown; default-state = "keep"; gpios = <&sled5_leds 1 GPIO_ACTIVE_LOW>; @@ -176,12 +195,14 @@ sled6_gpio_leds { compatible = "gpio-leds"; - sled6_amber { + led-0 { + label = "sled6_amber"; retain-state-shutdown; default-state = "keep"; gpios = <&sled6_leds 0 GPIO_ACTIVE_LOW>; }; - sled6_blue { + led-1 { + label = "sled6_blue"; retain-state-shutdown; default-state = "keep"; gpios = <&sled6_leds 1 GPIO_ACTIVE_LOW>; @@ -191,32 +212,32 @@ gpio-keys { compatible = "gpio-keys"; - presence-sled1 { + presence-sled1-switch { label = "presence-sled1"; gpios = <&gpio0 ASPEED_GPIO(H, 2) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(H, 2)>; }; - presence-sled2 { + presence-sled2-switch { label = "presence-sled2"; gpios = <&gpio0 ASPEED_GPIO(H, 3) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(H, 3)>; }; - presence-sled3 { + presence-sled3-switch { label = "presence-sled3"; gpios = <&gpio0 ASPEED_GPIO(H, 4) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(H, 4)>; }; - presence-sled4 { + presence-sled4-switch { label = "presence-sled4"; gpios = <&gpio0 ASPEED_GPIO(H, 5) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(H, 5)>; }; - presence-sled5 { + presence-sled5-switch { label = "presence-sled5"; gpios = <&gpio0 ASPEED_GPIO(H, 6) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(H, 6)>; }; - presence-sled6 { + presence-sled6-switch { label = "presence-sled6"; gpios = <&gpio0 ASPEED_GPIO(H, 7) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(H, 7)>; @@ -352,8 +373,6 @@ sled1_ioexp: pca9539@76 { compatible = "nxp,pca9539"; reg = <0x76>; - #address-cells = <1>; - #size-cells = <0>; gpio-controller; #gpio-cells = <2>; @@ -395,7 +414,6 @@ label = "USB-C"; pd-revision = /bits/ 8 <0x2 0x0 0x1 0x20>; power-role = "dual"; - try-power-role = "sink"; data-role = "dual"; source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; @@ -441,8 +459,6 @@ sled2_ioexp: pca9539@76 { compatible = "nxp,pca9539"; reg = <0x76>; - #address-cells = <1>; - #size-cells = <0>; gpio-controller; #gpio-cells = <2>; @@ -484,7 +500,6 @@ label = "USB-C"; pd-revision = /bits/ 8 <0x2 0x0 0x1 0x20>; power-role = "dual"; - try-power-role = "sink"; data-role = "dual"; source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; @@ -530,8 +545,6 @@ sled3_ioexp: pca9539@76 { compatible = "nxp,pca9539"; reg = <0x76>; - #address-cells = <1>; - #size-cells = <0>; gpio-controller; #gpio-cells = <2>; @@ -573,7 +586,6 @@ label = "USB-C"; pd-revision = /bits/ 8 <0x2 0x0 0x1 0x20>; power-role = "dual"; - try-power-role = "sink"; data-role = "dual"; source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; @@ -619,8 +631,6 @@ sled4_ioexp: pca9539@76 { compatible = "nxp,pca9539"; reg = <0x76>; - #address-cells = <1>; - #size-cells = <0>; gpio-controller; #gpio-cells = <2>; @@ -662,7 +672,6 @@ label = "USB-C"; pd-revision = /bits/ 8 <0x2 0x0 0x1 0x20>; power-role = "dual"; - try-power-role = "sink"; data-role = "dual"; source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; @@ -708,8 +717,6 @@ sled5_ioexp: pca9539@76 { compatible = "nxp,pca9539"; reg = <0x76>; - #address-cells = <1>; - #size-cells = <0>; gpio-controller; #gpio-cells = <2>; @@ -751,7 +758,6 @@ label = "USB-C"; pd-revision = /bits/ 8 <0x2 0x0 0x1 0x20>; power-role = "dual"; - try-power-role = "sink"; data-role = "dual"; source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; @@ -797,8 +803,6 @@ sled6_ioexp: pca9539@76 { compatible = "nxp,pca9539"; reg = <0x76>; - #address-cells = <1>; - #size-cells = <0>; gpio-controller; #gpio-cells = <2>; @@ -840,7 +844,6 @@ label = "USB-C"; pd-revision = /bits/ 8 <0x2 0x0 0x1 0x20>; power-role = "dual"; - try-power-role = "sink"; data-role = "dual"; source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; @@ -953,7 +956,6 @@ &i2c13 { multi-master; - aspeed,hw-timeout-ms = <1000>; status = "okay"; //USB Debug Connector @@ -1024,7 +1026,7 @@ }; &adc0 { - vref = <1800>; + aspeed,int-vref-microvolt = <2500000>; status = "okay"; pinctrl-names = "default"; @@ -1035,7 +1037,7 @@ }; &adc1 { - vref = <2500>; + aspeed,int-vref-microvolt = <2500000>; status = "okay"; pinctrl-names = "default"; @@ -1080,11 +1082,5 @@ &wdt1 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdtrst1_default>; aspeed,reset-type = "soc"; - aspeed,external-signal; - aspeed,ext-push-pull; - aspeed,ext-active-high; - aspeed,ext-pulse-duration = <256>; }; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts index 450446913e36..2aff21442f11 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts @@ -96,7 +96,12 @@ gpios = <&gpio0 ASPEED_GPIO(P, 5) (GPIO_ACTIVE_HIGH|GPIO_TRANSITORY)>; }; - led-hdd { + }; + + hdd-leds { + compatible = "gpio-leds"; + + led-0 { label = "hdd_led"; gpios = <&io_expander13 1 GPIO_ACTIVE_LOW>; }; @@ -311,6 +316,12 @@ #address-cells = <1>; #size-cells = <0>; reg = <0>; + + // HDD NVMe SSD FRU 0 + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + }; }; i2c0mux0ch1mux0ch1: i2c@1 { @@ -323,6 +334,12 @@ #address-cells = <1>; #size-cells = <0>; reg = <2>; + + // HDD NVMe SSD FRU 1 + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + }; }; i2c0mux0ch1mux0ch3: i2c@3 { @@ -493,6 +510,12 @@ #address-cells = <1>; #size-cells = <0>; reg = <0>; + + // HDD NVMe SSD FRU 2 + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + }; }; i2c0mux3ch1mux0ch1: i2c@1 { @@ -505,6 +528,12 @@ #address-cells = <1>; #size-cells = <0>; reg = <2>; + + // HDD NVMe SSD FRU 3 + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + }; }; i2c0mux3ch1mux0ch3: i2c@3 { @@ -619,6 +648,12 @@ #address-cells = <1>; #size-cells = <0>; reg = <1>; + + // BOOT DRIVE FRU + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + }; }; i2c0mux5ch2: i2c@2 { @@ -983,7 +1018,7 @@ "", "", "", - "", + "shdn_force_l_cpld", "", "", "", @@ -1258,10 +1293,6 @@ use-ncsi; }; -&udma { - status = "okay"; -}; - &uart1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts index 1c50e4a367b2..5602a502d07b 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts @@ -822,9 +822,13 @@ "irq-pvddcore1-ocp-alert","", "","", /*O4-O7 line 232-239*/ - "","","","","","","","", + "","","","", + "presence-lower-fanboard1","", + "presence-lower-fanboard2","", /*P0-P3 line 240-247*/ - "","","","","","","","", + "presence-upper-fanboard1","", + "presence-upper-fanboard2","", + "","","","", /*P4-P7 line 248-255*/ "","","","","","","",""; }; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-santabarbara.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-santabarbara.dts index f74f463cc878..0a3e2e241063 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-santabarbara.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-santabarbara.dts @@ -845,7 +845,14 @@ }; &i2c7 { + multi-master; status = "okay"; + + ipmb@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; }; &i2c8 { @@ -1328,6 +1335,20 @@ &i2c12 { status = "okay"; + gpio@27 { + compatible = "nxp,pca9555"; + reg = <0x27>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "PEX0_MODE_SEL1_R","PEX0_MODE_SEL2_R", + "PEX0_MODE_SEL3_R","PEX0_MODE_SEL4_R", + "","","","", + "UART_MUX_SEL","RST_SMB_NIC_R_N", + "RST_SMB_N","RST_CP2102N_N", + "SPI_MUX_SEL","","",""; + }; + // SWB FRU eeprom@52 { compatible = "atmel,24c64"; @@ -1758,11 +1779,11 @@ "","BIOS_DEBUG_MODE", /*H0-H3 line 112-119*/ "FM_IOEXP_U538_INT_N","", - "FM_IOEXP_U539_INT_N","", - "FM_IOEXP_U540_INT_N","", - "FM_IOEXP_U541_INT_N","", + "FM_IOEXP_U539_INT_N","FM_MODULE_PWR_EN_N_1B", + "FM_IOEXP_U540_INT_N","FM_MODULE_PWR_EN_N_2B", + "FM_IOEXP_U541_INT_N","FM_MODULE_PWR_EN_N_3B", /*H4-H7 line 120-127*/ - "FM_IOEXP_PDB2_U1003_INT_N","", + "FM_IOEXP_PDB2_U1003_INT_N","FM_MODULE_PWR_EN_N_4B", "","", "","", "FM_MAIN_PWREN_RMC_EN_ISO_R","", diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-everest.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-everest.dts index 5a0975d52492..561633d31039 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-everest.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-everest.dts @@ -2806,13 +2806,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; @@ -2823,13 +2823,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; @@ -2840,13 +2840,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; @@ -2857,13 +2857,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; }; @@ -3181,13 +3181,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; @@ -3198,13 +3198,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; @@ -3215,13 +3215,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; @@ -3232,13 +3232,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; }; @@ -3556,13 +3556,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; @@ -3573,13 +3573,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; @@ -3590,13 +3590,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; @@ -3607,13 +3607,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; }; @@ -3931,13 +3931,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; @@ -3948,13 +3948,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; @@ -3965,13 +3965,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; @@ -3982,13 +3982,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; }; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-msx4-bmc.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-msx4-bmc.dts new file mode 100644 index 000000000000..44f95a3986cb --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-msx4-bmc.dts @@ -0,0 +1,246 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "aspeed-g6.dtsi" +#include <dt-bindings/gpio/aspeed-gpio.h> +#include <dt-bindings/i2c/i2c.h> + +/ { + model = "AST2600 MSX4 BMC"; + compatible = "nvidia,msx4-bmc", "aspeed,ast2600"; + + aliases { + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + }; + + chosen { + stdout-path = "uart5:115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gfx_memory: framebuffer { + compatible = "shared-dma-pool"; + size = <0x01000000>; + alignment = <0x01000000>; + reusable; + }; + + video_engine_memory: jpegbuffer { + compatible = "shared-dma-pool"; + size = <0x02000000>; /* 32M */ + alignment = <0x01000000>; + reusable; + }; + }; +}; + +&ehci1 { + status = "okay"; +}; + +&fmc { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + label = "bmc"; + status = "okay"; + #include "openbmc-flash-layout-128.dtsi" + }; + + flash@1 { + compatible = "jedec,spi-nor"; + label = "alt-bmc"; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + status = "okay"; + }; +}; + +&gfx { + memory-region = <&gfx_memory>; + status = "okay"; +}; + +&gpio0 { + gpio-line-names = + /*A0-A7*/ "","","","","","","","", + /*B0-B7*/ "ASSERT_BMC_READY","","","","","","","", + /*C0-C7*/ "MON_PWR_GOOD","","","","","","","FP_ID_LED_N", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "","","","","","","","", + /*F0-F7*/ "","","","","","","","", + /*G0-G7*/ "","","FP_LED_STATUS_GREEN_N","FP_LED_STATUS_AMBER_N", + "","","","", + /*H0-H7*/ "","","","","","","","", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "MON_PWR_BTN_L","ASSERT_PWR_BTN_L","MON_RST_BTN_L", + "ASSERT_RST_BTN_L","","ASSERT_NMI_BTN_L","","", + /*Q0-Q7*/ "","","MEMORY_HOT_0","MEMORY_HOT_1","","","","", + /*R0-R7*/ "ID_BTN","","","","","VBAT_GPIO","","", + /*S0-S7*/ "","","RST_PCA_MUX","","","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "","","","","","","",""; +}; + +&gpio1 { + gpio-line-names = + /*18A0-18A7*/ "","","","","","","","", + /*18B0-18B7*/ "","","","","","","","", + /*18C0-18C7*/ "","","","","","","","", + /*18D0-18D7*/ "","","","","","","","", + /*18E0-18E3*/ "","","BMC_INIT_DONE",""; +}; + +// Devices on these busses are available after POST +// however there isn't a great way to defer probing +// until that point today, as the BMC doesn't +// have direct control over when the host completes +// POST, especially from the kernel. +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + + eeprom@51 { + compatible = "atmel,24c256"; + reg = <0x51>; + pagesize = <64>; + label = "sku"; + }; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c8 { + status = "okay"; +}; + +&i2c9 { + status = "okay"; +}; + +&i2c10 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; +}; + +&i2c12 { + status = "okay"; +}; + +&i2c13 { + status = "okay"; +}; + +&i2c15 { + status = "okay"; +}; + +&kcs1 { + aspeed,lpc-io-reg = <0xca0>; + status = "okay"; +}; + +&kcs2 { + aspeed,lpc-io-reg = <0xca8>; + status = "okay"; +}; + +&kcs3 { + aspeed,lpc-io-reg = <0xca2>; + status = "okay"; +}; + +&lpc_reset { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&sgpiom0 { + ngpios = <80>; + status = "okay"; +}; + +&uart_routing { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&video { + memory-region = <&video_engine_memory>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi index f8662c8ac089..189bc3bbb47c 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi @@ -68,13 +68,12 @@ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; - clocks = <&syscon ASPEED_CLK_HPLL>; arm,cpu-registers-not-fw-configured; always-on; }; edac: sdram@1e6e0000 { - compatible = "aspeed,ast2600-sdram-edac", "syscon"; + compatible = "aspeed,ast2600-sdram-edac"; reg = <0x1e6e0000 0x174>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; }; @@ -866,15 +865,6 @@ interrupt-controller; status = "disabled"; }; - - udma: dma-controller@1e79e000 { - compatible = "aspeed,ast2600-udma"; - reg = <0x1e79e000 0x1000>; - interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; - dma-channels = <28>; - #dma-cells = <1>; - status = "disabled"; - }; }; }; }; diff --git a/arch/arm/boot/dts/aspeed/ibm-power10-dual.dtsi b/arch/arm/boot/dts/aspeed/ibm-power10-dual.dtsi index 06fac236773f..79eaf442c5bf 100644 --- a/arch/arm/boot/dts/aspeed/ibm-power10-dual.dtsi +++ b/arch/arm/boot/dts/aspeed/ibm-power10-dual.dtsi @@ -88,13 +88,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; @@ -105,13 +105,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; @@ -122,13 +122,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; @@ -139,13 +139,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; }; @@ -257,13 +257,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; @@ -274,13 +274,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; @@ -291,13 +291,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; @@ -308,13 +308,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; }; diff --git a/arch/arm/boot/dts/aspeed/ibm-power10-quad.dtsi b/arch/arm/boot/dts/aspeed/ibm-power10-quad.dtsi index 9501f66d0030..a54be7d0af0b 100644 --- a/arch/arm/boot/dts/aspeed/ibm-power10-quad.dtsi +++ b/arch/arm/boot/dts/aspeed/ibm-power10-quad.dtsi @@ -739,13 +739,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; @@ -756,13 +756,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; @@ -773,13 +773,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; @@ -790,13 +790,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; }; @@ -1114,13 +1114,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; @@ -1131,13 +1131,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; @@ -1148,13 +1148,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; @@ -1165,13 +1165,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; }; diff --git a/arch/arm/boot/dts/broadcom/bcm2711.dtsi b/arch/arm/boot/dts/broadcom/bcm2711.dtsi index c06d9f5e53c8..5e3b4bb39396 100644 --- a/arch/arm/boot/dts/broadcom/bcm2711.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm2711.dtsi @@ -415,7 +415,7 @@ * The firmware will find whether the emmc2bus alias is defined, and if * so, it'll edit the dma-ranges property below accordingly. */ - emmc2bus: emmc2bus { + emmc2bus: emmc2-bus@fe000000 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <1>; @@ -542,7 +542,7 @@ }; }; - scb { + scb-bus@fc000000 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi index 35be14150f41..5dc8d33e8ad7 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi @@ -87,12 +87,13 @@ }; }; - base_fpga_region { + base_fpga_region: fpga-region { compatible = "fpga-region"; fpga-mgr = <&fpgamgr0>; #address-cells = <0x1>; #size-cells = <0x1>; + ranges; }; can0: can@ffc00000 { @@ -785,6 +786,9 @@ ocram: sram@ffff0000 { compatible = "mmio-sram"; reg = <0xffff0000 0x10000>; + #address-cells = <0x1>; + #size-cells = <0x1>; + ranges; }; qspi: spi@ff705000 { diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi index b108265e9bde..a53a94678df2 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi @@ -80,12 +80,13 @@ }; }; - base_fpga_region { + base_fpga_region: fpga-region { #address-cells = <0x1>; #size-cells = <0x1>; compatible = "fpga-region"; fpga-mgr = <&fpga_mgr>; + ranges; }; clkmgr@ffd04000 { @@ -686,6 +687,9 @@ ocram: sram@ffe00000 { compatible = "mmio-sram"; reg = <0xffe00000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; }; eccmgr: eccmgr { diff --git a/arch/arm/boot/dts/microchip/Makefile b/arch/arm/boot/dts/microchip/Makefile index 79cd38fdc7da..08986c24a470 100644 --- a/arch/arm/boot/dts/microchip/Makefile +++ b/arch/arm/boot/dts/microchip/Makefile @@ -102,4 +102,5 @@ dtb-$(CONFIG_SOC_LAN966) += \ lan966x-kontron-kswitch-d10-mmt-8g.dtb \ lan966x-pcb8290.dtb \ lan966x-pcb8291.dtb \ - lan966x-pcb8309.dtb + lan966x-pcb8309.dtb \ + lan966x-pcb8385.dtb diff --git a/arch/arm/boot/dts/microchip/lan966x-pcb8385.dts b/arch/arm/boot/dts/microchip/lan966x-pcb8385.dts new file mode 100644 index 000000000000..d18969275efe --- /dev/null +++ b/arch/arm/boot/dts/microchip/lan966x-pcb8385.dts @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * lan966x-pcb8385.dts - Device Tree file for PCB8385 + */ +/dts-v1/; + +#include "lan966x.dtsi" +#include "dt-bindings/phy/phy-lan966x-serdes.h" + +/ { + model = "Microchip EVB - LAN9668"; + compatible = "microchip,lan9668-pcb8385", "microchip,lan9668", "microchip,lan966"; + + aliases { + serial0 = &usart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpio 59 GPIO_ACTIVE_LOW>; + open-source; + priority = <200>; + }; + + leds { + compatible = "gpio-leds"; + + led-p1-green { + label = "cu0:green"; + gpios = <&sgpio_out 2 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-p1-yellow { + label = "cu0:yellow"; + gpios = <&sgpio_out 2 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-p2-green { + label = "cu1:green"; + gpios = <&sgpio_out 3 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-p2-yellow { + label = "cu1:yellow"; + gpios = <&sgpio_out 3 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; +}; + +&aes { + status = "reserved"; /* Reserved by secure OS */ +}; + +&flx0 { + atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>; + status = "okay"; +}; + +&flx3 { + atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>; + status = "okay"; +}; + +&gpio { + fc0_b_pins: fc0-b-pins { + /* SCL, SDA */ + pins = "GPIO_25", "GPIO_26"; + function = "fc0_b"; + }; + + fc3_b_pins: fc3-b-pins { + /* RX, TX */ + pins = "GPIO_52", "GPIO_53"; + function = "fc3_b"; + }; + + sgpio_a_pins: sgpio-a-pins { + /* SCK, D0, D1, LD */ + pins = "GPIO_32", "GPIO_33", "GPIO_34", "GPIO_35"; + function = "sgpio_a"; + }; +}; + +&i2c0 { + pinctrl-0 = <&fc0_b_pins>; + pinctrl-names = "default"; + dmas = <0>, <0>; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns = <35>; + i2c-sda-hold-time-ns = <1500>; + status = "okay"; + + eeprom@54 { + compatible = "atmel,24c01"; + reg = <0x54>; + }; + + eeprom@55 { + compatible = "atmel,24c01"; + reg = <0x55>; + }; +}; + +&sgpio { + pinctrl-0 = <&sgpio_a_pins>; + pinctrl-names = "default"; + microchip,sgpio-port-ranges = <0 3>; + status = "okay"; + + gpio@0 { + ngpios = <64>; + }; + gpio@1 { + ngpios = <64>; + }; +}; + +&usart3 { + pinctrl-0 = <&fc3_b_pins>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi index 868045c650a7..e21556f46384 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -414,10 +414,26 @@ dma-names = "tx", "rx"; atmel,use-dma-rx; atmel,use-dma-tx; + atmel,fifo-size = <32>; atmel,usart-mode = <AT91_USART_MODE_SERIAL>; status = "disabled"; }; + spi0: spi@400 { + compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; + clock-names = "spi_clk"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma1 AT91_XDMAC_DT_PERID(6)>, + <&dma1 AT91_XDMAC_DT_PERID(5)>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + i2c0: i2c@600 { compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; reg = <0x600 0x200>; @@ -442,6 +458,22 @@ #size-cells = <1>; status = "disabled"; + uart1: serial@200 { + compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 35>; + clock-names = "usart"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(8)>, + <&dma0 AT91_XDMAC_DT_PERID(7)>; + dma-names = "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <32>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; + status = "disabled"; + }; + spi1: spi@400 { compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; reg = <0x400 0x200>; @@ -492,9 +524,39 @@ dma-names = "tx", "rx"; atmel,use-dma-rx; atmel,use-dma-tx; + atmel,fifo-size = <32>; atmel,usart-mode = <AT91_USART_MODE_SERIAL>; status = "disabled"; }; + + spi2: spi@400 { + compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 36>; + clock-names = "spi_clk"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma1 AT91_XDMAC_DT_PERID(10)>, + <&dma1 AT91_XDMAC_DT_PERID(9)>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + + i2c2: i2c@600 { + compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 36>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma1 AT91_XDMAC_DT_PERID(10)>, + <&dma1 AT91_XDMAC_DT_PERID(9)>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; }; flx3: flexcom@e182c000 { @@ -517,10 +579,26 @@ dma-names = "tx", "rx"; atmel,use-dma-rx; atmel,use-dma-tx; + atmel,fifo-size = <32>; atmel,usart-mode = <AT91_USART_MODE_SERIAL>; status = "disabled"; }; + spi3: spi@400 { + compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; + clock-names = "spi_clk"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(12)>, + <&dma0 AT91_XDMAC_DT_PERID(11)>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + i2c3: i2c@600 { compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; reg = <0x600 0x200>; @@ -576,6 +654,20 @@ atmel,fifo-size = <32>; status = "disabled"; }; + + i2c4: i2c@600 { + compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma1 AT91_XDMAC_DT_PERID(14)>, + <&dma1 AT91_XDMAC_DT_PERID(13)>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; }; flx5: flexcom@e201c000 { @@ -587,6 +679,37 @@ #size-cells = <1>; status = "disabled"; + uart5: serial@200 { + compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; + clock-names = "usart"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(16)>, + <&dma0 AT91_XDMAC_DT_PERID(15)>; + dma-names = "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <32>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; + status = "disabled"; + }; + + spi5: spi@400 { + compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; + clock-names = "spi_clk"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(16)>, + <&dma0 AT91_XDMAC_DT_PERID(15)>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + i2c5: i2c@600 { compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; reg = <0x600 0x200>; @@ -617,10 +740,44 @@ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; clock-names = "usart"; + dmas = <&dma1 AT91_XDMAC_DT_PERID(18)>, + <&dma1 AT91_XDMAC_DT_PERID(17)>; + dma-names = "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; atmel,usart-mode = <AT91_USART_MODE_SERIAL>; atmel,fifo-size = <32>; status = "disabled"; }; + + spi6: spi@400 { + compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; + clock-names = "spi_clk"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma1 AT91_XDMAC_DT_PERID(18)>, + <&dma1 AT91_XDMAC_DT_PERID(17)>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + + i2c6: i2c@600 { + compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma1 AT91_XDMAC_DT_PERID(18)>, + <&dma1 AT91_XDMAC_DT_PERID(17)>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; }; flx7: flexcom@e2024000 { @@ -647,6 +804,35 @@ atmel,usart-mode = <AT91_USART_MODE_SERIAL>; status = "disabled"; }; + + spi7: spi@400 { + compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; + clock-names = "spi_clk"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma1 AT91_XDMAC_DT_PERID(20)>, + <&dma1 AT91_XDMAC_DT_PERID(19)>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + + i2c7: i2c@600 { + compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma1 AT91_XDMAC_DT_PERID(20)>, + <&dma1 AT91_XDMAC_DT_PERID(19)>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; }; flx8: flexcom@e281c000 { @@ -658,6 +844,37 @@ #size-cells = <1>; status = "disabled"; + uart8: serial@200 { + compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; + clock-names = "usart"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(22)>, + <&dma0 AT91_XDMAC_DT_PERID(21)>; + dma-names = "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <32>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; + status = "disabled"; + }; + + spi8: spi@400 { + compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; + clock-names = "spi_clk"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(22)>, + <&dma0 AT91_XDMAC_DT_PERID(21)>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + i2c8: i2c@600 { compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; reg = <0x600 0x200>; @@ -682,6 +899,37 @@ #size-cells = <1>; status = "disabled"; + uart9: serial@200 { + compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; + clock-names = "usart"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(24)>, + <&dma0 AT91_XDMAC_DT_PERID(23)>; + dma-names = "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <32>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; + status = "disabled"; + }; + + spi9: spi@400 { + compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; + clock-names = "spi_clk"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(24)>, + <&dma0 AT91_XDMAC_DT_PERID(23)>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + i2c9: i2c@600 { compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; reg = <0x600 0x200>; @@ -706,6 +954,37 @@ #size-cells = <1>; status = "disabled"; + uart10: serial@200 { + compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; + clock-names = "usart"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(26)>, + <&dma0 AT91_XDMAC_DT_PERID(25)>; + dma-names = "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <32>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; + status = "disabled"; + }; + + spi10: spi@400 { + compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; + clock-names = "spi_clk"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(26)>, + <&dma0 AT91_XDMAC_DT_PERID(25)>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + i2c10: i2c@600 { compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; reg = <0x600 0x200>; diff --git a/arch/arm/boot/dts/microchip/usb_a9g20-dab-mmx.dtsi b/arch/arm/boot/dts/microchip/usb_a9g20-dab-mmx.dtsi deleted file mode 100644 index 5b1d80c0ab26..000000000000 --- a/arch/arm/boot/dts/microchip/usb_a9g20-dab-mmx.dtsi +++ /dev/null @@ -1,93 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * calao-dab-mmx.dtsi - Device Tree Include file for Calao DAB-MMX Daughter Board - * - * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> - */ - -/ { - ahb { - apb { - usart1: serial@fffb4000 { - status = "okay"; - }; - - usart3: serial@fffd0000 { - status = "okay"; - }; - }; - }; - - i2c-gpio@0 { - status = "okay"; - }; - - leds { - compatible = "gpio-leds"; - - user_led1 { - label = "user_led1"; - gpios = <&pioB 20 GPIO_ACTIVE_LOW>; - }; - -/* -* led already used by mother board but active as high -* user_led2 { -* label = "user_led2"; -* gpios = <&pioB 21 GPIO_ACTIVE_LOW>; -* }; -*/ - user_led3 { - label = "user_led3"; - gpios = <&pioB 22 GPIO_ACTIVE_LOW>; - }; - - user_led4 { - label = "user_led4"; - gpios = <&pioB 23 GPIO_ACTIVE_LOW>; - }; - - red { - label = "red"; - gpios = <&pioB 24 GPIO_ACTIVE_LOW>; - }; - - orange { - label = "orange"; - gpios = <&pioB 30 GPIO_ACTIVE_LOW>; - }; - - green { - label = "green"; - gpios = <&pioB 31 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - button-user-pb1 { - label = "user_pb1"; - gpios = <&pioB 25 GPIO_ACTIVE_LOW>; - linux,code = <0x100>; - }; - - button-user-pb2 { - label = "user_pb2"; - gpios = <&pioB 13 GPIO_ACTIVE_LOW>; - linux,code = <0x101>; - }; - - button-user-pb3 { - label = "user_pb3"; - gpios = <&pioA 26 GPIO_ACTIVE_LOW>; - linux,code = <0x102>; - }; - - button-user-pb4 { - label = "user_pb4"; - gpios = <&pioC 9 GPIO_ACTIVE_LOW>; - linux,code = <0x103>; - }; - }; -}; diff --git a/arch/arm/boot/dts/nuvoton/nuvoton-common-npcm7xx.dtsi b/arch/arm/boot/dts/nuvoton/nuvoton-common-npcm7xx.dtsi index 98c35771534e..ab3c3c5713ae 100644 --- a/arch/arm/boot/dts/nuvoton/nuvoton-common-npcm7xx.dtsi +++ b/arch/arm/boot/dts/nuvoton/nuvoton-common-npcm7xx.dtsi @@ -154,7 +154,7 @@ status = "disabled"; reg = <0xf0842000 0x200>; interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk NPCM7XX_CLK_AHB>; + clocks = <&clk NPCM7XX_CLK_AHB>; clock-names = "clk_mmc"; pinctrl-names = "default"; pinctrl-0 = <&mmc8_pins @@ -166,7 +166,7 @@ status = "disabled"; reg = <0xf0840000 0x200>; interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk NPCM7XX_CLK_AHB>; + clocks = <&clk NPCM7XX_CLK_AHB>; clock-names = "clk_sdhc"; pinctrl-names = "default"; pinctrl-0 = <&sd1_pins>; diff --git a/arch/arm/boot/dts/nvidia/tegra20.dtsi b/arch/arm/boot/dts/nvidia/tegra20.dtsi index c60fc1971188..e4be3b62a51f 100644 --- a/arch/arm/boot/dts/nvidia/tegra20.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra20.dtsi @@ -230,7 +230,11 @@ reset-names = "dsi"; power-domains = <&pd_core>; operating-points-v2 = <&dsi_dvfs_opp_table>; + nvidia,mipi-calibrate = <&csi 3>; /* DSI pad */ status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; }; }; diff --git a/arch/arm/boot/dts/nvidia/tegra30.dtsi b/arch/arm/boot/dts/nvidia/tegra30.dtsi index 4c4e6097c916..ed1bbf86434c 100644 --- a/arch/arm/boot/dts/nvidia/tegra30.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra30.dtsi @@ -343,7 +343,11 @@ reset-names = "dsi"; power-domains = <&pd_core>; operating-points-v2 = <&dsia_dvfs_opp_table>; + nvidia,mipi-calibrate = <&csi 3>; /* DSIA pad */ status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; }; dsi@54400000 { @@ -356,7 +360,11 @@ reset-names = "dsi"; power-domains = <&pd_core>; operating-points-v2 = <&dsib_dvfs_opp_table>; + nvidia,mipi-calibrate = <&csi 4>; /* DSIB pad */ status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/e60k02.dtsi b/arch/arm/boot/dts/nxp/imx/e60k02.dtsi index 0029c12f16c8..aac7b9ef7627 100644 --- a/arch/arm/boot/dts/nxp/imx/e60k02.dtsi +++ b/arch/arm/boot/dts/nxp/imx/e60k02.dtsi @@ -23,6 +23,14 @@ stdout-path = &uart1; }; + epd_pmic_supply: regulator-epd-pmic-in { + compatible = "regulator-fixed"; + regulator-name = "epd_pmic_supply"; + gpio = <&gpio2 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <20000>; + }; + gpio_keys: gpio-keys { compatible = "gpio-keys"; @@ -119,8 +127,33 @@ vdd-supply = <&ldo5_reg>; }; - /* TODO: TPS65185 PMIC for E Ink at 0x68 */ + tps65185: pmic@68 { + compatible = "ti,tps65185"; + reg = <0x68>; + interrupt-parent = <&gpio2>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + vin-supply = <&epd_pmic_supply>; + pwr-good-gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; + vcom-ctrl-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; + wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; + + regulators { + vcom_reg: vcom { + regulator-name = "vcom"; + }; + + vposneg_reg: vposneg { + regulator-name = "vposneg"; + regulator-min-microvolt = <15000000>; + regulator-max-microvolt = <15000000>; + }; + v3p3_reg: v3p3 { + regulator-name = "v3p3"; + }; + }; + }; }; &i2c3 { diff --git a/arch/arm/boot/dts/nxp/imx/imx50-kobo-aura.dts b/arch/arm/boot/dts/nxp/imx/imx50-kobo-aura.dts index b1a6a9c58ac3..4725ee241cb1 100644 --- a/arch/arm/boot/dts/nxp/imx/imx50-kobo-aura.dts +++ b/arch/arm/boot/dts/nxp/imx/imx50-kobo-aura.dts @@ -58,6 +58,16 @@ }; }; + epd_pmic_supply: regulator-epd-pmic-in { + compatible = "regulator-fixed"; + regulator-name = "epd_pmic_supply"; + gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <20000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epd_pmic_supply>; + }; + sd2_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; pinctrl-names = "default"; @@ -135,7 +145,34 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; - /* TODO: TPS65185 PMIC for E Ink at 0x68 */ + pmic@68 { + compatible = "ti,tps65185"; + reg = <0x68>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epd_pmic>; + pwr-good-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; + vcom-ctrl-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio3 30 GPIO_ACTIVE_HIGH>; + wakeup-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; + vin-supply = <&epd_pmic_supply>; + interrupts-extended = <&gpio4 15 IRQ_TYPE_LEVEL_LOW>; + + regulators { + vcom { + regulator-name = "vcom"; + }; + + vposneg { + regulator-name = "vposneg"; + regulator-min-microvolt = <15000000>; + regulator-max-microvolt = <15000000>; + }; + + v3p3 { + regulator-name = "v3p3"; + }; + }; + }; }; &i2c3 { @@ -161,6 +198,27 @@ >; }; + pinctrl_epd_pmic: epd-pmic-grp { + fsl,pins = < + /* PWRUP */ + MX50_PAD_EPDC_PWRCTRL1__GPIO3_30 0x0 + /* WAKEUP */ + MX50_PAD_EPDC_PWRCTRL0__GPIO3_29 0x0 + /* VCOMCTRL */ + MX50_PAD_EPDC_VCOM0__GPIO4_21 0x0 + /* PWRGOOD: enable internal 100k pull-up */ + MX50_PAD_EPDC_PWRSTAT__GPIO3_28 0xe0 + /* INT: enable internal 100k pull-up */ + MX50_PAD_ECSPI1_SS0__GPIO4_15 0xe0 + >; + }; + + pinctrl_epd_pmic_supply: epd-pmic-supply-grp { + fsl,pins = < + MX50_PAD_EIM_CRE__GPIO1_27 0x0 + >; + }; + pinctrl_gpiokeys: gpiokeysgrp { fsl,pins = < MX50_PAD_CSPI_MISO__GPIO4_10 0x0 diff --git a/arch/arm/boot/dts/nxp/imx/imx6-logicpd-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6-logicpd-som.dtsi index 547fb141ec0c..f452764fae00 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6-logicpd-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6-logicpd-som.dtsi @@ -36,8 +36,12 @@ &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; status = "okay"; + + nand@0 { + reg = <0>; + nand-on-flash-bbt; + }; }; &i2c3 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-icore.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-icore.dtsi index 9975b6ee433d..58ecdb87c6d4 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-icore.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-icore.dtsi @@ -172,8 +172,12 @@ &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; status = "okay"; + + nand@0 { + reg = <0>; + nand-on-flash-bbt; + }; }; &i2c1 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-pfla02.dtsi index aa9a442852f4..6f3becd33a5b 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-pfla02.dtsi @@ -102,8 +102,12 @@ &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; status = "okay"; + + nand@0 { + reg = <0>; + nand-on-flash-bbt; + }; }; &i2c1 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi index 85e278eb2016..f2140dd8525f 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi @@ -73,8 +73,12 @@ &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; status = "disabled"; + + nand@0 { + reg = <0>; + nand-on-flash-bbt; + }; }; &i2c3 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu.dtsi index c93dbc595ef6..131a3428ddb8 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu.dtsi @@ -260,10 +260,14 @@ &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; #address-cells = <1>; #size-cells = <0>; status = "okay"; + + nand@0 { + reg = <0>; + nand-on-flash-bbt; + }; }; &i2c3 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi index 57297d6521cf..d29adfef5fdb 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi @@ -252,9 +252,13 @@ &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; fsl,no-blockmark-swap; status = "okay"; + + nand@0 { + reg = <0>; + nand-on-flash-bbt; + }; }; &i2c1 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi index 45bcfd7faf9d..76e6043e1f91 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi @@ -166,6 +166,8 @@ compatible = "fsl,imx6q-gpmi-nand"; reg = <0x00112000 0x2000>, <0x00114000 0x2000>; reg-names = "gpmi-nand", "bch"; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "bch"; clocks = <&clks IMX6QDL_CLK_GPMI_IO>, @@ -875,6 +877,7 @@ gpc: gpc@20dc000 { compatible = "fsl,imx6q-gpc"; reg = <0x020dc000 0x4000>; + #address-cells = <0>; interrupt-controller; #interrupt-cells = <3>; interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine2hd.dts b/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine2hd.dts index b6c336e3079e..4c655579f43e 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine2hd.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine2hd.dts @@ -37,6 +37,16 @@ stdout-path = &uart1; }; + epd_pmic_supply: regulator-epd-pmic-in { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epd_pmic_supply>; + regulator-name = "epd_pmic_supply"; + gpio = <&gpio2 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <20000>; + }; + gpio_keys: gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -147,8 +157,35 @@ touchscreen-inverted-x; }; - /* TODO: TPS65185 PMIC for E Ink at 0x68 */ + tps65185: pmic@68 { + compatible = "ti,tps65185"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tps65185_gpio>; + reg = <0x68>; + interrupt-parent = <&gpio2>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + vin-supply = <&epd_pmic_supply>; + pwr-good-gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; + vcom-ctrl-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; + wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; + + regulators { + vcom_reg: vcom { + regulator-name = "vcom"; + }; + + vposneg_reg: vposneg { + regulator-name = "vposneg"; + regulator-min-microvolt = <15000000>; + regulator-max-microvolt = <15000000>; + }; + v3p3_reg: v3p3 { + regulator-name = "v3p3"; + }; + }; + }; }; &i2c3 { @@ -328,6 +365,12 @@ >; }; + pinctrl_epd_pmic_supply: epdc-pmic-supplygrp { + fsl,pins = < + MX6SL_PAD_EPDC_PWRWAKEUP__GPIO2_IO14 0x40010059 /* pwrall */ + >; + }; + pinctrl_gpio_keys: gpio-keysgrp { fsl,pins = < MX6SL_PAD_SD1_DAT1__GPIO5_IO08 0x17059 @@ -425,6 +468,16 @@ >; }; + pinctrl_tps65185_gpio: tps65185-gpio-grp { + fsl,pins = < + MX6SL_PAD_EPDC_VCOM0__GPIO2_IO03 0x40010059 /* vcom_ctrl */ + MX6SL_PAD_EPDC_PWRCTRL0__GPIO2_IO07 0x40010059 /* wakeup */ + MX6SL_PAD_EPDC_PWRCTRL1__GPIO2_IO08 0x40010059 /* enable */ + MX6SL_PAD_EPDC_PWRCTRL2__GPIO2_IO09 0x17059 /* nINT */ + MX6SL_PAD_EPDC_PWRSTAT__GPIO2_IO13 0x17059 /* pwr-good */ + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1 diff --git a/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine3.dts b/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine3.dts index 5ba6f15e9ed5..58b9ccd9b605 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine3.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine3.dts @@ -26,6 +26,11 @@ compatible = "kobo,tolino-shine3", "fsl,imx6sl"; }; +&epd_pmic_supply { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epd_pmic_supply>; +}; + &gpio_keys { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; @@ -59,6 +64,12 @@ >; }; + pinctrl_epd_pmic_supply: epdc-pmic-supplygrp { + fsl,pins = < + MX6SL_PAD_EPDC_PWRWAKEUP__GPIO2_IO14 0x40010059 + >; + }; + pinctrl_gpio_keys: gpio-keysgrp { fsl,pins = < MX6SL_PAD_SD1_DAT1__GPIO5_IO08 0x17059 /* PWR_SW */ @@ -159,6 +170,16 @@ >; }; + pinctrl_tps65185_gpio: tps65185-gpio-grp { + fsl,pins = < + MX6SL_PAD_EPDC_VCOM0__GPIO2_IO03 0x40010059 /* vcom_ctrl */ + MX6SL_PAD_EPDC_PWRCTRL0__GPIO2_IO07 0x40010059 /* wakeup */ + MX6SL_PAD_EPDC_PWRCTRL1__GPIO2_IO08 0x40010059 /* enable */ + MX6SL_PAD_EPDC_PWRCTRL2__GPIO2_IO09 0x17059 /* nINT */ + MX6SL_PAD_EPDC_PWRSTAT__GPIO2_IO13 0x17059 /* pwr-good */ + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1 @@ -308,6 +329,11 @@ pinctrl-0 = <&pinctrl_ricoh_gpio>; }; +&tps65185 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tps65185_gpio>; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6sl.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sl.dtsi index 7381fb7f8912..13b0474aa42c 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sl.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6sl.dtsi @@ -776,7 +776,7 @@ }; lcdif: lcdif@20f8000 { - compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif"; + compatible = "fsl,imx6sl-lcdif", "fsl,imx6sx-lcdif"; reg = <0x020f8000 0x4000>; interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_LCDIF_PIX>, diff --git a/arch/arm/boot/dts/nxp/imx/imx6sll-kobo-clara2e-b.dts b/arch/arm/boot/dts/nxp/imx/imx6sll-kobo-clara2e-b.dts index f81aeacf5142..f5e88764a08c 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sll-kobo-clara2e-b.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6sll-kobo-clara2e-b.dts @@ -16,8 +16,67 @@ / { model = "Kobo Clara 2E"; compatible = "kobo,clara2e-b", "kobo,clara2e", "fsl,imx6sll"; + + epd_pmic_supply: regulator-epd-pmic-in { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epd_pmic_supply>; + regulator-name = "epd_pmic_supply"; + gpio = <&gpio2 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <20000>; + }; }; &i2c2 { - /* EPD PMIC JD9930 at 0x18 */ + jd9930: pmic@18 { + compatible = "fitipower,jd9930", "fitipower,fp9931"; + reg = <0x18>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_jd9930_gpio>; + vin-supply = <&epd_pmic_supply>; + pg-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; + en-ts-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; + fitipower,tdly-ms = <2 2 2 2>; + + regulators { + vcom_reg: vcom { + regulator-name = "vcom"; + /* + * For optimal performance these should be + * tuned on a per batch basis e.g. using + * overlays. + */ + regulator-min-microvolt = <2352840>; + regulator-max-microvolt = <2352840>; + }; + + vposneg_reg: vposneg { + regulator-name = "vposneg"; + regulator-min-microvolt = <15060000>; + regulator-max-microvolt = <15060000>; + }; + + v3p3_reg: v3p3 { + regulator-name = "v3p3"; + }; + }; + }; +}; + +&iomuxc { + pinctrl_jd9930_gpio: jd9930-gpiogrp { + fsl,pins = < + MX6SLL_PAD_EPDC_PWR_CTRL0__GPIO2_IO07 0x17059 /* PG */ + MX6SLL_PAD_EPDC_PWR_CTRL1__GPIO2_IO08 0x40010059 /* EN */ + MX6SLL_PAD_EPDC_PWR_CTRL2__GPIO2_IO09 0x40010059 /* EN_TS */ + >; + }; + + pinctrl_epd_pmic_supply: epd-pmic-supplygrp { + fsl,pins = < + MX6SLL_PAD_EPDC_PWR_WAKE__GPIO2_IO14 0x40010059 + >; + }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6sll-kobo-clarahd.dts b/arch/arm/boot/dts/nxp/imx/imx6sll-kobo-clarahd.dts index 18c9ac8f7560..1000ee8b807a 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sll-kobo-clarahd.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6sll-kobo-clarahd.dts @@ -36,6 +36,11 @@ soc-supply = <&dcdc1_reg>; }; +&epd_pmic_supply { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epd_pmic_supply>; +}; + &gpio_keys { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; @@ -69,6 +74,12 @@ >; }; + pinctrl_epd_pmic_supply: epdc-pmic-supplygrp { + fsl,pins = < + MX6SLL_PAD_EPDC_PWR_WAKE__GPIO2_IO14 0x40010059 + >; + }; + pinctrl_gpio_keys: gpio-keysgrp { fsl,pins = < MX6SLL_PAD_SD1_DATA1__GPIO5_IO08 0x17059 /* PWR_SW */ @@ -169,6 +180,16 @@ >; }; + pinctrl_tps65185_gpio: tps65185-gpio-grp { + fsl,pins = < + MX6SLL_PAD_EPDC_VCOM0__GPIO2_IO03 0x40010059 /* vcom_ctrl */ + MX6SLL_PAD_EPDC_PWR_CTRL0__GPIO2_IO07 0x40010059 /* wakeup */ + MX6SLL_PAD_EPDC_PWR_CTRL1__GPIO2_IO08 0x40010059 /* enable */ + MX6SLL_PAD_EPDC_PWR_CTRL2__GPIO2_IO09 0x17059 /* nINT */ + MX6SLL_PAD_EPDC_PWR_STAT__GPIO2_IO13 0x17059 /* pwr-good */ + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1 @@ -310,6 +331,11 @@ pinctrl-0 = <&pinctrl_ricoh_gpio>; }; +&tps65185 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tps65185_gpio>; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6sll.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sll.dtsi index 704870e8c10c..c96669605d1d 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sll.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6sll.dtsi @@ -657,7 +657,7 @@ }; lcdif: lcd-controller@20f8000 { - compatible = "fsl,imx6sll-lcdif", "fsl,imx28-lcdif"; + compatible = "fsl,imx6sll-lcdif", "fsl,imx6sx-lcdif"; reg = <0x020f8000 0x4000>; interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SLL_CLK_LCDIF_PIX>, diff --git a/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi index 5132b575b001..1426f357d474 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi @@ -224,7 +224,7 @@ gpmi: nand-controller@1806000 { compatible = "fsl,imx6sx-gpmi-nand"; #address-cells = <1>; - #size-cells = <1>; + #size-cells = <0>; reg = <0x01806000 0x2000>, <0x01808000 0x4000>; reg-names = "gpmi-nand", "bch"; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-geam.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-geam.dts index 2a6bb5ff808a..40d530c1dc29 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-geam.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-geam.dts @@ -133,8 +133,12 @@ &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; status = "okay"; + + nand@0 { + reg = <0>; + nand-on-flash-bbt; + }; }; &i2c1 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-isiot.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-isiot.dtsi index e34c8cbe36ae..776f6f78ee46 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-isiot.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-isiot.dtsi @@ -101,8 +101,12 @@ &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; status = "disabled"; + + nand@0 { + reg = <0>; + nand-on-flash-bbt; + }; }; &i2c1 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-phycore-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-phycore-som.dtsi index a3ea1b208462..27e4d2aec137 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-phycore-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-phycore-som.dtsi @@ -63,8 +63,12 @@ &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; status = "disabled"; + + nand@0 { + reg = <0>; + nand-on-flash-bbt; + }; }; &i2c1 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi index 1992dfb53b45..dc53f9286ffe 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi @@ -296,9 +296,13 @@ &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; fsl,no-blockmark-swap; status = "okay"; + + nand@0 { + reg = <0>; + nand-on-flash-bbt; + }; }; &i2c2 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-colibri.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri.dtsi index ec3c1e7301f4..eaed2cbf0c82 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-colibri.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri.dtsi @@ -160,11 +160,15 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; fsl,use-minimum-ecc; - nand-on-flash-bbt; - nand-ecc-mode = "hw"; - nand-ecc-strength = <8>; - nand-ecc-step-size = <512>; status = "okay"; + + nand@0 { + reg = <0>; + nand-on-flash-bbt; + nand-ecc-mode = "hw"; + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + }; }; /* I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) */ diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea.dtsi index 43518bf07602..3dfd43b32055 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea.dtsi @@ -43,11 +43,15 @@ &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <0>; - nand-ecc-step-size = <0>; - nand-on-flash-bbt; status = "okay"; + + nand@0 { + reg = <0>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <0>; + nand-ecc-step-size = <0>; + nand-on-flash-bbt; + }; }; &iomuxc { diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-myir-mys-6ulx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-myir-mys-6ulx.dtsi index 83b9de17cee2..fc298f57bfff 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-myir-mys-6ulx.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-myir-mys-6ulx.dtsi @@ -60,8 +60,12 @@ &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; status = "disabled"; + + nand@0 { + reg = <0>; + nand-on-flash-bbt; + }; }; &uart1 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6ulz-bsh-smm-m2.dts b/arch/arm/boot/dts/nxp/imx/imx6ulz-bsh-smm-m2.dts index 2d9f495660c9..8ec18eae98a4 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ulz-bsh-smm-m2.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ulz-bsh-smm-m2.dts @@ -25,8 +25,12 @@ &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; status = "okay"; + + nand@0 { + reg = <0>; + nand-on-flash-bbt; + }; }; &snvs_poweroff { diff --git a/arch/arm/boot/dts/nxp/imx/imx7-colibri.dtsi b/arch/arm/boot/dts/nxp/imx/imx7-colibri.dtsi index 8666dcd7fe97..a41dc4edfc0d 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7-colibri.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx7-colibri.dtsi @@ -375,10 +375,14 @@ /* NAND on such SKUs */ &gpmi { fsl,use-minimum-ecc; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; + + nand@0 { + reg = <0>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + }; }; /* On-module Power I2C */ diff --git a/arch/arm/boot/dts/nxp/lpc/lpc3250-ea3250.dts b/arch/arm/boot/dts/nxp/lpc/lpc3250-ea3250.dts index 63c6f17bb7c9..837a3cfa8e7c 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc3250-ea3250.dts +++ b/arch/arm/boot/dts/nxp/lpc/lpc3250-ea3250.dts @@ -27,55 +27,55 @@ gpios = <&gpio 4 1 0>; /* GPI_P3 1 */ }; - key1 { + key-1 { label = "KEY1"; linux,code = <1>; gpios = <&pca9532 0 0>; }; - key2 { + key-2 { label = "KEY2"; linux,code = <2>; gpios = <&pca9532 1 0>; }; - key3 { + key-3 { label = "KEY3"; linux,code = <3>; gpios = <&pca9532 2 0>; }; - key4 { + key-4 { label = "KEY4"; linux,code = <4>; gpios = <&pca9532 3 0>; }; - joy0 { + key-joy0 { label = "Joystick Key 0"; linux,code = <10>; gpios = <&gpio 2 0 0>; /* P2.0 */ }; - joy1 { + key-joy1 { label = "Joystick Key 1"; linux,code = <11>; gpios = <&gpio 2 1 0>; /* P2.1 */ }; - joy2 { + key-joy2 { label = "Joystick Key 2"; linux,code = <12>; gpios = <&gpio 2 2 0>; /* P2.2 */ }; - joy3 { + key-joy3 { label = "Joystick Key 3"; linux,code = <13>; gpios = <&gpio 2 3 0>; /* P2.3 */ }; - joy4 { + key-joy4 { label = "Joystick Key 4"; linux,code = <14>; gpios = <&gpio 2 4 0>; /* P2.4 */ diff --git a/arch/arm/boot/dts/nxp/lpc/lpc3250-phy3250.dts b/arch/arm/boot/dts/nxp/lpc/lpc3250-phy3250.dts index 21a6d0bca1e8..0f96ea0337a1 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc3250-phy3250.dts +++ b/arch/arm/boot/dts/nxp/lpc/lpc3250-phy3250.dts @@ -200,7 +200,7 @@ cs-gpios = <&gpio 3 5 0>; status = "okay"; - eeprom: at25@0 { + eeprom: eeprom@0 { compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <5000000>; @@ -213,9 +213,9 @@ pl022,wait-state = <0>; pl022,duplex = <0>; - at25,byte-len = <0x8000>; - at25,addr-mode = <2>; - at25,page-size = <64>; + size = <0x8000>; + address-width = <16>; + pagesize = <64>; }; }; diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi index 2236901a0031..e94df78def18 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi @@ -62,18 +62,23 @@ /* * Enable either SLC or MLC */ - slc: flash@20020000 { + slc: nand-controller@20020000 { compatible = "nxp,lpc3220-slc"; reg = <0x20020000 0x1000>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk LPC32XX_CLK_SLC>; + dmas = <&dma 1 1>; + dma-names = "rx-tx"; status = "disabled"; }; - mlc: flash@200a8000 { + mlc: nand-controller@200a8000 { compatible = "nxp,lpc3220-mlc"; reg = <0x200a8000 0x11000>; interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk LPC32XX_CLK_MLC>; + dmas = <&dma 12 1>; + dma-names = "rx-tx"; status = "disabled"; }; @@ -83,54 +88,55 @@ interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk LPC32XX_CLK_DMA>; clock-names = "apb_pclk"; + dma-channels = <8>; + dma-requests = <16>; + lli-bus-interface-ahb1; + lli-bus-interface-ahb2; + mem-bus-interface-ahb1; + mem-bus-interface-ahb2; + memcpy-burst-size = <256>; + memcpy-bus-width = <32>; #dma-cells = <2>; }; - usb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0x0 0x31020000 0x00001000>; - - /* - * Enable either ohci or usbd (gadget)! - */ - ohci: usb@0 { - compatible = "nxp,ohci-nxp", "usb-ohci"; - reg = <0x0 0x300>; - interrupt-parent = <&sic1>; - interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&usbclk LPC32XX_USB_CLK_HOST>; - status = "disabled"; - }; + /* + * Enable either ohci or usbd (gadget)! + */ + ohci: usb@31020000 { + compatible = "nxp,ohci-nxp", "usb-ohci"; + reg = <0x31020000 0x300>; + interrupt-parent = <&sic1>; + interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&usbclk LPC32XX_USB_CLK_HOST>; + status = "disabled"; + }; - usbd: usbd@0 { - compatible = "nxp,lpc3220-udc"; - reg = <0x0 0x300>; - interrupt-parent = <&sic1>; - interrupts = <29 IRQ_TYPE_LEVEL_HIGH>, - <30 IRQ_TYPE_LEVEL_HIGH>, - <28 IRQ_TYPE_LEVEL_HIGH>, - <26 IRQ_TYPE_LEVEL_LOW>; - clocks = <&usbclk LPC32XX_USB_CLK_DEVICE>; - status = "disabled"; - }; + usbd: usbd@31020000 { + compatible = "nxp,lpc3220-udc"; + reg = <0x31020000 0x300>; + interrupt-parent = <&sic1>; + interrupts = <29 IRQ_TYPE_LEVEL_HIGH>, + <30 IRQ_TYPE_LEVEL_HIGH>, + <28 IRQ_TYPE_LEVEL_HIGH>, + <26 IRQ_TYPE_LEVEL_LOW>; + clocks = <&usbclk LPC32XX_USB_CLK_DEVICE>; + status = "disabled"; + }; - i2cusb: i2c@300 { - compatible = "nxp,pnx-i2c"; - reg = <0x300 0x100>; - interrupt-parent = <&sic1>; - interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&usbclk LPC32XX_USB_CLK_I2C>; - #address-cells = <1>; - #size-cells = <0>; - }; + i2cusb: i2c@31020300 { + compatible = "nxp,pnx-i2c"; + reg = <0x31020300 0x100>; + interrupt-parent = <&sic1>; + interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&usbclk LPC32XX_USB_CLK_I2C>; + #address-cells = <1>; + #size-cells = <0>; + }; - usbclk: clock-controller@f00 { - compatible = "nxp,lpc3220-usb-clk"; - reg = <0xf00 0x100>; - #clock-cells = <1>; - }; + usbclk: clock-controller@31020f00 { + compatible = "nxp,lpc3220-usb-clk"; + reg = <0x31020f00 0x100>; + #clock-cells = <1>; }; clcd: clcd@31040000 { @@ -179,8 +185,8 @@ compatible = "arm,pl022", "arm,primecell"; reg = <0x20084000 0x1000>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk LPC32XX_CLK_SSP0>; - clock-names = "apb_pclk"; + clocks = <&clk LPC32XX_CLK_SSP0>, <&clk LPC32XX_CLK_SSP0>; + clock-names = "sspclk", "apb_pclk"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -190,6 +196,8 @@ compatible = "nxp,lpc3220-spi"; reg = <0x20088000 0x1000>; clocks = <&clk LPC32XX_CLK_SPI1>; + dmas = <&dmamux 11 1 0>; + dma-names = "rx-tx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -203,8 +211,8 @@ compatible = "arm,pl022", "arm,primecell"; reg = <0x2008c000 0x1000>; interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk LPC32XX_CLK_SSP1>; - clock-names = "apb_pclk"; + clocks = <&clk LPC32XX_CLK_SSP1>, <&clk LPC32XX_CLK_SSP1>; + clock-names = "sspclk", "apb_pclk"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -214,6 +222,8 @@ compatible = "nxp,lpc3220-spi"; reg = <0x20090000 0x1000>; clocks = <&clk LPC32XX_CLK_SPI2>; + dmas = <&dmamux 3 1 0>; + dma-names = "rx-tx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -222,6 +232,11 @@ i2s0: i2s@20094000 { compatible = "nxp,lpc3220-i2s"; reg = <0x20094000 0x1000>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk LPC32XX_CLK_I2S0>; + dmas = <&dma 0 1>, <&dma 13 1>; + dma-names = "rx", "tx"; + #sound-dai-cells = <0>; status = "disabled"; }; @@ -238,6 +253,11 @@ i2s1: i2s@2009c000 { compatible = "nxp,lpc3220-i2s"; reg = <0x2009c000 0x1000>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk LPC32XX_CLK_I2S1>; + dmas = <&dma 2 1>, <&dmamux 10 1 1>; + dma-names = "rx", "tx"; + #sound-dai-cells = <0>; status = "disabled"; }; @@ -302,6 +322,8 @@ mpwm: pwm@400e8000 { compatible = "nxp,lpc3220-motor-pwm"; reg = <0x400e8000 0x78>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk LPC32XX_CLK_MCPWM>; #pwm-cells = <3>; status = "disabled"; }; @@ -314,20 +336,27 @@ ranges = <0x20000000 0x20000000 0x30000000>; /* System Control Block */ - scb { - compatible = "simple-bus"; - ranges = <0x0 0x40004000 0x00001000>; + syscon@40004000 { + compatible = "nxp,lpc3220-scb", "syscon", "simple-mfd"; + reg = <0x40004000 0x1000>; #address-cells = <1>; #size-cells = <1>; + ranges = <0 0x40004000 0x1000>; clk: clock-controller@0 { compatible = "nxp,lpc3220-clk"; reg = <0x00 0x114>; #clock-cells = <1>; - clocks = <&xtal_32k>, <&xtal>; clock-names = "xtal_32k", "xtal"; }; + + dmamux: dma-router@78 { + compatible = "nxp,lpc3220-dmamux"; + reg = <0x78 0x8>; + dma-masters = <&dma>; + #dma-cells = <3>; + }; }; mic: interrupt-controller@40008000 { diff --git a/arch/arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts index 34b0cf35fdac..d3ae6c6a6f83 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts @@ -198,15 +198,12 @@ }; &remoteproc_adsp { - cx-supply = <&pm8841_s2>; - firmware-name = "qcom/apq8074/adsp.mbn"; status = "okay"; }; &remoteproc_mss { - cx-supply = <&pm8841_s2>; mss-supply = <&pm8841_s3>; mx-supply = <&pm8841_s1>; pll-supply = <&pm8941_l12>; @@ -225,20 +222,10 @@ regulator-max-microvolt = <1050000>; }; - pm8841_s2: s2 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - pm8841_s3: s3 { regulator-min-microvolt = <500000>; regulator-max-microvolt = <1050000>; }; - - pm8841_s4: s4 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; }; regulators-1 { diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi index 51a7a3fb36d8..bcf14a3b13a1 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi @@ -959,7 +959,7 @@ resets = <&gcc GCC_MSS_RESTART>; reset-names = "mss_restart"; - power-domains = <&rpmpd MSM8226_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; power-domain-names = "cx"; qcom,ext-bhs-reg = <&tcsr_regs_1 0x194>; @@ -1372,7 +1372,7 @@ <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; - power-domains = <&rpmpd MSM8226_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; power-domain-names = "cx"; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts b/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts index 5ee919dce75b..5a39abd6f3ce 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts @@ -54,6 +54,31 @@ }; }; +&gsbi2 { + qcom,mode = <GSBI_PROT_I2C>; + + status = "okay"; +}; + +&gsbi2_i2c { + status = "okay"; + + light-sensor@39 { + compatible = "amstaos,tmd2772"; + reg = <0x39>; + interrupts-extended = <&pm8921_gpio 6 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <&pm8921_l9>; + vddio-supply = <&pm8921_lvs4>; + + /* TODO: Proximity doesn't work */ + amstaos,proximity-diodes = <0>; + led-max-microamp = <100000>; + + pinctrl-0 = <&prox_sensor_int>; + pinctrl-names = "default"; + }; +}; + &gsbi5 { qcom,mode = <GSBI_PROT_I2C_UART>; status = "okay"; @@ -157,12 +182,45 @@ bias-disable; drive-strength = <2>; }; + + nfc_default: nfc-default-state { + irq-pins { + pins = "gpio106"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + firmware-pins { + pins = "gpio92"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; }; &pm8921 { interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>; }; +&pm8921_gpio { + prox_sensor_int: prox-sensor-int-state { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-disable; + }; + + nfc_enable: nfc-enable-state { + pins = "gpio21"; + function = "normal"; + bias-disable; + qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; + power-source = <PM8921_GPIO_S4>; + }; +}; + &rpm { regulators { compatible = "qcom,rpm-pm8921-regulators"; @@ -408,3 +466,54 @@ dr_mode = "otg"; status = "okay"; }; + +&gsbi7 { + qcom,mode = <GSBI_PROT_I2C>; + + status = "okay"; +}; + +&gsbi7_i2c { + status = "okay"; + + nfc@2b { + compatible = "nxp,pn544-i2c"; + reg = <0x2b>; + interrupts-extended = <&tlmm 106 IRQ_TYPE_EDGE_RISING>; + enable-gpios = <&pm8921_gpio 21 GPIO_ACTIVE_HIGH>; + firmware-gpios = <&tlmm 92 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&nfc_default &nfc_enable>; + pinctrl-names = "default"; + }; +}; + +&gsbi12 { + qcom,mode = <GSBI_PROT_I2C>; + + status = "okay"; +}; + +&gsbi12_i2c { + status = "okay"; + + accelerometer@18 { + compatible = "bosch,bma254"; + reg = <0x18>; + vdd-supply = <&pm8921_l9>; + vddio-supply = <&pm8921_lvs4>; + + mount-matrix = "-1", "0", "0", + "0", "-1", "0", + "0", "0", "1"; + }; + + magnetometer@2e { + compatible = "yamaha,yas532"; + reg = <0x2e>; + vdd-supply = <&pm8921_l9>; + iovdd-supply = <&pm8921_lvs4>; + + /* TODO: Figure out Mount Matrix */ + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi index 38bd4fd8dda5..fd28401cebb5 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi @@ -149,6 +149,24 @@ }; }; + i2c2_default_state: i2c2-default-state { + i2c2-pins { + pins = "gpio12", "gpio13"; + function = "gsbi2"; + drive-strength = <8>; + bias-disable; + }; + }; + + i2c2_sleep_state: i2c2-sleep-state { + i2c2-pins { + pins = "gpio12", "gpio13"; + function = "gpio"; + drive-strength = <2>; + bias-bus-hold; + }; + }; + i2c3_default_state: i2c3-default-state { i2c3-pins { pins = "gpio16", "gpio17"; @@ -167,6 +185,24 @@ }; }; + i2c7_default_state: i2c7-default-state { + i2c7-pins { + pins = "gpio32", "gpio33"; + function = "gsbi7"; + drive-strength = <8>; + bias-disable; + }; + }; + + i2c7_sleep_state: i2c7-sleep-state { + i2c7-pins { + pins = "gpio32", "gpio33"; + function = "gpio"; + drive-strength = <2>; + bias-bus-hold; + }; + }; + i2c8_default_state: i2c8-default-state { i2c8-pins { pins = "gpio36", "gpio37"; @@ -543,6 +579,36 @@ }; }; + gsbi2: gsbi@16100000 { + compatible = "qcom,gsbi-v1.0.0"; + reg = <0x16100000 0x100>; + ranges; + cell-index = <2>; + clocks = <&gcc GSBI2_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + + status = "disabled"; + + gsbi2_i2c: i2c@16180000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x16180000 0x1000>; + pinctrl-0 = <&i2c2_default_state>; + pinctrl-1 = <&i2c2_sleep_state>; + pinctrl-names = "default", "sleep"; + interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GSBI2_QUP_CLK>, + <&gcc GSBI2_H_CLK>; + clock-names = "core", + "iface"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + }; + gsbi3: gsbi@16200000 { compatible = "qcom,gsbi-v1.0.0"; reg = <0x16200000 0x100>; @@ -600,6 +666,36 @@ }; }; + gsbi7: gsbi@16600000 { + compatible = "qcom,gsbi-v1.0.0"; + reg = <0x16600000 0x100>; + ranges; + cell-index = <7>; + clocks = <&gcc GSBI7_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + + status = "disabled"; + + gsbi7_i2c: i2c@16680000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x16680000 0x1000>; + pinctrl-0 = <&i2c7_default_state>; + pinctrl-1 = <&i2c7_sleep_state>; + pinctrl-names = "default", "sleep"; + interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GSBI7_QUP_CLK>, + <&gcc GSBI7_H_CLK>; + clock-names = "core", + "iface"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + }; + gsbi8: gsbi@1a000000 { compatible = "qcom,gsbi-v1.0.0"; reg = <0x1a000000 0x100>; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts index b3127f0383cf..e34d7b864e30 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -7,7 +7,7 @@ #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> / { - model = "LGE MSM 8974 HAMMERHEAD"; + model = "LG Nexus 5"; compatible = "lge,hammerhead", "qcom,msm8974"; chassis-type = "handset"; @@ -369,12 +369,10 @@ }; &remoteproc_adsp { - cx-supply = <&pm8841_s2>; status = "okay"; }; &remoteproc_mss { - cx-supply = <&pm8841_s2>; mss-supply = <&pm8841_s3>; mx-supply = <&pm8841_s1>; pll-supply = <&pm8941_l12>; @@ -390,20 +388,10 @@ regulator-max-microvolt = <1050000>; }; - pm8841_s2: s2 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - pm8841_s3: s3 { regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; }; - - pm8841_s4: s4 { - regulator-min-microvolt = <815000>; - regulator-max-microvolt = <900000>; - }; }; regulators-1 { diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974-samsung-hlte.dts b/arch/arm/boot/dts/qcom/qcom-msm8974-samsung-hlte.dts index b7a1367d3470..7f61f80761e1 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974-samsung-hlte.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8974-samsung-hlte.dts @@ -188,12 +188,10 @@ }; &remoteproc_adsp { - cx-supply = <&pm8841_s2>; status = "okay"; }; &remoteproc_mss { - cx-supply = <&pm8841_s2>; mss-supply = <&pm8841_s3>; mx-supply = <&pm8841_s1>; pll-supply = <&pm8941_l12>; @@ -209,20 +207,10 @@ regulator-max-microvolt = <1050000>; }; - pm8841_s2: s2 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - pm8841_s3: s3 { regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; }; - - pm8841_s4: s4 { - regulator-min-microvolt = <815000>; - regulator-max-microvolt = <900000>; - }; }; regulators-1 { diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974-sony-xperia-rhine.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974-sony-xperia-rhine.dtsi index d7322fc6a095..96682d82b1c3 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974-sony-xperia-rhine.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8974-sony-xperia-rhine.dtsi @@ -204,12 +204,10 @@ }; &remoteproc_adsp { - cx-supply = <&pm8841_s2>; status = "okay"; }; &remoteproc_mss { - cx-supply = <&pm8841_s2>; mss-supply = <&pm8841_s3>; mx-supply = <&pm8841_s1>; pll-supply = <&pm8941_l12>; @@ -225,20 +223,10 @@ regulator-max-microvolt = <1050000>; }; - pm8841_s2: s2 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - pm8841_s3: s3 { regulator-min-microvolt = <500000>; regulator-max-microvolt = <1050000>; }; - - pm8841_s4: s4 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; }; regulators-1 { diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi index 7e119370f337..2a82ddce94a2 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi @@ -1,14 +1,15 @@ // SPDX-License-Identifier: GPL-2.0 /dts-v1/; -#include <dt-bindings/interconnect/qcom,msm8974.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/qcom,dsi-phy-28nm.h> #include <dt-bindings/clock/qcom,gcc-msm8974.h> #include <dt-bindings/clock/qcom,mmcc-msm8974.h> #include <dt-bindings/clock/qcom,rpmcc.h> -#include <dt-bindings/reset/qcom,gcc-msm8974.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interconnect/qcom,msm8974.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/power/qcom-rpmpd.h> +#include <dt-bindings/reset/qcom,gcc-msm8974.h> / { #address-cells = <1>; @@ -146,6 +147,40 @@ clocks = <&xo_board>; clock-names = "xo"; }; + + rpmpd: power-controller { + compatible = "qcom,msm8974-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level = <1>; + }; + + rpmpd_opp_svs_krait: opp2 { + opp-level = <2>; + }; + + rpmpd_opp_svs_soc: opp3 { + opp-level = <3>; + }; + + rpmpd_opp_nom: opp4 { + opp-level = <4>; + }; + + rpmpd_opp_turbo: opp5 { + opp-level = <5>; + }; + + rpmpd_opp_super_turbo: opp6 { + opp-level = <6>; + }; + }; + }; }; }; }; @@ -743,6 +778,9 @@ <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; + power-domains = <&rpmpd MSM8974_VDDCX>; + power-domain-names = "cx"; + qcom,smem-states = <&wcnss_smp2p_out 0>; qcom,smem-state-names = "stop"; @@ -1545,6 +1583,9 @@ resets = <&gcc GCC_MSS_RESTART>; reset-names = "mss_restart"; + power-domains = <&rpmpd MSM8974_VDDCX>; + power-domain-names = "cx"; + qcom,halt-regs = <&tcsr_mutex 0x1180 0x1200 0x1280>; qcom,smem-states = <&modem_smp2p_out 0>; @@ -2208,6 +2249,9 @@ clocks = <&xo_board>; clock-names = "xo"; + power-domains = <&rpmpd MSM8974_VDDCX>; + power-domain-names = "cx"; + memory-region = <&adsp_region>; qcom,smem-states = <&adsp_smp2p_out 0>; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-fairphone-fp2.dts b/arch/arm/boot/dts/qcom/qcom-msm8974pro-fairphone-fp2.dts index fe227fd3f908..a081aeadd1d4 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974pro-fairphone-fp2.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-fairphone-fp2.dts @@ -156,7 +156,6 @@ status = "okay"; vddmx-supply = <&pm8841_s1>; - vddcx-supply = <&pm8841_s2>; vddpx-supply = <&pm8941_s3>; pinctrl-names = "default"; @@ -181,12 +180,10 @@ &remoteproc_adsp { status = "okay"; - cx-supply = <&pm8841_s2>; }; &remoteproc_mss { status = "okay"; - cx-supply = <&pm8841_s2>; mss-supply = <&pm8841_s3>; mx-supply = <&pm8841_s1>; pll-supply = <&pm8941_l12>; @@ -201,11 +198,6 @@ regulator-max-microvolt = <1050000>; }; - pm8841_s2: s2 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - pm8841_s3: s3 { regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts b/arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts index b896cc1ad6f7..402372834c53 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts @@ -70,7 +70,6 @@ &pronto { vddmx-supply = <&pm8841_s1>; - vddcx-supply = <&pm8841_s2>; vddpx-supply = <&pm8941_s3>; pinctrl-0 = <&wcnss_pin_a>; @@ -104,20 +103,10 @@ regulator-max-microvolt = <1050000>; }; - pm8841_s2: s2 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - pm8841_s3: s3 { regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; }; - - pm8841_s4: s4 { - regulator-min-microvolt = <815000>; - regulator-max-microvolt = <900000>; - }; }; regulators-1 { diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-oneplus-bacon.dts b/arch/arm/boot/dts/qcom/qcom-msm8974pro-oneplus-bacon.dts index 88ff6535477b..258bbbecd927 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974pro-oneplus-bacon.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-oneplus-bacon.dts @@ -214,7 +214,6 @@ &pronto { vddmx-supply = <&pm8841_s1>; - vddcx-supply = <&pm8841_s2>; vddpx-supply = <&pm8941_s3>; pinctrl-names = "default"; @@ -240,8 +239,6 @@ }; &remoteproc_adsp { - cx-supply = <&pm8841_s2>; - status = "okay"; }; @@ -254,12 +251,6 @@ regulator-max-microvolt = <1050000>; }; - pm8841_s2: s2 { - regulator-min-microvolt = <875000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - }; - pm8841_s3: s3 { regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-samsung-klte-common.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974pro-samsung-klte-common.dtsi index d3959741d2ea..56a1a25f3df3 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974pro-samsung-klte-common.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-samsung-klte-common.dtsi @@ -453,12 +453,10 @@ &remoteproc_adsp { status = "okay"; - cx-supply = <&pma8084_s2>; }; &remoteproc_mss { status = "okay"; - cx-supply = <&pma8084_s2>; mss-supply = <&pma8084_s6>; mx-supply = <&pma8084_s1>; pll-supply = <&pma8084_l12>; @@ -474,11 +472,6 @@ regulator-always-on; }; - pma8084_s2: s2 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - pma8084_s3: s3 { regulator-min-microvolt = <1300000>; regulator-max-microvolt = <1300000>; @@ -648,6 +641,10 @@ }; }; +&rpmpd { + compatible = "qcom,msm8974pro-pma8084-rpmpd"; +}; + &sdhc_1 { status = "okay"; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-common.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-common.dtsi index 6af7c71c7158..3d2de30b495e 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-common.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-common.dtsi @@ -207,12 +207,10 @@ }; &remoteproc_adsp { - cx-supply = <&pm8841_s2>; status = "okay"; }; &remoteproc_mss { - cx-supply = <&pm8841_s2>; mss-supply = <&pm8841_s3>; mx-supply = <&pm8841_s1>; pll-supply = <&pm8941_l12>; @@ -228,20 +226,10 @@ regulator-max-microvolt = <1050000>; }; - pm8841_s2: s2 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - pm8841_s3: s3 { regulator-min-microvolt = <500000>; regulator-max-microvolt = <1050000>; }; - - pm8841_s4: s4 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; }; regulators-1 { diff --git a/arch/arm/boot/dts/renesas/gr-peach-audiocamerashield.dtsi b/arch/arm/boot/dts/renesas/gr-peach-audiocamerashield.dtsi deleted file mode 100644 index 8d77579807ec..000000000000 --- a/arch/arm/boot/dts/renesas/gr-peach-audiocamerashield.dtsi +++ /dev/null @@ -1,75 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the GR-Peach audiocamera shield expansion board - * - * Copyright (C) 2017 Jacopo Mondi <jacopo+renesas@jmondi.org> - */ - -#include "r7s72100.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/r7s72100-pinctrl.h> - -/ { - /* On-board camera clock. */ - camera_clk: camera_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <27000000>; - }; -}; - -&pinctrl { - i2c1_pins: i2c1 { - /* P1_2 as SCL; P1_3 as SDA */ - pinmux = <RZA1_PINMUX(1, 2, 1)>, <RZA1_PINMUX(1, 3, 1)>; - }; - - vio_pins: vio { - /* CEU pins: VIO_D[0-10], VIO_VD, VIO_HD, VIO_CLK */ - pinmux = <RZA1_PINMUX(1, 0, 5)>, /* VIO_VD */ - <RZA1_PINMUX(1, 1, 5)>, /* VIO_HD */ - <RZA1_PINMUX(2, 0, 7)>, /* VIO_D0 */ - <RZA1_PINMUX(2, 1, 7)>, /* VIO_D1 */ - <RZA1_PINMUX(2, 2, 7)>, /* VIO_D2 */ - <RZA1_PINMUX(2, 3, 7)>, /* VIO_D3 */ - <RZA1_PINMUX(2, 4, 7)>, /* VIO_D4 */ - <RZA1_PINMUX(2, 5, 7)>, /* VIO_D5 */ - <RZA1_PINMUX(2, 6, 7)>, /* VIO_D6 */ - <RZA1_PINMUX(2, 7, 7)>, /* VIO_D7 */ - <RZA1_PINMUX(10, 0, 6)>; /* VIO_CLK */ - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - status = "okay"; - clock-frequency = <100000>; - - camera@48 { - compatible = "aptina,mt9v111"; - reg = <0x48>; - - clocks = <&camera_clk>; - - port { - mt9v111_out: endpoint { - remote-endpoint = <&ceu_in>; - }; - }; - }; -}; - -&ceu { - pinctrl-names = "default"; - pinctrl-0 = <&vio_pins>; - - status = "okay"; - - port { - ceu_in: endpoint { - remote-endpoint = <&mt9v111_out>; - }; - }; -}; diff --git a/arch/arm/boot/dts/renesas/r8a77xx-aa121td01-panel.dtsi b/arch/arm/boot/dts/renesas/r8a77xx-aa121td01-panel.dtsi deleted file mode 100644 index 6e7589ea7562..000000000000 --- a/arch/arm/boot/dts/renesas/r8a77xx-aa121td01-panel.dtsi +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Common file for the AA121TD01 panel connected to Renesas R-Car boards - * - * Copyright (C) 2015 Renesas Electronics Corp. - */ - -/ { - panel { - compatible = "mitsubishi,aa121td01", "panel-lvds"; - - width-mm = <261>; - height-mm = <163>; - data-mapping = "jeida-18"; - - panel-timing { - /* 1280x800 @60Hz */ - clock-frequency = <71000000>; - hactive = <1280>; - vactive = <800>; - hsync-len = <70>; - hfront-porch = <20>; - hback-porch = <70>; - vsync-len = <5>; - vfront-porch = <3>; - vback-porch = <15>; - }; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds_connector>; - }; - }; - }; -}; - -&lvds_connector { - remote-endpoint = <&panel_in>; -}; diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/renesas/r9a06g032.dtsi index 8debb77803bb..f4f760aff28b 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi @@ -453,6 +453,12 @@ <&sysctrl R9A06G032_CLK_SWITCH>; clock-names = "hclk", "clk"; power-domains = <&sysctrl>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dlr", "switch", "prp", "hub", "ptrn"; status = "disabled"; ethernet-ports { @@ -509,6 +515,165 @@ <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; }; + /* + * The GPIO mapping to the corresponding pins is not obvious. + * See the hardware documentation for details. + */ + gpio0: gpio@5000b000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x5000b000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&sysctrl R9A06G032_HCLK_GPIO0>; + clock-names = "bus"; + + /* GPIO0a[0] connected to pin GPIO0 */ + /* GPIO0a[1..2] connected to pins GPIO3..4 */ + /* GPIO0a[3..4] connected to pins GPIO9..10 */ + /* GPIO0a[5] connected to pin GPIO12 */ + /* GPIO0a[6..7] connected to pins GPIO15..16 */ + /* GPIO0a[8..9] connected to pins GPIO21..22 */ + /* GPIO0a[10] connected to pin GPIO24 */ + /* GPIO0a[11..12] connected to pins GPIO27..28 */ + /* GPIO0a[13..14] connected to pins GPIO33..34 */ + /* GPIO0a[15] connected to pin GPIO36 */ + /* GPIO0a[16..17] connected to pins GPIO39..40 */ + /* GPIO0a[18..19] connected to pins GPIO45..46 */ + /* GPIO0a[20] connected to pin GPIO48 */ + /* GPIO0a[21..22] connected to pins GPIO51..52 */ + /* GPIO0a[23..24] connected to pins GPIO57..58 */ + /* GPIO0a[25..31] connected to pins GPIO62..68 */ + gpio0a: gpio-port@0 { + compatible = "snps,dw-apb-gpio-port"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + + interrupt-controller; + interrupt-parent = <&gpioirqmux>; + interrupts = < 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31>; + #interrupt-cells = <2>; + }; + + /* GPIO0b[0..1] connected to pins GPIO1..2 */ + /* GPIO0b[2..5] connected to pins GPIO5..8 */ + /* GPIO0b[6] connected to pin GPIO11 */ + /* GPIO0b[7..8] connected to pins GPIO13..14 */ + /* GPIO0b[9..12] connected to pins GPIO17..20 */ + /* GPIO0b[13] connected to pin GPIO23 */ + /* GPIO0b[14..15] connected to pins GPIO25..26 */ + /* GPIO0b[16..19] connected to pins GPIO29..32 */ + /* GPIO0b[20] connected to pin GPIO35 */ + /* GPIO0b[21..22] connected to pins GPIO37..38 */ + /* GPIO0b[23..26] connected to pins GPIO41..44 */ + /* GPIO0b[27] connected to pin GPIO47 */ + /* GPIO0b[28..29] connected to pins GPIO49..50 */ + /* GPIO0b[30..31] connected to pins GPIO53..54 */ + gpio0b: gpio-port@1 { + compatible = "snps,dw-apb-gpio-port"; + reg = <1>; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + }; + }; + + gpio1: gpio@5000c000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x5000c000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&sysctrl R9A06G032_HCLK_GPIO1>; + clock-names = "bus"; + + /* GPIO1a[0..4] connected to pins GPIO69..73 */ + /* GPIO1a[5..31] connected to pins GPIO95..121 */ + gpio1a: gpio-port@0 { + compatible = "snps,dw-apb-gpio-port"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + + interrupt-controller; + interrupt-parent = <&gpioirqmux>; + interrupts = <32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63>; + #interrupt-cells = <2>; + }; + + /* GPIO1b[0..1] connected to pins GPIO55..56 */ + /* GPIO1b[2..4] connected to pins GPIO59..61 */ + /* GPIO1b[5..25] connected to pins GPIO74..94 */ + /* GPIO1b[26..31] connected to pins GPIO150..155 */ + gpio1b: gpio-port@1 { + compatible = "snps,dw-apb-gpio-port"; + reg = <1>; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + }; + }; + + gpio2: gpio@5000d000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x5000d000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&sysctrl R9A06G032_HCLK_GPIO2>; + clock-names = "bus"; + + /* GPIO2a[0..27] connected to pins GPIO122..149 */ + /* GPIO2a[28..31] connected to pins GPIO156..159 */ + gpio2a: gpio-port@0 { + compatible = "snps,dw-apb-gpio-port"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + + interrupt-controller; + interrupt-parent = <&gpioirqmux>; + interrupts = <64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95>; + #interrupt-cells = <2>; + }; + + /* GPIO2b[0..9] connected to pins GPIO160..169 */ + gpio2b: gpio-port@1 { + compatible = "snps,dw-apb-gpio-port"; + reg = <1>; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <10>; + }; + }; + + gpioirqmux: interrupt-controller@51000480 { + compatible = "renesas,r9a06g032-gpioirqmux", "renesas,rzn1-gpioirqmux"; + reg = <0x51000480 0x20>; + #interrupt-cells = <1>; + #address-cells = <0>; + interrupt-map-mask = <0x7f>; + + /* + * Example mapping entry. Board DTs need to overwrite + * 'interrupt-map' with their specific mapping. Check + * the irqmux binding documentation for details. + */ + interrupt-map = <0 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + can0: can@52104000 { compatible = "renesas,r9a06g032-sja1000", "renesas,rzn1-sja1000"; reg = <0x52104000 0x800>; diff --git a/arch/arm/boot/dts/rockchip/rk3036.dtsi b/arch/arm/boot/dts/rockchip/rk3036.dtsi index fca21ebb224b..78afae42f8b2 100644 --- a/arch/arm/boot/dts/rockchip/rk3036.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3036.dtsi @@ -23,9 +23,6 @@ i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; - mshc0 = &emmc; - mshc1 = &sdmmc; - mshc2 = &sdio; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi index 7477fc5da3ec..4e5e7509de48 100644 --- a/arch/arm/boot/dts/rockchip/rk3288.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi @@ -1288,6 +1288,21 @@ power-domains = <&power RK3288_PD_VIDEO>; }; + hevc: video-codec@ff9c0000 { + compatible = "rockchip,rk3288-vdec"; + reg = <0x0 0xff9c0000 0x0 0x440>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>, + <&cru SCLK_HEVC_CABAC>, <&cru SCLK_HEVC_CORE>; + clock-names = "axi", "ahb", "cabac", "core"; + assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>, + <&cru SCLK_HEVC_CABAC>, <&cru SCLK_HEVC_CORE>; + assigned-clock-rates = <400000000>, <100000000>, + <300000000>, <300000000>; + iommus = <&hevc_mmu>; + power-domains = <&power RK3288_PD_HEVC>; + }; + hevc_mmu: iommu@ff9c0440 { compatible = "rockchip,iommu"; reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>; @@ -1295,7 +1310,7 @@ clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>; clock-names = "aclk", "iface"; #iommu-cells = <0>; - status = "disabled"; + power-domains = <&power RK3288_PD_HEVC>; }; gpu: gpu@ffa30000 { diff --git a/arch/arm/boot/dts/samsung/s3c6400.dtsi b/arch/arm/boot/dts/samsung/s3c6400.dtsi deleted file mode 100644 index 7cc785a63866..000000000000 --- a/arch/arm/boot/dts/samsung/s3c6400.dtsi +++ /dev/null @@ -1,38 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's S3C6400 SoC device tree source - * - * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com> - * - * Samsung's S3C6400 SoC device nodes are listed in this file. S3C6400 - * based board files can include this file and provide values for board specific - * bindings. - * - * Note: This file does not include device nodes for all the controllers in - * S3C6400 SoC. As device tree coverage for S3C6400 increases, additional - * nodes can be added to this file. - */ - -#include "s3c64xx.dtsi" - -/ { - compatible = "samsung,s3c6400"; -}; - -&vic0 { - valid-mask = <0xfffffe1f>; - valid-wakeup-mask = <0x00200004>; -}; - -&vic1 { - valid-mask = <0xffffffff>; - valid-wakeup-mask = <0x53020000>; -}; - -&soc { - clocks: clock-controller@7e00f000 { - compatible = "samsung,s3c6400-clock"; - reg = <0x7e00f000 0x1000>; - #clock-cells = <1>; - }; -}; diff --git a/arch/arm/boot/dts/st/spear320s.dtsi b/arch/arm/boot/dts/st/spear320s.dtsi deleted file mode 100644 index 133236dc190d..000000000000 --- a/arch/arm/boot/dts/st/spear320s.dtsi +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * DTS file for SPEAr320s SoC - * - * Copyright 2021 Herve Codina <herve.codina@bootlin.com> - */ - -/include/ "spear320.dtsi" - -/ { - ahb { - apb { - gpiopinctrl: gpio@b3000000 { - /* - * The "RM0321 SPEAr320s address and map - * registers" document mentions interrupt 6 - * (NPGIO_INTR) for the PL_GPIO interrupt. - */ - interrupts = <6>; - interrupt-parent = <&shirq>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/st/stm32429i-eval.dts b/arch/arm/boot/dts/st/stm32429i-eval.dts index afa417b34b25..f4b1c4eb64f2 100644 --- a/arch/arm/boot/dts/st/stm32429i-eval.dts +++ b/arch/arm/boot/dts/st/stm32429i-eval.dts @@ -48,8 +48,9 @@ /dts-v1/; #include "stm32f429.dtsi" #include "stm32f429-pinctrl.dtsi" -#include <dt-bindings/input/input.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> #include <dt-bindings/media/video-interfaces.h> / { @@ -82,40 +83,24 @@ dma-ranges = <0xc0000000 0x0 0x10000000>; }; - vdda: regulator-vdda { - compatible = "regulator-fixed"; - regulator-name = "vdda"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vref: regulator-vref { - compatible = "regulator-fixed"; - regulator-name = "vref"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd_panel: vdd-panel { - compatible = "regulator-fixed"; - regulator-name = "vdd_panel"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - leds { compatible = "gpio-leds"; - led-green { + led_green: led-green { + function = LED_FUNCTION_HEARTBEAT; + color = <LED_COLOR_ID_GREEN>; gpios = <&gpiog 6 1>; linux,default-trigger = "heartbeat"; }; led-orange { + color = <LED_COLOR_ID_ORANGE>; gpios = <&gpiog 7 1>; }; led-red { + color = <LED_COLOR_ID_RED>; gpios = <&gpiog 10 1>; }; led-blue { + color = <LED_COLOR_ID_BLUE>; gpios = <&gpiog 12 1>; }; }; @@ -135,11 +120,18 @@ }; }; - usbotg_hs_phy: usbphy { - #phy-cells = <0>; - compatible = "usb-nop-xceiv"; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHSULPI)>; - clock-names = "main_clk"; + mmc_vcard: mmc_vcard { + compatible = "regulator-fixed"; + regulator-name = "mmc_vcard"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + options { + u-boot { + compatible = "u-boot,config"; + boot-led = <&led_green>; + }; }; panel_rgb: panel-rgb { @@ -153,9 +145,30 @@ }; }; - mmc_vcard: mmc_vcard { + vdda: regulator-vdda { compatible = "regulator-fixed"; - regulator-name = "mmc_vcard"; + regulator-name = "vdda"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vref: regulator-vref { + compatible = "regulator-fixed"; + regulator-name = "vref"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + usbotg_hs_phy: usbphy { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHSULPI)>; + clock-names = "main_clk"; + }; + + vdd_panel: vdd-panel { + compatible = "regulator-fixed"; + regulator-name = "vdd_panel"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; diff --git a/arch/arm/boot/dts/st/stm32746g-eval.dts b/arch/arm/boot/dts/st/stm32746g-eval.dts index e9ac37b6eca0..6772c1f9d03e 100644 --- a/arch/arm/boot/dts/st/stm32746g-eval.dts +++ b/arch/arm/boot/dts/st/stm32746g-eval.dts @@ -45,6 +45,7 @@ #include "stm32f746-pinctrl.dtsi" #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/leds/common.h> / { model = "STMicroelectronics STM32746g-EVAL board"; @@ -66,17 +67,22 @@ leds { compatible = "gpio-leds"; - led-green { + led_green: led-green { + function = LED_FUNCTION_HEARTBEAT; + color = <LED_COLOR_ID_GREEN>; gpios = <&gpiof 10 1>; linux,default-trigger = "heartbeat"; }; led-orange { + color = <LED_COLOR_ID_ORANGE>; gpios = <&stmfx_pinctrl 17 1>; }; led-red { + color = <LED_COLOR_ID_RED>; gpios = <&gpiob 7 1>; }; led-blue { + color = <LED_COLOR_ID_BLUE>; gpios = <&stmfx_pinctrl 19 1>; }; }; @@ -127,6 +133,13 @@ }; }; + options { + u-boot { + compatible = "u-boot,config"; + boot-led = <&led_green>; + }; + }; + usbotg_hs_phy: usb-phy { #phy-cells = <0>; compatible = "usb-nop-xceiv"; diff --git a/arch/arm/boot/dts/st/stm32f429-disco.dts b/arch/arm/boot/dts/st/stm32f429-disco.dts index a3cb4aabdd5a..ded369abee4f 100644 --- a/arch/arm/boot/dts/st/stm32f429-disco.dts +++ b/arch/arm/boot/dts/st/stm32f429-disco.dts @@ -48,9 +48,10 @@ /dts-v1/; #include "stm32f429.dtsi" #include "stm32f429-pinctrl.dtsi" +#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> / { model = "STMicroelectronics STM32F429i-DISCO board"; @@ -73,9 +74,12 @@ leds { compatible = "gpio-leds"; led-red { + color = <LED_COLOR_ID_RED>; gpios = <&gpiog 14 0>; }; - led-green { + led_green: led-green { + function = LED_FUNCTION_HEARTBEAT; + color = <LED_COLOR_ID_GREEN>; gpios = <&gpiog 13 0>; linux,default-trigger = "heartbeat"; }; @@ -91,6 +95,13 @@ }; }; + options { + u-boot { + compatible = "u-boot,config"; + boot-led = <&led_green>; + }; + }; + /* This turns on vbus for otg for host mode (dwc2) */ vcc5v_otg: vcc5v-otg-regulator { compatible = "regulator-fixed"; diff --git a/arch/arm/boot/dts/st/stm32f469-disco.dts b/arch/arm/boot/dts/st/stm32f469-disco.dts index 8a4f8ddd083d..943afba06b5f 100644 --- a/arch/arm/boot/dts/st/stm32f469-disco.dts +++ b/arch/arm/boot/dts/st/stm32f469-disco.dts @@ -50,6 +50,7 @@ #include "stm32f469-pinctrl.dtsi" #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> / { model = "STMicroelectronics STM32F469i-DISCO board"; @@ -82,17 +83,22 @@ leds { compatible = "gpio-leds"; - led-green { + led_green: led-green { + function = LED_FUNCTION_HEARTBEAT; + color = <LED_COLOR_ID_GREEN>; gpios = <&gpiog 6 GPIO_ACTIVE_LOW>; linux,default-trigger = "heartbeat"; }; led-orange { + color = <LED_COLOR_ID_ORANGE>; gpios = <&gpiod 4 GPIO_ACTIVE_LOW>; }; led-red { + color = <LED_COLOR_ID_RED>; gpios = <&gpiod 5 GPIO_ACTIVE_LOW>; }; led-blue { + color = <LED_COLOR_ID_BLUE>; gpios = <&gpiok 3 GPIO_ACTIVE_LOW>; }; }; @@ -107,6 +113,13 @@ }; }; + options { + u-boot { + compatible = "u-boot,config"; + boot-led = <&led_green>; + }; + }; + /* This turns on vbus for otg for host mode (dwc2) */ vcc5v_otg: vcc5v-otg-regulator { compatible = "regulator-fixed"; diff --git a/arch/arm/boot/dts/st/stm32f746-disco.dts b/arch/arm/boot/dts/st/stm32f746-disco.dts index b57dbdce2f40..61ca41ea523e 100644 --- a/arch/arm/boot/dts/st/stm32f746-disco.dts +++ b/arch/arm/boot/dts/st/stm32f746-disco.dts @@ -46,6 +46,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/leds/common.h> / { model = "STMicroelectronics STM32F746-DISCO board"; @@ -80,7 +81,9 @@ leds { compatible = "gpio-leds"; - led-usr { + led_usr: led-usr { + function = LED_FUNCTION_HEARTBEAT; + color = <LED_COLOR_ID_GREEN>; gpios = <&gpioi 1 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; @@ -96,6 +99,13 @@ }; }; + options { + u-boot { + compatible = "u-boot,config"; + boot-led = <&led_usr>; + }; + }; + usbotg_hs_phy: usb-phy { #phy-cells = <0>; compatible = "usb-nop-xceiv"; diff --git a/arch/arm/boot/dts/st/stm32f769-disco.dts b/arch/arm/boot/dts/st/stm32f769-disco.dts index 535cfdc4681c..e5854fa1071b 100644 --- a/arch/arm/boot/dts/st/stm32f769-disco.dts +++ b/arch/arm/boot/dts/st/stm32f769-disco.dts @@ -45,6 +45,7 @@ #include "stm32f769-pinctrl.dtsi" #include <dt-bindings/input/input.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> / { model = "STMicroelectronics STM32F769-DISCO board"; @@ -79,14 +80,18 @@ leds { compatible = "gpio-leds"; - led-usr2 { + led_usr2: led-usr2 { + function = LED_FUNCTION_HEARTBEAT; + color = <LED_COLOR_ID_GREEN>; gpios = <&gpioj 5 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; led-usr1 { + color = <LED_COLOR_ID_RED>; gpios = <&gpioj 13 GPIO_ACTIVE_HIGH>; }; led-usr3 { + color = <LED_COLOR_ID_GREEN>; gpios = <&gpioa 12 GPIO_ACTIVE_HIGH>; }; }; @@ -101,6 +106,13 @@ }; }; + options { + u-boot { + compatible = "u-boot,config"; + boot-led = <&led_usr2>; + }; + }; + usbotg_hs_phy: usb-phy { #phy-cells = <0>; compatible = "usb-nop-xceiv"; diff --git a/arch/arm/boot/dts/st/stm32h743i-disco.dts b/arch/arm/boot/dts/st/stm32h743i-disco.dts index 8451a54a9a08..78d55b77db7c 100644 --- a/arch/arm/boot/dts/st/stm32h743i-disco.dts +++ b/arch/arm/boot/dts/st/stm32h743i-disco.dts @@ -43,6 +43,8 @@ /dts-v1/; #include "stm32h743.dtsi" #include "stm32h7-pinctrl.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> / { model = "STMicroelectronics STM32H743i-Discovery board"; @@ -69,6 +71,38 @@ regulator-max-microvolt = <3300000>; regulator-always-on; }; + + leds { + compatible = "gpio-leds"; + led_green: led-green { + function = LED_FUNCTION_HEARTBEAT; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioi 12 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + + led-orange { + color = <LED_COLOR_ID_ORANGE>; + gpios = <&gpioi 13 GPIO_ACTIVE_LOW>; + }; + + led-red { + color = <LED_COLOR_ID_RED>; + gpios = <&gpioi 14 GPIO_ACTIVE_LOW>; + }; + + led-blue { + color = <LED_COLOR_ID_BLUE>; + gpios = <&gpioi 15 GPIO_ACTIVE_LOW>; + }; + }; + + options { + u-boot { + compatible = "u-boot,config"; + boot-led = <&led_green>; + }; + }; }; &clk_hse { diff --git a/arch/arm/boot/dts/st/stm32h743i-eval.dts b/arch/arm/boot/dts/st/stm32h743i-eval.dts index 4b0ced27b80e..e5e10b0758ee 100644 --- a/arch/arm/boot/dts/st/stm32h743i-eval.dts +++ b/arch/arm/boot/dts/st/stm32h743i-eval.dts @@ -43,6 +43,8 @@ /dts-v1/; #include "stm32h743.dtsi" #include "stm32h7-pinctrl.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> / { model = "STMicroelectronics STM32H743i-EVAL board"; @@ -62,6 +64,29 @@ serial0 = &usart1; }; + led { + compatible = "gpio-leds"; + led_green: led-green { + function = LED_FUNCTION_HEARTBEAT; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpiof 10 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led-red { + color = <LED_COLOR_ID_RED>; + gpios = <&gpioa 4 GPIO_ACTIVE_LOW>; + }; + }; + + options { + u-boot { + compatible = "u-boot,config"; + boot-led = <&led_green>; + }; + }; + vdda: regulator-vdda { compatible = "regulator-fixed"; regulator-name = "vdda"; diff --git a/arch/arm/boot/dts/st/stm32h747i-disco.dts b/arch/arm/boot/dts/st/stm32h747i-disco.dts index 99f0255dae8e..c9dcc680e26d 100644 --- a/arch/arm/boot/dts/st/stm32h747i-disco.dts +++ b/arch/arm/boot/dts/st/stm32h747i-disco.dts @@ -8,6 +8,7 @@ #include "stm32h7-pinctrl.dtsi" #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> / { model = "STMicroelectronics STM32H747i-Discovery board"; @@ -38,17 +39,22 @@ leds { compatible = "gpio-leds"; - led-green { + led_green: led-green { + function = LED_FUNCTION_HEARTBEAT; + color = <LED_COLOR_ID_GREEN>; gpios = <&gpioi 12 GPIO_ACTIVE_LOW>; linux,default-trigger = "heartbeat"; }; led-orange { + color = <LED_COLOR_ID_ORANGE>; gpios = <&gpioi 13 GPIO_ACTIVE_LOW>; }; led-red { + color = <LED_COLOR_ID_RED>; gpios = <&gpioi 14 GPIO_ACTIVE_LOW>; }; led-blue { + color = <LED_COLOR_ID_BLUE>; gpios = <&gpioi 15 GPIO_ACTIVE_LOW>; }; }; @@ -87,6 +93,13 @@ gpios = <&gpiok 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; }; }; + + options { + u-boot { + compatible = "u-boot,config"; + boot-led = <&led_green>; + }; + }; }; &clk_hse { diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts b/arch/arm/boot/dts/st/stm32mp135f-dk.dts index f894ee35b3db..8dcf68b212b4 100644 --- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts @@ -73,13 +73,26 @@ leds { compatible = "gpio-leds"; - led-blue { + led_blue: led-blue { function = LED_FUNCTION_HEARTBEAT; color = <LED_COLOR_ID_BLUE>; gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; linux,default-trigger = "heartbeat"; default-state = "off"; }; + + led-red { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_RED>; + gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; + }; + }; + + options { + u-boot { + compatible = "u-boot,config"; + boot-led = <&led_blue>; + }; }; panel_backlight: panel-backlight { diff --git a/arch/arm/boot/dts/st/stm32mp157c-ed1.dts b/arch/arm/boot/dts/st/stm32mp157c-ed1.dts index f6c478dbd041..49dd555cc228 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-ed1.dts @@ -74,13 +74,26 @@ led { compatible = "gpio-leds"; - led-blue { + led_blue: led-blue { gpios = <&gpiod 9 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; default-state = "off"; function = LED_FUNCTION_HEARTBEAT; color = <LED_COLOR_ID_BLUE>; }; + + led-red { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_RED>; + gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; + }; + }; + + options { + u-boot { + compatible = "u-boot,config"; + boot-led = <&led_blue>; + }; }; sd_switch: regulator-sd_switch { diff --git a/arch/arm/boot/dts/st/stm32mp157c-ev1.dts b/arch/arm/boot/dts/st/stm32mp157c-ev1.dts index 8f99c30f1af1..4e46d58bf61f 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-ev1.dts @@ -296,8 +296,9 @@ }; &spi1 { - pinctrl-names = "default"; + pinctrl-names = "default", "sleep"; pinctrl-0 = <&spi1_pins_a>; + pinctrl-1 = <&spi1_sleep_pins_a>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi index 8cea6facd27b..7ed2b01958fe 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi @@ -5,6 +5,7 @@ */ #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> #include <dt-bindings/mfd/st,stpmic1.h> / { @@ -63,12 +64,26 @@ led { compatible = "gpio-leds"; - led-blue { - label = "heartbeat"; + led_blue: led-blue { + function = LED_FUNCTION_HEARTBEAT; + color = <LED_COLOR_ID_BLUE>; gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; default-state = "off"; }; + + led-red { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_RED>; + gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; + }; + }; + + options { + u-boot { + compatible = "u-boot,config"; + boot-led = <&led_blue>; + }; }; sound { diff --git a/arch/arm/boot/dts/st/stm32mp15xxab-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp15xxab-pinctrl.dtsi deleted file mode 100644 index 328dad140e9b..000000000000 --- a/arch/arm/boot/dts/st/stm32mp15xxab-pinctrl.dtsi +++ /dev/null @@ -1,57 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2019 - All Rights Reserved - * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics. - */ - -&pinctrl { - st,package = <STM32MP_PKG_AB>; - - gpioa: gpio@50002000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 0 16>; - }; - - gpiob: gpio@50003000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 16 16>; - }; - - gpioc: gpio@50004000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 32 16>; - }; - - gpiod: gpio@50005000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 48 16>; - }; - - gpioe: gpio@50006000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 64 16>; - }; - - gpiof: gpio@50007000 { - status = "okay"; - ngpios = <6>; - gpio-ranges = <&pinctrl 6 86 6>; - }; - - gpiog: gpio@50008000 { - status = "okay"; - ngpios = <10>; - gpio-ranges = <&pinctrl 6 102 10>; - }; - - gpioh: gpio@50009000 { - status = "okay"; - ngpios = <2>; - gpio-ranges = <&pinctrl 0 112 2>; - }; -}; diff --git a/arch/arm/boot/dts/ti/omap/Makefile b/arch/arm/boot/dts/ti/omap/Makefile index 14e500846875..3f54b515c471 100644 --- a/arch/arm/boot/dts/ti/omap/Makefile +++ b/arch/arm/boot/dts/ti/omap/Makefile @@ -86,7 +86,6 @@ dtb-$(CONFIG_SOC_AM33XX) += \ am335x-baltos-ir2110.dtb \ am335x-baltos-ir3220.dtb \ am335x-baltos-ir5221.dtb \ - am335x-base0033.dtb \ am335x-bone.dtb \ am335x-boneblack.dtb \ am335x-boneblack-wireless.dtb \ diff --git a/arch/arm/boot/dts/ti/omap/am335x-baltos-leds.dtsi b/arch/arm/boot/dts/ti/omap/am335x-baltos-leds.dtsi index ed194469973e..a827153ba6bb 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-baltos-leds.dtsi +++ b/arch/arm/boot/dts/ti/omap/am335x-baltos-leds.dtsi @@ -22,6 +22,7 @@ linux,default-trigger = "default-on"; gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; default-state = "on"; + panic-indicator; }; led_wlan: led-wlan { label = "onrisc:blue:wlan"; diff --git a/arch/arm/boot/dts/ti/omap/am335x-base0033.dts b/arch/arm/boot/dts/ti/omap/am335x-base0033.dts deleted file mode 100644 index 46078af4b7a3..000000000000 --- a/arch/arm/boot/dts/ti/omap/am335x-base0033.dts +++ /dev/null @@ -1,92 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * am335x-base0033.dts - Device Tree file for IGEP AQUILA EXPANSION - * - * Copyright (C) 2013 ISEE 2007 SL - https://www.isee.biz - */ - -#include "am335x-igep0033.dtsi" - -/ { - model = "IGEP COM AM335x on AQUILA Expansion"; - compatible = "isee,am335x-base0033", "isee,am335x-igep0033", "ti,am33xx"; - - hdmi { - compatible = "ti,tilcdc,slave"; - i2c = <&i2c0>; - pinctrl-names = "default", "off"; - pinctrl-0 = <&nxp_hdmi_pins>; - pinctrl-1 = <&nxp_hdmi_off_pins>; - status = "okay"; - }; - - leds_base { - pinctrl-names = "default"; - pinctrl-0 = <&leds_base_pins>; - - compatible = "gpio-leds"; - - led0 { - label = "base:red:user"; - gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; /* gpio1_21 */ - default-state = "off"; - }; - - led1 { - label = "base:green:user"; - gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>; /* gpio2_0 */ - default-state = "off"; - }; - }; -}; - -&am33xx_pinmux { - nxp_hdmi_pins: nxp-hdmi-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE3) /* xdma_event_intr0.clkout1 */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) - >; - }; - nxp_hdmi_off_pins: nxp-hdmi-off-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE3) /* xdma_event_intr0.clkout1 */ - >; - }; - - leds_base_pins: leds-base-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_csn3.gpio2_0 */ - >; - }; -}; - -&lcdc { - status = "okay"; -}; - -&i2c0 { - eeprom: eeprom@50 { - compatible = "atmel,24c256"; - reg = <0x50>; - }; -}; diff --git a/arch/arm/boot/dts/ti/omap/am3703.dtsi b/arch/arm/boot/dts/ti/omap/am3703.dtsi deleted file mode 100644 index 2b994ae790c9..000000000000 --- a/arch/arm/boot/dts/ti/omap/am3703.dtsi +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2020 André Hentschel <nerv@dawncrow.de> - */ - -#include "omap36xx.dtsi" - -&iva { - status = "disabled"; -}; - -&sgx_module { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/ti/omap/am3715.dtsi b/arch/arm/boot/dts/ti/omap/am3715.dtsi deleted file mode 100644 index ab328e8c0bd8..000000000000 --- a/arch/arm/boot/dts/ti/omap/am3715.dtsi +++ /dev/null @@ -1,10 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2020 André Hentschel <nerv@dawncrow.de> - */ - -#include "omap36xx.dtsi" - -&iva { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi b/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi index c9282f57ffa5..db6c53bbaf51 100644 --- a/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi +++ b/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi @@ -109,7 +109,6 @@ scm_conf1: scm_conf@1c04 { compatible = "syscon"; reg = <0x1c04 0x0020>; - #syscon-cells = <2>; }; scm_conf_pcie: scm_conf@1c24 { diff --git a/arch/arm/boot/dts/ti/omap/omap2430.dtsi b/arch/arm/boot/dts/ti/omap/omap2430.dtsi index b9a9e6e45266..222613d2a4d1 100644 --- a/arch/arm/boot/dts/ti/omap/omap2430.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap2430.dtsi @@ -332,7 +332,7 @@ interrupts = <93>; }; - wd_timer2: wdt@49016000 { + wd_timer2: watchdog@49016000 { compatible = "ti,omap2-wdt"; ti,hwmods = "wd_timer2"; reg = <0x49016000 0x80>; diff --git a/arch/arm/boot/dts/ti/omap/omap3.dtsi b/arch/arm/boot/dts/ti/omap/omap3.dtsi index 817474ee2d13..959069e24730 100644 --- a/arch/arm/boot/dts/ti/omap/omap3.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap3.dtsi @@ -553,7 +553,7 @@ status = "disabled"; }; - wdt2: wdt@48314000 { + wdt2: watchdog@48314000 { compatible = "ti,omap3-wdt"; reg = <0x48314000 0x80>; ti,hwmods = "wd_timer2"; diff --git a/arch/arm/boot/dts/ti/omap/omap3430es1-clocks.dtsi b/arch/arm/boot/dts/ti/omap/omap3430es1-clocks.dtsi deleted file mode 100644 index 6e754d265f18..000000000000 --- a/arch/arm/boot/dts/ti/omap/omap3430es1-clocks.dtsi +++ /dev/null @@ -1,237 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for OMAP3430 ES1 clock data - * - * Copyright (C) 2013 Texas Instruments, Inc. - */ -&cm_clocks { - gfx_l3_ck: gfx_l3_ck@b10 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&l3_ick>; - reg = <0x0b10>; - ti,bit-shift = <0>; - }; - - gfx_l3_fck: gfx_l3_fck@b40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&l3_ick>; - ti,max-div = <7>; - reg = <0x0b40>; - ti,index-starts-at-one; - }; - - gfx_l3_ick: gfx_l3_ick { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&gfx_l3_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - gfx_cg1_ck: gfx_cg1_ck@b00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&gfx_l3_fck>; - reg = <0x0b00>; - ti,bit-shift = <1>; - }; - - gfx_cg2_ck: gfx_cg2_ck@b00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&gfx_l3_fck>; - reg = <0x0b00>; - ti,bit-shift = <2>; - }; - - clock@a00 { - compatible = "ti,clksel"; - reg = <0xa00>; - #clock-cells = <2>; - #address-cells = <1>; - #size-cells = <0>; - - d2d_26m_fck: clock-d2d-26m-fck@3 { - reg = <3>; - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clock-output-names = "d2d_26m_fck"; - clocks = <&sys_ck>; - }; - - fshostusb_fck: clock-fshostusb-fck@5 { - reg = <5>; - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clock-output-names = "fshostusb_fck"; - clocks = <&core_48m_fck>; - }; - - ssi_ssr_gate_fck_3430es1: clock-ssi-ssr-gate-fck-3430es1@0 { - reg = <0>; - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clock-output-names = "ssi_ssr_gate_fck_3430es1"; - clocks = <&corex2_fck>; - }; - }; - - clock@a40 { - compatible = "ti,clksel"; - reg = <0xa40>; - #clock-cells = <2>; - #address-cells = <1>; - #size-cells = <0>; - - ssi_ssr_div_fck_3430es1: clock-ssi-ssr-div-fck-3430es1@8 { - reg = <8>; - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clock-output-names = "ssi_ssr_div_fck_3430es1"; - clocks = <&corex2_fck>; - ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; - }; - - usb_l4_div_ick: clock-usb-l4-div-ick@4 { - reg = <4>; - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clock-output-names = "usb_l4_div_ick"; - clocks = <&l4_ick>; - ti,max-div = <1>; - ti,index-starts-at-one; - }; - }; - - ssi_ssr_fck: ssi_ssr_fck_3430es1 { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&ssi_ssr_gate_fck_3430es1>, <&ssi_ssr_div_fck_3430es1>; - }; - - ssi_sst_fck: ssi_sst_fck_3430es1 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&ssi_ssr_fck>; - clock-mult = <1>; - clock-div = <2>; - }; - - clock@a10 { - compatible = "ti,clksel"; - reg = <0xa10>; - #clock-cells = <2>; - #address-cells = <1>; - #size-cells = <0>; - - hsotgusb_ick_3430es1: clock-hsotgusb-ick-3430es1@4 { - reg = <4>; - #clock-cells = <0>; - compatible = "ti,omap3-no-wait-interface-clock"; - clock-output-names = "hsotgusb_ick_3430es1"; - clocks = <&core_l3_ick>; - }; - - fac_ick: clock-fac-ick@8 { - reg = <8>; - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "fac_ick"; - clocks = <&core_l4_ick>; - }; - - ssi_ick: clock-ssi-ick-3430es1@0 { - reg = <0>; - #clock-cells = <0>; - compatible = "ti,omap3-no-wait-interface-clock"; - clock-output-names = "ssi_ick_3430es1"; - clocks = <&ssi_l4_ick>; - }; - - usb_l4_gate_ick: clock-usb-l4-gate-ick@5 { - reg = <5>; - #clock-cells = <0>; - compatible = "ti,composite-interface-clock"; - clock-output-names = "usb_l4_gate_ick"; - clocks = <&l4_ick>; - }; - }; - - ssi_l4_ick: ssi_l4_ick { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&l4_ick>; - clock-mult = <1>; - clock-div = <1>; - }; - - usb_l4_ick: usb_l4_ick { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>; - }; - - clock@e00 { - compatible = "ti,clksel"; - reg = <0xe00>; - #clock-cells = <2>; - #address-cells = <1>; - #size-cells = <0>; - - dss1_alwon_fck: clock-dss1-alwon-fck-3430es1@0 { - reg = <0>; - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "dss1_alwon_fck_3430es1"; - clocks = <&dpll4_m4x2_ck>; - ti,set-rate-parent; - }; - }; - - dss_ick: dss_ick_3430es1@e10 { - #clock-cells = <0>; - compatible = "ti,omap3-no-wait-interface-clock"; - clocks = <&l4_ick>; - reg = <0x0e10>; - ti,bit-shift = <0>; - }; -}; - -&cm_clockdomains { - core_l3_clkdm: core_l3_clkdm { - compatible = "ti,clockdomain"; - clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es1>; - }; - - gfx_3430es1_clkdm: gfx_3430es1_clkdm { - compatible = "ti,clockdomain"; - clocks = <&gfx_l3_ck>, <&gfx_cg1_ck>, <&gfx_cg2_ck>; - }; - - dss_clkdm: dss_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>, - <&dss1_alwon_fck>, <&dss_ick>; - }; - - d2d_clkdm: d2d_clkdm { - compatible = "ti,clockdomain"; - clocks = <&d2d_26m_fck>; - }; - - core_l4_clkdm: core_l4_clkdm { - compatible = "ti,clockdomain"; - clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, - <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, - <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, - <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, - <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, - <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, - <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, - <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, - <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, - <&fshostusb_fck>, <&fac_ick>, <&ssi_ick>; - }; -}; diff --git a/arch/arm/boot/dts/ti/omap/omap4-epson-embt2ws.dts b/arch/arm/boot/dts/ti/omap/omap4-epson-embt2ws.dts index c90f43cc2fae..673df1b693f2 100644 --- a/arch/arm/boot/dts/ti/omap/omap4-epson-embt2ws.dts +++ b/arch/arm/boot/dts/ti/omap/omap4-epson-embt2ws.dts @@ -229,6 +229,11 @@ interrupts = <11>; }; + pwrbutton { + compatible = "ti,twl6030-pwrbutton"; + interrupts = <0>; + }; + ldo2: regulator-ldo2 { compatible = "ti,twl6032-ldo2"; regulator-min-microvolt = <1000000>; diff --git a/arch/arm/boot/dts/ti/omap/omap4-l4-abe.dtsi b/arch/arm/boot/dts/ti/omap/omap4-l4-abe.dtsi index 59f546a278f8..78ac3d4eceb5 100644 --- a/arch/arm/boot/dts/ti/omap/omap4-l4-abe.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap4-l4-abe.dtsi @@ -279,7 +279,7 @@ ranges = <0x0 0x30000 0x1000>, <0x49030000 0x49030000 0x1000>; - wdt3: wdt@0 { + wdt3: watchdog@0 { compatible = "ti,omap4-wdt", "ti,omap3-wdt"; reg = <0x0 0x80>; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/ti/omap/omap4-l4.dtsi b/arch/arm/boot/dts/ti/omap/omap4-l4.dtsi index 4ee53dfb71b4..4881dd674393 100644 --- a/arch/arm/boot/dts/ti/omap/omap4-l4.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap4-l4.dtsi @@ -1133,7 +1133,7 @@ #size-cells = <1>; ranges = <0x0 0x4000 0x1000>; - wdt2: wdt@0 { + wdt2: watchdog@0 { compatible = "ti,omap4-wdt", "ti,omap3-wdt"; reg = <0x0 0x80>; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/ti/omap/omap5-l4.dtsi b/arch/arm/boot/dts/ti/omap/omap5-l4.dtsi index 9f6100c7c34d..487259132ebf 100644 --- a/arch/arm/boot/dts/ti/omap/omap5-l4.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap5-l4.dtsi @@ -2393,7 +2393,7 @@ #size-cells = <1>; ranges = <0x0 0x4000 0x1000>; - wdt2: wdt@0 { + wdt2: watchdog@0 { compatible = "ti,omap5-wdt", "ti,omap3-wdt"; reg = <0x0 0x80>; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/tps65910.dtsi b/arch/arm/boot/dts/tps65910.dtsi index a941d1e62328..f5a776229023 100644 --- a/arch/arm/boot/dts/tps65910.dtsi +++ b/arch/arm/boot/dts/tps65910.dtsi @@ -10,6 +10,10 @@ &tps { compatible = "ti,tps65910"; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; regulators { #address-cells = <1>; diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 200e5067560e..54eb1d7fd419 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -373,7 +373,6 @@ config ARCH_STM32 bool "STMicroelectronics STM32 SoC Family" select GPIOLIB select PINCTRL - select ARM_SMC_MBOX select ARM_SCMI_PROTOCOL select REGULATOR select REGULATOR_ARM_SCMI diff --git a/arch/arm64/boot/dts/airoha/en7581-evb.dts b/arch/arm64/boot/dts/airoha/en7581-evb.dts index dae9968a4ff6..886e2e4b5f64 100644 --- a/arch/arm64/boot/dts/airoha/en7581-evb.dts +++ b/arch/arm64/boot/dts/airoha/en7581-evb.dts @@ -47,17 +47,17 @@ reg = <0x00600000 0x03200000>; }; - tclinux_slave@3800000 { + tclinux-slave@3800000 { label = "tclinux_alt"; reg = <0x03800000 0x03200000>; }; - rootfs_data@6a00000 { + rootfs-data@6a00000 { label = "rootfs_data"; reg = <0x06a00000 0x01400000>; }; - reserved_bmt@7e00000 { + reserved-bmt@7e00000 { label = "reserved_bmt"; reg = <0x07e00000 0x00200000>; read-only; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi index bb5f9e4f3d42..b3fb1e0ee796 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi @@ -420,6 +420,20 @@ #size-cells = <0>; }; + ledc: led-controller@5018000 { + compatible = "allwinner,sun50i-a100-ledc"; + reg = <0x5018000 0x400>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_LEDC>, <&ccu CLK_LEDC>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_LEDC>; + dmas = <&dma 42>; + dma-names = "tx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + emac0: ethernet@5020000 { compatible = "allwinner,sun50i-a100-emac", "allwinner,sun50i-a64-emac"; diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi index 42dab01e3f56..9335977751e2 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -214,6 +214,43 @@ allwinner,pinmux = <2>; }; + /omit-if-no-ref/ + spi0_pc_pins: spi0-pc-pins { + pins = "PC2", "PC4", "PC12"; + function = "spi0"; + allwinner,pinmux = <4>; + }; + + /omit-if-no-ref/ + spi0_cs0_pc_pin: spi0-cs0-pc-pin { + pins = "PC3"; + function = "spi0"; + allwinner,pinmux = <4>; + }; + + /omit-if-no-ref/ + spi0_cs1_pc_pin: spi0-cs1-pc-pin { + pins = "PC7"; + function = "spi0"; + allwinner,pinmux = <4>; + }; + + /omit-if-no-ref/ + spi0_hold_pc_pin: spi0-hold-pc-pin { + /* conflicts with eMMC D7 */ + pins = "PC16"; + function = "spi0"; + allwinner,pinmux = <4>; + }; + + /omit-if-no-ref/ + spi0_wp_pc_pin: spi0-wp-pc-pin { + /* conflicts with eMMC D2 */ + pins = "PC15"; + function = "spi0"; + allwinner,pinmux = <4>; + }; + uart0_pb_pins: uart0-pb-pins { pins = "PB9", "PB10"; allwinner,pinmux = <2>; @@ -563,6 +600,49 @@ #size-cells = <0>; }; + spi0: spi@4025000 { + compatible = "allwinner,sun55i-a523-spi"; + reg = <0x04025000 0x1000>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; + clock-names = "ahb", "mod"; + dmas = <&dma 22>, <&dma 22>; + dma-names = "rx", "tx"; + resets = <&ccu RST_BUS_SPI0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@4026000 { + compatible = "allwinner,sun55i-a523-spi-dbi", + "allwinner,sun55i-a523-spi"; + reg = <0x04026000 0x1000>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; + clock-names = "ahb", "mod"; + dmas = <&dma 23>, <&dma 23>; + dma-names = "rx", "tx"; + resets = <&ccu RST_BUS_SPI1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi2: spi@4027000 { + compatible = "allwinner,sun55i-a523-spi"; + reg = <0x04027000 0x1000>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>; + clock-names = "ahb", "mod"; + dmas = <&dma 24>, <&dma 24>; + dma-names = "rx", "tx"; + resets = <&ccu RST_BUS_SPI2>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + usb_otg: usb@4100000 { compatible = "allwinner,sun55i-a523-musb", "allwinner,sun8i-a33-musb"; @@ -815,6 +895,20 @@ #clock-cells = <1>; }; + r_spi0: spi@7092000 { + compatible = "allwinner,sun55i-a523-spi"; + reg = <0x07092000 0x1000>; + interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&r_ccu CLK_BUS_R_SPI>, <&r_ccu CLK_R_SPI>; + clock-names = "ahb", "mod"; + dmas = <&dma 53>, <&dma 53>; + dma-names = "rx", "tx"; + resets = <&r_ccu RST_BUS_R_SPI>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + mcu_ccu: clock-controller@7102000 { compatible = "allwinner,sun55i-a523-mcu-ccu"; reg = <0x7102000 0x200>; diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts b/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts index 9e6b21cf293e..055be86e5fae 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts @@ -400,6 +400,21 @@ assigned-clock-rates = <32768>; }; +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pc_pins>, <&spi0_cs0_pc_pin>; + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + vcc-supply = <®_cldo1>; + }; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pb_pins>; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index 657e986e5dba..0d9cad0c0351 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -382,7 +382,7 @@ pinctrl0: pinctrl@ffd13000 { compatible = "pinctrl-single"; - reg = <0xffd13000 0xA0>; + reg = <0xffd13000 0xa0>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0x0000000f>; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts index 58f776e411fc..4ae18a013bbe 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts @@ -192,7 +192,7 @@ root: partition@4200000 { label = "Root Filesystem - UBIFS"; - reg = <0x04200000 0x0BE00000>; + reg = <0x04200000 0x0be00000>; }; }; }; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts index 92954c5beb54..7951ce46ae1f 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts @@ -174,12 +174,12 @@ qspi_boot: partition@0 { label = "Boot and fpga data"; - reg = <0x0 0x03FE0000>; + reg = <0x0 0x03fe0000>; }; qspi_rootfs: partition@3fe0000 { label = "Root Filesystem - JFFS2"; - reg = <0x03FE0000 0x0C020000>; + reg = <0x03fe0000 0x0c020000>; }; }; }; diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile index 219fb088c704..15f9c817e502 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -85,6 +85,7 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxm-ugoos-am3.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-vega-s96.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-wetek-core2.dtb dtb-$(CONFIG_ARCH_MESON) += meson-s4-s805x2-aq222.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-s4-s905y4-khadas-vim1s.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-a95xf3-air-gbit.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-a95xf3-air.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-bananapi-m2-pro.dtb diff --git a/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi index 13b7ac03f9b2..4e6757a57fb9 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi @@ -108,7 +108,7 @@ firmware { scmi: scmi { compatible = "arm,scmi-smc"; - arm,smc-id = <0x820000C1>; + arm,smc-id = <0x820000c1>; shmem = <&scmi_shmem>; #address-cells = <1>; #size-cells = <0>; @@ -780,7 +780,7 @@ #address-cells = <1>; #size-cells = <0>; - internal_ephy: ethernet_phy@8 { + internal_ephy: ethernet-phy@8 { compatible = "ethernet-phy-id0180.3301", "ethernet-phy-ieee802.3-c22"; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; @@ -969,6 +969,10 @@ no-sd; resets = <&reset RESET_SD_EMMC_A>; status = "disabled"; + + assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_A>; + assigned-clock-rates = <24000000>; + }; sd: mmc@8a000 { @@ -984,12 +988,15 @@ no-sdio; resets = <&reset RESET_SD_EMMC_B>; status = "disabled"; + + assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_B>; + assigned-clock-rates = <24000000>; }; nand: nand-controller@8d000 { compatible = "amlogic,meson-axg-nfc"; reg = <0x0 0x8d000 0x0 0x200>, - <0x0 0x8C000 0x0 0x4>; + <0x0 0x8c000 0x0 0x4>; reg-names = "nfc", "emmc"; interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>; clocks = <&clkc_periphs CLKID_SYS_SD_EMMC_C>, diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-an400.dts b/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-an400.dts index c05edebb90b5..cab2ee9ea0d3 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-an400.dts +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-an400.dts @@ -20,7 +20,7 @@ memory@0 { device_type = "memory"; - reg = <0x00000000 0x00000000 0x00000000 0xE0000000 + reg = <0x00000000 0x00000000 0x00000000 0xe0000000 0x00000001 0x00000000 0x00000000 0x20000000>; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi index 27b68ed85c4c..348411411f3d 100644 --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi @@ -674,11 +674,12 @@ clock-names = "core", "clkin0", "clkin1"; - assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_SEL2>; - assigned-clock-parents = <&xtal>; resets = <&reset RESET_SD_EMMC_A>; power-domains = <&pwrc PWRC_SD_EMMC_ID>; status = "disabled"; + + assigned-clocks = <&clkc_periphs CLKID_SD_EMMC>; + assigned-clock-rates = <24000000>; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts index 9611775b81ee..285c6ac1dd61 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts +++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts @@ -275,7 +275,6 @@ assigned-clocks = <&clkc CLKID_HIFI_PLL>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <589824000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index e95c91894968..cc72491eaf6f 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -1960,6 +1960,9 @@ <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; resets = <&reset RESET_SD_EMMC_B>; + + assigned-clocks = <&clkc CLKID_SD_EMMC_B_CLK0>; + assigned-clock-rates = <24000000>; }; sd_emmc_c: mmc@7000 { @@ -1972,6 +1975,9 @@ <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; resets = <&reset RESET_SD_EMMC_C>; + + assigned-clocks = <&clkc CLKID_SD_EMMC_C_CLK0>; + assigned-clock-rates = <24000000>; }; nfc: nand-controller@7800 { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi index ca455f634834..00609d2da674 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi @@ -2431,6 +2431,9 @@ <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; resets = <&reset RESET_SD_EMMC_A>; + + assigned-clocks = <&clkc CLKID_SD_EMMC_A_CLK0>; + assigned-clock-rates = <24000000>; }; sd_emmc_b: mmc@ffe05000 { @@ -2443,6 +2446,9 @@ <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; resets = <&reset RESET_SD_EMMC_B>; + + assigned-clocks = <&clkc CLKID_SD_EMMC_B_CLK0>; + assigned-clock-rates = <24000000>; }; sd_emmc_c: mmc@ffe07000 { @@ -2455,6 +2461,9 @@ <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; resets = <&reset RESET_SD_EMMC_C>; + + assigned-clocks = <&clkc CLKID_SD_EMMC_C_CLK0>; + assigned-clock-rates = <24000000>; }; usb: usb@ffe09000 { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am.dts index d0a3b4b9229c..4c9cd0024efb 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am.dts @@ -183,7 +183,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; @@ -265,26 +264,18 @@ &cpu0 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu1 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu2 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu3 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; ðmac { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts index 4353485c6f26..4bb1c2846c81 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts @@ -145,7 +145,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; @@ -218,26 +217,18 @@ &cpu0 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu1 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu2 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu3 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cvbs_vdac_port { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts index f39fcabc763f..8ca7f6ec9adc 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts @@ -208,7 +208,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; @@ -312,26 +311,18 @@ &cpu0 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu1 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu2 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu3 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cvbs_vdac_port { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts index b5bf8ecc91e6..a1c5d10f2f54 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts @@ -245,7 +245,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; @@ -405,26 +404,18 @@ &cpu0 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu1 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu2 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu3 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; &clkc_audio { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts index 5ab460a3e637..c393954354d5 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts @@ -165,7 +165,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; @@ -261,26 +260,18 @@ &cpu0 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu1 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu2 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu3 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cvbs_vdac_port { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi index 1321ad95923d..51317d11f263 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi @@ -25,6 +25,8 @@ i-cache-sets = <32>; next-level-cache = <&l2>; #cooling-cells = <2>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU_CLK>; }; cpu1: cpu@1 { @@ -40,6 +42,8 @@ i-cache-sets = <32>; next-level-cache = <&l2>; #cooling-cells = <2>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU_CLK>; }; cpu2: cpu@2 { @@ -55,6 +59,8 @@ i-cache-sets = <32>; next-level-cache = <&l2>; #cooling-cells = <2>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU_CLK>; }; cpu3: cpu@3 { @@ -70,6 +76,8 @@ i-cache-sets = <32>; next-level-cache = <&l2>; #cooling-cells = <2>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU_CLK>; }; l2: l2-cache0 { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-libretech-cc.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-libretech-cc.dts index 82546b738977..5747acf8f337 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-libretech-cc.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-libretech-cc.dts @@ -6,7 +6,6 @@ /dts-v1/; -#include <dt-bindings/clock/g12a-clkc.h> #include "meson-g12b-a311d.dtsi" #include "meson-libretech-cottonwood.dtsi" @@ -74,38 +73,26 @@ &cpu0 { cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu1 { cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu100 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu101 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu102 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu103 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &pwm_ab { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi index 8ecb5bd125c1..f15baa708b36 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi @@ -109,3 +109,27 @@ }; }; }; + +&cpu0 { + operating-points-v2 = <&cpu_opp_table_0>; +}; + +&cpu1 { + operating-points-v2 = <&cpu_opp_table_0>; +}; + +&cpu100 { + operating-points-v2 = <&cpub_opp_table_1>; +}; + +&cpu101 { + operating-points-v2 = <&cpub_opp_table_1>; +}; + +&cpu102 { + operating-points-v2 = <&cpub_opp_table_1>; +}; + +&cpu103 { + operating-points-v2 = <&cpub_opp_table_1>; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4-cm4io.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4-cm4io.dts index 2d74456e685d..cdb522f5365a 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4-cm4io.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4-cm4io.dts @@ -77,7 +77,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4-mnt-reform2.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4-mnt-reform2.dts index 0f48c32bec97..2d4071c51f3d 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4-mnt-reform2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4-mnt-reform2.dts @@ -86,7 +86,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi index 39011b645128..7a204d324dd4 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi @@ -153,38 +153,26 @@ &cpu0 { cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu1 { cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu100 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu101 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu102 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu103 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &ext_mdio { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi index 1b08303c4282..7b5d78f97215 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi @@ -201,7 +201,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; @@ -261,38 +260,26 @@ &cpu0 { cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu1 { cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu100 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu101 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu102 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu103 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; ðmac { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-dreambox.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-dreambox.dtsi index 8e3e3354ed67..a69d5531c540 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-dreambox.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-dreambox.dtsi @@ -47,7 +47,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-gsking-x.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-gsking-x.dts index 369c5cf889b6..8758a68136ea 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-gsking-x.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-gsking-x.dts @@ -55,7 +55,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-gtking-pro.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-gtking-pro.dts index 654449afd3a4..a9478e2cce4d 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-gtking-pro.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-gtking-pro.dts @@ -56,7 +56,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-gtking.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-gtking.dts index e20311386745..a2ff5040eadf 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-gtking.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-gtking.dts @@ -44,7 +44,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi index fc737499f207..b16247e0df9f 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi @@ -49,38 +49,26 @@ &cpu0 { cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu1 { cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu100 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu101 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu102 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu103 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &pwm_ab { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts index d5938a4a6da3..cac73c59a94f 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts @@ -241,7 +241,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; @@ -279,38 +278,26 @@ &cpu0 { cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu1 { cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu100 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu101 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu102 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu103 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; /* RK817 only supports 12.5mV steps, round up the values */ diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi index 3bca8023638d..edb7ed6b0ec0 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi @@ -102,7 +102,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2l.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2l.dts index 1b9097a30251..15795889cb53 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2l.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2l.dts @@ -46,7 +46,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid.dtsi index 3298d59833b6..88d995006f94 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid.dtsi @@ -225,38 +225,26 @@ &cpu0 { cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu1 { cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu100 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu101 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu102 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu103 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu_thermal { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts index 1e5c6f984945..50565851f3d8 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts @@ -183,7 +183,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; @@ -257,38 +256,26 @@ &cpu0 { cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu1 { cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu100 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu101 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu102 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu103 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu_thermal { @@ -364,12 +351,46 @@ }; }; +/* Also exposed on the 40-pin header: SDA pin 3, SCL pin 5 */ +&i2c3 { + pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; + pinctrl-names = "default"; + status = "okay"; + + fusb0: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + + pinctrl-0 = <&fusb302_irq_pins>; + pinctrl-names = "default"; + interrupt-parent = <&gpio_intc>; + interrupts = <74 IRQ_TYPE_LEVEL_LOW>; + + vbus-supply = <&ao_5v>; + + connector { + compatible = "usb-c-connector"; + }; + }; +}; + &ir { status = "disabled"; pinctrl-0 = <&remote_input_ao_pins>; pinctrl-names = "default"; }; +&periphs_pinctrl { + fusb302_irq_pins: fusb302-irq { + mux { + groups = "GPIOA_13"; + function = "gpio_periphs"; + bias-pull-up; + output-disable; + }; + }; +}; + &pwm_ab { pinctrl-0 = <&pwm_a_e_pins>; pinctrl-names = "default"; @@ -394,6 +415,10 @@ status = "okay"; }; +&npu { + status = "okay"; +}; + &saradc { status = "okay"; vref-supply = <&vddao_1v8>; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi index 19cad93a6889..eef98add05c6 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi @@ -99,3 +99,27 @@ }; }; }; + +&cpu0 { + operating-points-v2 = <&cpu_opp_table_0>; +}; + +&cpu1 { + operating-points-v2 = <&cpu_opp_table_0>; +}; + +&cpu100 { + operating-points-v2 = <&cpub_opp_table_1>; +}; + +&cpu101 { + operating-points-v2 = <&cpub_opp_table_1>; +}; + +&cpu102 { + operating-points-v2 = <&cpub_opp_table_1>; +}; + +&cpu103 { + operating-points-v2 = <&cpub_opp_table_1>; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-ugoos-am6.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-ugoos-am6.dts index 4c1a75b926ee..dbd72fe0f53f 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-ugoos-am6.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-ugoos-am6.dts @@ -39,7 +39,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi index 9b6d780eada7..4834f418bef5 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi @@ -211,38 +211,26 @@ &cpu0 { cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu1 { cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu100 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu101 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu102 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu103 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cvbs_vdac_port { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi index 23358d94844c..18506d54d239 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi @@ -57,6 +57,7 @@ i-cache-sets = <32>; next-level-cache = <&l2_cache_l>; #cooling-cells = <2>; + clocks = <&clkc CLKID_CPU_CLK>; }; cpu1: cpu@1 { @@ -73,6 +74,7 @@ i-cache-sets = <32>; next-level-cache = <&l2_cache_l>; #cooling-cells = <2>; + clocks = <&clkc CLKID_CPU_CLK>; }; cpu100: cpu@100 { @@ -89,6 +91,7 @@ i-cache-sets = <32>; next-level-cache = <&l2_cache_b>; #cooling-cells = <2>; + clocks = <&clkc CLKID_CPUB_CLK>; }; cpu101: cpu@101 { @@ -105,6 +108,7 @@ i-cache-sets = <32>; next-level-cache = <&l2_cache_b>; #cooling-cells = <2>; + clocks = <&clkc CLKID_CPUB_CLK>; }; cpu102: cpu@102 { @@ -121,6 +125,7 @@ i-cache-sets = <64>; next-level-cache = <&l2_cache_b>; #cooling-cells = <2>; + clocks = <&clkc CLKID_CPUB_CLK>; }; cpu103: cpu@103 { @@ -137,6 +142,8 @@ i-cache-sets = <64>; next-level-cache = <&l2_cache_b>; #cooling-cells = <2>; + operating-points-v2 = <&cpub_opp_table_1>; + clocks = <&clkc CLKID_CPUB_CLK>; }; l2_cache_l: l2-cache-cluster0 { diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi index 2da49cfbde77..c2bf6f4cdfd2 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi @@ -201,7 +201,6 @@ assigned-clocks = <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>, <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi index b4f88ed6273b..8d216a594d7b 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi @@ -136,7 +136,6 @@ assigned-clocks = <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>, <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-kii-pro.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-kii-pro.dts index 073b47ce8c3c..ff3ba97872ec 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-kii-pro.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-kii-pro.dts @@ -52,7 +52,6 @@ assigned-clocks = <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>, <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts index 2ecc6ebd5a43..5d9ddb814164 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts @@ -142,7 +142,6 @@ assigned-clocks = <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>, <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts index c09da40ff7b0..ab8e06aa2b32 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts @@ -149,7 +149,6 @@ assigned-clocks = <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>, <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts index 12e26f99d4f0..5943bc810678 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts @@ -184,7 +184,6 @@ assigned-clocks = <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>, <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts index bfac00e76ba3..b5981c0b1494 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts @@ -75,7 +75,6 @@ assigned-clocks = <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>, <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts index c10f66031ecd..602777702984 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts @@ -24,7 +24,6 @@ assigned-clocks = <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>, <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi index 6ff567225fee..a4d354cc93a5 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi @@ -115,7 +115,6 @@ assigned-clocks = <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>, <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts index ec281a9e9e77..a22a8a435427 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts @@ -23,7 +23,6 @@ assigned-clocks = <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>, <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts index 924414861b72..6a1b65bf84da 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts @@ -55,7 +55,6 @@ assigned-clocks = <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>, <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index f69923da07fe..a9c830a570cc 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -824,6 +824,9 @@ <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; resets = <&reset RESET_SD_EMMC_A>; + + assigned-clocks = <&clkc CLKID_SD_EMMC_A_CLK0>; + assigned-clock-rates = <24000000>; }; &sd_emmc_b { @@ -832,6 +835,9 @@ <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; resets = <&reset RESET_SD_EMMC_B>; + + assigned-clocks = <&clkc CLKID_SD_EMMC_B_CLK0>; + assigned-clock-rates = <24000000>; }; &sd_emmc_c { @@ -840,6 +846,9 @@ <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; resets = <&reset RESET_SD_EMMC_C>; + + assigned-clocks = <&clkc CLKID_SD_EMMC_C_CLK0>; + assigned-clock-rates = <24000000>; }; &simplefb_hdmi { diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts index c6132fb71dfc..3a9a801f33d4 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts @@ -130,7 +130,6 @@ assigned-clocks = <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>, <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts index ca7c4e8e7cac..75db2a5c96b3 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts @@ -135,7 +135,6 @@ assigned-clocks = <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>, <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s805y-xiaomi-aquaman.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s805y-xiaomi-aquaman.dts index cac15b89c573..9e571b96bde6 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s805y-xiaomi-aquaman.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s805y-xiaomi-aquaman.dts @@ -125,7 +125,6 @@ assigned-clocks = <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>, <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts index 4e89d6f6bb57..0a6664275bcb 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts @@ -74,7 +74,6 @@ assigned-clocks = <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>, <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts index 6cbdfde00e12..277fb34981c7 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts @@ -167,7 +167,6 @@ assigned-clocks = <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>, <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts index 401064b0428d..fe1df108892c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts @@ -149,7 +149,6 @@ assigned-clocks = <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>, <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts index 8b41e340f919..9da495cca787 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts @@ -57,7 +57,6 @@ assigned-clocks = <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>, <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-vero4k.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-vero4k.dts index a9c5881c9783..1e4d3fdd0b22 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-vero4k.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-vero4k.dts @@ -98,7 +98,6 @@ assigned-clocks = <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>, <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi index ba535010a3c9..e202d84f0672 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -894,6 +894,9 @@ <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; resets = <&reset RESET_SD_EMMC_A>; + + assigned-clocks = <&clkc CLKID_SD_EMMC_A_CLK0>; + assigned-clock-rates = <24000000>; }; &sd_emmc_b { @@ -902,6 +905,9 @@ <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; resets = <&reset RESET_SD_EMMC_B>; + + assigned-clocks = <&clkc CLKID_SD_EMMC_B_CLK0>; + assigned-clock-rates = <24000000>; }; &sd_emmc_c { @@ -910,6 +916,9 @@ <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; resets = <&reset RESET_SD_EMMC_C>; + + assigned-clocks = <&clkc CLKID_SD_EMMC_C_CLK0>; + assigned-clock-rates = <24000000>; }; &simplefb_hdmi { diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts index 2a09b3d550e2..5b1aafe16d5c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts @@ -157,7 +157,6 @@ assigned-clocks = <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>, <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-mecool-kiii-pro.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-mecool-kiii-pro.dts index f5b3424c0f61..dddbbe6dca7c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-mecool-kiii-pro.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-mecool-kiii-pro.dts @@ -17,7 +17,7 @@ memory@0 { device_type = "memory"; - reg = <0x0 0x0 0x0 0xC0000000>; + reg = <0x0 0x0 0x0 0xc0000000>; }; adc-keys { diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts index 773107cc47dd..81f5eb3da5dc 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts @@ -93,7 +93,6 @@ assigned-clocks = <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>, <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts index 9d5a481b309f..9626a2621a3d 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts @@ -108,7 +108,6 @@ assigned-clocks = <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>, <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi index 7daa9b122d5c..73aa6b5a5de7 100644 --- a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi @@ -189,7 +189,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-libretech-cottonwood.dtsi b/arch/arm64/boot/dts/amlogic/meson-libretech-cottonwood.dtsi index ac9c4c2673b1..cb8b0f98beb4 100644 --- a/arch/arm64/boot/dts/amlogic/meson-libretech-cottonwood.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-libretech-cottonwood.dtsi @@ -207,7 +207,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts b/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts index 6730c44642d2..0a3f81ea0fb0 100644 --- a/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts +++ b/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts @@ -9,7 +9,7 @@ / { model = "Amlogic Meson S4 AQ222 Development Board"; - compatible = "amlogic,aq222", "amlogic,s4"; + compatible = "amlogic,aq222", "amlogic,s805x2", "amlogic,s4"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; diff --git a/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts b/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts new file mode 100644 index 000000000000..27d0f6134ea9 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts @@ -0,0 +1,259 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2026 Khadas Technology Co., Ltd. + */ + +/dts-v1/; + +#include "meson-s4.dtsi" + +/ { + model = "Khadas VIM1S"; + compatible = "khadas,vim1s", "amlogic,s905y4", "amlogic,s4"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + mmc0 = &emmc; /* eMMC */ + mmc1 = &sd; /* SD card */ + mmc2 = &sdio; /* SDIO */ + serial0 = &uart_b; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* 52 MiB reserved for ARM Trusted Firmware */ + secmon_reserved: secmon@5000000 { + reg = <0x0 0x05000000 0x0 0x3400000>; + no-map; + }; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio GPIOB_9 GPIO_ACTIVE_LOW>; + }; + + sdio_32k: sdio-32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&sdio_32k>; + clock-names = "ext_clock"; + }; + + main_5v: regulator-main-5v { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + sd_3v3: regulator-sd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "SD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio GPIOD_4 GPIO_ACTIVE_LOW>; + regulator-always-on; + }; + + vddio_sd: regulator-vddio-sd { + compatible = "regulator-gpio"; + regulator-name = "VDDIO_SD"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio GPIOD_9 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <1800000 1 + 3300000 0>; + }; + + vddao_3v3: regulator-vddao-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&main_5v>; + regulator-always-on; + }; + + vddio_ao1v8: regulator-vddio-ao1v8 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + }; + + /* SY8120B1ABC DC/DC Regulator. */ + vddcpu: regulator-vddcpu { + compatible = "pwm-regulator"; + + regulator-name = "VDDCPU"; + regulator-min-microvolt = <689000>; + regulator-max-microvolt = <1049000>; + + vin-supply = <&main_5v>; + + pwms = <&pwm_ij 1 1500 0>; + pwm-dutycycle-range = <100 0>; + + regulator-boot-on; + regulator-always-on; + /* Voltage Duty-Cycle */ + voltage-table = <1049000 0>, + <1039000 3>, + <1029000 6>, + <1019000 9>, + <1009000 12>, + <999000 14>, + <989000 17>, + <979000 20>, + <969000 23>, + <959000 26>, + <949000 29>, + <939000 31>, + <929000 34>, + <919000 37>, + <909000 40>, + <899000 43>, + <889000 45>, + <879000 48>, + <869000 51>, + <859000 54>, + <849000 56>, + <839000 59>, + <829000 62>, + <819000 65>, + <809000 68>, + <799000 70>, + <789000 73>, + <779000 76>, + <769000 79>, + <759000 81>, + <749000 84>, + <739000 87>, + <729000 89>, + <719000 92>, + <709000 95>, + <699000 98>, + <689000 100>; + }; +}; + +&emmc { + status = "okay"; + pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + max-frequency = <200000000>; + non-removable; + disable-wp; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_ao1v8>; +}; + +ðmac { + status = "okay"; + phy-handle = <&internal_ephy>; + phy-mode = "rmii"; +}; + +&ir { + status = "okay"; + pinctrl-0 = <&remote_pins>; + pinctrl-names = "default"; +}; + +&pwm_ef { + status = "okay"; + pinctrl-0 = <&pwm_e_pins1>; + pinctrl-names = "default"; +}; + +&pwm_ij { + status = "okay"; +}; + +&sd { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + bus-width = <4>; + cap-sd-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + max-frequency = <200000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; + + vmmc-supply = <&sd_3v3>; + vqmmc-supply = <&vddio_sd>; +}; + +&sdio { + status = "okay"; + pinctrl-0 = <&sdio_pins>; + pinctrl-1 = <&sdio_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + #address-cells = <1>; + #size-cells = <0>; + bus-width = <4>; + cap-sd-highspeed; + sd-uhs-sdr50; + sd-uhs-sdr104; + max-frequency = <50000000>; + non-removable; + disable-wp; + + no-sd; + no-mmc; + mmc-pwrseq = <&sdio_pwrseq>; + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_ao1v8>; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm43456-fmac", "brcm,bcm4329-fmac"; + }; +}; + +&spicc0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins_x>; + cs-gpios = <&gpio GPIOX_10 GPIO_ACTIVE_LOW>; +}; + +&uart_b { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi index 9d99ed2994df..dfc0a30a6e61 100644 --- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi @@ -819,13 +819,16 @@ reg = <0x0 0xfe088000 0x0 0x800>; interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clkc_periphs CLKID_SDEMMC_A>, - <&xtal>, + <&clkc_periphs CLKID_SD_EMMC_A>, <&clkc_pll CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; resets = <&reset RESET_SD_EMMC_A>; cap-sdio-irq; keep-power-in-suspend; status = "disabled"; + + assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_A>; + assigned-clock-rates = <24000000>; }; sd: mmc@fe08a000 { @@ -838,6 +841,9 @@ clock-names = "core", "clkin0", "clkin1"; resets = <&reset RESET_SD_EMMC_B>; status = "disabled"; + + assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_B>; + assigned-clock-rates = <24000000>; }; emmc: mmc@fe08c000 { @@ -845,13 +851,16 @@ reg = <0x0 0xfe08c000 0x0 0x800>; interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; clocks = <&clkc_periphs CLKID_NAND>, - <&xtal>, + <&clkc_periphs CLKID_SD_EMMC_C>, <&clkc_pll CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; resets = <&reset RESET_NAND_EMMC>; no-sdio; no-sd; status = "disabled"; + + assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_C>; + assigned-clock-rates = <24000000>; }; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air-gbit.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air-gbit.dts index 3c43d3490e14..7c67e459c602 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air-gbit.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air-gbit.dts @@ -29,7 +29,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air.dts index 445c1671ede7..e841c44c69de 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air.dts @@ -29,7 +29,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi index 9be3084b090d..661e454ca673 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi @@ -145,26 +145,18 @@ &cpu0 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu1 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU1_CLK>; }; &cpu2 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU2_CLK>; }; &cpu3 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU3_CLK>; }; &cvbs_vdac_port { diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m2-pro.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m2-pro.dts index eeaff22edade..8d12bd1702d3 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m2-pro.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m2-pro.dts @@ -29,7 +29,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m5.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m5.dts index 697855fec476..0cd306569312 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m5.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m5.dts @@ -64,7 +64,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi index 5e07f0f9538e..f0e4b168a411 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi @@ -183,26 +183,18 @@ &cpu0 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu1 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU1_CLK>; }; &cpu2 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU2_CLK>; }; &cpu3 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU3_CLK>; }; &ext_mdio { diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-h96-max.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-h96-max.dts index 7b3a014d4cde..3c671676e453 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-h96-max.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-h96-max.dts @@ -29,7 +29,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts index a3d9b66b6878..4e1e9a502666 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts @@ -49,26 +49,18 @@ &cpu0 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu1 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU1_CLK>; }; &cpu2 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU2_CLK>; }; &cpu3 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU3_CLK>; }; &pwm_AO_cd { diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts index 0170139b8d32..3ece30a0a1ff 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts @@ -52,6 +52,7 @@ gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; enable-active-high; + regulator-boot-on; regulator-always-on; }; @@ -65,6 +66,7 @@ gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; enable-active-high; + regulator-boot-on; regulator-always-on; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi index c4524eb4f099..e6f02d738a21 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi @@ -37,6 +37,7 @@ gpio = <&gpio_ao GPIOAO_3 GPIO_OPEN_DRAIN>; enable-active-high; + regulator-boot-on; regulator-always-on; }; @@ -50,6 +51,7 @@ enable-gpios = <&gpio_ao GPIOE_2 GPIO_OPEN_DRAIN>; enable-active-high; + regulator-boot-on; regulator-always-on; gpios = <&gpio_ao GPIOAO_6 GPIO_OPEN_SOURCE>; @@ -81,6 +83,7 @@ regulator-name = "5V"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; + regulator-boot-on; regulator-always-on; vin-supply = <&main_12v>; gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; @@ -181,7 +184,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; @@ -248,26 +250,18 @@ &cpu0 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu1 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU1_CLK>; }; &cpu2 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU2_CLK>; }; &cpu3 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU3_CLK>; }; &ext_mdio { diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-s905d3-libretech-cc.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-s905d3-libretech-cc.dts index 5daadfb170b4..2a16f54332df 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-s905d3-libretech-cc.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-s905d3-libretech-cc.dts @@ -6,7 +6,6 @@ /dts-v1/; -#include <dt-bindings/clock/g12a-clkc.h> #include "meson-sm1.dtsi" #include "meson-libretech-cottonwood.dtsi" @@ -62,24 +61,16 @@ &cpu0 { cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu1 { cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU1_CLK>; }; &cpu2 { cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU2_CLK>; }; &cpu3 { cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU3_CLK>; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts index 024d2eb8e6ee..18b830a233a6 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts @@ -246,7 +246,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; @@ -357,26 +356,18 @@ &cpu0 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu1 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU1_CLK>; }; &cpu2 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU2_CLK>; }; &cpu3 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU3_CLK>; }; ðmac { diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-x96-air-gbit.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-x96-air-gbit.dts index e4a3a2a8ad06..ecb6aa79302d 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-x96-air-gbit.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-x96-air-gbit.dts @@ -29,7 +29,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-x96-air.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-x96-air.dts index fff92e0d6dd5..24a6a679b377 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-x96-air.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-x96-air.dts @@ -29,7 +29,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi index e5db8ce94062..8f5b850b1774 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi @@ -63,6 +63,8 @@ i-cache-sets = <32>; next-level-cache = <&l2>; #cooling-cells = <2>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU_CLK>; }; cpu1: cpu@1 { @@ -78,6 +80,8 @@ i-cache-sets = <32>; next-level-cache = <&l2>; #cooling-cells = <2>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU1_CLK>; }; cpu2: cpu@2 { @@ -93,6 +97,8 @@ i-cache-sets = <32>; next-level-cache = <&l2>; #cooling-cells = <2>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU2_CLK>; }; cpu3: cpu@3 { @@ -108,6 +114,8 @@ i-cache-sets = <32>; next-level-cache = <&l2>; #cooling-cells = <2>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU3_CLK>; }; l2: l2-cache0 { diff --git a/arch/arm64/boot/dts/apm/apm-merlin.dts b/arch/arm64/boot/dts/apm/apm-merlin.dts index b1160780a2a6..4ec05886dd41 100644 --- a/arch/arm64/boot/dts/apm/apm-merlin.dts +++ b/arch/arm64/boot/dts/apm/apm-merlin.dts @@ -38,6 +38,7 @@ poweroff: poweroff@10548010 { compatible = "syscon-poweroff"; + reg = <0x0 0x10548010 0x0 0x4>; regmap = <&poweroff_mbox>; offset = <0x10>; mask = <0x1>; diff --git a/arch/arm64/boot/dts/apm/apm-mustang.dts b/arch/arm64/boot/dts/apm/apm-mustang.dts index 2ef658796746..8f7eeba56dc4 100644 --- a/arch/arm64/boot/dts/apm/apm-mustang.dts +++ b/arch/arm64/boot/dts/apm/apm-mustang.dts @@ -38,6 +38,7 @@ poweroff: poweroff@10548010 { compatible = "syscon-poweroff"; + reg = <0x0 0x10548010 0x0 0x4>; regmap = <&poweroff_mbox>; offset = <0x10>; mask = <0x1>; diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index 5bbedb0a7107..e930f2f26f4b 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -224,7 +224,7 @@ clock-frequency = <50000000>; }; - i2cslimpro { + i2c { compatible = "apm,xgene-slimpro-i2c"; mboxes = <&mailbox 0>; }; @@ -295,7 +295,7 @@ socplldiv2: socplldiv2 { compatible = "fixed-factor-clock"; - #clock-cells = <1>; + #clock-cells = <0>; clocks = <&socpll 0>; clock-mult = <1>; clock-div = <2>; @@ -305,7 +305,7 @@ ahbclk: ahbclk@17000000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x17000000 0x0 0x2000>; reg-names = "div-reg"; divider-offset = <0x164>; @@ -329,7 +329,7 @@ sdioclk: sdioclk@1f2ac000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x1f2ac000 0x0 0x1000 0x0 0x17000000 0x0 0x2000>; reg-names = "csr-reg", "div-reg"; @@ -346,7 +346,7 @@ pcie0clk: pcie0clk@1f2bc000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x1f2bc000 0x0 0x1000>; reg-names = "csr-reg"; clock-output-names = "pcie0clk"; @@ -355,7 +355,7 @@ pcie1clk: pcie1clk@1f2cc000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x1f2cc000 0x0 0x1000>; reg-names = "csr-reg"; clock-output-names = "pcie1clk"; @@ -364,7 +364,7 @@ xge0clk: xge0clk@1f61c000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x1f61c000 0x0 0x1000>; reg-names = "csr-reg"; enable-mask = <0x3>; @@ -375,7 +375,7 @@ xge1clk: xge1clk@1f62c000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x1f62c000 0x0 0x1000>; reg-names = "csr-reg"; enable-mask = <0x3>; @@ -386,7 +386,7 @@ rngpkaclk: rngpkaclk@17000000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x17000000 0x0 0x2000>; reg-names = "csr-reg"; csr-offset = <0xc>; @@ -417,6 +417,7 @@ reboot: reboot@17000014 { compatible = "syscon-reboot"; + reg = <0x0 0x17000014 0x0 0x4>; regmap = <&scu>; offset = <0x14>; mask = <0x1>; @@ -799,7 +800,6 @@ compatible = "snps,designware-i2c"; reg = <0x0 0x10511000 0x0 0x1000>; interrupts = <0 0x45 0x4>; - #clock-cells = <1>; clocks = <&sbapbclk 0>; }; diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi index 4ca0ead120c1..4c4938faffb1 100644 --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi @@ -134,7 +134,7 @@ interrupts = <1 12 0xff04>; }; - i2cslimpro { + i2c { compatible = "apm,xgene-slimpro-i2c"; mboxes = <&mailbox 0>; }; @@ -462,6 +462,7 @@ reboot: reboot@17000014 { compatible = "syscon-reboot"; + reg = <0x0 0x17000014 0x0 0x4>; regmap = <&scu>; offset = <0x14>; mask = <0x1>; @@ -1082,7 +1083,6 @@ dma: dma@1f270000 { compatible = "apm,xgene-storm-dma"; - device_type = "dma"; reg = <0x0 0x1f270000 0x0 0x10000>, <0x0 0x1f200000 0x0 0x10000>, <0x0 0x1b000000 0x0 0x400000>, diff --git a/arch/arm64/boot/dts/apple/s8001-j98a-j99a.dtsi b/arch/arm64/boot/dts/apple/s8001-j98a-j99a.dtsi index e66a4c1c138f..67633c56a723 100644 --- a/arch/arm64/boot/dts/apple/s8001-j98a-j99a.dtsi +++ b/arch/arm64/boot/dts/apple/s8001-j98a-j99a.dtsi @@ -9,6 +9,10 @@ * Copyright (c) 2024, Nick Chan <towinchenmi@gmail.com> */ +&dwi_bl { + status = "okay"; +}; + &ps_dcs4 { apple,always-on; /* LPDDR4 interface */ }; diff --git a/arch/arm64/boot/dts/apple/s8001.dtsi b/arch/arm64/boot/dts/apple/s8001.dtsi index b5b00dca6ffa..209c7dd19b7c 100644 --- a/arch/arm64/boot/dts/apple/s8001.dtsi +++ b/arch/arm64/boot/dts/apple/s8001.dtsi @@ -209,6 +209,13 @@ power-domains = <&ps_aic>; }; + dwi_bl: backlight@20e200080 { + compatible = "apple,s8000-dwi-bl", "apple,dwi-bl"; + reg = <0x2 0x0e200080 0x0 0x8>; + power-domains = <&ps_dwi>; + status = "disabled"; + }; + pinctrl_ap: pinctrl@20f100000 { compatible = "apple,s8000-pinctrl", "apple,pinctrl"; reg = <0x2 0x0f100000 0x0 0x100000>; diff --git a/arch/arm64/boot/dts/apple/t6001.dtsi b/arch/arm64/boot/dts/apple/t6001.dtsi index ffbe823b71bc..6dcb71a1d65a 100644 --- a/arch/arm64/boot/dts/apple/t6001.dtsi +++ b/arch/arm64/boot/dts/apple/t6001.dtsi @@ -11,6 +11,7 @@ #include <dt-bindings/interrupt-controller/apple-aic.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/pinctrl/apple.h> +#include <dt-bindings/phy/phy.h> #include <dt-bindings/spmi/spmi.h> #include "multi-die-cpp.h" diff --git a/arch/arm64/boot/dts/apple/t6002-j375d.dts b/arch/arm64/boot/dts/apple/t6002-j375d.dts index 2b7f80119618..a2a24d028cbb 100644 --- a/arch/arm64/boot/dts/apple/t6002-j375d.dts +++ b/arch/arm64/boot/dts/apple/t6002-j375d.dts @@ -15,6 +15,10 @@ / { compatible = "apple,j375d", "apple,t6002", "apple,arm-platform"; model = "Apple Mac Studio (M1 Ultra, 2022)"; + aliases { + atcphy4 = &atcphy0_die1; + atcphy5 = &atcphy1_die1; + }; }; /* USB Type C */ @@ -26,6 +30,30 @@ interrupt-parent = <&pinctrl_ap>; interrupts = <174 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "irq"; + + typec4: connector { + compatible = "usb-c-connector"; + label = "USB-C Front Right"; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + typec4_connector_hs: endpoint { + remote-endpoint = <&dwc3_4_hs>; + }; + }; + port@1 { + reg = <1>; + typec4_connector_ss: endpoint { + remote-endpoint = <&atcphy4_typec_lanes>; + }; + }; + }; + }; }; /* front-left */ @@ -35,6 +63,30 @@ interrupt-parent = <&pinctrl_ap>; interrupts = <174 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "irq"; + + typec5: connector { + compatible = "usb-c-connector"; + label = "USB-C Front Left"; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + typec5_connector_hs: endpoint { + remote-endpoint = <&dwc3_5_hs>; + }; + }; + port@1 { + reg = <1>; + typec5_connector_ss: endpoint { + remote-endpoint = <&atcphy5_typec_lanes>; + }; + }; + }; + }; }; }; @@ -46,6 +98,104 @@ brcm,board-type = "apple,okinawa"; }; +/* USB controllers on die 1 */ +&dwc3_0_die1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dwc3_4_hs: endpoint { + remote-endpoint = <&typec4_connector_hs>; + }; + }; + + port@1 { + reg = <1>; + dwc3_4_ss: endpoint { + remote-endpoint = <&atcphy4_usb3>; + }; + }; + }; +}; + +&dwc3_1_die1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dwc3_5_hs: endpoint { + remote-endpoint = <&typec5_connector_hs>; + }; + }; + + port@1 { + reg = <1>; + dwc3_5_ss: endpoint { + remote-endpoint = <&atcphy5_usb3>; + }; + }; + }; +}; + +/* Type-C PHYs */ +&atcphy0_die1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + atcphy4_typec_lanes: endpoint { + remote-endpoint = <&typec4_connector_ss>; + }; + }; + + port@1 { + reg = <1>; + atcphy4_usb3: endpoint { + remote-endpoint = <&dwc3_4_ss>; + }; + }; + }; +}; + +&atcphy1_die1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + atcphy5_typec_lanes: endpoint { + remote-endpoint = <&typec5_connector_ss>; + }; + }; + + port@1 { + reg = <1>; + atcphy5_usb3: endpoint { + remote-endpoint = <&dwc3_5_ss>; + }; + }; + }; +}; + +/* delete unused USB nodes on die 1 */ + +/delete-node/ &dwc3_2_dart_0_die1; +/delete-node/ &dwc3_2_dart_1_die1; +/delete-node/ &dwc3_2_die1; +/delete-node/ &atcphy2_die1; + +/delete-node/ &dwc3_3_dart_0_die1; +/delete-node/ &dwc3_3_dart_1_die1; +/delete-node/ &dwc3_3_die1; +/delete-node/ &atcphy3_die1; + /* delete unused always-on power-domains on die 1 */ /delete-node/ &ps_atc2_usb_aon_die1; diff --git a/arch/arm64/boot/dts/apple/t6002.dtsi b/arch/arm64/boot/dts/apple/t6002.dtsi index 8fb648836b53..a532e5401c4e 100644 --- a/arch/arm64/boot/dts/apple/t6002.dtsi +++ b/arch/arm64/boot/dts/apple/t6002.dtsi @@ -11,6 +11,7 @@ #include <dt-bindings/interrupt-controller/apple-aic.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/pinctrl/apple.h> +#include <dt-bindings/phy/phy.h> #include <dt-bindings/spmi/spmi.h> #include "multi-die-cpp.h" diff --git a/arch/arm64/boot/dts/apple/t600x-die0.dtsi b/arch/arm64/boot/dts/apple/t600x-die0.dtsi index 3603b276a2ab..f715b19efd16 100644 --- a/arch/arm64/boot/dts/apple/t600x-die0.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-die0.dtsi @@ -44,6 +44,12 @@ nvmem-cell-names = "shutdown_flag", "boot_stage", "boot_error_count", "panic_count"; }; + + rtc { + compatible = "apple,smc-rtc"; + nvmem-cells = <&rtc_offset>; + nvmem-cell-names = "rtc_offset"; + }; }; smc_mbox: mbox@290408000 { diff --git a/arch/arm64/boot/dts/apple/t600x-dieX.dtsi b/arch/arm64/boot/dts/apple/t600x-dieX.dtsi index a32ff0c9d7b0..9676d5127039 100644 --- a/arch/arm64/boot/dts/apple/t600x-dieX.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-dieX.dtsi @@ -119,3 +119,215 @@ interrupt-controller; #interrupt-cells = <2>; }; + + DIE_NODE(dwc3_0): usb@702280000 { + compatible = "apple,t6000-dwc3", "apple,t8103-dwc3"; + reg = <0x7 0x02280000 0x0 0xcd00>, <0x7 0x0228cd00 0x0 0x3200>; + reg-names = "dwc3-core", "dwc3-apple"; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ DIE_NO 1190 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "otg"; + usb-role-switch; + role-switch-default-mode = "host"; + iommus = <&DIE_NODE(dwc3_0_dart_0) 0>, + <&DIE_NODE(dwc3_0_dart_1) 1>; + power-domains = <&DIE_NODE(ps_atc0_usb)>; + resets = <&DIE_NODE(atcphy0)>; + phys = <&DIE_NODE(atcphy0) PHY_TYPE_USB2>, <&DIE_NODE(atcphy0) PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + }; + + DIE_NODE(dwc3_0_dart_0): iommu@702f00000 { + compatible = "apple,t6000-dart"; + reg = <0x7 0x02f00000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ DIE_NO 1194 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&DIE_NODE(ps_atc0_usb)>; + #iommu-cells = <1>; + }; + + DIE_NODE(dwc3_0_dart_1): iommu@702f80000 { + compatible = "apple,t6000-dart"; + reg = <0x7 0x02f80000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ DIE_NO 1194 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&DIE_NODE(ps_atc0_usb)>; + #iommu-cells = <1>; + }; + + DIE_NODE(atcphy0): phy@703000000 { + compatible = "apple,t6000-atcphy", "apple,t8103-atcphy"; + reg = <0x7 0x03000000 0x0 0x4c000>, + <0x7 0x03050000 0x0 0x8000>, + <0x7 0x00000000 0x0 0x4000>, + <0x7 0x02a90000 0x0 0x4000>, + <0x7 0x02a84000 0x0 0x4000>; + reg-names = "core", "lpdptx", "axi2af", "usb2phy", + "pipehandler"; + + #phy-cells = <1>; + #reset-cells = <0>; + + orientation-switch; + mode-switch; + power-domains = <&DIE_NODE(ps_atc0_usb)>; + }; + + DIE_NODE(dwc3_1): usb@b02280000 { + compatible = "apple,t6000-dwc3", "apple,t8103-dwc3"; + reg = <0xb 0x02280000 0x0 0xcd00>, <0xb 0x0228cd00 0x0 0x3200>; + reg-names = "dwc3-core", "dwc3-apple"; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ DIE_NO 1207 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "otg"; + usb-role-switch; + role-switch-default-mode = "host"; + iommus = <&DIE_NODE(dwc3_1_dart_0) 0>, + <&DIE_NODE(dwc3_1_dart_1) 1>; + power-domains = <&DIE_NODE(ps_atc1_usb)>; + resets = <&DIE_NODE(atcphy1)>; + phys = <&DIE_NODE(atcphy1) PHY_TYPE_USB2>, <&DIE_NODE(atcphy1) PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + }; + + DIE_NODE(dwc3_1_dart_0): iommu@b02f00000 { + compatible = "apple,t6000-dart"; + reg = <0xb 0x02f00000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ DIE_NO 1211 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&DIE_NODE(ps_atc1_usb)>; + #iommu-cells = <1>; + }; + + DIE_NODE(dwc3_1_dart_1): iommu@b02f80000 { + compatible = "apple,t6000-dart"; + reg = <0xb 0x02f80000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ DIE_NO 1211 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&DIE_NODE(ps_atc1_usb)>; + #iommu-cells = <1>; + }; + + DIE_NODE(atcphy1): phy@b03000000 { + compatible = "apple,t6000-atcphy", "apple,t8103-atcphy"; + reg = <0xb 0x03000000 0x0 0x4c000>, + <0xb 0x03050000 0x0 0x8000>, + <0xb 0x00000000 0x0 0x4000>, + <0xb 0x02a90000 0x0 0x4000>, + <0xb 0x02a84000 0x0 0x4000>; + reg-names = "core", "lpdptx", "axi2af", "usb2phy", + "pipehandler"; + + #phy-cells = <1>; + #reset-cells = <0>; + + orientation-switch; + mode-switch; + power-domains = <&DIE_NODE(ps_atc1_usb)>; + }; + + DIE_NODE(dwc3_2): usb@f02280000 { + compatible = "apple,t6000-dwc3", "apple,t8103-dwc3"; + reg = <0xf 0x02280000 0x0 0xcd00>, <0xf 0x0228cd00 0x0 0x3200>; + reg-names = "dwc3-core", "dwc3-apple"; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ DIE_NO 1224 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "otg"; + usb-role-switch; + role-switch-default-mode = "host"; + iommus = <&DIE_NODE(dwc3_2_dart_0) 0>, + <&DIE_NODE(dwc3_2_dart_1) 1>; + power-domains = <&DIE_NODE(ps_atc2_usb)>; + resets = <&DIE_NODE(atcphy2)>; + phys = <&DIE_NODE(atcphy2) PHY_TYPE_USB2>, <&DIE_NODE(atcphy2) PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + }; + + DIE_NODE(dwc3_2_dart_0): iommu@f02f00000 { + compatible = "apple,t6000-dart"; + reg = <0xf 0x02f00000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ DIE_NO 1228 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&DIE_NODE(ps_atc2_usb)>; + #iommu-cells = <1>; + }; + + DIE_NODE(dwc3_2_dart_1): iommu@f02f80000 { + compatible = "apple,t6000-dart"; + reg = <0xf 0x02f80000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ DIE_NO 1228 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&DIE_NODE(ps_atc2_usb)>; + #iommu-cells = <1>; + }; + + DIE_NODE(atcphy2): phy@f03000000 { + compatible = "apple,t6000-atcphy", "apple,t8103-atcphy"; + reg = <0xf 0x03000000 0x0 0x4c000>, + <0xf 0x03050000 0x0 0x8000>, + <0xf 0x00000000 0x0 0x4000>, + <0xf 0x02a90000 0x0 0x4000>, + <0xf 0x02a84000 0x0 0x4000>; + reg-names = "core", "lpdptx", "axi2af", "usb2phy", + "pipehandler"; + + #phy-cells = <1>; + #reset-cells = <0>; + + orientation-switch; + mode-switch; + power-domains = <&DIE_NODE(ps_atc2_usb)>; + }; + + DIE_NODE(dwc3_3): usb@1302280000 { + compatible = "apple,t6000-dwc3", "apple,t8103-dwc3"; + reg = <0x13 0x02280000 0x0 0xcd00>, <0x13 0x0228cd00 0x0 0x3200>; + reg-names = "dwc3-core", "dwc3-apple"; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ DIE_NO 1241 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "otg"; + usb-role-switch; + role-switch-default-mode = "host"; + iommus = <&DIE_NODE(dwc3_3_dart_0) 0>, + <&DIE_NODE(dwc3_3_dart_1) 1>; + power-domains = <&DIE_NODE(ps_atc3_usb)>; + resets = <&DIE_NODE(atcphy3)>; + phys = <&DIE_NODE(atcphy3) PHY_TYPE_USB2>, <&DIE_NODE(atcphy3) PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + }; + + DIE_NODE(dwc3_3_dart_0): iommu@1302f00000 { + compatible = "apple,t6000-dart"; + reg = <0x13 0x02f00000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ DIE_NO 1245 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&DIE_NODE(ps_atc3_usb)>; + #iommu-cells = <1>; + }; + + DIE_NODE(dwc3_3_dart_1): iommu@1302f80000 { + compatible = "apple,t6000-dart"; + reg = <0x13 0x02f80000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ DIE_NO 1245 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&DIE_NODE(ps_atc3_usb)>; + #iommu-cells = <1>; + }; + + DIE_NODE(atcphy3): phy@1303000000 { + compatible = "apple,t6000-atcphy", "apple,t8103-atcphy"; + reg = <0x13 0x03000000 0x0 0x4c000>, + <0x13 0x03050000 0x0 0x8000>, + <0x13 0x00000000 0x0 0x4000>, + <0x13 0x02a90000 0x0 0x4000>, + <0x13 0x02a84000 0x0 0x4000>; + reg-names = "core", "lpdptx", "axi2af", "usb2phy", + "pipehandler"; + + #phy-cells = <1>; + #reset-cells = <0>; + + orientation-switch; + mode-switch; + power-domains = <&DIE_NODE(ps_atc3_usb)>; + }; diff --git a/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi b/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi index c0aac59a6fae..fee84f809a9c 100644 --- a/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi @@ -12,7 +12,13 @@ #include <dt-bindings/leds/common.h> / { + chassis-type = "laptop"; + aliases { + atcphy0 = &atcphy0; + atcphy1 = &atcphy1; + atcphy2 = &atcphy2; + atcphy3 = &atcphy3; bluetooth0 = &bluetooth0; serial0 = &serial0; wifi0 = &wifi0; @@ -63,6 +69,30 @@ interrupt-parent = <&pinctrl_ap>; interrupts = <174 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "irq"; + + typec0: connector { + compatible = "usb-c-connector"; + label = "USB-C Left Rear"; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + typec0_connector_hs: endpoint { + remote-endpoint = <&dwc3_0_hs>; + }; + }; + port@1 { + reg = <1>; + typec0_connector_ss: endpoint { + remote-endpoint = <&atcphy0_typec_lanes>; + }; + }; + }; + }; }; hpm1: usb-pd@3f { @@ -71,6 +101,30 @@ interrupt-parent = <&pinctrl_ap>; interrupts = <174 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "irq"; + + typec1: connector { + compatible = "usb-c-connector"; + label = "USB-C Left Front"; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + typec1_connector_hs: endpoint { + remote-endpoint = <&dwc3_1_hs>; + }; + }; + port@1 { + reg = <1>; + typec1_connector_ss: endpoint { + remote-endpoint = <&atcphy1_typec_lanes>; + }; + }; + }; + }; }; hpm2: usb-pd@3b { @@ -79,6 +133,30 @@ interrupt-parent = <&pinctrl_ap>; interrupts = <174 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "irq"; + + typec2: connector { + compatible = "usb-c-connector"; + label = "USB-C Right"; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + typec2_connector_hs: endpoint { + remote-endpoint = <&dwc3_2_hs>; + }; + }; + port@1 { + reg = <1>; + typec2_connector_ss: endpoint { + remote-endpoint = <&atcphy2_typec_lanes>; + }; + }; + }; + }; }; /* MagSafe port */ @@ -130,4 +208,162 @@ status = "okay"; }; +/* USB controllers */ +&dwc3_0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dwc3_0_hs: endpoint { + remote-endpoint = <&typec0_connector_hs>; + }; + }; + + port@1 { + reg = <1>; + dwc3_0_ss: endpoint { + remote-endpoint = <&atcphy0_usb3>; + }; + }; + }; +}; + +&dwc3_1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dwc3_1_hs: endpoint { + remote-endpoint = <&typec1_connector_hs>; + }; + }; + + port@1 { + reg = <1>; + dwc3_1_ss: endpoint { + remote-endpoint = <&atcphy1_usb3>; + }; + }; + }; +}; + +&dwc3_2 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dwc3_2_hs: endpoint { + remote-endpoint = <&typec2_connector_hs>; + }; + }; + + port@1 { + reg = <1>; + dwc3_2_ss: endpoint { + remote-endpoint = <&atcphy2_usb3>; + }; + }; + }; +}; + +/* + * ps_atc3_usb_aon power-domain is always-on to keep dwc3 working over suspend. + * atc3 is used exclusively for the DP-to-HDMI so do not keep this always on. + */ +&ps_atc3_usb_aon { + /delete-property/ apple,always-on; +}; + +/* ATC3 is used for DisplayPort -> HDMI only */ +&dwc3_3_dart_0 { + status = "disabled"; +}; + +&dwc3_3_dart_1 { + status = "disabled"; +}; + +&dwc3_3 { + status = "disabled"; +}; + +/* Delete unused dwc3_3 to prevent dt_disable_missing_devs() from disabling + * atcphy3 via phandle references from a disablecd device. + */ +/delete-node/ &dwc3_3; + +/* Type-C PHYs */ +&atcphy0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + atcphy0_typec_lanes: endpoint { + remote-endpoint = <&typec0_connector_ss>; + }; + }; + + port@1 { + reg = <1>; + atcphy0_usb3: endpoint { + remote-endpoint = <&dwc3_0_ss>; + }; + }; + }; +}; + +&atcphy1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + atcphy1_typec_lanes: endpoint { + remote-endpoint = <&typec1_connector_ss>; + }; + }; + + port@1 { + reg = <1>; + atcphy1_usb3: endpoint { + remote-endpoint = <&dwc3_1_ss>; + }; + }; + }; +}; + +&atcphy2 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + atcphy2_typec_lanes: endpoint { + remote-endpoint = <&typec2_connector_ss>; + }; + }; + + port@1 { + reg = <1>; + atcphy2_usb3: endpoint { + remote-endpoint = <&dwc3_2_ss>; + }; + }; + }; +}; + +&atcphy3 { + status = "disabled"; +}; + #include "spi1-nvram.dtsi" diff --git a/arch/arm64/boot/dts/apple/t600x-j375.dtsi b/arch/arm64/boot/dts/apple/t600x-j375.dtsi index c0fb93ae72f4..8a1494949e4c 100644 --- a/arch/arm64/boot/dts/apple/t600x-j375.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-j375.dtsi @@ -10,7 +10,13 @@ */ / { + chassis-type = "desktop"; + aliases { + atcphy0 = &atcphy0; + atcphy1 = &atcphy1; + atcphy2 = &atcphy2; + atcphy3 = &atcphy3; bluetooth0 = &bluetooth0; ethernet0 = ðernet0; serial0 = &serial0; @@ -50,6 +56,30 @@ interrupt-parent = <&pinctrl_ap>; interrupts = <174 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "irq"; + + typec0: connector { + compatible = "usb-c-connector"; + label = "USB-C Back Left"; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + typec0_connector_hs: endpoint { + remote-endpoint = <&dwc3_0_hs>; + }; + }; + port@1 { + reg = <1>; + typec0_connector_ss: endpoint { + remote-endpoint = <&atcphy0_typec_lanes>; + }; + }; + }; + }; }; hpm1: usb-pd@3f { @@ -58,6 +88,30 @@ interrupt-parent = <&pinctrl_ap>; interrupts = <174 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "irq"; + + typec1: connector { + compatible = "usb-c-connector"; + label = "USB-C Back Left Middle"; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + typec1_connector_hs: endpoint { + remote-endpoint = <&dwc3_1_hs>; + }; + }; + port@1 { + reg = <1>; + typec1_connector_ss: endpoint { + remote-endpoint = <&atcphy1_typec_lanes>; + }; + }; + }; + }; }; hpm2: usb-pd@3b { @@ -66,6 +120,30 @@ interrupt-parent = <&pinctrl_ap>; interrupts = <174 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "irq"; + + typec2: connector { + compatible = "usb-c-connector"; + label = "USB-C Back Right Middle"; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + typec2_connector_hs: endpoint { + remote-endpoint = <&dwc3_2_hs>; + }; + }; + port@1 { + reg = <1>; + typec2_connector_ss: endpoint { + remote-endpoint = <&atcphy2_typec_lanes>; + }; + }; + }; + }; }; hpm3: usb-pd@3c { @@ -74,6 +152,200 @@ interrupt-parent = <&pinctrl_ap>; interrupts = <174 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "irq"; + + typec3: connector { + compatible = "usb-c-connector"; + label = "USB-C Back Right"; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + typec3_connector_hs: endpoint { + remote-endpoint = <&dwc3_3_hs>; + }; + }; + port@1 { + reg = <1>; + typec3_connector_ss: endpoint { + remote-endpoint = <&atcphy3_typec_lanes>; + }; + }; + }; + }; + }; +}; + +/* USB controllers */ +&dwc3_0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dwc3_0_hs: endpoint { + remote-endpoint = <&typec0_connector_hs>; + }; + }; + + port@1 { + reg = <1>; + dwc3_0_ss: endpoint { + remote-endpoint = <&atcphy0_usb3>; + }; + }; + }; +}; + +&dwc3_1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dwc3_1_hs: endpoint { + remote-endpoint = <&typec1_connector_hs>; + }; + }; + + port@1 { + reg = <1>; + dwc3_1_ss: endpoint { + remote-endpoint = <&atcphy1_usb3>; + }; + }; + }; +}; + +&dwc3_2 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dwc3_2_hs: endpoint { + remote-endpoint = <&typec2_connector_hs>; + }; + }; + + port@1 { + reg = <1>; + dwc3_2_ss: endpoint { + remote-endpoint = <&atcphy2_usb3>; + }; + }; + }; +}; + +&dwc3_3 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dwc3_3_hs: endpoint { + remote-endpoint = <&typec3_connector_hs>; + }; + }; + + port@1 { + reg = <1>; + dwc3_3_ss: endpoint { + remote-endpoint = <&atcphy3_usb3>; + }; + }; + }; +}; + +/* Type-C PHYs */ +&atcphy0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + atcphy0_typec_lanes: endpoint { + remote-endpoint = <&typec0_connector_ss>; + }; + }; + + port@1 { + reg = <1>; + atcphy0_usb3: endpoint { + remote-endpoint = <&dwc3_0_ss>; + }; + }; + }; +}; + +&atcphy1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + atcphy1_typec_lanes: endpoint { + remote-endpoint = <&typec1_connector_ss>; + }; + }; + + port@1 { + reg = <1>; + atcphy1_usb3: endpoint { + remote-endpoint = <&dwc3_1_ss>; + }; + }; + }; +}; + +&atcphy2 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + atcphy2_typec_lanes: endpoint { + remote-endpoint = <&typec2_connector_ss>; + }; + }; + + port@1 { + reg = <1>; + atcphy2_usb3: endpoint { + remote-endpoint = <&dwc3_2_ss>; + }; + }; + }; +}; + +&atcphy3 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + atcphy3_typec_lanes: endpoint { + remote-endpoint = <&typec3_connector_ss>; + }; + }; + + port@1 { + reg = <1>; + atcphy3_usb3: endpoint { + remote-endpoint = <&dwc3_3_ss>; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/apple/t6022-j180d.dts b/arch/arm64/boot/dts/apple/t6022-j180d.dts index dca6bd167c22..f76b887429dd 100644 --- a/arch/arm64/boot/dts/apple/t6022-j180d.dts +++ b/arch/arm64/boot/dts/apple/t6022-j180d.dts @@ -15,7 +15,17 @@ / { compatible = "apple,j180d", "apple,t6022", "apple,arm-platform"; model = "Apple Mac Pro (M2 Ultra, 2023)"; + chassis-type = "server"; + aliases { + atcphy0 = &atcphy0; + atcphy1 = &atcphy1; + atcphy2 = &atcphy2; + atcphy3 = &atcphy3; + atcphy4 = &atcphy0_die1; + atcphy5 = &atcphy1_die1; + atcphy6 = &atcphy2_die1; + atcphy7 = &atcphy3_die1; nvram = &nvram; serial0 = &serial0; }; @@ -54,6 +64,30 @@ interrupt-parent = <&pinctrl_ap>; interrupts = <44 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "irq"; + + typec2: connector { + compatible = "usb-c-connector"; + label = "USB-C Back 1"; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + typec2_connector_hs: endpoint { + remote-endpoint = <&dwc3_2_hs>; + }; + }; + port@1 { + reg = <1>; + typec2_connector_ss: endpoint { + remote-endpoint = <&atcphy2_typec_lanes>; + }; + }; + }; + }; }; hpm3: usb-pd@3c { @@ -62,6 +96,30 @@ interrupt-parent = <&pinctrl_ap>; interrupts = <44 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "irq"; + + typec3: connector { + compatible = "usb-c-connector"; + label = "USB-C Back 2"; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + typec3_connector_hs: endpoint { + remote-endpoint = <&dwc3_3_hs>; + }; + }; + port@1 { + reg = <1>; + typec3_connector_ss: endpoint { + remote-endpoint = <&atcphy3_typec_lanes>; + }; + }; + }; + }; }; /* hpm4 and hpm5 included from t6022-jxxxd.dtsi */ @@ -72,6 +130,30 @@ interrupt-parent = <&pinctrl_ap>; interrupts = <44 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "irq"; + + typec6: connector { + compatible = "usb-c-connector"; + label = "USB-C Back 5"; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + typec6_connector_hs: endpoint { + remote-endpoint = <&dwc3_6_hs>; + }; + }; + port@1 { + reg = <1>; + typec6_connector_ss: endpoint { + remote-endpoint = <&atcphy6_typec_lanes>; + }; + }; + }; + }; }; hpm7: usb-pd@3e { @@ -80,9 +162,41 @@ interrupt-parent = <&pinctrl_ap>; interrupts = <44 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "irq"; + + typec7: connector { + compatible = "usb-c-connector"; + label = "USB-C Back 6"; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + typec7_connector_hs: endpoint { + remote-endpoint = <&dwc3_7_hs>; + }; + }; + port@1 { + reg = <1>; + typec7_connector_ss: endpoint { + remote-endpoint = <&atcphy7_typec_lanes>; + }; + }; + }; + }; }; }; +&typec4 { + label = "USB-C Back 3"; +}; + +&typec5 { + label = "USB-C Back 4"; +}; + /* USB Type C Front */ &i2c3 { status = "okay"; @@ -93,6 +207,30 @@ interrupt-parent = <&pinctrl_ap>; interrupts = <60 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "irq"; + + typec0: connector { + compatible = "usb-c-connector"; + label = "USB-C Top Right"; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + typec0_connector_hs: endpoint { + remote-endpoint = <&dwc3_0_hs>; + }; + }; + port@1 { + reg = <1>; + typec0_connector_ss: endpoint { + remote-endpoint = <&atcphy0_typec_lanes>; + }; + }; + }; + }; }; hpm1: usb-pd@3f { @@ -101,6 +239,285 @@ interrupt-parent = <&pinctrl_ap>; interrupts = <60 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "irq"; + + typec1: connector { + compatible = "usb-c-connector"; + label = "USB-C Top Left"; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + typec1_connector_hs: endpoint { + remote-endpoint = <&dwc3_1_hs>; + }; + }; + port@1 { + reg = <1>; + typec1_connector_ss: endpoint { + remote-endpoint = <&atcphy1_typec_lanes>; + }; + }; + }; + }; + }; +}; + +/* USB controllers */ +&dwc3_0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dwc3_0_hs: endpoint { + remote-endpoint = <&typec0_connector_hs>; + }; + }; + + port@1 { + reg = <1>; + dwc3_0_ss: endpoint { + remote-endpoint = <&atcphy0_usb3>; + }; + }; + }; +}; + +&dwc3_1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dwc3_1_hs: endpoint { + remote-endpoint = <&typec1_connector_hs>; + }; + }; + + port@1 { + reg = <1>; + dwc3_1_ss: endpoint { + remote-endpoint = <&atcphy1_usb3>; + }; + }; + }; +}; + +&dwc3_2 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dwc3_2_hs: endpoint { + remote-endpoint = <&typec2_connector_hs>; + }; + }; + + port@1 { + reg = <1>; + dwc3_2_ss: endpoint { + remote-endpoint = <&atcphy2_usb3>; + }; + }; + }; +}; + +&dwc3_3 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dwc3_3_hs: endpoint { + remote-endpoint = <&typec3_connector_hs>; + }; + }; + + port@1 { + reg = <1>; + dwc3_3_ss: endpoint { + remote-endpoint = <&atcphy3_usb3>; + }; + }; + }; +}; + +/* USB controllers on die 1 */ +&dwc3_2_die1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dwc3_6_hs: endpoint { + remote-endpoint = <&typec6_connector_hs>; + }; + }; + + port@1 { + reg = <1>; + dwc3_6_ss: endpoint { + remote-endpoint = <&atcphy6_usb3>; + }; + }; + }; +}; + +&dwc3_3_die1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dwc3_7_hs: endpoint { + remote-endpoint = <&typec7_connector_hs>; + }; + }; + + port@1 { + reg = <1>; + dwc3_7_ss: endpoint { + remote-endpoint = <&atcphy7_usb3>; + }; + }; + }; +}; + +/* Type-C PHYs */ +&atcphy0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + atcphy0_typec_lanes: endpoint { + remote-endpoint = <&typec0_connector_ss>; + }; + }; + + port@1 { + reg = <1>; + atcphy0_usb3: endpoint { + remote-endpoint = <&dwc3_0_ss>; + }; + }; + }; +}; + +&atcphy1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + atcphy1_typec_lanes: endpoint { + remote-endpoint = <&typec1_connector_ss>; + }; + }; + + port@1 { + reg = <1>; + atcphy1_usb3: endpoint { + remote-endpoint = <&dwc3_1_ss>; + }; + }; + }; +}; + +&atcphy2 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + atcphy2_typec_lanes: endpoint { + remote-endpoint = <&typec2_connector_ss>; + }; + }; + + port@1 { + reg = <1>; + atcphy2_usb3: endpoint { + remote-endpoint = <&dwc3_2_ss>; + }; + }; + }; +}; + +&atcphy3 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + atcphy3_typec_lanes: endpoint { + remote-endpoint = <&typec3_connector_ss>; + }; + }; + + port@1 { + reg = <1>; + atcphy3_usb3: endpoint { + remote-endpoint = <&dwc3_3_ss>; + }; + }; + }; +}; + +&atcphy2_die1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + atcphy6_typec_lanes: endpoint { + remote-endpoint = <&typec6_connector_ss>; + }; + }; + + port@1 { + reg = <1>; + atcphy6_usb3: endpoint { + remote-endpoint = <&dwc3_6_ss>; + }; + }; + }; +}; + +&atcphy3_die1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + atcphy7_typec_lanes: endpoint { + remote-endpoint = <&typec7_connector_ss>; + }; + }; + + port@1 { + reg = <1>; + atcphy7_usb3: endpoint { + remote-endpoint = <&dwc3_7_ss>; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/apple/t6022-j475d.dts b/arch/arm64/boot/dts/apple/t6022-j475d.dts index 736594544f79..31f24bbda968 100644 --- a/arch/arm64/boot/dts/apple/t6022-j475d.dts +++ b/arch/arm64/boot/dts/apple/t6022-j475d.dts @@ -16,6 +16,11 @@ / { compatible = "apple,j475d", "apple,t6022", "apple,arm-platform"; model = "Apple Mac Studio (M2 Ultra, 2023)"; + + aliases { + atcphy4 = &atcphy0_die1; + atcphy5 = &atcphy1_die1; + }; }; &framebuffer0 { @@ -31,6 +36,32 @@ status = "okay"; }; +&typec4 { + label = "USB-C Front Right"; +}; + +&typec5 { + label = "USB-C Front Left"; +}; + +/* delete unused USB nodes on die 1 */ +/delete-node/ &dwc3_2_dart_0_die1; +/delete-node/ &dwc3_2_dart_1_die1; +/delete-node/ &dwc3_2_die1; +/delete-node/ &atcphy2_die1; + +/delete-node/ &dwc3_3_dart_0_die1; +/delete-node/ &dwc3_3_dart_1_die1; +/delete-node/ &dwc3_3_die1; +/delete-node/ &atcphy3_die1; + +/* delete unused always-on power-domains on die 1 */ +/delete-node/ &ps_atc2_usb_aon_die1; +/delete-node/ &ps_atc2_usb_die1; + +/delete-node/ &ps_atc3_usb_aon_die1; +/delete-node/ &ps_atc3_usb_die1; + &wifi0 { compatible = "pci14e4,4434"; brcm,board-type = "apple,canary"; diff --git a/arch/arm64/boot/dts/apple/t6022-jxxxd.dtsi b/arch/arm64/boot/dts/apple/t6022-jxxxd.dtsi index 4f7bf2ebfe39..dc877bd604f8 100644 --- a/arch/arm64/boot/dts/apple/t6022-jxxxd.dtsi +++ b/arch/arm64/boot/dts/apple/t6022-jxxxd.dtsi @@ -25,6 +25,29 @@ interrupt-parent = <&pinctrl_ap>; interrupts = <44 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "irq"; + + typec4: connector { + compatible = "usb-c-connector"; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + typec4_connector_hs: endpoint { + remote-endpoint = <&dwc3_4_hs>; + }; + }; + port@1 { + reg = <1>; + typec4_connector_ss: endpoint { + remote-endpoint = <&atcphy4_typec_lanes>; + }; + }; + }; + }; }; /* front-left */ @@ -34,5 +57,115 @@ interrupt-parent = <&pinctrl_ap>; interrupts = <44 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "irq"; + + typec5: connector { + compatible = "usb-c-connector"; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + typec5_connector_hs: endpoint { + remote-endpoint = <&dwc3_5_hs>; + }; + }; + port@1 { + reg = <1>; + typec5_connector_ss: endpoint { + remote-endpoint = <&atcphy5_typec_lanes>; + }; + }; + }; + }; + }; +}; + + +/* USB controllers on die 1 */ +&dwc3_0_die1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dwc3_4_hs: endpoint { + remote-endpoint = <&typec4_connector_hs>; + }; + }; + + port@1 { + reg = <1>; + dwc3_4_ss: endpoint { + remote-endpoint = <&atcphy4_usb3>; + }; + }; + }; +}; + +&dwc3_1_die1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dwc3_5_hs: endpoint { + remote-endpoint = <&typec5_connector_hs>; + }; + }; + + port@1 { + reg = <1>; + dwc3_5_ss: endpoint { + remote-endpoint = <&atcphy5_usb3>; + }; + }; + }; +}; + +/* Type-C PHYs */ +&atcphy0_die1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + atcphy4_typec_lanes: endpoint { + remote-endpoint = <&typec4_connector_ss>; + }; + }; + + port@1 { + reg = <1>; + atcphy4_usb3: endpoint { + remote-endpoint = <&dwc3_4_ss>; + }; + }; + }; +}; + +&atcphy1_die1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + atcphy5_typec_lanes: endpoint { + remote-endpoint = <&typec5_connector_ss>; + }; + }; + + port@1 { + reg = <1>; + atcphy5_usb3: endpoint { + remote-endpoint = <&dwc3_5_ss>; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/apple/t602x-die0.dtsi b/arch/arm64/boot/dts/apple/t602x-die0.dtsi index 2e7d2bf08ddc..8622ddea7b44 100644 --- a/arch/arm64/boot/dts/apple/t602x-die0.dtsi +++ b/arch/arm64/boot/dts/apple/t602x-die0.dtsi @@ -121,6 +121,12 @@ nvmem-cell-names = "shutdown_flag", "boot_stage", "boot_error_count", "panic_count"; }; + + rtc { + compatible = "apple,smc-rtc"; + nvmem-cells = <&rtc_offset>; + nvmem-cell-names = "rtc_offset"; + }; }; pinctrl_smc: pinctrl@2a2820000 { diff --git a/arch/arm64/boot/dts/apple/t602x-dieX.dtsi b/arch/arm64/boot/dts/apple/t602x-dieX.dtsi index cb07fd82b32e..ae3d535c5acb 100644 --- a/arch/arm64/boot/dts/apple/t602x-dieX.dtsi +++ b/arch/arm64/boot/dts/apple/t602x-dieX.dtsi @@ -126,3 +126,215 @@ reg = <0x4 0x4e80000 0 0x4000>; }; + + DIE_NODE(dwc3_0): usb@702280000 { + compatible = "apple,t6020-dwc3", "apple,t8103-dwc3"; + reg = <0x7 0x02280000 0x0 0xcd00>, <0x7 0x0228cd00 0x0 0x3200>; + reg-names = "dwc3-core", "dwc3-apple"; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ DIE_NO 1256 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "otg"; + usb-role-switch; + role-switch-default-mode = "host"; + iommus = <&DIE_NODE(dwc3_0_dart_0) 0>, + <&DIE_NODE(dwc3_0_dart_1) 1>; + power-domains = <&DIE_NODE(ps_atc0_usb)>; + resets = <&DIE_NODE(atcphy0)>; + phys = <&DIE_NODE(atcphy0) PHY_TYPE_USB2>, <&DIE_NODE(atcphy0) PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + }; + + DIE_NODE(dwc3_0_dart_0): iommu@702f00000 { + compatible = "apple,t6020-dart", "apple,t8110-dart"; + reg = <0x7 0x02f00000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ DIE_NO 1260 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&DIE_NODE(ps_atc0_usb)>; + #iommu-cells = <1>; + }; + + DIE_NODE(dwc3_0_dart_1): iommu@702f80000 { + compatible = "apple,t6020-dart", "apple,t8110-dart"; + reg = <0x7 0x02f80000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ DIE_NO 1260 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&DIE_NODE(ps_atc0_usb)>; + #iommu-cells = <1>; + }; + + DIE_NODE(atcphy0): phy@703000000 { + compatible = "apple,t6020-atcphy", "apple,t8103-atcphy"; + reg = <0x7 0x03000000 0x0 0x4c000>, + <0x7 0x03050000 0x0 0x8000>, + <0x7 0x00000000 0x0 0x4000>, + <0x7 0x02a90000 0x0 0x4000>, + <0x7 0x02a84000 0x0 0x4000>; + reg-names = "core", "lpdptx", "axi2af", "usb2phy", + "pipehandler"; + + #phy-cells = <1>; + #reset-cells = <0>; + + orientation-switch; + mode-switch; + power-domains = <&DIE_NODE(ps_atc0_usb)>; + }; + + DIE_NODE(dwc3_1): usb@b02280000 { + compatible = "apple,t6020-dwc3", "apple,t8103-dwc3"; + reg = <0xb 0x02280000 0x0 0xcd00>, <0xb 0x0228cd00 0x0 0x3200>; + reg-names = "dwc3-core", "dwc3-apple"; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ DIE_NO 1274 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "otg"; + usb-role-switch; + role-switch-default-mode = "host"; + iommus = <&DIE_NODE(dwc3_1_dart_0) 0>, + <&DIE_NODE(dwc3_1_dart_1) 1>; + power-domains = <&DIE_NODE(ps_atc1_usb)>; + resets = <&DIE_NODE(atcphy1)>; + phys = <&DIE_NODE(atcphy1) PHY_TYPE_USB2>, <&DIE_NODE(atcphy1) PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + }; + + DIE_NODE(dwc3_1_dart_0): iommu@b02f00000 { + compatible = "apple,t6020-dart", "apple,t8110-dart"; + reg = <0xb 0x02f00000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ DIE_NO 1278 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&DIE_NODE(ps_atc1_usb)>; + #iommu-cells = <1>; + }; + + DIE_NODE(dwc3_1_dart_1): iommu@b02f80000 { + compatible = "apple,t6020-dart", "apple,t8110-dart"; + reg = <0xb 0x02f80000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ DIE_NO 1278 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&DIE_NODE(ps_atc1_usb)>; + #iommu-cells = <1>; + }; + + DIE_NODE(atcphy1): phy@b03000000 { + compatible = "apple,t6020-atcphy", "apple,t8103-atcphy"; + reg = <0xb 0x03000000 0x0 0x4c000>, + <0xb 0x03050000 0x0 0x8000>, + <0xb 0x00000000 0x0 0x4000>, + <0xb 0x02a90000 0x0 0x4000>, + <0xb 0x02a84000 0x0 0x4000>; + reg-names = "core", "lpdptx", "axi2af", "usb2phy", + "pipehandler"; + + #phy-cells = <1>; + #reset-cells = <0>; + + orientation-switch; + mode-switch; + power-domains = <&DIE_NODE(ps_atc1_usb)>; + }; + + DIE_NODE(dwc3_2): usb@f02280000 { + compatible = "apple,t6020-dwc3", "apple,t8103-dwc3"; + reg = <0xf 0x02280000 0x0 0xcd00>, <0xf 0x0228cd00 0x0 0x3200>; + reg-names = "dwc3-core", "dwc3-apple"; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ DIE_NO 1292 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "otg"; + usb-role-switch; + role-switch-default-mode = "host"; + iommus = <&DIE_NODE(dwc3_2_dart_0) 0>, + <&DIE_NODE(dwc3_2_dart_1) 1>; + power-domains = <&DIE_NODE(ps_atc2_usb)>; + resets = <&DIE_NODE(atcphy2)>; + phys = <&DIE_NODE(atcphy2) PHY_TYPE_USB2>, <&DIE_NODE(atcphy2) PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + }; + + DIE_NODE(dwc3_2_dart_0): iommu@f02f00000 { + compatible = "apple,t6020-dart", "apple,t8110-dart"; + reg = <0xf 0x02f00000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ DIE_NO 1296 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&DIE_NODE(ps_atc2_usb)>; + #iommu-cells = <1>; + }; + + DIE_NODE(dwc3_2_dart_1): iommu@f02f80000 { + compatible = "apple,t6020-dart", "apple,t8110-dart"; + reg = <0xf 0x02f80000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ DIE_NO 1296 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&DIE_NODE(ps_atc2_usb)>; + #iommu-cells = <1>; + }; + + DIE_NODE(atcphy2): phy@f03000000 { + compatible = "apple,t6020-atcphy", "apple,t8103-atcphy"; + reg = <0xf 0x03000000 0x0 0x4c000>, + <0xf 0x03050000 0x0 0x8000>, + <0xf 0x00000000 0x0 0x4000>, + <0xf 0x02a90000 0x0 0x4000>, + <0xf 0x02a84000 0x0 0x4000>; + reg-names = "core", "lpdptx", "axi2af", "usb2phy", + "pipehandler"; + + #phy-cells = <1>; + #reset-cells = <0>; + + orientation-switch; + mode-switch; + power-domains = <&DIE_NODE(ps_atc2_usb)>; + }; + + DIE_NODE(dwc3_3): usb@1302280000 { + compatible = "apple,t6020-dwc3", "apple,t8103-dwc3"; + reg = <0x13 0x02280000 0x0 0xcd00>, <0x13 0x0228cd00 0x0 0x3200>; + reg-names = "dwc3-core", "dwc3-apple"; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ DIE_NO 1310 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "otg"; + usb-role-switch; + role-switch-default-mode = "host"; + iommus = <&DIE_NODE(dwc3_3_dart_0) 0>, + <&DIE_NODE(dwc3_3_dart_1) 1>; + power-domains = <&DIE_NODE(ps_atc3_usb)>; + resets = <&DIE_NODE(atcphy3)>; + phys = <&DIE_NODE(atcphy3) PHY_TYPE_USB2>, <&DIE_NODE(atcphy3) PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + }; + + DIE_NODE(dwc3_3_dart_0): iommu@1302f00000 { + compatible = "apple,t6020-dart", "apple,t8110-dart"; + reg = <0x13 0x02f00000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ DIE_NO 1314 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&DIE_NODE(ps_atc3_usb)>; + #iommu-cells = <1>; + }; + + DIE_NODE(dwc3_3_dart_1): iommu@1302f80000 { + compatible = "apple,t6020-dart", "apple,t8110-dart"; + reg = <0x13 0x02f80000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ DIE_NO 1314 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&DIE_NODE(ps_atc3_usb)>; + #iommu-cells = <1>; + }; + + DIE_NODE(atcphy3): phy@1303000000 { + compatible = "apple,t6020-atcphy", "apple,t8103-atcphy"; + reg = <0x13 0x03000000 0x0 0x4c000>, + <0x13 0x03050000 0x0 0x8000>, + <0x13 0x00000000 0x0 0x4000>, + <0x13 0x02a90000 0x0 0x4000>, + <0x13 0x02a84000 0x0 0x4000>; + reg-names = "core", "lpdptx", "axi2af", "usb2phy", + "pipehandler"; + + #phy-cells = <1>; + #reset-cells = <0>; + + orientation-switch; + mode-switch; + power-domains = <&DIE_NODE(ps_atc3_usb)>; + }; diff --git a/arch/arm64/boot/dts/apple/t8103-j274.dts b/arch/arm64/boot/dts/apple/t8103-j274.dts index 1c3e37f86d46..52965258200d 100644 --- a/arch/arm64/boot/dts/apple/t8103-j274.dts +++ b/arch/arm64/boot/dts/apple/t8103-j274.dts @@ -15,6 +15,7 @@ / { compatible = "apple,j274", "apple,t8103", "apple,arm-platform"; model = "Apple Mac mini (M1, 2020)"; + chassis-type = "desktop"; aliases { ethernet0 = ðernet0; @@ -30,6 +31,18 @@ }; /* + * Provide labels for the USB type C ports. + */ + +&typec0 { + label = "USB-C Back-left"; +}; + +&typec1 { + label = "USB-C Back-right"; +}; + +/* * Force the bus number assignments so that we can declare some of the * on-board devices and properties that are populated by the bootloader * (such as MAC addresses). diff --git a/arch/arm64/boot/dts/apple/t8103-j293.dts b/arch/arm64/boot/dts/apple/t8103-j293.dts index 5b3c42e9f0e6..52f63ae7a58d 100644 --- a/arch/arm64/boot/dts/apple/t8103-j293.dts +++ b/arch/arm64/boot/dts/apple/t8103-j293.dts @@ -16,6 +16,7 @@ / { compatible = "apple,j293", "apple,t8103", "apple,arm-platform"; model = "Apple MacBook Pro (13-inch, M1, 2020)"; + chassis-type = "laptop"; /* * All of those are used by the bootloader to pass calibration @@ -46,6 +47,18 @@ brcm,board-type = "apple,honshu"; }; +/* + * Provide labels for the USB type C ports. + */ + +&typec0 { + label = "USB-C Left-back"; +}; + +&typec1 { + label = "USB-C Left-front"; +}; + &i2c2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/apple/t8103-j313.dts b/arch/arm64/boot/dts/apple/t8103-j313.dts index 97a4344d8dca..9eb2825d25dc 100644 --- a/arch/arm64/boot/dts/apple/t8103-j313.dts +++ b/arch/arm64/boot/dts/apple/t8103-j313.dts @@ -16,6 +16,7 @@ / { compatible = "apple,j313", "apple,t8103", "apple,arm-platform"; model = "Apple MacBook Air (M1, 2020)"; + chassis-type = "laptop"; led-controller { compatible = "pwm-leds"; @@ -41,3 +42,15 @@ &fpwm1 { status = "okay"; }; + +/* + * Provide labels for the USB type C ports. + */ + +&typec0 { + label = "USB-C Left-back"; +}; + +&typec1 { + label = "USB-C Left-front"; +}; diff --git a/arch/arm64/boot/dts/apple/t8103-j456.dts b/arch/arm64/boot/dts/apple/t8103-j456.dts index 58c8e43789b4..090c97bb781b 100644 --- a/arch/arm64/boot/dts/apple/t8103-j456.dts +++ b/arch/arm64/boot/dts/apple/t8103-j456.dts @@ -15,6 +15,7 @@ / { compatible = "apple,j456", "apple,t8103", "apple,arm-platform"; model = "Apple iMac (24-inch, 4x USB-C, M1, 2021)"; + chassis-type = "all-in-one"; aliases { ethernet0 = ðernet0; @@ -48,6 +49,18 @@ }; /* + * Provide labels for the USB type C ports. + */ + +&typec0 { + label = "USB-C Back-right"; +}; + +&typec1 { + label = "USB-C Back-right-middle"; +}; + +/* * Force the bus number assignments so that we can declare some of the * on-board devices and properties that are populated by the bootloader * (such as MAC addresses). diff --git a/arch/arm64/boot/dts/apple/t8103-j457.dts b/arch/arm64/boot/dts/apple/t8103-j457.dts index 7089ccf3ce55..ebddde75455c 100644 --- a/arch/arm64/boot/dts/apple/t8103-j457.dts +++ b/arch/arm64/boot/dts/apple/t8103-j457.dts @@ -15,6 +15,7 @@ / { compatible = "apple,j457", "apple,t8103", "apple,arm-platform"; model = "Apple iMac (24-inch, 2x USB-C, M1, 2021)"; + chassis-type = "all-in-one"; aliases { ethernet0 = ðernet0; @@ -38,6 +39,18 @@ }; /* + * Provide labels for the USB type C ports. + */ + +&typec0 { + label = "USB-C Back-right"; +}; + +&typec1 { + label = "USB-C Back-left"; +}; + +/* * Force the bus number assignments so that we can declare some of the * on-board devices and properties that are populated by the bootloader * (such as MAC addresses). diff --git a/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi b/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi index 0c8206156bfe..686fb1dd215d 100644 --- a/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi +++ b/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi @@ -15,6 +15,8 @@ serial0 = &serial0; serial2 = &serial2; wifi0 = &wifi0; + atcphy0 = &atcphy0; + atcphy1 = &atcphy1; }; chosen { @@ -53,6 +55,29 @@ interrupt-parent = <&pinctrl_ap>; interrupts = <106 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "irq"; + + typec0: connector { + compatible = "usb-c-connector"; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + typec0_connector_hs: endpoint { + remote-endpoint = <&dwc3_0_hs>; + }; + }; + port@1 { + reg = <1>; + typec0_connector_ss: endpoint { + remote-endpoint = <&atcphy0_typec_lanes>; + }; + }; + }; + }; }; hpm1: usb-pd@3f { @@ -61,6 +86,115 @@ interrupt-parent = <&pinctrl_ap>; interrupts = <106 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "irq"; + + typec1: connector { + compatible = "usb-c-connector"; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + typec1_connector_hs: endpoint { + remote-endpoint = <&dwc3_1_hs>; + }; + }; + port@1 { + reg = <1>; + typec1_connector_ss: endpoint { + remote-endpoint = <&atcphy1_typec_lanes>; + }; + }; + }; + }; + }; +}; + +/* USB controllers */ +&dwc3_0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dwc3_0_hs: endpoint { + remote-endpoint = <&typec0_connector_hs>; + }; + }; + + port@1 { + reg = <1>; + dwc3_0_ss: endpoint { + remote-endpoint = <&atcphy0_usb3>; + }; + }; + }; +}; + +&dwc3_1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dwc3_1_hs: endpoint { + remote-endpoint = <&typec1_connector_hs>; + }; + }; + + port@1 { + reg = <1>; + dwc3_1_ss: endpoint { + remote-endpoint = <&atcphy1_usb3>; + }; + }; + }; +}; + +/* Type-C PHYs */ +&atcphy0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + atcphy0_typec_lanes: endpoint { + remote-endpoint = <&typec0_connector_ss>; + }; + }; + + port@1 { + reg = <1>; + atcphy0_usb3: endpoint { + remote-endpoint = <&dwc3_0_ss>; + }; + }; + }; +}; + +&atcphy1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + atcphy1_typec_lanes: endpoint { + remote-endpoint = <&typec1_connector_ss>; + }; + }; + + port@1 { + reg = <1>; + atcphy1_usb3: endpoint { + remote-endpoint = <&dwc3_1_ss>; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi b/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi index c41c57d63997..fef8a4058f14 100644 --- a/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi +++ b/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi @@ -733,6 +733,7 @@ #power-domain-cells = <0>; #reset-cells = <0>; label = "gfx"; + power-domains = <&ps_pmp>; }; ps_dcs4: power-controller@320 { @@ -1103,6 +1104,7 @@ #power-domain-cells = <0>; #reset-cells = <0>; label = "atc0_usb_aon"; + apple,always-on; /* Needs to stay on for dwc3 to work */ }; ps_atc1_usb_aon: power-controller@90 { @@ -1111,6 +1113,7 @@ #power-domain-cells = <0>; #reset-cells = <0>; label = "atc1_usb_aon"; + apple,always-on; /* Needs to stay on for dwc3 to work */ }; ps_atc0_usb: power-controller@98 { diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/apple/t8103.dtsi index 8b7b27887968..da774096b667 100644 --- a/arch/arm64/boot/dts/apple/t8103.dtsi +++ b/arch/arm64/boot/dts/apple/t8103.dtsi @@ -12,6 +12,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/pinctrl/apple.h> #include <dt-bindings/spmi/spmi.h> +#include <dt-bindings/phy/phy.h> / { compatible = "apple,t8103", "apple,arm-platform"; @@ -916,6 +917,12 @@ nvmem-cell-names = "shutdown_flag", "boot_stage", "boot_error_count", "panic_count"; }; + + rtc { + compatible = "apple,smc-rtc"; + nvmem-cells = <&rtc_offset>; + nvmem-cell-names = "rtc_offset"; + }; }; smc_mbox: mbox@23e408000 { @@ -1007,6 +1014,110 @@ resets = <&ps_ans2>; }; + dwc3_0: usb@382280000 { + compatible = "apple,t8103-dwc3"; + reg = <0x3 0x82280000 0x0 0xcd00>, <0x3 0x8228cd00 0x0 0x3200>; + reg-names = "dwc3-core", "dwc3-apple"; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 777 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "otg"; + usb-role-switch; + role-switch-default-mode = "host"; + iommus = <&dwc3_0_dart_0 0>, <&dwc3_0_dart_1 1>; + power-domains = <&ps_atc0_usb>; + resets = <&atcphy0>; + phys = <&atcphy0 PHY_TYPE_USB2>, <&atcphy0 PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + }; + + dwc3_0_dart_0: iommu@382f00000 { + compatible = "apple,t8103-dart"; + reg = <0x3 0x82f00000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 781 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + power-domains = <&ps_atc0_usb>; + }; + + dwc3_0_dart_1: iommu@382f80000 { + compatible = "apple,t8103-dart"; + reg = <0x3 0x82f80000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 781 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + power-domains = <&ps_atc0_usb>; + }; + + atcphy0: phy@383000000 { + compatible = "apple,t8103-atcphy"; + reg = <0x3 0x83000000 0x0 0x4c000>, + <0x3 0x83050000 0x0 0x8000>, + <0x3 0x80000000 0x0 0x4000>, + <0x3 0x82a90000 0x0 0x4000>, + <0x3 0x82a84000 0x0 0x4000>; + reg-names = "core", "lpdptx", "axi2af", "usb2phy", + "pipehandler"; + + #phy-cells = <1>; + #reset-cells = <0>; + + orientation-switch; + mode-switch; + power-domains = <&ps_atc0_usb>; + }; + + dwc3_1: usb@502280000 { + compatible = "apple,t8103-dwc3"; + reg = <0x5 0x02280000 0x0 0xcd00>, <0x5 0x0228cd00 0x0 0x3200>; + reg-names = "dwc3-core", "dwc3-apple"; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 857 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "otg"; + usb-role-switch; + role-switch-default-mode = "host"; + iommus = <&dwc3_1_dart_0 0>, <&dwc3_1_dart_1 1>; + power-domains = <&ps_atc1_usb>; + resets = <&atcphy1>; + phys = <&atcphy1 PHY_TYPE_USB2>, <&atcphy1 PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + }; + + dwc3_1_dart_0: iommu@502f00000 { + compatible = "apple,t8103-dart"; + reg = <0x5 0x02f00000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 861 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + power-domains = <&ps_atc1_usb>; + }; + + dwc3_1_dart_1: iommu@502f80000 { + compatible = "apple,t8103-dart"; + reg = <0x5 0x02f80000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 861 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + power-domains = <&ps_atc1_usb>; + }; + + atcphy1: phy@503000000 { + compatible = "apple,t8103-atcphy"; + reg = <0x5 0x03000000 0x0 0x4c000>, + <0x5 0x03050000 0x0 0x8000>, + <0x5 0x0 0x0 0x4000>, + <0x5 0x02a90000 0x0 0x4000>, + <0x5 0x02a84000 0x0 0x4000>; + reg-names = "core", "lpdptx", "axi2af", "usb2phy", + "pipehandler"; + + #phy-cells = <1>; + #reset-cells = <0>; + + orientation-switch; + mode-switch; + power-domains = <&ps_atc1_usb>; + }; + pcie0_dart_0: iommu@681008000 { compatible = "apple,t8103-dart"; reg = <0x6 0x81008000 0x0 0x4000>; diff --git a/arch/arm64/boot/dts/apple/t8112-j413.dts b/arch/arm64/boot/dts/apple/t8112-j413.dts index 6f69658623bf..1a08a41f369b 100644 --- a/arch/arm64/boot/dts/apple/t8112-j413.dts +++ b/arch/arm64/boot/dts/apple/t8112-j413.dts @@ -16,6 +16,7 @@ / { compatible = "apple,j413", "apple,t8112", "apple,arm-platform"; model = "Apple MacBook Air (13-inch, M2, 2022)"; + chassis-type = "laptop"; aliases { bluetooth0 = &bluetooth0; @@ -60,6 +61,18 @@ }; }; +/* + * Provide labels for the USB type C ports. + */ + +&typec0 { + label = "USB-C Left-back"; +}; + +&typec1 { + label = "USB-C Left-front"; +}; + &i2c0 { /* MagSafe port */ hpm5: usb-pd@3a { diff --git a/arch/arm64/boot/dts/apple/t8112-j415.dts b/arch/arm64/boot/dts/apple/t8112-j415.dts index b54e218e5384..e37c56d9fb4d 100644 --- a/arch/arm64/boot/dts/apple/t8112-j415.dts +++ b/arch/arm64/boot/dts/apple/t8112-j415.dts @@ -16,6 +16,7 @@ / { compatible = "apple,j415", "apple,t8112", "apple,arm-platform"; model = "Apple MacBook Air (15-inch, M2, 2023)"; + chassis-type = "laptop"; aliases { bluetooth0 = &bluetooth0; @@ -60,6 +61,18 @@ }; }; +/* + * Provide labels for the USB type C ports. + */ + +&typec0 { + label = "USB-C Left-back"; +}; + +&typec1 { + label = "USB-C Left-front"; +}; + &i2c0 { /* MagSafe port */ hpm5: usb-pd@3a { diff --git a/arch/arm64/boot/dts/apple/t8112-j473.dts b/arch/arm64/boot/dts/apple/t8112-j473.dts index 06fe257f08be..438f972546b8 100644 --- a/arch/arm64/boot/dts/apple/t8112-j473.dts +++ b/arch/arm64/boot/dts/apple/t8112-j473.dts @@ -15,6 +15,7 @@ / { compatible = "apple,j473", "apple,t8112", "apple,arm-platform"; model = "Apple Mac mini (M2, 2023)"; + chassis-type = "desktop"; aliases { ethernet0 = ðernet0; @@ -22,6 +23,25 @@ }; /* + * Keep the power-domains used for the HDMI port on. + */ +&framebuffer0 { + power-domains = <&ps_dispext_cpu0>, <&ps_dptx_ext_phy>; +}; + +/* + * The M2 Mac mini uses dispext for the HDMI output so it's not necessary to + * keep disp0 power-domains always-on. + */ +&ps_disp0_sys { + /delete-property/ apple,always-on; +}; + +&ps_disp0_fe { + /delete-property/ apple,always-on; +}; + +/* * Force the bus number assignments so that we can declare some of the * on-board devices and properties that are populated by the bootloader * (such as MAC addresses). @@ -52,3 +72,15 @@ &pcie2_dart { status = "okay"; }; + +/* + * Provide labels for the USB type C ports. + */ + +&typec0 { + label = "USB-C Back-left"; +}; + +&typec1 { + label = "USB-C Back-right"; +}; diff --git a/arch/arm64/boot/dts/apple/t8112-j493.dts b/arch/arm64/boot/dts/apple/t8112-j493.dts index fb8ad7d4c65a..ec116da3e4dd 100644 --- a/arch/arm64/boot/dts/apple/t8112-j493.dts +++ b/arch/arm64/boot/dts/apple/t8112-j493.dts @@ -16,6 +16,7 @@ / { compatible = "apple,j493", "apple,t8112", "apple,arm-platform"; model = "Apple MacBook Pro (13-inch, M2, 2022)"; + chassis-type = "laptop"; /* * All of those are used by the bootloader to pass calibration @@ -108,6 +109,18 @@ }; }; +/* + * Provide labels for the USB type C ports. + */ + +&typec0 { + label = "USB-C Left-back"; +}; + +&typec1 { + label = "USB-C Left-front"; +}; + &i2c4 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/apple/t8112-jxxx.dtsi b/arch/arm64/boot/dts/apple/t8112-jxxx.dtsi index 6da35496a4c8..562e7a25a1e8 100644 --- a/arch/arm64/boot/dts/apple/t8112-jxxx.dtsi +++ b/arch/arm64/boot/dts/apple/t8112-jxxx.dtsi @@ -11,6 +11,8 @@ / { aliases { + atcphy0 = &atcphy0; + atcphy1 = &atcphy1; serial0 = &serial0; serial2 = &serial2; }; @@ -53,6 +55,29 @@ interrupt-parent = <&pinctrl_ap>; interrupts = <8 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "irq"; + + typec0: connector { + compatible = "usb-c-connector"; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + typec0_connector_hs: endpoint { + remote-endpoint = <&dwc3_0_hs>; + }; + }; + port@1 { + reg = <1>; + typec0_connector_ss: endpoint { + remote-endpoint = <&atcphy0_typec_lanes>; + }; + }; + }; + }; }; hpm1: usb-pd@3f { @@ -61,6 +86,115 @@ interrupt-parent = <&pinctrl_ap>; interrupts = <8 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "irq"; + + typec1: connector { + compatible = "usb-c-connector"; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + typec1_connector_hs: endpoint { + remote-endpoint = <&dwc3_1_hs>; + }; + }; + port@1 { + reg = <1>; + typec1_connector_ss: endpoint { + remote-endpoint = <&atcphy1_typec_lanes>; + }; + }; + }; + }; + }; +}; + +/* USB controllers */ +&dwc3_0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dwc3_0_hs: endpoint { + remote-endpoint = <&typec0_connector_hs>; + }; + }; + + port@1 { + reg = <1>; + dwc3_0_ss: endpoint { + remote-endpoint = <&atcphy0_usb3>; + }; + }; + }; +}; + +&dwc3_1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dwc3_1_hs: endpoint { + remote-endpoint = <&typec1_connector_hs>; + }; + }; + + port@1 { + reg = <1>; + dwc3_1_ss: endpoint { + remote-endpoint = <&atcphy1_usb3>; + }; + }; + }; +}; + +/* Type-C PHYs */ +&atcphy0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + atcphy0_typec_lanes: endpoint { + remote-endpoint = <&typec0_connector_ss>; + }; + }; + + port@1 { + reg = <1>; + atcphy0_usb3: endpoint { + remote-endpoint = <&dwc3_0_ss>; + }; + }; + }; +}; + +&atcphy1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + atcphy1_typec_lanes: endpoint { + remote-endpoint = <&typec1_connector_ss>; + }; + }; + + port@1 { + reg = <1>; + atcphy1_usb3: endpoint { + remote-endpoint = <&dwc3_1_ss>; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/apple/t8112.dtsi b/arch/arm64/boot/dts/apple/t8112.dtsi index 3f79878b25af..85c47422d4e8 100644 --- a/arch/arm64/boot/dts/apple/t8112.dtsi +++ b/arch/arm64/boot/dts/apple/t8112.dtsi @@ -11,6 +11,7 @@ #include <dt-bindings/interrupt-controller/apple-aic.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/pinctrl/apple.h> +#include <dt-bindings/phy/phy.h> #include <dt-bindings/spmi/spmi.h> / { @@ -919,6 +920,12 @@ nvmem-cell-names = "shutdown_flag", "boot_stage", "boot_error_count", "panic_count"; }; + + rtc { + compatible = "apple,smc-rtc"; + nvmem-cells = <&rtc_offset>; + nvmem-cell-names = "rtc_offset"; + }; }; smc_mbox: mbox@23e408000 { @@ -1010,6 +1017,110 @@ resets = <&ps_ans>; }; + dwc3_0: usb@382280000 { + compatible = "apple,t8112-dwc3", "apple,t8103-dwc3"; + reg = <0x3 0x82280000 0x0 0xcd00>, <0x3 0x8228cd00 0x0 0x3200>; + reg-names = "dwc3-core", "dwc3-apple"; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 1031 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "otg"; + usb-role-switch; + role-switch-default-mode = "host"; + iommus = <&dwc3_0_dart_0 0>, <&dwc3_0_dart_1 1>; + power-domains = <&ps_atc0_usb>; + resets = <&atcphy0>; + phys = <&atcphy0 PHY_TYPE_USB2>, <&atcphy0 PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + }; + + dwc3_0_dart_0: iommu@382f00000 { + compatible = "apple,t8110-dart"; + reg = <0x3 0x82f00000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 1035 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + power-domains = <&ps_atc0_usb>; + }; + + dwc3_0_dart_1: iommu@382f80000 { + compatible = "apple,t8110-dart"; + reg = <0x3 0x82f80000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 1035 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + power-domains = <&ps_atc0_usb>; + }; + + atcphy0: phy@383000000 { + compatible = "apple,t8112-atcphy", "apple,t8103-atcphy"; + reg = <0x3 0x83000000 0x0 0x4c000>, + <0x3 0x83050000 0x0 0x8000>, + <0x3 0x80000000 0x0 0x4000>, + <0x3 0x82a90000 0x0 0x4000>, + <0x3 0x82a84000 0x0 0x4000>; + reg-names = "core", "lpdptx", "axi2af", "usb2phy", + "pipehandler"; + + #phy-cells = <1>; + #reset-cells = <0>; + + orientation-switch; + mode-switch; + power-domains = <&ps_atc0_usb>; + }; + + dwc3_1: usb@502280000 { + compatible = "apple,t8112-dwc3", "apple,t8103-dwc3"; + reg = <0x5 0x02280000 0x0 0xcd00>, <0x5 0x0228cd00 0x0 0x3200>; + reg-names = "dwc3-core", "dwc3-apple"; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 1112 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "otg"; + usb-role-switch; + role-switch-default-mode = "host"; + iommus = <&dwc3_1_dart_0 0>, <&dwc3_1_dart_1 1>; + power-domains = <&ps_atc1_usb>; + resets = <&atcphy1>; + phys = <&atcphy1 PHY_TYPE_USB2>, <&atcphy1 PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + }; + + dwc3_1_dart_0: iommu@502f00000 { + compatible = "apple,t8110-dart"; + reg = <0x5 0x02f00000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 1116 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + power-domains = <&ps_atc1_usb>; + }; + + dwc3_1_dart_1: iommu@502f80000 { + compatible = "apple,t8110-dart"; + reg = <0x5 0x02f80000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 1116 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + power-domains = <&ps_atc1_usb>; + }; + + atcphy1: phy@503000000 { + compatible = "apple,t8112-atcphy", "apple,t8103-atcphy"; + reg = <0x5 0x03000000 0x0 0x4c000>, + <0x5 0x03050000 0x0 0x8000>, + <0x5 0x0 0x0 0x4000>, + <0x5 0x02a90000 0x0 0x4000>, + <0x5 0x02a84000 0x0 0x4000>; + reg-names = "core", "lpdptx", "axi2af", "usb2phy", + "pipehandler"; + + #phy-cells = <1>; + #reset-cells = <0>; + + orientation-switch; + mode-switch; + power-domains = <&ps_atc1_usb>; + }; + pcie0_dart: iommu@681008000 { compatible = "apple,t8110-dart"; reg = <0x6 0x81008000 0x0 0x4000>; diff --git a/arch/arm64/boot/dts/arm/morello-fvp.dts b/arch/arm64/boot/dts/arm/morello-fvp.dts index 2072c0b72325..4a3f217555f7 100644 --- a/arch/arm64/boot/dts/arm/morello-fvp.dts +++ b/arch/arm64/boot/dts/arm/morello-fvp.dts @@ -25,25 +25,25 @@ clock-output-names = "bp:clock24mhz"; }; - block_0: virtio_block@1c170000 { + block_0: virtio-block@1c170000 { compatible = "virtio,mmio"; reg = <0x0 0x1c170000 0x0 0x200>; interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; }; - net_0: virtio_net@1c180000 { + net_0: virtio-net@1c180000 { compatible = "virtio,mmio"; reg = <0x0 0x1c180000 0x0 0x200>; interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; }; - rng_0: virtio_rng@1c190000 { + rng_0: virtio-rng@1c190000 { compatible = "virtio,mmio"; reg = <0x0 0x1c190000 0x0 0x200>; interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; }; - p9_0: virtio_p9@1c1a0000 { + p9_0: virtio-p9@1c1a0000 { compatible = "virtio,mmio"; reg = <0x0 0x1c1a0000 0x0 0x200>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm64/boot/dts/arm/morello-sdp.dts b/arch/arm64/boot/dts/arm/morello-sdp.dts index cee49dee7571..42c85f450fa9 100644 --- a/arch/arm64/boot/dts/arm/morello-sdp.dts +++ b/arch/arm64/boot/dts/arm/morello-sdp.dts @@ -108,6 +108,13 @@ dma-coherent; }; + pmu@50000000 { + compatible = "arm,cmn-600"; + reg = <0x0 0x50000000 0x0 0x4000000>; + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; + arm,root-node = <0x804000>; + }; + pcie_ctlr: pcie@28c0000000 { device_type = "pci"; compatible = "pci-host-ecam-generic"; diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi index 205b87f557d6..d57a9b1bff70 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi @@ -250,6 +250,15 @@ status = "disabled"; }; + pm: watchdog@7d200000 { + compatible = "brcm,bcm2712-pm", "brcm,bcm2835-pm-wdt"; + reg = <0x7d200000 0x604>; + reg-names = "pm"; + #power-domain-cells = <1>; + #reset-cells = <1>; + system-power-controller; + }; + pinctrl: pinctrl@7d504100 { compatible = "brcm,bcm2712c0-pinctrl"; reg = <0x7d504100 0x30>; @@ -283,6 +292,12 @@ reg = <0x7d510700 0x20>; }; + random: rng@7d208000 { + compatible = "brcm,bcm2711-rng200"; + reg = <0x7d208000 0x28>; + status = "okay"; + }; + interrupt-controller@7d517000 { compatible = "brcm,bcm7271-l2-intc"; reg = <0x7d517000 0x10>; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts index a5f9ec92bd5e..c6d76ba04903 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts @@ -146,9 +146,6 @@ partition@0 { label = "cferom"; reg = <0x0 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0x100000>; nvmem-layout { compatible = "fixed-layout"; diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2-clock.dtsi b/arch/arm64/boot/dts/broadcom/northstar2/ns2-clock.dtsi deleted file mode 100644 index 99009fdf10a4..000000000000 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2-clock.dtsi +++ /dev/null @@ -1,105 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright (c) 2016 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include <dt-bindings/clock/bcm-ns2.h> - - osc: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - }; - - lcpll_ddr: lcpll_ddr@6501d058 { - #clock-cells = <1>; - compatible = "brcm,ns2-lcpll-ddr"; - reg = <0x6501d058 0x20>, - <0x6501c020 0x4>, - <0x6501d04c 0x4>; - clocks = <&osc>; - clock-output-names = "lcpll_ddr", "pcie_sata_usb", - "ddr", "ddr_ch2_unused", - "ddr_ch3_unused", "ddr_ch4_unused", - "ddr_ch5_unused"; - }; - - lcpll_ports: lcpll_ports@6501d078 { - #clock-cells = <1>; - compatible = "brcm,ns2-lcpll-ports"; - reg = <0x6501d078 0x20>, - <0x6501c020 0x4>, - <0x6501d054 0x4>; - clocks = <&osc>; - clock-output-names = "lcpll_ports", "wan", "rgmii", - "ports_ch2_unused", - "ports_ch3_unused", - "ports_ch4_unused", - "ports_ch5_unused"; - }; - - genpll_scr: genpll_scr@6501d098 { - #clock-cells = <1>; - compatible = "brcm,ns2-genpll-scr"; - reg = <0x6501d098 0x32>, - <0x6501c020 0x4>, - <0x6501d044 0x4>; - clocks = <&osc>; - clock-output-names = "genpll_scr", "scr", "fs", - "audio_ref", "scr_ch3_unused", - "scr_ch4_unused", "scr_ch5_unused"; - }; - - iprocmed: iprocmed { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>; - clock-div = <2>; - clock-mult = <1>; - }; - - iprocslow: iprocslow { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>; - clock-div = <4>; - clock-mult = <1>; - }; - - genpll_sw: genpll_sw@6501d0c4 { - #clock-cells = <1>; - compatible = "brcm,ns2-genpll-sw"; - reg = <0x6501d0c4 0x32>, - <0x6501c020 0x4>, - <0x6501d044 0x4>; - clocks = <&osc>; - clock-output-names = "genpll_sw", "rpe", "250", "nic", - "chimp", "port", "sdio"; - }; diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts b/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts index 5939d342aec7..de238a9b1845 100644 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts @@ -106,34 +106,18 @@ &ssp0 { status = "okay"; - - slic@0 { - compatible = "silabs,si3226x"; - reg = <0>; - spi-max-frequency = <5000000>; - spi-cpha; - spi-cpol; - pl022,interface = <0>; - pl022,slave-tx-disable = <0>; - pl022,com-mode = <0>; - pl022,rx-level-trig = <1>; - pl022,tx-level-trig = <1>; - pl022,ctrl-len = <11>; - pl022,wait-state = <0>; - pl022,duplex = <0>; - }; }; &ssp1 { status = "okay"; - at25@0 { + eeprom@0 { compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <5000000>; - at25,byte-len = <0x8000>; - at25,addr-mode = <2>; - at25,page-size = <64>; + size = <0x8000>; + address-width = <16>; + pagesize = <64>; spi-cpha; spi-cpol; pl022,interface = <0>; @@ -167,7 +151,7 @@ }; &nand { - nandcs@0 { + nand@0 { compatible = "brcm,nandcs"; reg = <0>; nand-ecc-mode = "hw"; diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts b/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts index 0e134a94e142..be0876648afd 100644 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts @@ -74,7 +74,7 @@ }; &nand { - nandcs@0 { + nand@0 { compatible = "brcm,nandcs"; reg = <0>; nand-ecc-mode = "hw"; diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi index 9888a1fabd5c..f0374b90f6aa 100644 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi @@ -113,6 +113,28 @@ <&A57_3>; }; + osc: clock-25000000 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + }; + + iprocmed: iprocmed { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>; + clock-div = <2>; + clock-mult = <1>; + }; + + iprocslow: iprocslow { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>; + clock-div = <4>; + clock-mult = <1>; + }; + pcie0: pcie@20020000 { compatible = "brcm,iproc-pcie"; reg = <0 0x20020000 0 0x1000>; @@ -132,7 +154,6 @@ ranges = <0x83000000 0 0x00000000 0 0x00000000 0 0x20000000>; brcm,pcie-ob; - brcm,pcie-ob-oarr-size; brcm,pcie-ob-axi-offset = <0x00000000>; status = "disabled"; @@ -162,7 +183,6 @@ ranges = <0x83000000 0 0x00000000 0 0x30000000 0 0x20000000>; brcm,pcie-ob; - brcm,pcie-ob-oarr-size; brcm,pcie-ob-axi-offset = <0x30000000>; status = "disabled"; @@ -197,8 +217,6 @@ #size-cells = <1>; ranges = <0 0 0 0xffffffff>; - #include "ns2-clock.dtsi" - enet: ethernet@61000000 { compatible = "brcm,ns2-amac"; reg = <0x61000000 0x1000>, @@ -334,6 +352,55 @@ #iommu-cells = <1>; }; + lcpll_ddr: clock-controller@6501d058 { + #clock-cells = <1>; + compatible = "brcm,ns2-lcpll-ddr"; + reg = <0x6501d058 0x20>, + <0x6501c020 0x4>, + <0x6501d04c 0x4>; + clocks = <&osc>; + clock-output-names = "lcpll_ddr", "pcie_sata_usb", + "ddr", "ddr_ch2_unused", + "ddr_ch3_unused", "ddr_ch4_unused", + "ddr_ch5_unused"; + }; + + lcpll_ports: clock-controller@6501d078 { + #clock-cells = <1>; + compatible = "brcm,ns2-lcpll-ports"; + reg = <0x6501d078 0x20>, + <0x6501c020 0x4>, + <0x6501d054 0x4>; + clocks = <&osc>; + clock-output-names = "lcpll_ports", "wan", "rgmii", + "ports_ch2_unused", + "ports_ch3_unused", + "ports_ch4_unused", + "ports_ch5_unused"; + }; + + genpll_scr: clock-controller@6501d098 { + #clock-cells = <1>; + compatible = "brcm,ns2-genpll-scr"; + reg = <0x6501d098 0x32>, + <0x6501c020 0x4>, + <0x6501d044 0x4>; + clocks = <&osc>; + clock-output-names = "genpll_scr", "scr", "fs", + "audio_ref", "scr_ch3_unused", + "scr_ch4_unused", "scr_ch5_unused"; + }; + + genpll_sw: clock-controller@6501d0c4 { + #clock-cells = <1>; + compatible = "brcm,ns2-genpll-sw"; + reg = <0x6501d0c4 0x32>, + <0x6501c020 0x4>, + <0x6501d044 0x4>; + clocks = <&osc>; + clock-output-names = "genpll_sw", "rpe", "250", "nic", + "chimp", "port", "sdio"; + }; pinctrl: pinctrl@6501d130 { compatible = "brcm,ns2-pinmux"; reg = <0x6501d130 0x08>, @@ -438,8 +505,7 @@ ranges = <0 0x65590000 0x10000>; pmu@9000 { - compatible = "arm,cci-400-pmu,r1", - "arm,cci-400-pmu"; + compatible = "arm,cci-400-pmu,r1"; reg = <0x9000 0x4000>; interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, @@ -657,7 +723,7 @@ reg = <0x66220000 0x28>; }; - sata_phy: sata_phy@663f0100 { + sata_phy: sata-phy@663f0100 { compatible = "brcm,iproc-ns2-sata-phy"; reg = <0x663f0100 0x1f00>, <0x663f004c 0x10>; @@ -701,7 +767,7 @@ }; }; - sdio0: sdhci@66420000 { + sdio0: mmc@66420000 { compatible = "brcm,sdhci-iproc-cygnus"; reg = <0x66420000 0x100>; interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; @@ -711,7 +777,7 @@ status = "disabled"; }; - sdio1: sdhci@66430000 { + sdio1: mmc@66430000 { compatible = "brcm,sdhci-iproc-cygnus"; reg = <0x66430000 0x100>; interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; @@ -721,7 +787,7 @@ status = "disabled"; }; - nand: nand@66460000 { + nand: nand-controller@66460000 { compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; reg = <0x66460000 0x600>, <0x67015408 0x600>, @@ -746,7 +812,6 @@ interrupts = <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "spi_l1_intr"; clocks = <&iprocmed>; - clock-names = "iprocmed"; num-cs = <2>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi b/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi index 8fe7325cfbb2..18152b16cfed 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi @@ -88,7 +88,7 @@ &nand { status = "okay"; - nandcs@0 { + nand@0 { compatible = "brcm,nandcs"; reg = <0>; nand-ecc-mode = "hw"; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-clock.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-clock.dtsi deleted file mode 100644 index 10a106aca229..000000000000 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray-clock.dtsi +++ /dev/null @@ -1,182 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2016-2017 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include <dt-bindings/clock/bcm-sr.h> - - osc: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - - crmu_ref25m: crmu_ref25m { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&osc>; - clock-div = <2>; - clock-mult = <1>; - }; - - genpll0: genpll0@1d104 { - #clock-cells = <1>; - compatible = "brcm,sr-genpll0"; - reg = <0x0001d104 0x32>, - <0x0001c854 0x4>; - clocks = <&osc>; - clock-output-names = "genpll0", "clk_125m", "clk_scr", - "clk_250", "clk_pcie_axi", - "clk_paxc_axi_x2", - "clk_paxc_axi"; - }; - - genpll2: genpll2@1d1ac { - #clock-cells = <1>; - compatible = "brcm,sr-genpll2"; - reg = <0x0001d1ac 0x32>, - <0x0001c854 0x4>; - clocks = <&osc>; - clock-output-names = "genpll2", "clk_nic", - "clk_ts_500_ref", "clk_125_nitro", - "clk_chimp", "clk_nic_flash", - "clk_fs"; - }; - - genpll3: genpll3@1d1e0 { - #clock-cells = <1>; - compatible = "brcm,sr-genpll3"; - reg = <0x0001d1e0 0x32>, - <0x0001c854 0x4>; - clocks = <&osc>; - clock-output-names = "genpll3", "clk_hsls", - "clk_sdio"; - }; - - genpll4: genpll4@1d214 { - #clock-cells = <1>; - compatible = "brcm,sr-genpll4"; - reg = <0x0001d214 0x32>, - <0x0001c854 0x4>; - clocks = <&osc>; - clock-output-names = "genpll4", "clk_ccn", - "clk_tpiu_pll", "clk_noc", - "clk_chclk_fs4", - "clk_bridge_fscpu"; - }; - - genpll5: genpll5@1d248 { - #clock-cells = <1>; - compatible = "brcm,sr-genpll5"; - reg = <0x0001d248 0x32>, - <0x0001c870 0x4>; - clocks = <&osc>; - clock-output-names = "genpll5", "clk_fs4_hf", - "clk_crypto_ae", "clk_raid_ae"; - }; - - lcpll0: lcpll0@1d0c4 { - #clock-cells = <1>; - compatible = "brcm,sr-lcpll0"; - reg = <0x0001d0c4 0x3c>, - <0x0001c870 0x4>; - clocks = <&osc>; - clock-output-names = "lcpll0", "clk_sata_refp", - "clk_sata_refn", "clk_sata_350", - "clk_sata_500"; - }; - - lcpll1: lcpll1@1d138 { - #clock-cells = <1>; - compatible = "brcm,sr-lcpll1"; - reg = <0x0001d138 0x3c>, - <0x0001c870 0x4>; - clocks = <&osc>; - clock-output-names = "lcpll1", "clk_wan", - "clk_usb_ref", - "clk_crmu_ts"; - }; - - hsls_clk: hsls_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&genpll3 1>; - clock-div = <1>; - clock-mult = <1>; - }; - - hsls_div2_clk: hsls_div2_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&genpll3 BCM_SR_GENPLL3_HSLS_CLK>; - clock-div = <2>; - clock-mult = <1>; - - }; - - hsls_div4_clk: hsls_div4_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&genpll3 BCM_SR_GENPLL3_HSLS_CLK>; - clock-div = <4>; - clock-mult = <1>; - }; - - hsls_25m_clk: hsls_25m_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&crmu_ref25m>; - clock-div = <1>; - clock-mult = <1>; - }; - - hsls_25m_div2_clk: hsls_25m_div2_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&hsls_25m_clk>; - clock-div = <2>; - clock-mult = <1>; - }; - - sdio0_clk: sdio0_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&genpll3 BCM_SR_GENPLL3_SDIO_CLK>; - clock-div = <1>; - clock-mult = <1>; - }; - - sdio1_clk: sdio1_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&genpll3 BCM_SR_GENPLL3_SDIO_CLK>; - clock-div = <1>; - clock-mult = <1>; - }; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-fs4.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-fs4.dtsi index 9666969c8c88..d704c4ab2147 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray-fs4.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray-fs4.dtsi @@ -30,7 +30,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ - fs4: fs4 { + fs4: fs4-bus@67000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -51,68 +51,68 @@ msi-parent = <&gic_its 0x4300>; #mbox-cells = <3>; }; + }; - raid0: raid@0 { - compatible = "brcm,iproc-sba-v2"; - mboxes = <&raid_mbox 0 0x1 0xff00>, - <&raid_mbox 1 0x1 0xff00>, - <&raid_mbox 2 0x1 0xff00>, - <&raid_mbox 3 0x1 0xff00>; - }; + raid0: raid-0 { + compatible = "brcm,iproc-sba-v2"; + mboxes = <&raid_mbox 0 0x1 0xff00>, + <&raid_mbox 1 0x1 0xff00>, + <&raid_mbox 2 0x1 0xff00>, + <&raid_mbox 3 0x1 0xff00>; + }; - raid1: raid@1 { - compatible = "brcm,iproc-sba-v2"; - mboxes = <&raid_mbox 4 0x1 0xff00>, - <&raid_mbox 5 0x1 0xff00>, - <&raid_mbox 6 0x1 0xff00>, - <&raid_mbox 7 0x1 0xff00>; - }; + raid1: raid-1 { + compatible = "brcm,iproc-sba-v2"; + mboxes = <&raid_mbox 4 0x1 0xff00>, + <&raid_mbox 5 0x1 0xff00>, + <&raid_mbox 6 0x1 0xff00>, + <&raid_mbox 7 0x1 0xff00>; + }; - raid2: raid@2 { - compatible = "brcm,iproc-sba-v2"; - mboxes = <&raid_mbox 8 0x1 0xff00>, - <&raid_mbox 9 0x1 0xff00>, - <&raid_mbox 10 0x1 0xff00>, - <&raid_mbox 11 0x1 0xff00>; - }; + raid2: raid-2 { + compatible = "brcm,iproc-sba-v2"; + mboxes = <&raid_mbox 8 0x1 0xff00>, + <&raid_mbox 9 0x1 0xff00>, + <&raid_mbox 10 0x1 0xff00>, + <&raid_mbox 11 0x1 0xff00>; + }; - raid3: raid@3 { - compatible = "brcm,iproc-sba-v2"; - mboxes = <&raid_mbox 12 0x1 0xff00>, - <&raid_mbox 13 0x1 0xff00>, - <&raid_mbox 14 0x1 0xff00>, - <&raid_mbox 15 0x1 0xff00>; - }; + raid3: raid-3 { + compatible = "brcm,iproc-sba-v2"; + mboxes = <&raid_mbox 12 0x1 0xff00>, + <&raid_mbox 13 0x1 0xff00>, + <&raid_mbox 14 0x1 0xff00>, + <&raid_mbox 15 0x1 0xff00>; + }; - raid4: raid@4 { - compatible = "brcm,iproc-sba-v2"; - mboxes = <&raid_mbox 16 0x1 0xff00>, - <&raid_mbox 17 0x1 0xff00>, - <&raid_mbox 18 0x1 0xff00>, - <&raid_mbox 19 0x1 0xff00>; - }; + raid4: raid-4 { + compatible = "brcm,iproc-sba-v2"; + mboxes = <&raid_mbox 16 0x1 0xff00>, + <&raid_mbox 17 0x1 0xff00>, + <&raid_mbox 18 0x1 0xff00>, + <&raid_mbox 19 0x1 0xff00>; + }; - raid5: raid@5 { - compatible = "brcm,iproc-sba-v2"; - mboxes = <&raid_mbox 20 0x1 0xff00>, - <&raid_mbox 21 0x1 0xff00>, - <&raid_mbox 22 0x1 0xff00>, - <&raid_mbox 23 0x1 0xff00>; - }; + raid5: raid-5 { + compatible = "brcm,iproc-sba-v2"; + mboxes = <&raid_mbox 20 0x1 0xff00>, + <&raid_mbox 21 0x1 0xff00>, + <&raid_mbox 22 0x1 0xff00>, + <&raid_mbox 23 0x1 0xff00>; + }; - raid6: raid@6 { - compatible = "brcm,iproc-sba-v2"; - mboxes = <&raid_mbox 24 0x1 0xff00>, - <&raid_mbox 25 0x1 0xff00>, - <&raid_mbox 26 0x1 0xff00>, - <&raid_mbox 27 0x1 0xff00>; - }; + raid6: raid-6 { + compatible = "brcm,iproc-sba-v2"; + mboxes = <&raid_mbox 24 0x1 0xff00>, + <&raid_mbox 25 0x1 0xff00>, + <&raid_mbox 26 0x1 0xff00>, + <&raid_mbox 27 0x1 0xff00>; + }; - raid7: raid@7 { - compatible = "brcm,iproc-sba-v2"; - mboxes = <&raid_mbox 28 0x1 0xff00>, - <&raid_mbox 29 0x1 0xff00>, - <&raid_mbox 30 0x1 0xff00>, - <&raid_mbox 31 0x1 0xff00>; - }; + raid7: raid-7 { + compatible = "brcm,iproc-sba-v2"; + mboxes = <&raid_mbox 28 0x1 0xff00>, + <&raid_mbox 29 0x1 0xff00>, + <&raid_mbox 30 0x1 0xff00>, + <&raid_mbox 31 0x1 0xff00>; }; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-pcie.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-pcie.dtsi index 663e51756746..fbb2621d1b29 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray-pcie.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray-pcie.dtsi @@ -38,7 +38,7 @@ pcie8: pcie@60400000 { phy-names = "pcie-phy"; }; -pcie-ss { +pcie-ss-bus@40000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi index 46a827521921..b8da71463ad7 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi @@ -32,7 +32,7 @@ #include <dt-bindings/pinctrl/brcm,pinctrl-stingray.h> - pinconf: pinconf@140000 { + pinconf: pinctrl@140000 { compatible = "pinconf-single"; reg = <0x00140000 0x250>; pinctrl-single,register-width = <32>; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi index ac4f7b8f9273..850988287e48 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi @@ -2,7 +2,7 @@ /* *Copyright(c) 2018 Broadcom */ - usb { + usb-bus@68500000 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; @@ -31,16 +31,6 @@ status = "disabled"; }; - bdc0: usb@2000 { - compatible = "brcm,bdc-v0.16"; - reg = <0x0 0x00002000 0x0 0x1000>; - interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; - phys = <&usbphy0 0>, <&usbphy0 1>; - phy-names = "phy0", "phy1"; - dma-coherent; - status = "disabled"; - }; - usbphy1: usb-phy@10000 { compatible = "brcm,sr-usb-combo-phy"; reg = <0x0 0x00010000 0x0 0x100>; @@ -65,13 +55,4 @@ status = "disabled"; }; - bdc1: usb@21000 { - compatible = "brcm,bdc-v0.16"; - reg = <0x0 0x00021000 0x0 0x1000>; - interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; - phys = <&usbphy2>; - phy-names = "phy0"; - dma-coherent; - status = "disabled"; - }; }; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi index 857fa427e195..05139bcb3184 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi @@ -30,6 +30,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +#include <dt-bindings/clock/bcm-sr.h> #include <dt-bindings/interrupt-controller/arm-gic.h> / { @@ -159,7 +160,46 @@ reg = <0 0x60401000 0 0x38c>; }; - scr { + osc: clock-50000000 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + + crmu_ref25m: hsls_25m_clk: clock-25000000 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&osc>; + clock-div = <2>; + clock-mult = <1>; + }; + + hsls_div2_clk: hsls_div2_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&genpll3 BCM_SR_GENPLL3_HSLS_CLK>; + clock-div = <2>; + clock-mult = <1>; + + }; + + hsls_div4_clk: hsls_div4_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&genpll3 BCM_SR_GENPLL3_HSLS_CLK>; + clock-div = <4>; + clock-mult = <1>; + }; + + hsls_25m_div2_clk: clock-12500000 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&hsls_25m_clk>; + clock-div = <2>; + clock-mult = <1>; + }; + + scr-bus@61000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -263,14 +303,12 @@ }; }; - crmu: crmu { + crmu: crmu-bus@66400000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x66400000 0x100000>; - #include "stingray-clock.dtsi" - otp: otp@1c400 { compatible = "brcm,ocotp-v2"; reg = <0x0001c400 0x68>; @@ -283,6 +321,84 @@ reg = <0x0001d000 0x400>; }; + lcpll0: clock-controller@1d0c4 { + #clock-cells = <1>; + compatible = "brcm,sr-lcpll0"; + reg = <0x0001d0c4 0x3c>, + <0x0001c870 0x4>; + clocks = <&osc>; + clock-output-names = "lcpll0", "clk_sata_refp", + "clk_sata_refn", "clk_sata_350", + "clk_sata_500"; + }; + + genpll0: clock-controller@1d104 { + #clock-cells = <1>; + compatible = "brcm,sr-genpll0"; + reg = <0x0001d104 0x32>, + <0x0001c854 0x4>; + clocks = <&osc>; + clock-output-names = "genpll0", "clk_125m", "clk_scr", + "clk_250", "clk_pcie_axi", + "clk_paxc_axi_x2", + "clk_paxc_axi"; + }; + + lcpll1: clock-controller@1d138 { + #clock-cells = <1>; + compatible = "brcm,sr-lcpll1"; + reg = <0x0001d138 0x3c>, + <0x0001c870 0x4>; + clocks = <&osc>; + clock-output-names = "lcpll1", "clk_wan", + "clk_usb_ref", + "clk_crmu_ts"; + }; + + genpll2: clock-controller@1d1ac { + #clock-cells = <1>; + compatible = "brcm,sr-genpll2"; + reg = <0x0001d1ac 0x32>, + <0x0001c854 0x4>; + clocks = <&osc>; + clock-output-names = "genpll2", "clk_nic", + "clk_ts_500_ref", "clk_125_nitro", + "clk_chimp", "clk_nic_flash", + "clk_fs"; + }; + + genpll3: clock-controller@1d1e0 { + #clock-cells = <1>; + compatible = "brcm,sr-genpll3"; + reg = <0x0001d1e0 0x32>, + <0x0001c854 0x4>; + clocks = <&osc>; + clock-output-names = "genpll3", "clk_hsls", + "clk_sdio"; + }; + + genpll4: clock-controller@1d214 { + #clock-cells = <1>; + compatible = "brcm,sr-genpll4"; + reg = <0x0001d214 0x32>, + <0x0001c854 0x4>; + clocks = <&osc>; + clock-output-names = "genpll4", "clk_ccn", + "clk_tpiu_pll", "clk_noc", + "clk_chclk_fs4", + "clk_bridge_fscpu"; + }; + + genpll5: clock-controller@1d248 { + #clock-cells = <1>; + compatible = "brcm,sr-genpll5"; + reg = <0x0001d248 0x32>, + <0x0001c870 0x4>; + clocks = <&osc>; + clock-output-names = "genpll5", "clk_fs4_hf", + "clk_crypto_ae", "clk_raid_ae"; + }; + gpio_crmu: gpio@24800 { compatible = "brcm,iproc-gpio"; reg = <0x00024800 0x4c>; @@ -296,7 +412,7 @@ #include "stingray-pcie.dtsi" #include "stingray-usb.dtsi" - hsls { + hsls-bus@68900000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -575,7 +691,7 @@ status = "disabled"; }; - nand: nand@360000 { + nand: nand-controller@360000 { compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; reg = <0x00360000 0x600>, <0x0050a408 0x600>, @@ -588,28 +704,28 @@ status = "disabled"; }; - sdio0: sdhci@3f1000 { + sdio0: mmc@3f1000 { compatible = "brcm,sdhci-iproc"; reg = <0x003f1000 0x100>; interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; bus-width = <8>; - clocks = <&sdio0_clk>; + clocks = <&genpll3 BCM_SR_GENPLL3_SDIO_CLK>; iommus = <&smmu 0x6002 0x0000>; status = "disabled"; }; - sdio1: sdhci@3f2000 { + sdio1: mmc@3f2000 { compatible = "brcm,sdhci-iproc"; reg = <0x003f2000 0x100>; interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; bus-width = <8>; - clocks = <&sdio1_clk>; + clocks = <&genpll3 BCM_SR_GENPLL3_SDIO_CLK>; iommus = <&smmu 0x6003 0x0000>; status = "disabled"; }; }; - tmons { + tmons-bus@8f100000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -698,18 +814,18 @@ }; }; - nic-hsls { + nic-hsls-bus@60800000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x0 0x0 0x0 0x7fffffff>; + ranges = <0x0 0x0 0x60800000 0x6fffff>; - nic_i2c0: i2c@60826100 { + nic_i2c0: i2c@26100 { compatible = "brcm,iproc-nic-i2c"; #address-cells = <1>; #size-cells = <0>; - reg = <0x60826100 0x100>, - <0x60e00408 0x1000>; + reg = <0x026100 0x100>, + <0x600408 0x1000>; brcm,ape-hsls-addr-mask = <0x03400000>; clock-frequency = <100000>; status = "disabled"; diff --git a/arch/arm64/boot/dts/cavium/Makefile b/arch/arm64/boot/dts/cavium/Makefile index c178f7e06e18..8a1854380993 100644 --- a/arch/arm64/boot/dts/cavium/Makefile +++ b/arch/arm64/boot/dts/cavium/Makefile @@ -1,3 +1,2 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_THUNDER) += thunder-88xx.dtb -dtb-$(CONFIG_ARCH_THUNDER2) += thunder2-99xx.dtb diff --git a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi index cc860a80af51..70430cb2b053 100644 --- a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi +++ b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi @@ -401,16 +401,16 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0x87e0 0x24000000 0x0 0x1000>; interrupts = <1 21 4>; - clocks = <&refclk50mhz>; - clock-names = "apb_pclk"; + clocks = <&refclk50mhz>, <&refclk50mhz>; + clock-names = "uartclk", "apb_pclk"; }; uaa1: serial@87e025000000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x87e0 0x25000000 0x0 0x1000>; interrupts = <1 22 4>; - clocks = <&refclk50mhz>; - clock-names = "apb_pclk"; + clocks = <&refclk50mhz>, <&refclk50mhz>; + clock-names = "uartclk", "apb_pclk"; }; }; }; diff --git a/arch/arm64/boot/dts/cavium/thunder2-99xx.dts b/arch/arm64/boot/dts/cavium/thunder2-99xx.dts deleted file mode 100644 index 89fc4107a0c4..000000000000 --- a/arch/arm64/boot/dts/cavium/thunder2-99xx.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * dts file for Cavium ThunderX2 CN99XX Evaluation Platform - * - * Copyright (c) 2017 Cavium Inc. - * Copyright (c) 2013-2016 Broadcom - */ - -/dts-v1/; - -#include "thunder2-99xx.dtsi" - -/ { - model = "Cavium ThunderX2 CN99XX"; - compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; - - memory@80000000 { - device_type = "memory"; - reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */ - <0x00000008 0x80000000 0x0 0x80000000>; /* 2G @ 34G */ - }; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; diff --git a/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi deleted file mode 100644 index 966fb57280f3..000000000000 --- a/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi +++ /dev/null @@ -1,144 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * dtsi file for Cavium ThunderX2 CN99XX processor - * - * Copyright (c) 2017 Cavium Inc. - * Copyright (c) 2013-2016 Broadcom - * Author: Zi Shen Lim <zlim@broadcom.com> - */ - -#include <dt-bindings/interrupt-controller/arm-gic.h> - -/ { - model = "Cavium ThunderX2 CN99XX"; - compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - /* just 4 cpus now, 128 needed in full config */ - cpus { - #address-cells = <0x2>; - #size-cells = <0x0>; - - cpu@0 { - device_type = "cpu"; - compatible = "cavium,thunder2", "brcm,vulcan"; - reg = <0x0 0x0>; - enable-method = "psci"; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "cavium,thunder2", "brcm,vulcan"; - reg = <0x0 0x1>; - enable-method = "psci"; - }; - - cpu@2 { - device_type = "cpu"; - compatible = "cavium,thunder2", "brcm,vulcan"; - reg = <0x0 0x2>; - enable-method = "psci"; - }; - - cpu@3 { - device_type = "cpu"; - compatible = "cavium,thunder2", "brcm,vulcan"; - reg = <0x0 0x3>; - enable-method = "psci"; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - gic: interrupt-controller@4000080000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - interrupt-controller; - #redistributor-regions = <1>; - reg = <0x04 0x00080000 0x0 0x20000>, /* GICD */ - <0x04 0x01000000 0x0 0x1000000>; /* GICR */ - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; - - gicits: msi-controller@4000100000 { - compatible = "arm,gic-v3-its"; - msi-controller; - reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */ - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, - <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, - <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, - <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; - }; - - pmu { - compatible = "brcm,vulcan-pmu"; - interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; /* PMU overflow */ - }; - - clk125mhz: uart_clk125mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "clk125mhz"; - }; - - pcie@30000000 { - compatible = "pci-host-ecam-generic"; - device_type = "pci"; - #interrupt-cells = <1>; - #address-cells = <3>; - #size-cells = <2>; - - /* ECAM at 0x3000_0000 - 0x4000_0000 */ - reg = <0x0 0x30000000 0x0 0x10000000>; - - /* - * PCI ranges: - * IO no supported - * MEM 0x4000_0000 - 0x6000_0000 - * MEM64 pref 0x40_0000_0000 - 0x60_0000_0000 - */ - ranges = - <0x02000000 0 0x40000000 0 0x40000000 0 0x20000000 - 0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>; - bus-range = <0 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = - /* addr pin ic icaddr icintr */ - <0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH - 0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH - 0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH - 0 0 0 4 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - msi-parent = <&gicits>; - dma-coherent; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - uart0: serial@402020000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x04 0x02020000 0x0 0x1000>; - interrupt-parent = <&gic>; - interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk125mhz>, <&clk125mhz>; - clock-names = "uartclk", "apb_pclk"; - }; - }; - -}; diff --git a/arch/arm64/boot/dts/cix/Makefile b/arch/arm64/boot/dts/cix/Makefile index ed3713982012..8a6c6fdc4ec0 100644 --- a/arch/arm64/boot/dts/cix/Makefile +++ b/arch/arm64/boot/dts/cix/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_CIX) += sky1-orion-o6.dtb +dtb-$(CONFIG_ARCH_CIX) += sky1-xcp.dtb diff --git a/arch/arm64/boot/dts/cix/sky1-xcp.dts b/arch/arm64/boot/dts/cix/sky1-xcp.dts new file mode 100644 index 000000000000..1fae52dc9bb0 --- /dev/null +++ b/arch/arm64/boot/dts/cix/sky1-xcp.dts @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright 2025 Cix Technology Group Co., Ltd. + * + */ + +/dts-v1/; + +#include "sky1.dtsi" +#include "sky1-pinfunc.h" + +/ { + model = "Xunlong,OrangePi 6 Plus"; + compatible = "xunlong,orangepi-6-plus", "cix,sky1"; + + aliases { + serial2 = &uart2; + }; + + chosen { + stdout-path = &uart2; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x28000000>; + linux,cma-default; + }; + }; + +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hog-cfg { + pins { + pinmux = <CIX_PAD_GPIO144_FUNC_GPIO144>, + <CIX_PAD_GPIO145_FUNC_GPIO145>, + <CIX_PAD_GPIO146_FUNC_GPIO146>, + <CIX_PAD_GPIO147_FUNC_GPIO147>; + bias-pull-down; + drive-strength = <8>; + }; + }; +}; + +&iomuxc_s5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_s5>; + + pinctrl_hog_s5: hog-s5-cfg { + pins { + pinmux = <CIX_PAD_GPIO014_FUNC_GPIO014>; + bias-pull-up; + drive-strength = <8>; + + }; + }; +}; + +&pcie_x8_rc { + status = "okay"; +}; + +&pcie_x2_rc { + status = "okay"; +}; + +&pcie_x1_1_rc { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi index 64b76905cbff..fb8c826bbc97 100644 --- a/arch/arm64/boot/dts/cix/sky1.dtsi +++ b/arch/arm64/boot/dts/cix/sky1.dtsi @@ -523,7 +523,7 @@ reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg"; ranges = <0x01000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000>, <0x02000000 0x0 0x38200000 0x0 0x38200000 0x0 0x07e00000>, - <0x43000000 0x0C 0x00000000 0x0C 0x00000000 0x04 0x00000000>; + <0x43000000 0x0c 0x00000000 0x0c 0x00000000 0x04 0x00000000>; #address-cells = <3>; #size-cells = <2>; bus-range = <0x30 0x5f>; diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi index 6ee74d260776..02bf2ca52fdc 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi @@ -1462,6 +1462,17 @@ "wfd"; }; + cmu_mfd: clock-controller@19e00000 { + compatible = "samsung,exynosautov920-cmu-mfd"; + reg = <0x19e00000 0x8000>; + #clock-cells = <1>; + + clocks = <&xtcxo>, + <&cmu_top DOUT_CLKCMU_MFD_NOC>; + clock-names = "oscclk", + "noc"; + }; + pinctrl_aud: pinctrl@1a460000 { compatible = "samsung,exynosautov920-pinctrl"; reg = <0x1a460000 0x10000>; diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index d06d1d05f364..d085f9fb0f62 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -571,6 +571,14 @@ #size-cells = <1>; ranges = <0x0 0x0 0x0 0x40000000>; + efuse@10000000 { + compatible = "google,gs101-otp"; + reg = <0x10000000 0xf084>; + clocks = <&cmu_misc CLK_GOUT_MISC_OTP_CON_TOP_PCLK>; + clock-names = "pclk"; + interrupts = <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH 0>; + }; + cmu_misc: clock-controller@10010000 { compatible = "google,gs101-cmu-misc"; reg = <0x10010000 0x10000>; @@ -578,6 +586,7 @@ clocks = <&cmu_top CLK_DOUT_CMU_MISC_BUS>, <&cmu_top CLK_DOUT_CMU_MISC_SSS>; clock-names = "bus", "sss"; + samsung,sysreg = <&sysreg_misc>; }; sysreg_misc: syscon@10030000 { @@ -630,6 +639,15 @@ status = "disabled"; }; + trng: rng@10141400 { + compatible = "google,gs101-trng", + "samsung,exynos850-trng"; + reg = <0x10141400 0x100>; + clocks = <&cmu_misc CLK_GOUT_MISC_SSS_I_ACLK>, + <&cmu_misc CLK_GOUT_MISC_SSS_I_PCLK>; + clock-names = "secss", "pclk"; + }; + gic: interrupt-controller@10400000 { compatible = "arm,gic-v3"; #address-cells = <0>; @@ -662,6 +680,7 @@ <&cmu_top CLK_DOUT_CMU_PERIC0_BUS>, <&cmu_top CLK_DOUT_CMU_PERIC0_IP>; clock-names = "oscclk", "bus", "ip"; + samsung,sysreg = <&sysreg_peric0>; }; sysreg_peric0: syscon@10820000 { @@ -1208,6 +1227,7 @@ <&cmu_top CLK_DOUT_CMU_PERIC1_BUS>, <&cmu_top CLK_DOUT_CMU_PERIC1_IP>; clock-names = "oscclk", "bus", "ip"; + samsung,sysreg = <&sysreg_peric1>; }; sysreg_peric1: syscon@10c20000 { @@ -1566,6 +1586,7 @@ <&cmu_top CLK_DOUT_CMU_HSI0_USBDPDBG>; clock-names = "oscclk", "bus", "dpgtc", "usb31drd", "usbdpdbg"; + samsung,sysreg = <&sysreg_hsi0>; }; sysreg_hsi0: syscon@11020000 { @@ -1637,6 +1658,7 @@ <&cmu_top CLK_DOUT_CMU_HSI2_UFS_EMBD>, <&cmu_top CLK_DOUT_CMU_HSI2_MMC_CARD>; clock-names = "oscclk", "bus", "pcie", "ufs", "mmc"; + samsung,sysreg = <&sysreg_hsi2>; }; sysreg_hsi2: syscon@14420000 { @@ -1697,6 +1719,7 @@ clocks = <&ext_24_5m>; clock-names = "oscclk"; + samsung,sysreg = <&sysreg_apm>; }; sysreg_apm: syscon@17420000 { @@ -1705,7 +1728,7 @@ }; pmu_system_controller: system-controller@17460000 { - compatible = "google,gs101-pmu", "syscon"; + compatible = "google,gs101-pmu"; reg = <0x17460000 0x10000>; google,pmu-intr-gen-syscon = <&pmu_intr_gen>; @@ -1792,6 +1815,23 @@ status = "disabled"; }; + cmu_dpu: clock-controller@1c000000 { + compatible = "google,gs101-cmu-dpu"; + reg = <0x1c000000 0x10000>; + #clock-cells = <1>; + + clocks = <&ext_24_5m>, + <&cmu_top CLK_DOUT_CMU_DPU_BUS>; + clock-names = "oscclk", "bus"; + samsung,sysreg = <&sysreg_dpu>; + }; + + sysreg_dpu: syscon@1c020000 { + compatible = "google,gs101-dpu-sysreg", "syscon"; + reg = <0x1c020000 0x10000>; + clocks = <&cmu_dpu CLK_GOUT_DPU_SYSREG_DPU_PCLK>; + }; + cmu_top: clock-controller@1e080000 { compatible = "google,gs101-cmu-top"; reg = <0x1e080000 0x10000>; diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index f30d3fd724d0..700bab4d3e60 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -16,6 +16,8 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var3-ads2.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var4.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-rdb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-tqmls1028a-mbls1028a.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-tqmls1028a-mbls1028a-ind.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-tqmls1043a-mbls10xxa.dtb @@ -191,6 +193,25 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-venice-gw7902.dtb +imx8mn-vhip4-evalboard-v1-overlay-ksz8794-dtbs := imx8mn-vhip4-evalboard-v1.dtb \ + imx8mn-vhip4-evalboard-v1-overlay-ksz8794.dtbo +imx8mn-vhip4-evalboard-v1-overlay-ksz9031-dtbs := imx8mn-vhip4-evalboard-v1.dtb \ + imx8mn-vhip4-evalboard-v1-overlay-ksz9031.dtbo +imx8mn-vhip4-evalboard-v2-overlay-ksz8794-dtbs := imx8mn-vhip4-evalboard-v2.dtb \ + imx8mn-vhip4-evalboard-v2-overlay-ksz8794.dtbo +imx8mn-vhip4-evalboard-v2-overlay-adin1300-dtbs := imx8mn-vhip4-evalboard-v2.dtb \ + imx8mn-vhip4-evalboard-v2-overlay-adin1300.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8mn-vhip4-evalboard-v1.dtb \ + imx8mn-vhip4-evalboard-v1-overlay-ksz8794.dtb \ + imx8mn-vhip4-evalboard-v1-overlay-ksz8794.dtbo \ + imx8mn-vhip4-evalboard-v1-overlay-ksz9031.dtb \ + imx8mn-vhip4-evalboard-v1-overlay-ksz9031.dtbo \ + imx8mn-vhip4-evalboard-v2.dtb \ + imx8mn-vhip4-evalboard-v2-overlay-adin1300.dtb \ + imx8mn-vhip4-evalboard-v2-overlay-adin1300.dtbo \ + imx8mn-vhip4-evalboard-v2-overlay-ksz8794.dtb \ + imx8mn-vhip4-evalboard-v2-overlay-ksz8794.dtbo + imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33-dtbs += imx8mn-tqma8mqnl-mba8mx.dtb imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtbo imx8mn-tqma8mqnl-mba8mx-usbotg-dtbs += imx8mn-tqma8mqnl-mba8mx.dtb imx8mn-tqma8mqnl-mba8mx-usbotg.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtb @@ -212,6 +233,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk3.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-picoitx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-edm-g-wb.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-frdm.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-mate.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-pro.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-pulse.dtb @@ -225,8 +247,15 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-kontron-dl.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-kontron-smarc-eval-carrier.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-libra-rdk-fpsc.dtb -imx8mp-libra-rdk-fpsc-lvds-dtbs += imx8mp-libra-rdk-fpsc.dtb imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtbo -dtb-$(CONFIG_ARCH_MXC) += imx8mp-libra-rdk-fpsc-lvds.dtb +imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra-dtbs += imx8mp-libra-rdk-fpsc.dtb \ + imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtbo +imx8mp-libra-rdk-fpsc-lvds-ph128800t006-zhc01-dtbs += imx8mp-libra-rdk-fpsc.dtb \ + imx8mp-libra-rdk-fpsc-lvds-ph128800t006-zhc01.dtbo +imx8mp-libra-rdk-fpsc-lvds-peb-av-10-dtbs += imx8mp-libra-rdk-fpsc.dtb \ + imx8mp-libra-rdk-fpsc-lvds-peb-av-10.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-libra-rdk-fpsc-lvds-ph128800t006-zhc01.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-libra-rdk-fpsc-lvds-peb-av-10.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-msc-sm2s-ep1.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-navqp.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-nitrogen-enc-carrier-board.dtb @@ -243,12 +272,15 @@ imx8mp-phyboard-pollux-peb-av-10-ph128800t006-dtbs += imx8mp-phyboard-pollux-rdk imx8mp-phyboard-pollux-ph128800t006-dtbs += imx8mp-phyboard-pollux-rdk.dtb \ imx8mp-phyboard-pollux-ph128800t006.dtbo imx8mp-phyboard-pollux-rdk-no-eth-dtbs += imx8mp-phyboard-pollux-rdk.dtb imx8mp-phycore-no-eth.dtbo +imx8mp-phyboard-pollux-wlbt-dtbs += imx8mp-phyboard-pollux-rdk.dtb \ + imx8mp-phyboard-pollux-peb-wlbt-05.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-etml1010g3dra.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-peb-av-10.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-peb-av-10-etml1010g3dra.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-peb-av-10-ph128800t006.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-ph128800t006.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk-no-eth.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-wlbt.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-prt8ml.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-basic.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-hdmi.dtb @@ -350,6 +382,11 @@ dtb-${CONFIG_ARCH_MXC} += imx8qm-mek-ov5640-csi1.dtb imx8qm-mek-ov5640-dual-dtbs := imx8qm-mek.dtb imx8qm-mek-ov5640-csi0.dtbo imx8qm-mek-ov5640-csi1.dtbo dtb-${CONFIG_ARCH_MXC} += imx8qm-mek-ov5640-dual.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qp-apalis-v1.1-eval.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qp-apalis-v1.1-eval-v1.2.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qp-apalis-v1.1-ixora-v1.1.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qp-apalis-v1.1-ixora-v1.2.dtb + dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-aster.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb @@ -368,14 +405,18 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqps-mb-smarc-2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8ulp-9x9-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-frdm.dtb dtb-$(CONFIG_ARCH_MXC) += imx91-phyboard-segin.dtb dtb-$(CONFIG_ARCH_MXC) += imx91-tqma9131-mba91xxca.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb.dtb +imx93-9x9-qsb-can1-dtbs += imx93-9x9-qsb.dtb imx93-9x9-qsb-can1.dtbo imx93-9x9-qsb-i3c-dtbs += imx93-9x9-qsb.dtb imx93-9x9-qsb-i3c.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb-can1.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb-i3c.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-frdm.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-14x14-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-kontron-bl-osm-s.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-nash.dtb @@ -400,6 +441,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx943-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-frdm.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk-sof.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-toradex-smarc-dev.dtb @@ -414,6 +456,8 @@ dtb-$(CONFIG_ARCH_MXC) += imx95-libra-rdk-fpsc.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-verdin-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx952-evk.dtb + imx8mm-kontron-dl-dtbs := imx8mm-kontron-bl.dtb imx8mm-kontron-dl.dtbo imx8mm-kontron-bl-lte-dtbs := imx8mm-kontron-bl.dtb imx8mm-kontron-bl-lte.dtbo diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi index ef80bf6a604f..b07022e3b6d5 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi @@ -278,7 +278,7 @@ clock-names = "sfp"; }; - sec_mon: sec_mon@1e90000 { + sec_mon: sec-mon@1e90000 { compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon", "fsl,sec-v4.0-mon"; reg = <0x0 0x1e90000 0x0 0x10000>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-tqmls1028a-mbls1028a-ind.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-tqmls1028a-mbls1028a-ind.dts new file mode 100644 index 000000000000..571b801c4f14 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-tqmls1028a-mbls1028a-ind.dts @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2019-2025 TQ-Systems GmbH <linux@ew.tq-group.com>, + * D-82229 Seefeld, Germany. + * Author: Michael Krummsdorf + * Author: Matthias Schiffer + * Author: Alexander Stein + */ + +/dts-v1/; + +#include "fsl-ls1028a-tqmls1028a-mbls1028a.dtsi" + +/ { + model = "MBLS1028A-IND starterkit"; + compatible = "tq,ls1028a-tqmls1028a-mbls1028a-ind", "tq,ls1028a-tqmls1028a", "fsl,ls1028a"; +}; + +&i2c5 { + gpio_exp_3v3: gpio@71 { + compatible = "nxp,pca9538"; + reg = <0x71>; + #gpio-cells = <2>; + gpio-controller; + + clk-intn-hog { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + input; + line-name = "CLK_INT#"; + }; + + mpcie-waken-hog { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + input; + line-name = "MPCIE_WAKE#"; + }; + + mpcie-disn-hog { + gpio-hog; + gpios = <3 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "MPCIE_DIS#"; + }; + + mpcie-rstn-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "MPCIE_RST#"; + }; + + sata-perstn-hog { + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "SATA_PERST#"; + }; + + dcdc-reset-hog { + gpio-hog; + gpios = <7 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "DCDC_RESET"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-tqmls1028a-mbls1028a.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-tqmls1028a-mbls1028a.dts new file mode 100644 index 000000000000..02563f982ff8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-tqmls1028a-mbls1028a.dts @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2019-2025 TQ-Systems GmbH <linux@ew.tq-group.com>, + * D-82229 Seefeld, Germany. + * Author: Michael Krummsdorf + * Author: Matthias Schiffer + * Author: Alexander Stein + */ + +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include "fsl-ls1028a-tqmls1028a-mbls1028a.dtsi" + +/ { + model = "MBLS1028A starterkit"; + compatible = "tq,ls1028a-tqmls1028a-mbls1028a", "tq,ls1028a-tqmls1028a", "fsl,ls1028a"; + + gpio-beeper { + compatible = "gpio-beeper"; + gpios = <&gpio_exp_3v3 15 GPIO_ACTIVE_HIGH>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + button-0 { + label = "S4"; + linux,code = <BTN_0>; + gpios = <&gpio_exp_3v3 11 GPIO_ACTIVE_LOW>; + }; + + button-1 { + label = "S5"; + linux,code = <BTN_1>; + gpios = <&gpio_exp_3v3 12 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-1 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_STATUS; + function-enumerator = <1>; + gpios = <&gpio_exp_3v3 14 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led-2 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio_exp_3v3 13 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&gpio_exp_1v8 { + dcdc-reset-hog { + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + line-name = "DCDC_RESET"; + output-low; + }; +}; + +&i2c5 { + gpio_exp_3v3: gpio@25 { + compatible = "nxp,pca9555"; + reg = <0x25>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&gpio1>; + interrupts = <30 IRQ_TYPE_LEVEL_LOW>; + vcc-supply = <®_3p3v>; + + clk-intn-hog { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + input; + line-name = "CLK_INT#"; + }; + + mpcie-waken-hog { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + input; + line-name = "MPCIE_WAKE#"; + }; + + mpcie-disn-hog { + gpio-hog; + gpios = <3 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "MPCIE_DIS#"; + }; + + mpcie-rstn-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "MPCIE_RST#"; + }; + + sata-perstn-hog { + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "SATA_PERST#"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-tqmls1028a-mbls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a-tqmls1028a-mbls1028a.dtsi new file mode 100644 index 000000000000..cf338b2e8006 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-tqmls1028a-mbls1028a.dtsi @@ -0,0 +1,287 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2019-2025 TQ-Systems GmbH <linux@ew.tq-group.com>, + * D-82229 Seefeld, Germany. + * Author: Michael Krummsdorf + * Author: Matthias Schiffer + * Author: Alexander Stein + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/net/ti-dp83867.h> +#include "fsl-ls1028a-tqmls1028a.dtsi" + +/ { + aliases { + crypto = &crypto; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + mmc0 = &esdhc; /* SD-Card */ + mmc1 = &esdhc1; /* eMMC */ + serial0 = &duart0; + serial1 = &duart1; + }; + + chosen { + stdout-path = &duart0; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "V_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "V_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + /* 256 MiB */ + size = <0 0x10000000>; + linux,cma-default; + }; + }; +}; + +&can0 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&dspi2 { + bus-num = <2>; + status = "okay"; +}; + +&duart0 { + status = "okay"; +}; + +&duart1 { + status = "okay"; +}; + +&esdhc { + cd-gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; + disable-wp; + no-mmc; + no-sdio; + no-1-8-v; + bus-width = <4>; + status = "okay"; +}; + +/* When switched to baseboard-internal i2c bus, + * IIC5 has access to the following devices. + */ +&i2c4 { + /* TUSB8041 only supports 100 KHz, but it is not connected */ + clock-frequency = <400000>; + status = "okay"; + + /* SI5338 - set up in U-Boot */ + /* clockgen@70 */ +}; + +&i2c5 { + clock-frequency = <400000>; + status = "okay"; + + gpio_exp_1v8: gpio@70 { + compatible = "nxp,pca9538"; + reg = <0x70>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&gpio1>; + interrupts = <30 IRQ_TYPE_LEVEL_LOW>; + vcc-supply = <®_1p8v>; + + ec1-intn-hog { + gpio-hog; + gpios = <0 0>; + input; + line-name = "EC1_INT#"; + }; + + sgmii-intn-hog { + gpio-hog; + gpios = <2 0>; + input; + line-name = "SGMII_INT#"; + }; + + qsgmii-intn-hog { + gpio-hog; + gpios = <4 0>; + input; + line-name = "QSGMII_INT#"; + }; + + qsgmii-rstn-hog { + gpio-hog; + gpios = <5 0>; + output-high; + line-name = "QSGMII_RESET#"; + }; + }; +}; + +&enetc_mdio_pf3 { + mdio0_rgmii_phy00: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x00>; + reset-gpios = <&gpio_exp_1v8 1 GPIO_ACTIVE_LOW>; + reset-assert-us = <1>; + reset-deassert-us = <200>; + interrupt-parent = <&gpio_exp_1v8>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + }; + + mdio0_sgmii_phy03: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x03>; + reset-gpios = <&gpio_exp_1v8 3 GPIO_ACTIVE_LOW>; + /* + * Long reset to work around PHY incorrect strap pin sampling + * due to external capacitors for SGMII + */ + reset-assert-us = <2500>; + reset-deassert-us = <200>; + interrupt-parent = <&gpio_exp_1v8>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + }; + + qsgmii_phy1: ethernet-phy@1c { + reg = <0x1c>; + }; + + qsgmii_phy2: ethernet-phy@1d { + reg = <0x1d>; + }; + + qsgmii_phy3: ethernet-phy@1e { + reg = <0x1e>; + }; + + qsgmii_phy4: ethernet-phy@1f { + reg = <0x1f>; + }; +}; + +&enetc_port0 { + phy-handle = <&mdio0_sgmii_phy03>; + phy-mode = "sgmii"; + managed = "in-band-status"; + status = "okay"; +}; + +&enetc_port1 { + phy-handle = <&mdio0_rgmii_phy00>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&enetc_port2 { + status = "okay"; +}; + +&mscc_felix { + status = "okay"; +}; + +/* l2switch ports */ +&mscc_felix_port0 { + phy-handle = <&qsgmii_phy1>; + phy-mode = "qsgmii"; + status = "okay"; +}; + +&mscc_felix_port1 { + phy-handle = <&qsgmii_phy2>; + phy-mode = "qsgmii"; + status = "okay"; +}; + +&mscc_felix_port2 { + phy-handle = <&qsgmii_phy3>; + phy-mode = "qsgmii"; + status = "okay"; +}; + +&mscc_felix_port3 { + phy-handle = <&qsgmii_phy4>; + phy-mode = "qsgmii"; + status = "okay"; +}; + +&mscc_felix_port4 { + ethernet = <&enetc_port2>; + status = "okay"; +}; + +&pcie2 { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&usb0 { + /* dual role is implemented, but not a full featured OTG */ + hnp-disable; + srp-disable; + adp-disable; + dr_mode = "otg"; + status = "okay"; +}; + +&usb1 { + dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + hub_2_0: hub@1 { + compatible = "usb451,8142"; + reg = <1>; + peer-hub = <&hub_3_0>; + reset-gpios = <&gpio_exp_3v3 1 GPIO_ACTIVE_LOW>; + vdd-supply = <®_3p3v>; + }; + + hub_3_0: hub@2 { + compatible = "usb451,8140"; + reg = <2>; + peer-hub = <&hub_2_0>; + reset-gpios = <&gpio_exp_3v3 1 GPIO_ACTIVE_LOW>; + vdd-supply = <®_3p3v>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-tqmls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a-tqmls1028a.dtsi new file mode 100644 index 000000000000..dbf24dbc043b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-tqmls1028a.dtsi @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2019-2025 TQ-Systems GmbH <linux@ew.tq-group.com>, + * D-82229 Seefeld, Germany. + * Author: Michael Krummsdorf + * Author: Matthias Schiffer + * Author: Alexander Stein + */ + +#include "fsl-ls1028a.dtsi" + +/ { + compatible = "tq,ls1028a-tqmls1028a", "fsl,ls1028a"; + + reg_1p8v_som: regulator-1p8v-som { + compatible = "regulator-fixed"; + regulator-name = "1P8V_SOM"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_3p3v_som: regulator-3p3v-som { + compatible = "regulator-fixed"; + regulator-name = "3P3V_SOM"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + thermal-zones { + /* + * TQMLS1028A uses an external temperature sensor + * instead of TMU + */ + /delete-node/ ddr-controller; + + cluster-thermal { + thermal-sensors = <&sa56004_4c 1>; + }; + }; +}; + +&esdhc1 { + no-sdio; + no-sd; + non-removable; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-ddr-1_8v; + bus-width = <8>; + vmmc-supply = <®_3p3v_som>; + vqmmc-supply = <®_1p8v_som>; + status = "okay"; +}; + +&fspi { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <100000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + vcc-supply = <®_1p8v_som>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + }; + }; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + + js42_18: temperature-sensor@18 { + compatible = "nxp,se97b", "jedec,jc-42.4-temp"; + reg = <0x18>; + }; + + sa56004_4c: temperature-sensor@4c { + compatible = "nxp,sa56004"; + reg = <0x4c>; + #thermal-sensor-cells = <1>; + vcc-supply = <®_3p3v_som>; + }; + + se97_50: eeprom@50 { + compatible = "nxp,se97b", "atmel,24c02"; + read-only; + reg = <0x50>; + pagesize = <16>; + vcc-supply = <®_3p3v_som>; + }; + + rtc1: rtc@51 { + compatible = "nxp,pcf85063a"; + reg = <0x51>; + quartz-load-femtofarads = <12500>; + }; + + m24c256_57: eeprom@57 { + compatible = "atmel,24c256"; + reg = <0x57>; + pagesize = <32>; + vcc-supply = <®_3p3v_som>; + }; +}; + +/* + * We use a separate sensor IC to measure core temperature. Disable the TMU + * as its driver can cause log spam outside of its measurement range (0-125C). + * + * Will have to be reevaluated if this DTS is ported to a mainline kernel, + * as both sensors of the TMU are referenced by the default LS1028A + * thermal-zones definitions there. + */ +&tmu { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-tqmls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a-tqmls1046a.dtsi index fa543db99def..7059ab8bc9d4 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-tqmls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-tqmls1046a.dtsi @@ -10,6 +10,18 @@ #include "fsl-ls1046a.dtsi" #include "tqmls10xxa.dtsi" +&bman_fbpr { + alloc-ranges = <0 0x88000000 1 0x00000000>; +}; + +&qman_fqd { + alloc-ranges = <0 0x88000000 1 0x00000000>; +}; + +&qman_pfdr { + alloc-ranges = <0 0x88000000 1 0x00000000>; +}; + &qspi { num-cs = <2>; status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index 22173d69713d..6fefe837f434 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -851,7 +851,7 @@ status = "disabled"; }; - pcie_ep1: pcie_ep@3400000 { + pcie_ep1: pcie-ep@3400000 { compatible = "fsl,ls1046a-pcie-ep"; reg = <0x00 0x03400000 0x0 0x00100000>, <0x40 0x00000000 0x8 0x00000000>; @@ -890,7 +890,7 @@ status = "disabled"; }; - pcie_ep2: pcie_ep@3500000 { + pcie_ep2: pcie-ep@3500000 { compatible = "fsl,ls1046a-pcie-ep"; reg = <0x00 0x03500000 0x0 0x00100000>, <0x48 0x00000000 0x8 0x00000000>; @@ -929,7 +929,7 @@ status = "disabled"; }; - pcie_ep3: pcie_ep@3600000 { + pcie_ep3: pcie-ep@3600000 { compatible = "fsl,ls1046a-pcie-ep"; reg = <0x00 0x03600000 0x0 0x00100000>, <0x50 0x00000000 0x8 0x00000000>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts index 71765ec91745..f51508952d51 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts @@ -392,13 +392,13 @@ /* ubia (first OpenWrt) - a/b names to prevent confusion with ubi0/1/etc. */ partition@2800000 { label = "ubia"; - reg = <0x2800000 0x6C00000>; + reg = <0x2800000 0x6c00000>; }; /* ubib (second OpenWrt) */ partition@9400000 { label = "ubib"; - reg = <0x9400000 0x6C00000>; + reg = <0x9400000 0x6c00000>; }; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index b2f6cd237be0..99016768b73f 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -684,7 +684,7 @@ compatible = "arm,mmu-500"; reg = <0 0x5000000 0 0x800000>; #iommu-cells = <1>; - stream-match-mask = <0x7C00>; + stream-match-mask = <0x7c00>; dma-coherent; #global-interrupts = <12>; // global secure fault diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index 9421fdd7e30e..6073e426774a 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -881,7 +881,7 @@ reg = <0 0x5000000 0 0x800000>; #global-interrupts = <12>; #iommu-cells = <1>; - stream-match-mask = <0x7C00>; + stream-match-mask = <0x7c00>; dma-coherent; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, /* global secure fault */ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, /* combined secure interrupt */ diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index d899c0355e51..853b01452813 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -35,7 +35,7 @@ d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <192>; next-level-cache = <&cluster0_l2>; @@ -52,7 +52,7 @@ d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <192>; next-level-cache = <&cluster0_l2>; @@ -69,7 +69,7 @@ d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <192>; next-level-cache = <&cluster1_l2>; @@ -86,7 +86,7 @@ d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <192>; next-level-cache = <&cluster1_l2>; @@ -103,7 +103,7 @@ d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <192>; next-level-cache = <&cluster2_l2>; @@ -120,7 +120,7 @@ d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <192>; next-level-cache = <&cluster2_l2>; @@ -137,7 +137,7 @@ d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <192>; next-level-cache = <&cluster3_l2>; @@ -154,7 +154,7 @@ d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <192>; next-level-cache = <&cluster3_l2>; @@ -171,7 +171,7 @@ d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <192>; next-level-cache = <&cluster4_l2>; @@ -188,7 +188,7 @@ d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <192>; next-level-cache = <&cluster4_l2>; @@ -205,7 +205,7 @@ d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <192>; next-level-cache = <&cluster5_l2>; @@ -222,7 +222,7 @@ d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <192>; next-level-cache = <&cluster5_l2>; @@ -239,7 +239,7 @@ d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <192>; next-level-cache = <&cluster6_l2>; @@ -256,7 +256,7 @@ d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <192>; next-level-cache = <&cluster6_l2>; @@ -273,7 +273,7 @@ d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <192>; next-level-cache = <&cluster7_l2>; @@ -290,7 +290,7 @@ d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <192>; next-level-cache = <&cluster7_l2>; diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi index 9153dddfd3b8..6fc82b5eb58c 100644 --- a/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi @@ -6,6 +6,10 @@ #include <dt-bindings/pwm/pwm.h> / { + aliases { + ethernet0 = &fec1; + }; + chosen { stdout-path = &lpuart1; }; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi index 7d5183c6c5be..37e68865b026 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi @@ -11,7 +11,7 @@ ddr_subsys: bus@5c000000 { ranges = <0x5c000000 0x0 0x5c000000 0x1000000>; ddr_pmu0: ddr-pmu@5c020000 { - compatible = "fsl,imx8-ddr-pmu"; + compatible = "fsl,imx8qxp-ddr-pmu", "fsl,imx8-ddr-pmu"; reg = <0x5c020000 0x10000>; interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi index 3569abb5bb9b..adc6e394dbc5 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi @@ -7,3 +7,25 @@ compatible = "fsl,imx8dxl-ddr-pmu", "fsl,imx8-ddr-pmu"; interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; }; + +&ddr_subsys { + db_pmu0: db-pmu@5ca40000 { + compatible = "fsl,imx8dxl-db-pmu"; + reg = <0x5ca40000 0x10000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&db_pmu0_lpcg IMX_LPCG_CLK_4>, <&db_pmu0_lpcg IMX_LPCG_CLK_0>; + clock-names = "ipg", "cnt"; + }; + + db_pmu0_lpcg: clock-controller@5cae0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5cae0000 0x10000>; + #clock-cells = <1>; + clocks = <&db_ipg_clk>, <&db_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; + clock-output-names = "perf_lpcg_cnt_clk", + "perf_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_PERF>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi index 8d60827822ed..5106be2fde6e 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi @@ -236,6 +236,13 @@ clock-output-names = "xtal_24MHz"; }; + db_ipg_clk: clock-db-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <456000000>; + clock-output-names = "db_ipg_clk"; + }; + /* sorted in register address */ #include "imx8-ss-cm40.dtsi" #include "imx8-ss-adma.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phycore-rpmsg.dtso b/arch/arm64/boot/dts/freescale/imx8mm-phycore-rpmsg.dtso index 43d5905f3d72..414f44b85564 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-phycore-rpmsg.dtso +++ b/arch/arm64/boot/dts/freescale/imx8mm-phycore-rpmsg.dtso @@ -33,7 +33,7 @@ no-map; }; - rsc_table: rsc_table@b80ff000 { + rsc_table: rsc-table@b80ff000 { reg = <0 0xb80ff000 0 0x1000>; no-map; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi index 3d66c6701342..b764f7734868 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi @@ -83,6 +83,7 @@ enet-phy-lane-no-swap; ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,min-output-impedance; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; reg = <0>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts index b941c8c4f7bb..8dcc5cbcb8f6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts @@ -101,6 +101,10 @@ status = "okay"; }; +®_usdhc2_vqmmc { + status = "okay"; +}; + &sai3 { assigned-clocks = <&clk IMX8MM_CLK_SAI3>; assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; @@ -276,8 +280,7 @@ <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4>, <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4>, <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4>, - <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>, - <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x84>; + <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>; }; pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { @@ -286,8 +289,7 @@ <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4>, <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4>, <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4>, - <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>, - <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x84>; + <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>; }; pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { @@ -296,7 +298,6 @@ <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4>, <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4>, <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4>, - <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>, - <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x84>; + <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi index b82e9790ea20..29b298af0d73 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi @@ -16,20 +16,18 @@ reg = <0x00000000 0x40000000 0 0x40000000>; }; - /* e-MMC IO, needed for HS modes */ - reg_vcc1v8: regulator-vcc1v8 { - compatible = "regulator-fixed"; - regulator-name = "TQMA8MXML_VCC1V8"; + reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vqmmc>; + regulator-name = "V_SD2"; regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - /* identical to buck4_reg, but should never change */ - reg_vcc3v3: regulator-vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "TQMA8MXML_VCC3V3"; - regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + states = <1800000 0x1>, + <3300000 0x0>; + vin-supply = <&ldo5_reg>; + status = "disabled"; }; reserved-memory { @@ -211,7 +209,6 @@ }; }; - pcf85063: rtc@51 { compatible = "nxp,pcf85063a"; reg = <0x51>; @@ -223,14 +220,14 @@ read-only; reg = <0x53>; pagesize = <16>; - vcc-supply = <®_vcc3v3>; + vcc-supply = <&buck4_reg>; }; eeprom0: eeprom@57 { compatible = "atmel,24c64"; reg = <0x57>; pagesize = <32>; - vcc-supply = <®_vcc3v3>; + vcc-supply = <&buck4_reg>; }; }; @@ -244,6 +241,10 @@ fsl,clkreq-unsupported; }; +&usdhc2 { + vqmmc-supply = <®_usdhc2_vqmmc>; +}; + &usdhc3 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc3>; @@ -253,8 +254,8 @@ non-removable; no-sd; no-sdio; - vmmc-supply = <®_vcc3v3>; - vqmmc-supply = <®_vcc1v8>; + vmmc-supply = <&buck4_reg>; + vqmmc-supply = <&buck5_reg>; status = "okay"; }; @@ -298,6 +299,10 @@ fsl,pins = <MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x84>; }; + pinctrl_reg_usdhc2_vqmmc: regusdhc2vqmmcgrp { + fsl,pins = <MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0xc0>; + }; + pinctrl_usdhc3: usdhc3grp { fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d4>, <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>, diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi index 429be2bab8a2..320806d3d073 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi @@ -92,6 +92,15 @@ interrupt-parent = <&gpio4>; interrupts = <5 IRQ_TYPE_LEVEL_LOW>; }; + + magnetometer@1e { + compatible = "st,lis2mdl"; + reg = <0x1e>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mag>; + interrupt-parent = <&gpio4>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + }; }; /* off-board header */ @@ -174,6 +183,12 @@ >; }; + pinctrl_mag: maggrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x159 + >; + }; + pinctrl_gpio_leds: gpioledgrp { fsl,pins = < MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19 diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index fc3cd639310e..9f49c0b386d3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -234,7 +234,7 @@ arm,no-tick-in-suspend; }; - thermal-zones { + thermal_zones: thermal-zones { cpu-thermal { polling-delay-passive = <250>; polling-delay = <2000>; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts index d7f7f9aafb7d..664f4a6950a8 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts @@ -69,6 +69,10 @@ samsung,esc-clock-frequency = <20000000>; }; +®_usdhc2_vqmmc { + status = "okay"; +}; + &sai3 { assigned-clocks = <&clk IMX8MN_CLK_SAI3>; assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; @@ -143,23 +147,23 @@ }; pinctrl_i2c2: i2c2grp { - fsl,pins = <MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001C4>, - <MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001C4>; + fsl,pins = <MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c4>, + <MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c4>; }; pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = <MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001C4>, - <MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001C4>; + fsl,pins = <MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c4>, + <MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c4>; }; pinctrl_i2c3: i2c3grp { - fsl,pins = <MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001C4>, - <MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001C4>; + fsl,pins = <MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c4>, + <MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c4>; }; pinctrl_i2c3_gpio: i2c3gpiogrp { - fsl,pins = <MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001C4>, - <MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001C4>; + fsl,pins = <MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c4>, + <MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c4>; }; pinctrl_pwm3: pwm3grp { @@ -216,8 +220,7 @@ <MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4>, <MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4>, <MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4>, - <MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>, - <MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x84>; + <MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>; }; pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { @@ -226,8 +229,7 @@ <MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4>, <MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4>, <MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4>, - <MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>, - <MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x84>; + <MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>; }; pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { @@ -236,8 +238,7 @@ <MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4>, <MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4>, <MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4>, - <MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>, - <MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x84>; + <MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>; }; pinctrl_usdhc2_gpio: usdhc2-gpiogrp { diff --git a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi index 1d23814e11cd..31a3ca137e63 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi @@ -15,19 +15,18 @@ reg = <0x00000000 0x40000000 0 0x40000000>; }; - /* e-MMC IO, needed for HS modes */ - reg_vcc1v8: regulator-vcc1v8 { - compatible = "regulator-fixed"; - regulator-name = "TQMA8MXNL_VCC1V8"; + reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vqmmc>; + regulator-name = "V_SD2"; regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - reg_vcc3v3: regulator-vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "TQMA8MXNL_VCC3V3"; - regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + states = <1800000 0x1>, + <3300000 0x0>; + vin-supply = <&ldo5_reg>; + status = "disabled"; }; reserved-memory { @@ -217,14 +216,14 @@ read-only; reg = <0x53>; pagesize = <16>; - vcc-supply = <®_vcc3v3>; + vcc-supply = <&buck4_reg>; }; eeprom0: eeprom@57 { compatible = "atmel,24c64"; reg = <0x57>; pagesize = <32>; - vcc-supply = <®_vcc3v3>; + vcc-supply = <&buck4_reg>; }; }; @@ -233,6 +232,10 @@ vddio-supply = <&ldo3_reg>; }; +&usdhc2 { + vqmmc-supply = <®_usdhc2_vqmmc>; +}; + &usdhc3 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc3>; @@ -242,8 +245,8 @@ non-removable; no-sd; no-sdio; - vmmc-supply = <®_vcc3v3>; - vqmmc-supply = <®_vcc1v8>; + vmmc-supply = <&buck4_reg>; + vqmmc-supply = <&buck5_reg>; status = "okay"; }; @@ -287,6 +290,10 @@ fsl,pins = <MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x84>; }; + pinctrl_reg_usdhc2_vqmmc: regusdhc2vqmmcgrp { + fsl,pins = <MX8MN_IOMUXC_GPIO1_IO04_GPIO1_IO4 0xc0>; + }; + pinctrl_usdhc3: usdhc3grp { fsl,pins = <MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d4>, <MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>, diff --git a/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-common.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-common.dtsi new file mode 100644 index 000000000000..aaf9761703aa --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-common.dtsi @@ -0,0 +1,396 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020-2024 Fedor Ross <fedor.ross@ifm.com> + */ + +#include "imx8mn.dtsi" +#include <dt-bindings/leds/common.h> + +/ { + model = "ifm i.MX8MNano VHIP4 Evaluation Board"; + compatible = "ifm,imx8mn-vhip4-evalboard", "ifm,imx8mn-vhip4", "fsl,imx8mn"; + + aliases { + mmc0 = &usdhc3; + mmc1 = &usdhc1; + mmc2 = &usdhc2; + rtc0 = &hw_rtc; + rtc1 = &snvs_rtc; + }; + + chosen { + bootargs = "console=ttymxc2,115200 earlycon=ec_imx6q,0x30880000,115200 rootwait"; + stdout-path = &uart3; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x40000000>; + }; + + can_clk20m: can-clk20m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <20000000>; + }; + + can_clk40m: can-clk40m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pinctrl_gpio_button>; + pinctrl-names = "default"; + + button-2 { + label = "Button2"; + gpios = <&gpio2 16 GPIO_ACTIVE_LOW>; + linux,code = <KEY_2>; + }; + + button-3 { + label = "Button3"; + gpios = <&gpio2 18 GPIO_ACTIVE_LOW>; + linux,code = <KEY_3>; + }; + }; + + ifm_led: led { + compatible = "gpio-leds"; + pinctrl-0 = <&pinctrl_gpio_led>; + pinctrl-names = "default", "extended"; + + led-0 { + function = LED_FUNCTION_STATUS; + function-enumerator = <1>; + color = <LED_COLOR_ID_YELLOW>; + gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + + led-1 { + function = LED_FUNCTION_STATUS; + function-enumerator = <2>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + }; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&A53_1 { + cpu-supply = <&buck2_reg>; +}; + +&A53_2 { + cpu-supply = <&buck2_reg>; +}; + +&A53_3 { + cpu-supply = <&buck2_reg>; +}; + +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25000000 { + opp-hz = /bits/ 64 <25000000>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + }; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_ecspi1_cs>; + /delete-property/ dmas; + /delete-property/ dma-names; +}; + +&ecspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>, <&pinctrl_ecspi3_cs>; + /delete-property/ dmas; + /delete-property/ dma-names; +}; + +&gpu { + /* SoC has GPU fused off. */ + status = "disabled"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + + eeprom@51 { + compatible = "atmel,24c128"; + reg = <0x51>; + }; + + hw_rtc: rtc@52 { + compatible = "microcrystal,rv3028"; + reg = <0x52>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + + ifm_pmic: pmic@4b { + compatible = "rohm,bd71847"; + reg = <0x4b>; + pinctrl-0 = <&pinctrl_pmic>; + rohm,reset-snvs-powered; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "buck1"; + regulator-min-microvolt = <790000>; + regulator-max-microvolt = <860000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: BUCK2 { + regulator-name = "buck2"; + regulator-min-microvolt = <840000>; + regulator-max-microvolt = <960000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck3_reg: BUCK3 { + // BUCK5 in datasheet + regulator-name = "buck3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + }; + + buck4_reg: BUCK4 { + // BUCK6 in datasheet + regulator-name = "buck4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: BUCK5 { + // BUCK7 in datasheet + regulator-name = "buck5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: BUCK6 { + // BUCK8 in datasheet + regulator-name = "buck6"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: LDO1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + }; + + ldo5_reg: LDO5 { + regulator-name = "ldo5"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo6_reg: LDO6 { + regulator-name = "ldo6"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1-grp { + fsl,pins = < + MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x110 + MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x110 + MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x190 + >; + }; + + pinctrl_ecspi3: ecspi3-grp { + fsl,pins = < + /* SPI3_CAN_CLK */ + MX8MN_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x110 + /* SPI3_CAN_MOSI */ + MX8MN_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x110 + /* SPI3_CAN_MISO */ + MX8MN_IOMUXC_UART2_RXD_ECSPI3_MISO 0x190 + >; + }; + + pinctrl_gpio_button: gpiobutton-grp { + fsl,pins = < + MX8MN_IOMUXC_SD2_DATA1_GPIO2_IO16 0x96 + MX8MN_IOMUXC_SD2_DATA3_GPIO2_IO18 0x96 + >; + }; + + pinctrl_gpio_led: gpioled-grp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_GPIO2_IO13 0x116 + MX8MN_IOMUXC_SD2_DATA0_GPIO2_IO15 0x116 + >; + }; + + pinctrl_usdhc3: usdhc3-grp { + fsl,pins = < + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000110 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x150 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp { + fsl,pins = < + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000114 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x150 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp { + fsl,pins = < + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000116 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x150 + >; + }; + + pinctrl_wdog: wdog-grp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x64 + >; + }; +}; + +&pgc_gpumix { + /* SoC has GPU fused off. */ + status = "disabled"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart3 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usbotg1 { + status = "okay"; +}; + +&usdhc3 { + assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-ksz8794-common.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-ksz8794-common.dtsi new file mode 100644 index 000000000000..c1a98ec2f438 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-ksz8794-common.dtsi @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2025 Fedor Ross <fedor.ross@ifm.com> + */ + +#include <dt-bindings/gpio/gpio.h> + +#include "imx8mn-pinfunc.h" + +&ecspi1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ksz8794: ethernet-switch@1 { + compatible = "microchip,ksz8794"; + pinctrl-names = "default", "reset"; + pinctrl-0 = <&pinctrl_ks8794>; + pinctrl-1 = <&pinctrl_ks8794>; + reg = <1>; + reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; + spi-max-frequency = <5000000>; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@4 { + reg = <4>; + label = "cpu"; + ethernet = <&fec1>; + phy-mode = "rgmii-id"; + rx-internal-delay-ps = <2000>; + tx-internal-delay-ps = <2000>; + fixed-link { + full-duplex; + speed = <1000>; + }; + }; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + status = "okay"; + + fixed-link { + full-duplex; + speed = <1000>; + }; +}; + +&iomuxc { + pinctrl_fec1: fec1-grp { + fsl,pins = < + MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x16 + MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x96 + MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x16 + MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x16 + MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x16 + MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x16 + MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x96 + MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x96 + MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x96 + MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x96 + MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x10 + MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x96 + MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x96 + MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x16 + MX8MN_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1d6 + >; + }; + + pinctrl_ks8794: ks8794-grp { + fsl,pins = < + /* KSZ8794 reset line */ + MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x16 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v1-overlay-ksz8794.dtso b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v1-overlay-ksz8794.dtso new file mode 100644 index 000000000000..20eb427f3dd6 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v1-overlay-ksz8794.dtso @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 Marek Vasut + */ +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> + +#include "imx8mn-pinfunc.h" + +&pinctrl_ecspi1 { + fsl,pins = < + MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x10 + MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x10 + MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x90 + /* KS8794 nCS */ + MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0x150 + /* ANV32C81 nCS */ + MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x150 + >; +}; + +#include "imx8mn-vhip4-evalboard-ksz8794-common.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v1-overlay-ksz9031.dtso b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v1-overlay-ksz9031.dtso new file mode 100644 index 000000000000..de24206106b3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v1-overlay-ksz9031.dtso @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 Marek Vasut + */ +/dts-v1/; +/plugin/; + +#include "imx8mn-pinfunc.h" + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + }; +}; + +&iomuxc { + pinctrl_fec1: fec1-grp { + fsl,pins = < + MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x16 + MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x96 + MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x16 + MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x16 + MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x16 + MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x16 + MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x96 + MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x96 + MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x96 + MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x96 + MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x16 + MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x96 + MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x96 + MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x16 + MX8MN_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1d6 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v1.dts b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v1.dts new file mode 100644 index 000000000000..5f37065bf43f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v1.dts @@ -0,0 +1,258 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020-2024 Fedor Ross <fedor.ross@ifm.com> + */ + +/dts-v1/; + +#include "imx8mn-vhip4-evalboard-common.dtsi" + +/ { + model = "ifm i.MX8MNano VHIP4 Evaluation Board v1"; + compatible = "ifm,imx8mn-vhip4-evalboard-v1", "ifm,imx8mn-vhip4-evalboard", + "ifm,imx8mn-vhip4", "fsl,imx8mn"; +}; + +&ifm_led { + pinctrl-1 = <&pinctrl_gpio_led_v1>; + + led-2 { + function = LED_FUNCTION_STATUS; + function-enumerator = <3>; + color = <LED_COLOR_ID_YELLOW>; + gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + + led-3 { + function = LED_FUNCTION_STATUS; + function-enumerator = <4>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; +}; + +&ecspi1 { + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, <&gpio5 21 GPIO_ACTIVE_LOW>; + status = "okay"; + + eeprom@0 { + compatible = "anvo,anv32c81w", "atmel,at25"; + reg = <0>; + spi-max-frequency = <20000000>; + spi-cpha; + spi-cpol; + pagesize = <1>; + size = <32768>; + address-width = <16>; + }; +}; + +&ecspi3 { + cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>, <&gpio5 4 GPIO_ACTIVE_LOW>; + status = "okay"; + + can0: can@0 { + compatible = "microchip,mcp25625"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcp25625>; + reg = <0>; + clocks = <&can_clk20m>; + interrupt-parent = <&gpio4>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + #gpio-cells = <2>; + }; + + can1: can@1 { + compatible = "microchip,mcp2518fd"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcp2518>; + reg = <1>; + clocks = <&can_clk40m>; + interrupt-parent = <&gpio5>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + microchip,rx-int-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; + spi-max-frequency = <20000000>; + }; +}; + +&i2c1 { + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; + status = "okay"; + + temperature-sensor@48 { + compatible = "national,lm75"; + reg = <0x48>; + }; + + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&i2c3 { + scl-gpios = <&gpio2 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&ifm_pmic { + interrupt-parent = <&gpio2>; + interrupts = <0 GPIO_ACTIVE_LOW>; +}; + +&iomuxc { + pinctrl_ecspi1_cs: ecspi1-cs-grp { + fsl,pins = < + /* KS8794 nCS */ + MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0x150 + /* ANV32C81 nCS */ + MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x150 + >; + }; + + pinctrl_ecspi3_cs: ecspi3-cs-grp { + fsl,pins = < + /* MCP25625 nCS */ + MX8MN_IOMUXC_UART2_TXD_GPIO5_IO25 0x150 + /* MCP2518FD nCS */ + MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x150 + >; + }; + + pinctrl_gpio_5: gpio5-grp { + fsl,pins = < + /* CFG_EEPROM_WP */ + MX8MN_IOMUXC_I2C4_SCL_GPIO5_IO20 0x140 + >; + }; + + pinctrl_gpio_led_v1: gpioled-v1-grp { + fsl,pins = < + MX8MN_IOMUXC_SD2_DATA2_GPIO2_IO17 0x116 + MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x116 + >; + }; + + pinctrl_i2c1: i2c1-grp { + fsl,pins = < + MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000056 + MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400000d6 + >; + }; + + pinctrl_i2c1_gpio: i2c1-gpio-grp { + fsl,pins = < + MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x56 + MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0xd6 + >; + }; + + pinctrl_i2c2: i2c2-grp { + fsl,pins = < + MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000056 + MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400000d6 + >; + }; + + pinctrl_i2c2_gpio: i2c2-gpio-grp { + fsl,pins = < + MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x56 + MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0xd6 + >; + }; + + pinctrl_i2c3: i2c3-grp { + fsl,pins = < + MX8MN_IOMUXC_SD1_RESET_B_I2C3_SCL 0x40000056 + MX8MN_IOMUXC_SD1_STROBE_I2C3_SDA 0x400000d6 + >; + }; + + pinctrl_i2c3_gpio: i2c3-gpio-grp { + fsl,pins = < + MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x56 + MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0xd6 + >; + }; + + pinctrl_mcp2518: mcp2518-grp { + fsl,pins = < + /* MCP2518 nINT line */ + MX8MN_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x116 + /* MCP2518 nINT1/GPIO1 line */ + MX8MN_IOMUXC_SAI3_TXD_GPIO5_IO1 0x116 + >; + }; + + pinctrl_mcp25625: mcp25625-grp { + fsl,pins = < + /* MCP25625 nINT line */ + MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x156 + >; + }; + + pinctrl_pmic: pmic-irq-grp { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_GPIO2_IO0 0x16 + >; + }; + + pinctrl_uart3: uart3-grp { + fsl,pins = < + MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x142 + MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x142 + >; + }; + + pinctrl_usb_nreset: usbnreset-grp { + fsl,pins = < + MX8MN_IOMUXC_SAI3_RXC_GPIO4_IO29 0x14a + >; + }; + + pinctrl_wdog: wdog-grp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x64 + >; + }; +}; + +&gpio5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_5>; + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", + "ifm_device_info_eeprom_wp", + "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_nreset>; + #address-cells = <1>; + #size-cells = <0>; + + usb-hub@1 { + compatible = "usb424,2512", "usb424,2514"; + reg = <1>; + reset-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v2-overlay-adin1300.dtso b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v2-overlay-adin1300.dtso new file mode 100644 index 000000000000..6ad7434a1787 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v2-overlay-adin1300.dtso @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2024 Fedor Ross <fedor.ross@ifm.com> + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include "imx8mn-pinfunc.h" + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + + adi,rx-internal-delay-ps = <1800>; + adi,tx-internal-delay-ps = <2200>; + interrupts-extended = <&gpio4 31 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <10000>; + }; + }; +}; + +&iomuxc { + pinctrl_fec1: fec1-grp { + fsl,pins = < + MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x16 + MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x96 + MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x16 + MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x16 + MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x16 + MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x16 + MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x96 + MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x96 + MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x96 + MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x96 + MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x16 + MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x96 + MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x96 + MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x16 + /* nRST */ + MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x156 + /* nIRQ */ + MX8MN_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1d6 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v2-overlay-ksz8794.dtso b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v2-overlay-ksz8794.dtso new file mode 100644 index 000000000000..ab1304ebd965 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v2-overlay-ksz8794.dtso @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 Marek Vasut + */ +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> + +#include "imx8mn-pinfunc.h" + +&pinctrl_ecspi1 { + fsl,pins = < + MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x10 + MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x10 + MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x90 + /* KS8794 nCS */ + MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x150 + /* ANV32C81 nCS */ + MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x150 + >; +}; + +#include "imx8mn-vhip4-evalboard-ksz8794-common.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v2.dts b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v2.dts new file mode 100644 index 000000000000..4dadfb7f78de --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v2.dts @@ -0,0 +1,221 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2024 Fedor Ross <fedor.ross@ifm.com> + */ + +/dts-v1/; + +#include "imx8mn-vhip4-evalboard-common.dtsi" + +/ { + model = "ifm i.MX8MNano VHIP4 Evaluation Board v2"; + compatible = "ifm,imx8mn-vhip4-evalboard-v2", "ifm,imx8mn-vhip4-evalboard", + "ifm,imx8mn-vhip4", "fsl,imx8mn"; + + multi-led { + compatible = "leds-group-multicolor"; + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_INDICATOR; + leds = <&rgb_0>, <&rgb_1>, <&rgb_2>; + }; +}; + +&ifm_led { + pinctrl-1 = <&pinctrl_gpio_led_v2>; + + rgb_0: rgb-led-red { + color = <LED_COLOR_ID_RED>; + gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + + rgb_1: rgb-led-green { + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + + rgb_2: rgb-led-blue { + color = <LED_COLOR_ID_BLUE>; + gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; +}; + +&ecspi1 { + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, <&gpio1 11 GPIO_ACTIVE_LOW>; + status = "okay"; + + eeprom@0 { + compatible = "fujitsu,mb85rs64", "atmel,at25"; + reg = <0>; + spi-max-frequency = <20000000>; + spi-cpha; + spi-cpol; + pagesize = <1>; + size = <32768>; + address-width = <16>; + }; +}; + +&ecspi3 { + cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; + status = "okay"; + + can0: can@0 { + compatible = "microchip,mcp2518fd"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcp2518>; + reg = <0>; + clocks = <&can_clk40m>; + interrupt-parent = <&gpio1>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + microchip,rx-int-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + spi-max-frequency = <20000000>; + }; +}; + +&i2c1 { + scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; + status = "okay"; + + temperature-sensor@48 { + compatible = "ti,tmp1075"; + reg = <0x48>; + }; + + eeprom@54 { + compatible = "atmel,24c128"; + reg = <0x54>; + }; +}; + +&i2c3 { + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&ifm_pmic { + interrupt-parent = <&gpio5>; + interrupts = <17 GPIO_ACTIVE_LOW>; +}; + +&iomuxc { + pinctrl_ecspi1_cs: ecspi1-cs-grp { + fsl,pins = < + /* KS8794 nCS */ + MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x150 + /* Retain memory nCS (FRAM or MRAM) */ + MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x150 + /* RETAIN_nHOLD */ + MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x140 + >; + }; + + pinctrl_ecspi3_cs: ecspi3-cs-grp { + fsl,pins = < + /* MCP2518FD nCS */ + MX8MN_IOMUXC_UART2_TXD_GPIO5_IO25 0x150 + >; + }; + + pinctrl_gpio_led_v2: gpioled-v2-grp { + fsl,pins = < + /* LED_RGB_RED */ + MX8MN_IOMUXC_SD2_DATA2_GPIO2_IO17 0x116 + /* LED_RGB_GREEN */ + MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x116 + /* LED_RGB_BLUE */ + MX8MN_IOMUXC_SD2_WP_GPIO2_IO20 0x116 + >; + }; + + pinctrl_i2c1: i2c1-grp { + fsl,pins = < + MX8MN_IOMUXC_SD1_DATA4_I2C1_SCL 0x40000056 + MX8MN_IOMUXC_SD1_DATA5_I2C1_SDA 0x400000d6 + >; + }; + + pinctrl_i2c1_gpio: i2c1-gpio-grp { + fsl,pins = < + MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x56 + MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0xd6 + /* CFG_EEPROM_WP */ + MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x140 + /* RTC_nIRQ */ + MX8MN_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x116 + /* LOG_EE_WP */ + MX8MN_IOMUXC_SPDIF_TX_GPIO5_IO3 0x140 + >; + }; + + pinctrl_i2c3: i2c3-grp { + fsl,pins = < + MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000056 + MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400000d6 + >; + }; + + pinctrl_i2c3_gpio: i2c3-gpio-grp { + fsl,pins = < + MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x56 + MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0xd6 + >; + }; + + pinctrl_mcp2518: mcp2518-grp { + fsl,pins = < + /* CAN0_CLKO */ + MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x116 + /* CAN0_nINT0 */ + MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x116 + /* CAN0_nINT1 */ + MX8MN_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x116 + /* CAN0_nINT */ + MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x116 + >; + }; + + pinctrl_pmic: pmic-irq-grp { + fsl,pins = < + /* PMIC_nIRQ */ + MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1d6 + >; + }; + + pinctrl_uart3: uart3-grp { + fsl,pins = < + MX8MN_IOMUXC_SD1_DATA6_UART3_DCE_TX 0x142 + MX8MN_IOMUXC_SD1_DATA7_UART3_DCE_RX 0x142 + >; + }; + + pinctrl_wdog: wdog-grp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x64 + >; + }; +}; + +&gpio2 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", + "ifm_device_info_eeprom_wp", + "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio5 { + gpio-line-names = + "", "", "", + "ifm_logging_eeprom_wp", + "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index b98b3d0ddf25..3199bc0966b0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -628,6 +628,11 @@ wakeup-source; status = "disabled"; }; + + snvs_lpgpr: snvs-lpgpr { + compatible = "fsl,imx8mn-snvs-lpgpr", + "fsl,imx7d-snvs-lpgpr"; + }; }; clk: clock-controller@30380000 { diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts index 16078ff60ef0..7e46537a22a0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts @@ -93,6 +93,17 @@ status = "disabled"; }; + reg_pcie0: regulator-pcie { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi>; + regulator-name = "WIFI_BT_RST#"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -190,7 +201,7 @@ &eqos { /* First ethernet */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_eqos>; - phy-handle = <&phy_eqos>; + phy-handle = <&phy_eqos_bcm>; phy-mode = "rgmii-id"; status = "okay"; @@ -200,7 +211,7 @@ #size-cells = <0>; /* Atheros AR8031 PHY */ - phy_eqos: ethernet-phy@0 { + phy_eqos_ath: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; /* @@ -213,6 +224,7 @@ reset-deassert-us = <10000>; qca,keep-pll-enabled; vddio-supply = <&vddio_eqos>; + status = "disabled"; vddio_eqos: vddio-regulator { regulator-name = "VDDIO_EQOS"; @@ -224,13 +236,27 @@ regulator-name = "VDDH_EQOS"; }; }; + + /* Broadcom BCM54213PE PHY */ + phy_eqos_bcm: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + /* + * Dedicated ENET_INT# and ENET_WOL# signals are + * unused, the PHY does not provide cable detect + * interrupt. + */ + reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <10000>; + }; }; }; &fec { /* Second ethernet */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec>; - phy-handle = <&phy_fec>; + phy-handle = <&phy_fec_bcm>; phy-mode = "rgmii-id"; fsl,magic-packet; status = "okay"; @@ -240,7 +266,7 @@ #size-cells = <0>; /* Atheros AR8031 PHY */ - phy_fec: ethernet-phy@0 { + phy_fec_ath: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; /* @@ -253,6 +279,7 @@ reset-deassert-us = <10000>; qca,keep-pll-enabled; vddio-supply = <&vddio_fec>; + status = "disabled"; vddio_fec: vddio-regulator { regulator-name = "VDDIO_FEC"; @@ -264,6 +291,20 @@ regulator-name = "VDDH_FEC"; }; }; + + /* Broadcom BCM54213PE PHY */ + phy_fec_bcm: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + /* + * Dedicated ENET_INT# and ENET_WOL# signals are + * unused, the PHY does not provide cable detect + * interrupt. + */ + reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <10000>; + }; }; }; @@ -378,13 +419,26 @@ self-powered; }; - eeprom: eeprom@50 { + tpm: tpm@2e { + compatible = "st,st33tphf2ei2c", "tcg,tpm-tis-i2c"; + reg = <0x2e>; + }; + + eeprom900: eeprom@50 { /* board rev.900 */ compatible = "atmel,24c32"; reg = <0x50>; pagesize = <32>; + status = "disabled"; + }; + + eeprom902: eeprom@51 { /* board rev.902 */ + compatible = "atmel,24c32"; + reg = <0x51>; + pagesize = <32>; }; rtc: rtc@68 { + #clock-cells = <1>; compatible = "st,m41t62"; reg = <0x68>; pinctrl-names = "default"; @@ -408,6 +462,46 @@ scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; + + gpiolvds: io-expander@20 { + compatible = "nxp,pca9554"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "BL_ENABLE_V", "SEL_BL_12V", + "SEL_PANEL_5V", "SEL_PANEL_12V", + "SEL_BL_PWM", "SEL_BL_EN", + "REVERSE_SCAN_PANEL", "GND_REV903"; + }; + + gpiowifi: io-expander@21 { + compatible = "nxp,pca9554"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "BL_LVDS_ENABLE_3V3", "BL_LVDS_PWM_3V3", + "M2_BT_WAKE_3V3#", "M2_W_DISABLE2_3V3#", + "TFT_PANEL_ENABLE_3V3", "TPM_RESET_3V3#", + "CSI2_PD_3V3", "CSI2_RESET_3V3#"; + + /* BL_LVDS_PWM_3V3 is patch-wired to BL_PWM_3V3 on rev.903 */ + pwm-input-hog { + gpio-hog; + gpios = <1 0>; + input; + line-name = "BL_LVDS_PWM_3V3_HOG"; + }; + }; + + eepromlvds: eeprom@51 { + compatible = "atmel,24c32"; + reg = <0x51>; + pagesize = <32>; + /* Optional EEPROM, disabled by default. */ + status = "disabled"; + }; }; &i2c3 { @@ -521,6 +615,7 @@ pinctrl-0 = <&pinctrl_pcie0>; fsl,max-link-speed = <3>; reset-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_pcie0>; status = "okay"; }; @@ -598,7 +693,17 @@ &uart4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart4>; - status = "disabled"; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "infineon,cyw55572-bt"; + brcm,requires-autobaud-mode; + clocks = <&rtc 0>; + clock-names = "txco"; + max-speed = <921600>; + shutdown-gpios = <&gpiowifi 3 GPIO_ACTIVE_HIGH>; + }; }; &usb3_phy0 { @@ -686,8 +791,6 @@ MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 /* ENET_RST# */ MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x6 - /* ENET_INT# */ - MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000090 >; }; @@ -709,8 +812,6 @@ MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f /* ENET2_RST# */ MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x6 - /* ENET2_INT# */ - MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x40000090 >; }; @@ -754,10 +855,6 @@ /* PG_V_IN_VAR# */ MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x40000000 - /* CSI2_PD_1V8 */ - MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x0 - /* CSI2_RESET_1V8# */ - MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x0 /* DIS_USB_DN1 */ MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x0 @@ -771,8 +868,14 @@ /* GRAPHICS_PRSNT_1V8# */ MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000000 + /* TOUCH_RESET_3V3# */ + MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x2 + /* TOUCH_INT# */ + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x40000140 /* CLK_CCM_CLKO1_3V3 */ MX8MP_IOMUXC_GPIO1_IO14__CCM_CLKO1 0x10 + /* ENET_INT# (rev.900,901) or M2_WDIS_BTIRQ_3V3# (rev.903) */ + MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000092 >; }; @@ -875,12 +978,10 @@ fsl,pins = < /* M2_PCIE_RST# */ MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x2 - /* M2_W_DISABLE1_1V8# */ + /* M2_PCIE_WAKE_1V8# */ MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x2 - /* M2_W_DISABLE2_1V8# */ - MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x2 - /* CLK_M2_32K768 */ - MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x14 + /* M2_UART_WAKE_1V8# */ + MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x40000002 /* M2_PCIE_WAKE# */ MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x40000140 /* M2_PCIE_CLKREQ# */ @@ -974,6 +1075,8 @@ fsl,pins = < MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49 MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49 + MX8MP_IOMUXC_NAND_DATA02__UART4_DCE_CTS 0x149 + MX8MP_IOMUXC_NAND_DATA03__UART4_DCE_RTS 0x149 >; }; @@ -1100,4 +1203,11 @@ MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x26 >; }; + + pinctrl_wifi: wifi-grp { + fsl,pins = < + /* WIFI_BT_RST_3V3# */ + MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x40000090 + >; + }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-edm-g-wb.dts b/arch/arm64/boot/dts/freescale/imx8mp-edm-g-wb.dts index 138f21e257aa..242fa930bd2f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-edm-g-wb.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-edm-g-wb.dts @@ -117,7 +117,7 @@ }; &easrc { - fsl,asrc-rate = <48000>; + fsl,asrc-rate = <48000>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index c6facb2ad9aa..b256be710ea1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -56,6 +56,16 @@ <0x1 0x00000000 0 0xc0000000>; }; + flexcan_phy: can-phy { + compatible = "nxp,tja1048"; + #phy-cells = <1>; + max-bitrate = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan_phy>; + standby-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>, + <&gpio4 27 GPIO_ACTIVE_LOW>; + }; + native-hdmi-connector { compatible = "hdmi-connector"; label = "HDMI OUT"; @@ -74,6 +84,27 @@ clock-frequency = <100000000>; }; + reg_1v5: regulator-1v5 { + compatible = "regulator-fixed"; + regulator-name = "1v5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_2v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "2v8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + reg_audio_3v3: regulator-audio-3v3 { compatible = "regulator-fixed"; regulator-name = "audio-3v3"; @@ -103,28 +134,6 @@ enable-active-high; }; - reg_can1_stby: regulator-can1-stby { - compatible = "regulator-fixed"; - regulator-name = "can1-stby"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1_reg>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_can2_stby: regulator-can2-stby { - compatible = "regulator-fixed"; - regulator-name = "can2-stby"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2_reg>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - reg_pcie0: regulator-pcie { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -431,14 +440,14 @@ &flexcan1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_can1_stby>; + phys = <&flexcan_phy 0>; status = "okay"; }; &flexcan2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_can2_stby>; + phys = <&flexcan_phy 1>; status = "disabled";/* can2 pin conflict with pdm */ }; @@ -560,6 +569,30 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; + camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>, <&pinctrl_csi_mclk>; + clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + clock-names = "xclk"; + assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + assigned-clock-rates = <24000000>; + powerdown-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; + AVDD-supply = <®_2v8>; + DVDD-supply = <®_1v5>; + DOVDD-supply = <®_1v8>; + status = "okay"; + + port { + ov5640_mipi_0_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + data-lanes = <1 2>; + }; + }; + }; + hdmi@3d { compatible = "adi,adv7535"; reg = <0x3d>; @@ -664,6 +697,10 @@ */ }; +&isi_0 { + status = "okay"; +}; + &lcdif1 { status = "okay"; }; @@ -682,6 +719,19 @@ status = "okay"; }; +&mipi_csi_0 { + status = "okay"; + + ports { + port@0 { + mipi_csi0_ep: endpoint { + remote-endpoint = <&ov5640_mipi_0_ep>; + data-lanes = <1 2>; + }; + }; + }; +}; + &mipi_dsi { samsung,esc-clock-frequency = <10000000>; status = "okay"; @@ -855,6 +905,24 @@ >; }; + pinctrl_csi_mclk: csi_mclk_grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO15__CCM_CLKO2 0x50 + >; + }; + + pinctrl_csi0_pwn: csi0_pwn_grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x10 + >; + }; + + pinctrl_csi0_rst: csi0_rst_grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x10 + >; + }; + pinctrl_eqos: eqosgrp { fsl,pins = < MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 @@ -909,14 +977,9 @@ >; }; - pinctrl_flexcan1_reg: flexcan1reggrp { + pinctrl_flexcan_phy: flexcanphygrp { fsl,pins = < MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */ - >; - }; - - pinctrl_flexcan2_reg: flexcan2reggrp { - fsl,pins = < MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */ >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-frdm.dts b/arch/arm64/boot/dts/freescale/imx8mp-frdm.dts new file mode 100644 index 000000000000..55690f5e53d7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-frdm.dts @@ -0,0 +1,355 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8mp.dtsi" + +/ { + model = "NXP i.MX8MPlus FRDM board"; + compatible = "fsl,imx8mp-frdm", "fsl,imx8mp"; + + chosen { + stdout-path = &uart2; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-0 { + label = "red"; + gpios = <&pcal6416_0 13 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-1 { + label = "green"; + gpios = <&pcal6416_0 14 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + led-2 { + label = "blue"; + gpios = <&pcal6416_0 15 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0xc0000000>, + <0x1 0x00000000 0 0x40000000>; + }; +}; + +&A53_0 { + cpu-supply = <®_arm>; +}; + +&A53_1 { + cpu-supply = <®_arm>; +}; + +&A53_2 { + cpu-supply = <®_arm>; +}; + +&A53_3 { + cpu-supply = <®_arm>; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic@25 { + compatible = "nxp,pca9450c"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + regulators { + BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + reg_arm: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1025000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3600000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_buck5: BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + regulator-boot-on; + regulator-always-on; + }; + + BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <1045000>; + regulator-max-microvolt = <1155000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <1890000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + pcal6416_0: gpio@20 { + compatible = "nxp,pcal6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcal6416_0_int>; + interrupt-parent = <&gpio3>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + gpio-line-names = "CSI1_nRST", + "CSI2_nRST", + "DSI_CTP_RST", + "EXT_PWREN1", + "CAN_STBY", + "EXP_P0_5", + "EXP_P0_6", + "P0_7", + "LVDS0_BLT_EN", + "LVDS1_BLT_EN", + "LVDS0_CTP_RST", + "LVDS1_CTP_RST", + "SPK_PWREN", + "RLED_GPIO", + "GLED_GPIO", + "BLED_GPIO"; + }; + + pcal6416_1: gpio@21 { + compatible = "nxp,pcal6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcal6416_1_int>; + interrupt-parent = <&gpio2>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + gpio-line-names = "P0_0", + "P0_1", + "AUD_nINT", + "RTC_nINTA", + "USB1_SS_SEL", + "USB2_PWR_EN", + "SPI_EXP_SEL", + "P0_7", + "W2_HOST_WAKE_SD_3V3", + "W2_HOST_WAKE_BT_3V3", + "EXP_WIFI_BT_PDN_3V3", + "EXP_BT_RST_3V3", + "W2_RST_IND_3V3", + "SPI_nINT_3V3", + "KEYM_PCIE_nWAKE", + "P1_7"; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MP_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + uart-has-rtscts; + status = "okay"; +}; + +&usdhc3 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&iomuxc { + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0 + >; + }; + + pinctrl_pcal6416_0_int: pcal6416-0-int-grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x146 + >; + }; + + pinctrl_pcal6416_1_int: pcal6416-1-int-grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x146 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 + MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 + MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140 + MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-common.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-common.dtsi index 825ad6a2ba14..fa7cb9759d01 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-common.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-common.dtsi @@ -141,7 +141,7 @@ }; &i2c3 { - carrier_eeprom: eeprom@57{ + carrier_eeprom: eeprom@57 { compatible = "st,24c02", "atmel,24c02"; reg = <0x57>; pagesize = <16>; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtso b/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtso index 1dcf249ca90d..02889d691c01 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtso +++ b/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtso @@ -34,7 +34,7 @@ status = "okay"; }; -&panel0_lvds { +&panel_lvds0 { compatible = "edt,etml1010g3dra"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-peb-av-10.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-peb-av-10.dtsi new file mode 100644 index 000000000000..57bbbdd734e7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-peb-av-10.dtsi @@ -0,0 +1,196 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clock/imx8mp-clock.h> +#include "imx8mp-pinfunc.h" + +&{/} { + + backlight_lvds1: backlight-lvds1 { + compatible = "pwm-backlight"; + pinctrl-0 = <&pinctrl_lvds1>; + pinctrl-names = "default"; + power-supply = <®_vcc_12v>; + status = "disabled"; + }; + + panel_lvds1: panel-lvds1 { + backlight = <&backlight_lvds1>; + power-supply = <®_vdd_3v3>; + status = "disabled"; + + port { + panel1_in: endpoint { + remote-endpoint = <&ldb_lvds_ch1>; + }; + }; + }; + + reg_vcc_12v: regulator-12v { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <12000000>; + regulator-min-microvolt = <12000000>; + regulator-name = "VCC_12V"; + }; + + reg_vcc_1v8_audio: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "VCC_1V8_Audio"; + }; + + reg_vcc_3v3_analog: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VCC_3V3_Analog"; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "snd-peb-av-10"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,mclk-fs = <32>; + simple-audio-card,widgets = + "Line", "Line In", + "Speaker", "Speaker", + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Speaker", "SPOP", + "Speaker", "SPOM", + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "LINE1L", "Line In", + "LINE1R", "Line In", + "MIC3R", "Microphone Jack", + "Microphone Jack", "Mic Bias"; + + simple-audio-card,codec { + sound-dai = <&codec>; + }; + + dailink_master: simple-audio-card,cpu { + sound-dai = <&sai5>; + }; + }; +}; + +&i2c5 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_i2c5>; + pinctrl-1 = <&pinctrl_i2c5_gpio>; + pinctrl-names = "default", "gpio"; + scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + codec: audio-codec@18 { + compatible = "ti,tlv320aic3007"; + reg = <0x18>; + pinctrl-0 = <&pinctrl_tlv320>; + pinctrl-names = "default"; + #sound-dai-cells = <0>; + ai3x-gpio-func = <0xd 0x0>; + ai3x-micbias-vg = <2>; + AVDD-supply = <®_vcc_3v3_analog>; + DRVDD-supply = <®_vcc_3v3_analog>; + DVDD-supply = <®_vcc_1v8_audio>; + IOVDD-supply = <®_vdd_3v3>; + }; + + eeprom@57 { + compatible = "atmel,24c32"; + reg = <0x57>; + pagesize = <32>; + vcc-supply = <®_vdd_3v3>; + }; +}; + +&ldb_lvds_ch1 { + remote-endpoint = <&panel1_in>; +}; + +&pwm2 { + pinctrl-0 = <&pinctrl_pwm2>; + pinctrl-names = "default"; +}; + +&sai5 { + pinctrl-0 = <&pinctrl_sai5>; + pinctrl-names = "default"; + assigned-clocks = <&clk IMX8MP_CLK_SAI5>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12288000>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_IPG>, + <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>, + <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_AUDIO_PLL1_OUT>, + <&clk IMX8MP_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", + "pll11k"; + #sound-dai-cells = <0>; + fsl,sai-mclk-direction-output; + fsl,sai-synchronous-rx; + status = "okay"; +}; + +&iomuxc { + pinctrl_i2c5: i2c5grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXD0__I2C5_SCL 0x400001c2 + MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c2 + >; + }; + + pinctrl_i2c5_gpio: i2c5gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x1e2 + MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x1e2 + >; + }; + + pinctrl_lvds1: lvds1grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x12 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO09__PWM2_OUT 0x12 + >; + }; + + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI5_TX_DATA00 0xd6 + MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI5_RX_DATA00 0xd6 + MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI5_MCLK 0xd6 + MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK 0xd6 + >; + }; + + pinctrl_tlv320: tlv320grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x16 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-peb-av-10.dtso b/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-peb-av-10.dtso new file mode 100644 index 000000000000..803a199dffa3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-peb-av-10.dtso @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +/dts-v1/; +/plugin/; + +#include "imx8mp-libra-rdk-fpsc-lvds-peb-av-10.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-ph128800t006-zhc01.dtso b/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-ph128800t006-zhc01.dtso new file mode 100644 index 000000000000..418c8536e791 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-ph128800t006-zhc01.dtso @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clock/imx8mp-clock.h> + +/dts-v1/; +/plugin/; + +&backlight_lvds0 { + brightness-levels = <0 8 16 32 64 128 255>; + default-brightness-level = <8>; + enable-gpios = <&gpio5 23 GPIO_ACTIVE_LOW>; + num-interpolated-steps = <2>; + pwms = <&pwm1 0 66667 0>; + status = "okay"; +}; + +&lcdif2 { + status = "okay"; +}; + +&lvds_bridge { + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>, <&clk IMX8MP_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; + /* + * The LVDS panel uses 66.5 MHz pixel clock, set IMX8MP_VIDEO_PLL1 to + * 66.5 * 7 = 465.5 MHz so the LDB serializer and LCDIFv3 scanout + * engine can reach accurate pixel clock of exactly 66.5 MHz. + */ + assigned-clock-rates = <0>, <465500000>; + status = "okay"; +}; + +&panel_lvds0 { + compatible = "powertip,ph128800t006-zhc01"; + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc.dts b/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc.dts index 6f3a7b863dca..86b8c5af4153 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc.dts @@ -15,7 +15,7 @@ "phytec,imx8mp-phycore-fpsc", "fsl,imx8mp"; model = "PHYTEC i.MX8MP Libra RDK FPSC"; - backlight_lvds0: backlight0 { + backlight_lvds0: backlight-lvds0 { compatible = "pwm-backlight"; pinctrl-0 = <&pinctrl_lvds0>; pinctrl-names = "default"; @@ -27,7 +27,7 @@ stdout-path = &uart4; }; - panel0_lvds: panel-lvds { + panel_lvds0: panel-lvds0 { /* compatible panel in overlay */ backlight = <&backlight_lvds0>; power-supply = <®_vdd_3v3>; @@ -226,7 +226,7 @@ }; pinctrl_rtc: rtcgrp { fsl,pins = < - MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x1C0 + MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x1c0 >; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-wlbt-05.dtso b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-wlbt-05.dtso new file mode 100644 index 000000000000..0e98f4d94271 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-wlbt-05.dtso @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +#include <dt-bindings/clock/imx8mp-clock.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include "imx8mp-pinfunc.h" + +/dts-v1/; +/plugin/; + +&{/} { + wlbt_clock: clock-32768 { + compatible = "fixed-clock"; + clock-accuracy = <20000>; + clock-frequency = <32768>; + clock-output-names = "WIFIBT_SLOW_CLK"; + #clock-cells = <0>; + }; + + usdhc1_pwrseq: pwr-seq { + compatible = "mmc-pwrseq-simple"; + post-power-on-delay-ms = <250>; + reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; + }; +}; + +&iomuxc { + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_RESET_B__UART3_DCE_RTS 0x140 /* RTS */ + MX8MP_IOMUXC_SD1_STROBE__UART3_DCE_CTS 0x140 /* CTS */ + MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140 /* RX */ + MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140 /* TX */ + >; + }; + + pinctrl_bluetooth: bluetoothgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x106 /* BT_DEV_WAKE_EXP */ + MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x106 /* BT_REG_ON_EXP */ + MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x106 /* BT_HOST_WAKE_EXP */ + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 /* SDIO_CLK */ + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 /* SDIO_CMD */ + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 /* SDIO_D0 */ + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 /* SDIO_D1 */ + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 /* SDIO_D2 */ + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 /* SDIO_D3 */ + >; + }; + + pinctrl_wifi: wifigrp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x106 /* WL_REG_ON_EXP */ + >; + }; +}; + +&uart3 { + assigned-clocks = <&clk IMX8MP_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + pinctrl-0 = <&pinctrl_uart3>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + pinctrl-0 = <&pinctrl_bluetooth>; + pinctrl-names = "default"; + clock-names = "lpo"; + clocks = <&wlbt_clock>; + device-wakeup-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; + max-speed = <3000000>; + shutdown-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; + vbat-supply = <®_vcc_3v3_sw>; + vddio-supply = <®_vcc_1v8_exp_con>; + }; +}; + +&usdhc1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-names = "default"; + bus-width = <4>; + max-frequency = <50000000>; + mmc-pwrseq = <&usdhc1_pwrseq>; + non-removable; + vmmc-supply = <®_vcc_3v3_sw>; + status = "okay"; + + wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + pinctrl-0 = <&pinctrl_wifi>; + pinctrl-names = "default"; + reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts index 9687b4ded8f4..0fe52c73fc8f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts @@ -31,6 +31,7 @@ compatible = "gpio-fan"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fan>; + fan-supply = <®_vcc_5v_sw>; gpio-fan,speed-map = <0 0 13000 1>; gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; @@ -118,6 +119,13 @@ regulator-max-microvolt = <3300000>; }; + reg_vcc_1v8_exp_con: regulator-vcc-1v8 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "VCC_1V8_EXP_CON"; + }; + thermal-zones { soc-thermal { trips { @@ -227,6 +235,15 @@ }; }; +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + sda-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + &ldb_lvds_ch1 { remote-endpoint = <&panel1_in>; }; @@ -441,6 +458,20 @@ >; }; + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 + >; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x1e2 + MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x1e2 + >; + }; + pinctrl_lvds1: lvds1grp { fsl,pins = < MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x12 @@ -470,7 +501,7 @@ pinctrl_rtc: rtcgrp { fsl,pins = < - MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1C0 + MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1c0 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi index 88831c0fbb7b..63adb1c4b3eb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi @@ -28,6 +28,13 @@ regulator-min-microvolt = <3300000>; regulator-name = "VDD_IO"; }; + + reg_vdd_1v8: regulator-vdd-1v8 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "VDD_1V8"; + }; }; &A53_0 { @@ -83,6 +90,7 @@ spi-max-frequency = <80000000>; spi-rx-bus-width = <4>; spi-tx-bus-width = <1>; + vcc-supply = <®_vdd_1v8>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi index 4e6629f940bf..3cdb0bc0ab72 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi @@ -198,7 +198,7 @@ nxp,dvs-standby-voltage = <850000>; }; - buck4: BUCK4{ + buck4: BUCK4 { regulator-name = "BUCK4"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <3400000>; @@ -206,7 +206,7 @@ regulator-always-on; }; - buck5: BUCK5{ + buck5: BUCK5 { regulator-name = "BUCK5"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <3400000>; @@ -264,7 +264,7 @@ }; }; - som_eeprom: eeprom@50{ + som_eeprom: eeprom@50 { compatible = "st,24c01", "atmel,24c01"; reg = <0x50>; pagesize = <16>; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc-dev.dts b/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc-dev.dts index 6f9dcd3a75c8..b31de307093c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc-dev.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc-dev.dts @@ -107,6 +107,10 @@ pinctrl-0 = <&pinctrl_gpio4>, <&pinctrl_gpio6>; }; +&hdmi_pai { + status = "okay"; +}; + &hdmi_pvi { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc.dtsi index bebe19eb360f..0348da385f23 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc.dtsi @@ -1044,7 +1044,7 @@ }; pinctrl_mcu_int: mcuintgrp { - fsl,pins = <MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x1C0>; /* MCU_INT# */ + fsl,pins = <MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x1c0>; /* MCU_INT# */ }; /* SMARC LCD1_BKLT_PWM */ @@ -1096,12 +1096,12 @@ /* SMARC SLEEP# */ pinctrl_sleep: sleepgrp { - fsl,pins = <MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x1C0>; /* SMARC S149 - SLEEP# */ + fsl,pins = <MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x1c0>; /* SMARC S149 - SLEEP# */ }; /* SMARC SMB_ALERT# */ pinctrl_smb_alert: smbalertgrp { - fsl,pins = <MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x1C0>; /* SMARC P1 - SMB_ALERT# */ + fsl,pins = <MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x1c0>; /* SMARC P1 - SMB_ALERT# */ }; /* TPM_CS# */ diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts index f7346b3d35fe..b7f69c92b774 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts @@ -134,7 +134,7 @@ compatible = "shared-dma-pool"; reusable; size = <0 0x38000000>; - alloc-ranges = <0 0x40000000 0 0xB0000000>; + alloc-ranges = <0 0x40000000 0 0xb0000000>; linux,cma-default; }; }; @@ -159,6 +159,17 @@ "Headphone Jack", "HPL", "Headphone Jack", "HPR"; }; + + sound-hdmi { + compatible = "fsl,imx-audio-hdmi"; + model = "audio-hdmi"; + audio-cpu = <&aud2htx>; + hdmi-out; + }; +}; + +&aud2htx { + status = "okay"; }; &ecspi3 { @@ -190,7 +201,7 @@ reset-deassert-us = <50000>; enet-phy-lane-no-swap; interrupt-parent = <&gpio4>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; @@ -222,7 +233,7 @@ reset-deassert-us = <50000>; enet-phy-lane-no-swap; interrupt-parent = <&gpio4>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; @@ -335,6 +346,10 @@ status = "disabled"; }; +&hdmi_pai { + status = "okay"; +}; + &hdmi_pvi { status = "okay"; }; @@ -704,7 +719,7 @@ fsl,pins = <MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c2>, <MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c2>, <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000010>, - <MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000154>; + <MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000030>; }; pinctrl_gpt1: gpt1grp { diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts index 59642a8a2c44..ad49bf85a04d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts @@ -1,7 +1,8 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2021-2022 TQ-Systems GmbH - * Author: Alexander Stein <alexander.stein@tq-group.com> + * Copyright 2021-2025 TQ-Systems GmbH <linux@ew.tq-group.com>, + * D-82229 Seefeld, Germany. + * Author: Alexander Stein */ /dts-v1/; @@ -227,7 +228,7 @@ compatible = "shared-dma-pool"; reusable; size = <0 0x38000000>; - alloc-ranges = <0 0x40000000 0 0xB0000000>; + alloc-ranges = <0 0x40000000 0 0xb0000000>; linux,cma-default; }; }; @@ -247,6 +248,13 @@ "Line Out Jack", "LOR"; }; + sound-hdmi { + compatible = "fsl,imx-audio-hdmi"; + model = "audio-hdmi"; + audio-cpu = <&aud2htx>; + hdmi-out; + }; + thermal-zones { soc-thermal { trips { @@ -289,6 +297,10 @@ }; }; +&aud2htx { + status = "okay"; +}; + &ecspi1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; @@ -344,7 +356,7 @@ reset-deassert-us = <50000>; enet-phy-lane-no-swap; interrupt-parent = <&gpio4>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; }; }; }; @@ -374,7 +386,7 @@ reset-deassert-us = <50000>; enet-phy-lane-no-swap; interrupt-parent = <&gpio4>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; }; }; }; @@ -485,6 +497,10 @@ "", "", "", ""; }; +&hdmi_pai { + status = "okay"; +}; + &hdmi_pvi { status = "okay"; }; @@ -791,7 +807,8 @@ <MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x12>, <MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x12>, <MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x12>, - <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x14>; + <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x14>, + <MX8MP_IOMUXC_SAI2_RXD0__ENET_QOS_1588_EVENT2_OUT 0x16>; }; pinctrl_eqos_event: eqosevtgrp { @@ -867,7 +884,7 @@ fsl,pins = <MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c2>, <MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c2>, <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000010>, - <MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000010>; + <MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000030>; }; pinctrl_hoggpio2: hoggpio2grp { diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts index 36d3eb865202..291f65e36865 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts @@ -8,4 +8,149 @@ / { model = "Variscite VAR-SOM-MX8M-PLUS on Symphony-Board"; compatible = "variscite,var-som-mx8mp-symphony", "variscite,var-som-mx8mp", "fsl,imx8mp"; + + chosen { + stdout-path = &uart2; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-0 { + function = LED_FUNCTION_POWER; + gpios = <&pca9534 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; + + reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { + compatible = "regulator-gpio"; + regulator-name = "VSD_VSEL"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; + states = <3300000 0x0 1800000 0x1>; + vin-supply = <&ldo5>; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + /* GPIO expander */ + pca9534: gpio@20 { + compatible = "nxp,pca9534"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pca9534>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = <15 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + + usb3-sata-sel-hog { + gpio-hog; + gpios = <4 0>; + output-low; + line-name = "usb3_sata_sel"; + }; + }; +}; + +/* Console */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +/* SD-card */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + vqmmc-supply = <®_usdhc2_vqmmc>; + bus-width = <4>; + status = "okay"; +}; + +&iomuxc { + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 + >; + }; + + pinctrl_pca9534: pca9534grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0xc0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x40 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x40 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2-gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x1c4 + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10 + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0xc0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + >; + }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi index 29f080904482..49467b48d0b0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi @@ -15,45 +15,26 @@ / { model = "Variscite VAR-SOM-MX8M Plus module"; - chosen { - stdout-path = &uart2; - }; - - gpio-leds { - compatible = "gpio-leds"; - - led-0 { - function = LED_FUNCTION_POWER; - gpios = <&pca9534 0 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - memory@40000000 { device_type = "memory"; reg = <0x0 0x40000000 0 0xc0000000>, <0x1 0x00000000 0 0xc0000000>; }; - reg_usdhc2_vmmc: regulator-usdhc2-vmmc { - compatible = "regulator-fixed"; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - startup-delay-us = <100>; - off-on-delay-us = <12000>; + iw61x_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + post-power-on-delay-ms = <100>; + power-off-delay-us = <10000>; + reset-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>, /* WIFI_RESET */ + <&gpio2 19 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */ }; - reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { - compatible = "regulator-gpio"; - regulator-name = "VSD_VSEL"; - regulator-min-microvolt = <1800000>; + reg_audio_supply: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "wm8904-supply"; + regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; - states = <3300000 0x0 1800000 0x1>; - vin-supply = <&ldo5>; + regulator-always-on; }; reg_phy_supply: regulator-phy-supply { @@ -73,6 +54,34 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "wm8904-audio"; + simple-audio-card,routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "IN1L", "Microphone Jack", + "IN1R", "Microphone Jack"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + + codec_dai: simple-audio-card,codec { + sound-dai = <&wm8904>; + }; + + simple-audio-card,cpu { + sound-dai = <&sai3>; + }; + }; }; &A53_0 { @@ -91,6 +100,37 @@ cpu-supply = <&buck2>; }; +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; + status = "okay"; + + /* Resistive touch controller */ + tsc2046: touchscreen@0 { + compatible = "ti,tsc2046"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_restouch>; + interrupt-parent = <&gpio1>; + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; + spi-max-frequency = <1500000>; + pendown-gpio = <&gpio1 12 GPIO_ACTIVE_LOW>; + ti,x-min = /bits/ 16 <125>; + ti,x-max = /bits/ 16 <4008>; + ti,y-min = /bits/ 16 <282>; + ti,y-max = /bits/ 16 <3864>; + ti,x-plate-ohms = /bits/ 16 <180>; + ti,pressure-max = /bits/ 16 <255>; + ti,debounce-max = /bits/ 16 <10>; + ti,debounce-tol = /bits/ 16 <3>; + ti,debounce-rep = /bits/ 16 <1>; + ti,settle-delay-usec = /bits/ 16 <150>; + ti,keep-vref-on; + wakeup-source; + }; +}; + &eqos { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_eqos>; @@ -235,53 +275,79 @@ }; }; }; -}; -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - /* GPIO expander */ - pca9534: gpio@20 { - compatible = "nxp,pca9534"; - reg = <0x20>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pca9534>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gpio1>; - interrupts = <15 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - - usb3-sata-sel-hog { - gpio-hog; - gpios = <4 0>; - output-low; - line-name = "usb3_sata_sel"; - }; + wm8904: audio-codec@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + #sound-dai-cells = <0>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>; + clock-names = "mclk"; + AVDD-supply = <®_audio_supply>; + CPVDD-supply = <®_audio_supply>; + DBVDD-supply = <®_audio_supply>; + DCVDD-supply = <®_audio_supply>; + MICVDD-supply = <®_audio_supply>; + wlf,drc-cfg-names = "default", "peaklimiter", "tradition", + "soft", "music"; + /* + * Config registers per name, respectively: + * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1 + * KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1 + * KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1 + * KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1 + * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1 + */ + wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>, + /bits/ 16 <0x04af 0x324b 0x0010 0x0408>, + /bits/ 16 <0x04af 0x324b 0x0028 0x0704>, + /bits/ 16 <0x04af 0x324b 0x0018 0x078c>, + /bits/ 16 <0x04af 0x324b 0x0010 0x050e>; + /* GPIO1 = DMIC_CLK, don't touch others */ + wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>; }; }; -/* Console */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MP_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <11536000>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, + <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, + <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + fsl,sai-mclk-direction-output; + status = "okay"; }; -/* SD-card */ -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_usdhc2_vmmc>; - vqmmc-supply = <®_usdhc2_vqmmc>; - bus-width = <4>; - status = "okay"; +/* BT */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_bluetooth>; + assigned-clocks = <&clk IMX8MP_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +/* WIFI */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wifi>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wifi>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wifi>; + bus-width = <4>; + non-removable; + keep-power-in-suspend; + mmc-pwrseq = <&iw61x_pwrseq>; + status = "okay"; }; /* eMMC */ @@ -304,6 +370,23 @@ &iomuxc { + pinctrl_bluetooth: bluetoothgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0xc0 + MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 0xc0 + MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0xc0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__ECSPI1_SCLK 0x12 + MX8MP_IOMUXC_I2C1_SDA__ECSPI1_MOSI 0x12 + MX8MP_IOMUXC_I2C2_SCL__ECSPI1_MISO 0x12 + MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x12 + >; + }; + pinctrl_eqos: eqosgrp { fsl,pins = < MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 @@ -332,71 +415,70 @@ >; }; - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 - MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 - >; - }; - - pinctrl_pca9534: pca9534grp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0xc0 - >; - }; - pinctrl_pmic: pmicgrp { fsl,pins = < MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x1c0 >; }; - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x40 - MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x40 + pinctrl_restouch: restouchgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0xc0 >; }; - pinctrl_usdhc2_gpio: usdhc2-gpiogrp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x1c4 - MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10 - MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0xc0 - >; + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 + MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 + MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 + MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_SYNC 0xd6 + MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI3_RX_BCLK 0xd6 + >; }; - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 - >; + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 + MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 + MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140 + MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140 + >; }; - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 - >; + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 + >; }; - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 - >; + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 + >; }; pinctrl_usdhc3: usdhc3grp { @@ -452,4 +534,11 @@ MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 >; }; + + pinctrl_wifi: wifigrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0xc0 + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0xc0 + >; + }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi index 4bf818873fe3..9317e62304e3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi @@ -101,6 +101,15 @@ interrupt-parent = <&gpio4>; interrupts = <21 IRQ_TYPE_LEVEL_LOW>; }; + + magnetometer@1e { + compatible = "st,lis2mdl"; + reg = <0x1e>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mag>; + interrupt-parent = <&gpio4>; + interrupts = <25 IRQ_TYPE_LEVEL_LOW>; + }; }; &pcie_phy { @@ -198,6 +207,12 @@ >; }; + pinctrl_mag: maggrp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x150 /* IRQ */ + >; + }; + pinctrl_gpio_leds: gpioledgrp { fsl,pins = < MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x6 /* LEDG */ diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi index 1493319aa748..0e218e6b8e29 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi @@ -112,6 +112,10 @@ }; /* Verdin HDMI_1 */ +&hdmi_pai { + status = "okay"; +}; + &hdmi_pvi { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi index a38e7c947a42..72a4f846d694 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi @@ -121,6 +121,10 @@ }; /* Verdin HDMI_1 */ +&hdmi_pai { + status = "okay"; +}; + &hdmi_pvi { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-mallow.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-mallow.dtsi index 11cf3bdc95c4..846b36706821 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-mallow.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-mallow.dtsi @@ -109,6 +109,10 @@ }; /* Verdin HDMI_1 */ +&hdmi_pai { + status = "okay"; +}; + &hdmi_pvi { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi index cc389cda2af2..f3d28e23ba6c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi @@ -123,6 +123,10 @@ }; /* Verdin HDMI_1 */ +&hdmi_pai { + status = "okay"; +}; + &hdmi_pvi { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi index d43ba0087126..d31f8082394f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi @@ -832,10 +832,6 @@ #pwm-cells = <3>; }; -/* TODO: Verdin I2S_1 */ - -/* TODO: Verdin I2S_2 */ - &snvs_pwrkey { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts index d9f203c79519..aadaeef928bd 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts @@ -633,7 +633,7 @@ pinctrl_hpdet: hpdetgrp { fsl,pins = < - MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0xC0 /* HP_DET */ + MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0xc0 /* HP_DET */ >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 9e0e2d7271ef..eee390c27210 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -17,6 +17,11 @@ compatible = "purism,librem5", "fsl,imx8mq"; chassis-type = "handset"; + aliases { + rtc0 = &rtc; + rtc1 = &snvs_rtc; + }; + backlight_dsi: backlight-dsi { compatible = "led-backlight"; leds = <&led_backlight>; @@ -287,7 +292,7 @@ vibrator { compatible = "pwm-vibrator"; - pwms = <&pwm1 0 1000000000 0>; + pwms = <&pwm1 0 50000 0>; pwm-names = "enable"; vcc-supply = <®_vdd_3v3>; }; @@ -512,6 +517,13 @@ >; }; + pinctrl_i2c1_gpio: i2c1-gpiogrp { + fsl,pins = < + MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14 0x26 + MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15 0x26 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000026 @@ -519,6 +531,13 @@ >; }; + pinctrl_i2c2_gpio: i2c2-gpiogrp { + fsl,pins = < + MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16 0x26 + MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17 0x26 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000026 @@ -526,6 +545,13 @@ >; }; + pinctrl_i2c3_gpio: i2c3-gpiogrp { + fsl,pins = < + MX8MQ_IOMUXC_I2C3_SCL_GPIO5_IO18 0x26 + MX8MQ_IOMUXC_I2C3_SDA_GPIO5_IO19 0x26 + >; + }; + pinctrl_i2c4: i2c4grp { fsl,pins = < MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000026 @@ -533,12 +559,19 @@ >; }; + pinctrl_i2c4_gpio: i2c4-gpiogrp { + fsl,pins = < + MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20 0x26 + MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21 0x26 + >; + }; + pinctrl_keys: keysgrp { fsl,pins = < /* VOL- */ - MX8MQ_IOMUXC_ENET_MDIO_GPIO1_IO17 0x01C0 + MX8MQ_IOMUXC_ENET_MDIO_GPIO1_IO17 0x01c0 /* VOL+ */ - MX8MQ_IOMUXC_ENET_MDC_GPIO1_IO16 0x01C0 + MX8MQ_IOMUXC_ENET_MDC_GPIO1_IO16 0x01c0 >; }; @@ -620,7 +653,7 @@ pinctrl_tcpc: tcpcgrp { fsl,pins = < /* TCPC_INT */ - MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x01C0 + MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x01c0 >; }; @@ -782,8 +815,11 @@ &i2c1 { clock-frequency = <384000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; typec_pd: usb-pd@3f { @@ -970,7 +1006,7 @@ }; }; - rtc@68 { + rtc: rtc@68 { compatible = "microcrystal,rv4162"; reg = <0x68>; pinctrl-names = "default"; @@ -982,8 +1018,11 @@ &i2c2 { clock-frequency = <384000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; magnetometer: magnetometer@1e { @@ -1031,8 +1070,11 @@ &i2c3 { clock-frequency = <384000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; codec: audio-codec@1a { @@ -1043,7 +1085,6 @@ assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; assigned-clock-rates = <24576000>; #sound-dai-cells = <0>; - mic-cfg = <0x200>; DCVDD-supply = <®_aud_1v8>; DBVDD-supply = <®_aud_1v8>; AVDD-supply = <®_aud_1v8>; @@ -1121,8 +1162,11 @@ &i2c4 { clock-frequency = <384000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; vcm@c { @@ -1276,10 +1320,6 @@ status = "okay"; }; -&snvs_rtc { - status = "disabled"; -}; - &uart1 { /* console */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; @@ -1383,7 +1423,7 @@ &usdhc2 { assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; - assigned-clock-rates = <200000000>; + assigned-clock-rates = <50000000>; pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2>; pinctrl-1 = <&pinctrl_usdhc2_100mhz>; @@ -1393,9 +1433,10 @@ mmc-pwrseq = <&usdhc2_pwrseq>; post-power-on-delay-ms = <20>; cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - max-frequency = <100000000>; + max-frequency = <50000000>; disable-wp; cap-sdio-irq; + cap-power-off-card; keep-power-in-suspend; wakeup-source; status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts index f1b0563d3a09..dadc136aec6e 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts @@ -1215,17 +1215,17 @@ pinctrl_mipi_csi0: mipi-csi0grp { fsl,pins = < - IMX8QM_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27 0xC0000041 - IMX8QM_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28 0xC0000041 - IMX8QM_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT 0xC0000041 + IMX8QM_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27 0xc0000041 + IMX8QM_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28 0xc0000041 + IMX8QM_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT 0xc0000041 >; }; pinctrl_mipi_csi1: mipi-csi1grp { fsl,pins = < - IMX8QM_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30 0xC0000041 - IMX8QM_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31 0xC0000041 - IMX8QM_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT 0xC0000041 + IMX8QM_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30 0xc0000041 + IMX8QM_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31 0xc0000041 + IMX8QM_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT 0xc0000041 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-ddr.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-ddr.dtsi new file mode 100644 index 000000000000..c831567cfbc1 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-ddr.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 NXP + * Dong Aisheng <aisheng.dong@nxp.com> + */ + +&ddr_pmu0 { + compatible = "fsl,imx8qm-ddr-pmu", "fsl,imx8-ddr-pmu"; + interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; +}; + +&ddr_subsys { + ddr_pmu1: ddr-pmu@5c120000 { + compatible = "fsl,imx8qm-ddr-pmu", "fsl,imx8-ddr-pmu"; + reg = <0x5c120000 0x10000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi index cb66853b1cd3..ae7de9f99055 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi @@ -38,7 +38,7 @@ #size-cells = <0>; cpu-map { - cluster0 { + cluster0: cluster0 { core0 { cpu = <&A53_0>; }; @@ -53,7 +53,7 @@ }; }; - cluster1 { + cluster1: cluster1 { core0 { cpu = <&A72_0>; }; @@ -137,7 +137,7 @@ reg = <0x0 0x100>; clocks = <&clk IMX_SC_R_A72 IMX_SC_PM_CLK_CPU>; enable-method = "psci"; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <256>; d-cache-size = <0x8000>; @@ -241,7 +241,7 @@ gic: interrupt-controller@51a00000 { compatible = "arm,gic-v3"; reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ - <0x0 0x51b00000 0 0xC0000>, /* GICR */ + <0x0 0x51b00000 0 0xc0000>, /* GICR */ <0x0 0x52000000 0 0x2000>, /* GICC */ <0x0 0x52010000 0 0x1000>, /* GICH */ <0x0 0x52020000 0 0x20000>; /* GICV */ @@ -635,6 +635,7 @@ #include "imx8-ss-img.dtsi" #include "imx8-ss-dma.dtsi" #include "imx8-ss-conn.dtsi" + #include "imx8-ss-ddr.dtsi" #include "imx8-ss-lsio.dtsi" #include "imx8-ss-hsio.dtsi" }; @@ -647,5 +648,6 @@ #include "imx8qm-ss-lvds.dtsi" #include "imx8qm-ss-mipi.dtsi" #include "imx8qm-ss-hsio.dtsi" +#include "imx8qm-ss-ddr.dtsi" /delete-node/ &dsp; diff --git a/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-eval-v1.2.dts b/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-eval-v1.2.dts new file mode 100644 index 000000000000..b5318de67cb0 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-eval-v1.2.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2024 Toradex + */ + +/dts-v1/; + +#include "imx8qp-apalis-v1.1.dtsi" +#include "imx8-apalis-eval-v1.2.dtsi" + +/ { + model = "Toradex Apalis iMX8QP V1.1 on Apalis Evaluation Board V1.2"; + compatible = "toradex,apalis-imx8-v1.1-eval-v1.2", + "toradex,apalis-imx8-v1.1", + "fsl,imx8qp"; +}; + +/* Apalis MMC1 */ +&usdhc2 { + /delete-property/ no-1-8-v; +}; + +/* Apalis SD1 */ +&usdhc3 { + /delete-property/ no-1-8-v; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-eval.dts b/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-eval.dts new file mode 100644 index 000000000000..d558cff2582f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-eval.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx8qp-apalis-v1.1.dtsi" +#include "imx8-apalis-eval-v1.1.dtsi" + +/ { + model = "Toradex Apalis iMX8QP V1.1 on Apalis Evaluation Board"; + compatible = "toradex,apalis-imx8-v1.1-eval", + "toradex,apalis-imx8-v1.1", + "fsl,imx8qp"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-ixora-v1.1.dts b/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-ixora-v1.1.dts new file mode 100644 index 000000000000..a73a6324f552 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-ixora-v1.1.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx8qp-apalis-v1.1.dtsi" +#include "imx8-apalis-ixora-v1.1.dtsi" + +/ { + model = "Toradex Apalis iMX8QP V1.1 on Apalis Ixora V1.1 Carrier Board"; + compatible = "toradex,apalis-imx8-v1.1-ixora-v1.1", + "toradex,apalis-imx8-v1.1", + "fsl,imx8qp"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-ixora-v1.2.dts b/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-ixora-v1.2.dts new file mode 100644 index 000000000000..71568d7ec8e5 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-ixora-v1.2.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx8qp-apalis-v1.1.dtsi" +#include "imx8-apalis-ixora-v1.2.dtsi" + +/ { + model = "Toradex Apalis iMX8QP V1.1 on Apalis Ixora V1.2 Carrier Board"; + compatible = "toradex,apalis-imx8-v1.1-ixora-v1.2", + "toradex,apalis-imx8-v1.1", + "fsl,imx8qp"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1.dtsi b/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1.dtsi new file mode 100644 index 000000000000..1e5311512344 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +#include "imx8qp.dtsi" +#include "imx8-apalis-v1.1.dtsi" + +&cooling_maps_map0 { + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qp.dtsi b/arch/arm64/boot/dts/freescale/imx8qp.dtsi new file mode 100644 index 000000000000..26af9c5a51c5 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qp.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) + +#include "imx8qm.dtsi" + +/delete-node/ &A72_1; + +&cluster1 { + /delete-node/ core1; +}; + +&gpu_3d0 { + assigned-clock-rates = <625000000>, <625000000>; +}; + +&thermal_zones { + cpu1-thermal { + cooling-maps { + map0 { + cooling-device = + <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts index 523f48896b6b..40a0bc9f4e84 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -485,12 +485,38 @@ #size-cells = <0>; reg = <2>; + accelerometer@1e { + compatible = "nxp,fxos8700"; + reg = <0x1e>; + }; + + gyroscope@21 { + compatible = "nxp,fxas21002c"; + reg = <0x21>; + }; + pressure-sensor@60 { compatible = "fsl,mpl3115"; reg = <0x60>; vdd-supply = <®_3v3>; vddio-supply = <®_3v3>; }; + + /* Ref SCH-54536 */ + inertial-meter@68 { + compatible = "invensense,icm20602"; + reg = <0x68>; + }; + + inertial-meter@69 { + compatible = "invensense,iam20380"; + reg = <0x69>; + }; + + pressure-sensor@77 { + compatible = "meas,ms5611"; + reg = <0x77>; + }; }; i2c@3 { @@ -520,6 +546,12 @@ interrupt-parent = <&lsio_gpio1>; interrupts = <2 IRQ_TYPE_EDGE_FALLING>; }; + + /* Ref SCH-54536 */ + light-sensort@60 { + compatible = "vishay,vcnl4035"; + reg = <0x60>; + }; }; }; @@ -1030,9 +1062,9 @@ pinctrl_mipi_csi0: mipi-csi0grp { fsl,pins = < - IMX8QXP_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 0xC0000041 - IMX8QXP_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 0xC0000041 - IMX8QXP_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT 0xC0000041 + IMX8QXP_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 0xc0000041 + IMX8QXP_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 0xc0000041 + IMX8QXP_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT 0xc0000041 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi index 13b01f3aa2a4..9b5d98766512 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -776,6 +776,23 @@ "ch28", "ch29", "ch30", "ch31"; }; + sim_lpav: clock-controller@2da50000 { + compatible = "fsl,imx8ulp-sim-lpav"; + reg = <0x2da50000 0x10000>; + clocks = <&cgc2 IMX8ULP_CLK_LPAV_BUS_DIV>, + <&cgc2 IMX8ULP_CLK_HIFI_DIVCORE>, + <&cgc2 IMX8ULP_CLK_HIFI_DIVPLAT>; + clock-names = "bus", "core", "plat"; + #clock-cells = <1>; + #reset-cells = <1>; + + sim_lpav_mux: mux-controller { + compatible = "reg-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x8 0x00000200>; + }; + }; + cgc2: clock-controller@2da60000 { compatible = "fsl,imx8ulp-cgc2"; reg = <0x2da60000 0x10000>; diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi index 8e9e841cc828..47895ff8cb24 100644 --- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi @@ -3,7 +3,21 @@ * Copyright 2019 Toradex */ +#include "dt-bindings/pwm/pwm.h" + / { + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_bl_on>; + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + enable-gpios = <&lsio_gpio3 12 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */ + power-supply = <®_module_3v3>; + pwms = <&adma_pwm 0 6666667 PWM_POLARITY_INVERTED>; + status = "disabled"; + }; + chosen { stdout-path = &lpuart3; }; @@ -72,6 +86,19 @@ regulator-name = "usbh_vbus"; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + linux,cma-default; + reusable; + size = <0 0x1a000000>; + }; + }; + sound-card { compatible = "simple-audio-card"; simple-audio-card,bitclock-master = <&dailink_master>; @@ -476,7 +503,7 @@ /* On-module PCIe for Wi-Fi */ &pcieb { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcieb>; + pinctrl-0 = <&pinctrl_pcieb>, <&pinctrl_wifi>; phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; phy-names = "pcie-phy"; reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; @@ -623,7 +650,7 @@ }; pinctrl_csi_mclk: csimclkgrp { - fsl,pins = <IMX8QXP_CSI_MCLK_CI_PI_MCLK 0xC0000041>; /* SODIMM 75 / X3-12 */ + fsl,pins = <IMX8QXP_CSI_MCLK_CI_PI_MCLK 0xc0000041>; /* SODIMM 75 / X3-12 */ }; pinctrl_ext_io0: extio0grp { diff --git a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts index aca78768dbd4..03f460d62f7a 100644 --- a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts @@ -31,6 +31,11 @@ serial4 = &lpuart5; }; + bt_sco_codec: bt-sco-codec { + compatible = "linux,bt-sco"; + #sound-dai-cells = <1>; + }; + chosen { stdout-path = &lpuart1; }; @@ -77,6 +82,68 @@ linux,cma-default; }; }; + + sound-wm8962 { + compatible = "fsl,imx-audio-wm8962"; + model = "wm8962-audio"; + audio-cpu = <&sai3>; + audio-codec = <&wm8962>; + hp-det-gpio = <&pcal6524 4 GPIO_ACTIVE_HIGH>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "AMIC", "MICBIAS", + "IN3R", "AMIC", + "IN1R", "AMIC"; + }; + + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + simple-audio-card,codec { + sound-dai = <&bt_sco_codec 1>; + }; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + }; + + sound-micfil { + compatible = "fsl,imx-audio-card"; + model = "micfil-audio"; + + pri-dai-link { + link-name = "micfil hifi"; + format = "i2s"; + + cpu { + sound-dai = <&micfil>; + }; + }; + }; + + sound-xcvr { + compatible = "fsl,imx-audio-card"; + model = "imx-audio-xcvr"; + + pri-dai-link { + link-name = "XCVR PCM"; + + cpu { + sound-dai = <&xcvr>; + }; + }; + }; }; &adc1 { @@ -132,7 +199,7 @@ pinctrl-names = "default"; status = "okay"; - audio_codec: wm8962@1a { + wm8962: audio-codec@1a { compatible = "wlf,wm8962"; reg = <0x1a>; clocks = <&clk IMX93_CLK_SAI3_GATE>; @@ -372,6 +439,38 @@ }; }; +&micfil { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_pdm>; + pinctrl-1 = <&pinctrl_pdm_sleep>; + assigned-clocks = <&clk IMX93_CLK_PDM>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <49152000>; + status = "okay"; +}; + +&sai1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_sai1>; + pinctrl-1 = <&pinctrl_sai1_sleep>; + assigned-clocks = <&clk IMX93_CLK_SAI1>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&sai3 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_sai3>; + pinctrl-1 = <&pinctrl_sai3_sleep>; + assigned-clocks = <&clk IMX93_CLK_SAI3>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + &usbotg1 { adp-disable; disable-over-current; @@ -437,6 +536,18 @@ status = "okay"; }; +&xcvr { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_spdif>; + pinctrl-1 = <&pinctrl_spdif_sleep>; + assigned-clocks = <&clk IMX93_CLK_SPDIF>, + <&clk IMX93_CLK_AUDIO_XCVR>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <12288000>, <200000000>; + status = "okay"; +}; + &iomuxc { pinctrl_eqos: eqosgrp { fsl,pins = < @@ -528,6 +639,74 @@ >; }; + pinctrl_pdm: pdmgrp { + fsl,pins = < + MX91_PAD_PDM_CLK__PDM_CLK 0x31e + MX91_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM0 0x31e + MX91_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM1 0x31e + >; + }; + + pinctrl_pdm_sleep: pdmsleepgrp { + fsl,pins = < + MX91_PAD_PDM_CLK__GPIO1_IO8 0x51e + MX91_PAD_PDM_BIT_STREAM0__GPIO1_IO9 0x51e + MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x51e + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX91_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e + MX91_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e + MX91_PAD_SAI1_TXD0__SAI1_TX_DATA0 0x31e + MX91_PAD_SAI1_RXD0__SAI1_RX_DATA0 0x31e + >; + }; + + pinctrl_sai1_sleep: sai1sleepgrp { + fsl,pins = < + MX91_PAD_SAI1_TXC__GPIO1_IO12 0x51e + MX91_PAD_SAI1_TXFS__GPIO1_IO11 0x51e + MX91_PAD_SAI1_TXD0__GPIO1_IO13 0x51e + MX91_PAD_SAI1_RXD0__GPIO1_IO14 0x51e + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX91_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e + MX91_PAD_GPIO_IO17__SAI3_MCLK 0x31e + MX91_PAD_GPIO_IO19__SAI3_TX_DATA0 0x31e + MX91_PAD_GPIO_IO20__SAI3_RX_DATA0 0x31e + MX91_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e + >; + }; + + pinctrl_sai3_sleep: sai3sleepgrp { + fsl,pins = < + MX91_PAD_GPIO_IO16__GPIO2_IO16 0x51e + MX91_PAD_GPIO_IO17__GPIO2_IO17 0x51e + MX91_PAD_GPIO_IO19__GPIO2_IO19 0x51e + MX91_PAD_GPIO_IO20__GPIO2_IO20 0x51e + MX91_PAD_GPIO_IO26__GPIO2_IO26 0x51e + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX91_PAD_GPIO_IO22__SPDIF_IN 0x31e + MX91_PAD_GPIO_IO23__SPDIF_OUT 0x31e + >; + }; + + pinctrl_spdif_sleep: spdifsleepgrp { + fsl,pins = < + MX91_PAD_GPIO_IO22__GPIO2_IO22 0x51e + MX91_PAD_GPIO_IO23__GPIO2_IO23 0x51e + >; + }; + pinctrl_lpi2c3: lpi2c3grp { fsl,pins = < MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e diff --git a/arch/arm64/boot/dts/freescale/imx91-11x11-frdm.dts b/arch/arm64/boot/dts/freescale/imx91-11x11-frdm.dts new file mode 100644 index 000000000000..c25561574d3f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx91-11x11-frdm.dts @@ -0,0 +1,906 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 NXP + */ + +/dts-v1/; + +#include <dt-bindings/usb/pd.h> +#include "imx91.dtsi" + +/ { + compatible = "fsl,imx91-11x11-frdm", "fsl,imx91"; + model = "NXP i.MX91 11x11 FRDM Board"; + + aliases { + ethernet0 = &fec; + ethernet1 = &eqos; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + rtc0 = &bbnsm_rtc; + rtc1 = &pcf2131; + serial0 = &lpuart1; + serial4 = &lpuart5; + }; + + chosen { + stdout-path = &lpuart1; + }; + + flexcan_phy: can-phy { + compatible = "nxp,tja1051"; + #phy-cells = <0>; + max-bitrate = <5000000>; + silent-gpios = <&pcal6524 23 GPIO_ACTIVE_HIGH>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-k2 { + interrupt-parent = <&pcal6524>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + label = "Button K2"; + gpios = <&pcal6524 5 GPIO_PULL_UP>; + linux,code = <BTN_1>; + }; + + button-k3 { + interrupt-parent = <&pcal6524>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + label = "Button K3"; + gpios = <&pcal6524 6 GPIO_PULL_UP>; + linux,code = <BTN_2>; + }; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vref_1v8"; + }; + + reg_m2_pwr: regulator-m2-pwr { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "M.2-power"; + gpio = <&pcal6524 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + off-on-delay-us = <12000>; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VSD_3V3"; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + bootph-pre-ram; + bootph-some-ram; + }; + + reg_usdhc3_vmmc: regulator-usdhc3 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "WLAN_EN"; + vin-supply = <®_m2_pwr>; + gpio = <&pcal6524 20 GPIO_ACTIVE_HIGH>; + enable-active-high; + /* + * This regulator defined as PDn pin of the IW610 wifi module. + * IW610 wifi chip needs more delay than other wifi chips to complete + * the host interface initialization after power up, otherwise the + * internal state of IW610 may be unstable, resulting in the failure of + * the SDIO3.0 switch voltage. + */ + startup-delay-us = <20000>; + }; + + reg_vdd_12v: regulator-vdd-12v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <12000000>; + regulator-min-microvolt = <12000000>; + regulator-name = "reg_vdd_12v"; + gpio = <&pcal6524 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vexp_3v3: regulator-vexp-3v3 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VEXP_3V3"; + vin-supply = <&buck4>; + gpio = <&pcal6524 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vexp_5v: regulator-vexp-5v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "VEXP_5V"; + gpio = <&pcal6524 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reserved-memory { + ranges; + #address-cells = <2>; + #size-cells = <2>; + + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x80000000 0 0x30000000>; + reusable; + size = <0 0x10000000>; + linux,cma-default; + }; + }; + + soc@0 { + bootph-all; + bootph-pre-ram; + }; + + sound-mqs { + compatible = "fsl,imx6sx-sdb-mqs", + "fsl,imx-audio-mqs"; + audio-codec = <&mqs1>; + audio-cpu = <&sai1>; + model = "mqs-audio"; + }; + + usdhc3_pwrseq: usdhc3-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pcal6524 12 GPIO_ACTIVE_LOW>; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&aips1 { + bootph-pre-ram; + bootph-all; +}; + +&aips2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&aips3 { + bootph-pre-ram; + bootph-some-ram; +}; + +&clk { + bootph-all; + bootph-pre-ram; +}; + +&clk_ext1 { + bootph-all; + bootph-pre-ram; +}; + +&eqos { + phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; + pinctrl-0 = <&pinctrl_eqos>; + pinctrl-1 = <&pinctrl_eqos_sleep>; + pinctrl-names = "default", "sleep"; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy1: ethernet-phy@1 { + reg = <1>; + reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; + reset-assert-us = <15000>; + reset-deassert-us = <100000>; + }; + }; +}; + +&fec { + phy-handle = <ðphy2>; + phy-mode = "rgmii-id"; + pinctrl-0 = <&pinctrl_fec>; + pinctrl-1 = <&pinctrl_fec_sleep>; + pinctrl-names = "default", "sleep"; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy2: ethernet-phy@2 { + reg = <2>; + reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>; + reset-assert-us = <15000>; + reset-deassert-us = <100000>; + }; + }; +}; + +&flexcan2 { + pinctrl-0 = <&pinctrl_flexcan2>; + pinctrl-1 = <&pinctrl_flexcan2_sleep>; + pinctrl-names = "default", "sleep"; + phys = <&flexcan_phy>; + status = "okay"; +}; + +&gpio1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio3 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio4 { + bootph-pre-ram; + bootph-some-ram; +}; + +&lpi2c1 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c1>; + pinctrl-names = "default"; + bootph-pre-ram; + bootph-some-ram; + status = "okay"; + + pcal6408: gpio@20 { + compatible = "nxp,pcal9554b"; + reg = <0x20>; + #gpio-cells = <2>; + gpio-controller; + vcc-supply = <®_usdhc3_vmmc>; + status = "okay"; + }; +}; + +&lpi2c2 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-names = "default"; + bootph-pre-ram; + bootph-some-ram; + status = "okay"; + + pcal6524: gpio@22 { + compatible = "nxp,pcal6524"; + reg = <0x22>; + #interrupt-cells = <2>; + interrupt-controller; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + #gpio-cells = <2>; + gpio-controller; + interrupt-parent = <&gpio3>; + pinctrl-0 = <&pinctrl_pcal6524>; + pinctrl-names = "default"; + }; + + pmic@25 { + compatible = "nxp,pca9451a"; + reg = <0x25>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&pcal6524>; + bootph-pre-ram; + bootph-some-ram; + + regulators { + bootph-pre-ram; + bootph-some-ram; + + buck1: BUCK1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2237500>; + regulator-min-microvolt = <650000>; + regulator-name = "BUCK1"; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2187500>; + regulator-min-microvolt = <600000>; + regulator-name = "BUCK2"; + regulator-ramp-delay = <3125>; + }; + + buck4: BUCK4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <600000>; + regulator-name = "BUCK4"; + }; + + buck5: BUCK5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <600000>; + regulator-name = "BUCK5"; + }; + + buck6: BUCK6 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <600000>; + regulator-name = "BUCK6"; + }; + + ldo1: LDO1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1600000>; + regulator-name = "LDO1"; + }; + + ldo4: LDO4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <800000>; + regulator-name = "LDO4"; + }; + + ldo5: LDO5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-name = "LDO5"; + }; + }; + }; +}; + +&lpi2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-names = "default"; + bootph-pre-ram; + bootph-some-ram; + status = "okay"; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x50>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio3>; + + typec1_con: connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + op-sink-microwatt = <15000000>; + power-role = "dual"; + self-powered; + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) + PDO_VAR(5000, 20000, 3000)>; + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + try-power-role = "sink"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + }; + }; + }; + + pcf2131: rtc@53 { + compatible = "nxp,pcf2131"; + reg = <0x53>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&pcal6524>; + status = "okay"; + }; +}; + +&lpuart1 { + pinctrl-0 = <&pinctrl_uart1>; + pinctrl-names = "default"; + bootph-pre-ram; + bootph-some-ram; + status = "okay"; +}; + +&lpuart5 { + pinctrl-0 = <&pinctrl_uart5>; + pinctrl-names = "default"; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +&mqs1 { + clocks = <&clk IMX93_CLK_MQS1_GATE>; + clock-names = "mclk"; + pinctrl-0 = <&pinctrl_mqs1>; + pinctrl-names = "default"; + status = "okay"; +}; + +&osc_32k { + bootph-all; + bootph-pre-ram; +}; + +&osc_24m { + bootph-all; + bootph-pre-ram; +}; + +&sai1 { + clocks = <&clk IMX93_CLK_SAI1_IPG>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_SAI1_GATE>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_AUDIO_PLL>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k"; + assigned-clocks = <&clk IMX93_CLK_SAI1>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <24576000>; + #sound-dai-cells = <0>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&usbotg1 { + adp-disable; + disable-over-current; + dr_mode = "otg"; + hnp-disable; + srp-disable; + usb-role-switch; + samsung,picophy-dc-vol-level-adjust = <7>; + samsung,picophy-pre-emp-curr-control = <3>; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&usbotg2 { + disable-over-current; + dr_mode = "host"; + samsung,picophy-dc-vol-level-adjust = <7>; + samsung,picophy-pre-emp-curr-control = <3>; + status = "okay"; +}; + +&usdhc1 { + bus-width = <8>; + non-removable; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + bootph-pre-ram; + bootph-some-ram; + status = "okay"; +}; + +&usdhc2 { + bus-width = <4>; + cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; + no-mmc; + no-sdio; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + vmmc-supply = <®_usdhc2_vmmc>; + bootph-pre-ram; + bootph-some-ram; + status = "okay"; +}; + +&usdhc3 { + bus-width = <4>; + keep-power-in-suspend; + mmc-pwrseq = <&usdhc3_pwrseq>; + non-removable; + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_wlan>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_wlan>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_wlan>; + pinctrl-3 = <&pinctrl_usdhc3_sleep>, <&pinctrl_usdhc3_wlan>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + vmmc-supply = <®_usdhc3_vmmc>; + wakeup-source; + status = "okay"; +}; + +&wdog3 { + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + bootph-pre-ram; + bootph-some-ram; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX91_PAD_ENET1_MDC__ENET1_MDC 0x57e + MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e + MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e + MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e + MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x5fe + MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e + MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x57e + MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e + MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e + MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe + MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_eqos_sleep: eqossleepgrp { + fsl,pins = < + MX91_PAD_ENET1_MDC__GPIO4_IO0 0x31e + MX91_PAD_ENET1_MDIO__GPIO4_IO1 0x31e + MX91_PAD_ENET1_RD0__GPIO4_IO10 0x31e + MX91_PAD_ENET1_RD1__GPIO4_IO11 0x31e + MX91_PAD_ENET1_RD2__GPIO4_IO12 0x31e + MX91_PAD_ENET1_RD3__GPIO4_IO13 0x31e + MX91_PAD_ENET1_RXC__GPIO4_IO9 0x31e + MX91_PAD_ENET1_RX_CTL__GPIO4_IO8 0x31e + MX91_PAD_ENET1_TD0__GPIO4_IO5 0x31e + MX91_PAD_ENET1_TD1__GPIO4_IO4 0x31e + MX91_PAD_ENET1_TD2__GPIO4_IO3 0x31e + MX91_PAD_ENET1_TD3__GPIO4_IO2 0x31e + MX91_PAD_ENET1_TXC__GPIO4_IO7 0x31e + MX91_PAD_ENET1_TX_CTL__GPIO4_IO6 0x31e + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX91_PAD_ENET2_MDC__ENET2_MDC 0x57e + MX91_PAD_ENET2_MDIO__ENET2_MDIO 0x57e + MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x57e + MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x57e + MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x57e + MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x57e + MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x5fe + MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x57e + MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x57e + MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x57e + MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x57e + MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x57e + MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x5fe + MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_fec_sleep: fecsleepgrp { + fsl,pins = < + MX91_PAD_ENET2_MDC__GPIO4_IO14 0x51e + MX91_PAD_ENET2_MDIO__GPIO4_IO15 0x51e + MX91_PAD_ENET2_RD0__GPIO4_IO24 0x51e + MX91_PAD_ENET2_RD1__GPIO4_IO25 0x51e + MX91_PAD_ENET2_RD2__GPIO4_IO26 0x51e + MX91_PAD_ENET2_RD3__GPIO4_IO27 0x51e + MX91_PAD_ENET2_RXC__GPIO4_IO23 0x51e + MX91_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e + MX91_PAD_ENET2_TD0__GPIO4_IO19 0x51e + MX91_PAD_ENET2_TD1__GPIO4_IO18 0x51e + MX91_PAD_ENET2_TD2__GPIO4_IO17 0x51e + MX91_PAD_ENET2_TD3__GPIO4_IO16 0x51e + MX91_PAD_ENET2_TXC__GPIO4_IO21 0x51e + MX91_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX91_PAD_GPIO_IO25__CAN2_TX 0x139e + MX91_PAD_GPIO_IO27__CAN2_RX 0x139e + >; + }; + + pinctrl_flexcan2_sleep: flexcan2sleepgrp { + fsl,pins = < + MX91_PAD_GPIO_IO25__GPIO2_IO25 0x31e + MX91_PAD_GPIO_IO27__GPIO2_IO27 0x31e + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e + MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e + >; + bootph-pre-ram; + bootph-some-ram; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + MX91_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e + MX91_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e + >; + bootph-pre-ram; + bootph-some-ram; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + bootph-pre-ram; + bootph-some-ram; + }; + + pinctrl_lpspi3: lpspi3grp { + fsl,pins = < + MX91_PAD_GPIO_IO08__GPIO2_IO8 0x3fe + MX91_PAD_GPIO_IO09__LPSPI3_SIN 0x3fe + MX91_PAD_GPIO_IO10__LPSPI3_SOUT 0x3fe + MX91_PAD_GPIO_IO11__LPSPI3_SCK 0x3fe + >; + }; + + pinctrl_mqs1: mqs1grp { + fsl,pins = < + MX91_PAD_PDM_CLK__MQS1_LEFT 0x31e + MX91_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x31e + >; + }; + + pinctrl_pcal6524: pcal6524grp { + fsl,pins = < + MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x31e + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x31e + >; + bootph-pre-ram; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX91_PAD_UART1_RXD__LPUART1_RX 0x31e + MX91_PAD_UART1_TXD__LPUART1_TX 0x31e + >; + bootph-pre-ram; + bootph-some-ram; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e + MX91_PAD_DAP_TDI__LPUART5_RX 0x31e + MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e + MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x1582 + MX91_PAD_SD1_CMD__USDHC1_CMD 0x1382 + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x1382 + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x1382 + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x1382 + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x1382 + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x1382 + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x1382 + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x1382 + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x1382 + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 + >; + bootph-pre-ram; + bootph-some-ram; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x158e + MX91_PAD_SD1_CMD__USDHC1_CMD 0x138e + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x15fe + MX91_PAD_SD1_CMD__USDHC1_CMD 0x13fe + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX91_PAD_SD2_CD_B__GPIO3_IO0 0x31e + >; + bootph-pre-ram; + bootph-some-ram; + }; + + pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp { + fsl,pins = < + MX91_PAD_SD2_CD_B__GPIO3_IO0 0x51e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x1582 + MX91_PAD_SD2_CMD__USDHC2_CMD 0x1382 + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x1382 + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x1382 + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x1382 + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x1382 + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + bootph-pre-ram; + bootph-some-ram; + }; + + pinctrl_usdhc2_sleep: usdhc2sleepgrp { + fsl,pins = < + MX91_PAD_SD2_CLK__GPIO3_IO1 0x51e + MX91_PAD_SD2_CMD__GPIO3_IO2 0x51e + MX91_PAD_SD2_DATA0__GPIO3_IO3 0x51e + MX91_PAD_SD2_DATA1__GPIO3_IO4 0x51e + MX91_PAD_SD2_DATA2__GPIO3_IO5 0x51e + MX91_PAD_SD2_DATA3__GPIO3_IO6 0x51e + MX91_PAD_SD2_VSELECT__GPIO3_IO19 0x51e + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e + MX91_PAD_SD2_CMD__USDHC2_CMD 0x138e + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x15fe + MX91_PAD_SD2_CMD__USDHC2_CMD 0x13fe + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX91_PAD_SD3_CLK__USDHC3_CLK 0x1582 + MX91_PAD_SD3_CMD__USDHC3_CMD 0x1382 + MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x1382 + MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x1382 + MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x1382 + MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x1382 + >; + }; + + pinctrl_usdhc3_sleep: usdhc3sleepgrp { + fsl,pins = < + MX91_PAD_SD3_CLK__GPIO3_IO20 0x31e + MX91_PAD_SD3_CMD__GPIO3_IO21 0x31e + MX91_PAD_SD3_DATA0__GPIO3_IO22 0x31e + MX91_PAD_SD3_DATA1__GPIO3_IO23 0x31e + MX91_PAD_SD3_DATA2__GPIO3_IO24 0x31e + MX91_PAD_SD3_DATA3__GPIO3_IO25 0x31e + >; + }; + + pinctrl_usdhc3_wlan: usdhc3wlangrp { + fsl,pins = < + MX91_PAD_CCM_CLKO1__GPIO3_IO26 0x31e + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX91_PAD_SD3_CLK__USDHC3_CLK 0x158e + MX91_PAD_SD3_CMD__USDHC3_CMD 0x138e + MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x138e + MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x138e + MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x138e + MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x138e + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX91_PAD_SD3_CLK__USDHC3_CLK 0x15fe + MX91_PAD_SD3_CMD__USDHC3_CMD 0x13fe + MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe + MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe + MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe + MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx91.dtsi b/arch/arm64/boot/dts/freescale/imx91.dtsi index 4d8300b2a7bc..f075592bfc01 100644 --- a/arch/arm64/boot/dts/freescale/imx91.dtsi +++ b/arch/arm64/boot/dts/freescale/imx91.dtsi @@ -6,6 +6,54 @@ #include "imx91-pinfunc.h" #include "imx91_93_common.dtsi" +/{ + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tmu 0>; + + trips { + cpu_alert: cpu-alert { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit: cpu-crit { + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert>; + cooling-device = + <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; +}; + +&aips1 { + tmu: thermal-sensor@44482000 { + compatible = "fsl,imx91-tmu"; + reg = <0x44482000 0x1000>; + #thermal-sensor-cells = <0>; + clocks = <&clk IMX93_CLK_TMC_GATE>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "thr1", "thr2", "ready"; + nvmem-cells = <&tmu_trim1>, <&tmu_trim2>; + nvmem-cell-names = "trim1", "trim2"; + }; +}; + &clk { compatible = "fsl,imx91-ccm"; }; @@ -69,3 +117,13 @@ clock-names = "apb", "axi", "nic", "disp", "cam", "lcdif", "isi", "csi"; }; + +&ocotp { + tmu_trim1: tmu-trim@a0 { + reg = <0xa0 0x4>; + }; + + tmu_trim2: tmu-trim@a4 { + reg = <0xa4 0x4>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts index b94a24193e19..8dd5340e8141 100644 --- a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts @@ -81,6 +81,13 @@ }; + flexcan_phy: can-phy { + compatible = "nxp,tja1057"; + #phy-cells = <0>; + max-bitrate = <5000000>; + silent-gpios = <&adp5585 6 GPIO_ACTIVE_HIGH>; + }; + reg_vdd_12v: regulator-vdd-12v { compatible = "regulator-fixed"; regulator-name = "VDD_12V"; @@ -106,14 +113,6 @@ enable-active-high; }; - reg_can2_standby: regulator-can2-standby { - compatible = "regulator-fixed"; - regulator-name = "can2-stby"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&adp5585 6 GPIO_ACTIVE_LOW>; - }; - reg_m2_pwr: regulator-m2-pwr { compatible = "regulator-fixed"; regulator-name = "M.2-power"; @@ -302,7 +301,7 @@ &flexcan2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_can2_standby>; + phys = <&flexcan_phy>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts new file mode 100644 index 000000000000..bd14ba28690c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts @@ -0,0 +1,807 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/dts-v1/; + +#include <dt-bindings/usb/pd.h> +#include "imx93.dtsi" + +/ { + compatible = "fsl,imx93-11x11-frdm", "fsl,imx93"; + model = "NXP i.MX93 11X11 FRDM board"; + + aliases { + can0 = &flexcan2; + ethernet0 = &fec; + ethernet1 = &eqos; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + mmc0 = &usdhc1; /* EMMC */ + mmc1 = &usdhc2; /* uSD */ + rtc0 = &pcf2131; + serial0 = &lpuart1; + serial4 = &lpuart5; + }; + + chosen { + stdout-path = &lpuart1; + }; + + flexcan2_phy: can-phy { + compatible = "nxp,tja1051"; + #phy-cells = <0>; + max-bitrate = <5000000>; + silent-gpios = <&pcal6524 23 GPIO_ACTIVE_HIGH>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-k2 { + label = "Button K2"; + linux,code = <BTN_1>; + gpios = <&pcal6524 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + interrupt-parent = <&pcal6524>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + }; + + button-k3 { + label = "Button K3"; + linux,code = <BTN_2>; + gpios = <&pcal6524 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + interrupt-parent = <&pcal6524>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + }; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + off-on-delay-us = <12000>; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + pinctrl-names = "default"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "VSD_3V3"; + vin-supply = <&buck4>; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc3_vmmc: regulator-usdhc3 { + compatible = "regulator-fixed"; + regulator-name = "VPCIe_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <20000>; + gpio = <&pcal6524 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reserved-memory { + ranges; + #address-cells = <2>; + #size-cells = <2>; + + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x80000000 0 0x30000000>; + reusable; + size = <0 0x10000000>; + linux,cma-default; + }; + + rsc_table: rsc-table@2021e000 { + reg = <0 0x2021e000 0 0x1000>; + no-map; + }; + + vdev0vring0: vdev0vring0@a4000000 { + reg = <0 0xa4000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@a4008000 { + reg = <0 0xa4008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@a4010000 { + reg = <0 0xa4010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@a4018000 { + reg = <0 0xa4018000 0 0x8000>; + no-map; + }; + + vdevbuffer: vdevbuffer@a4020000 { + compatible = "shared-dma-pool"; + reg = <0 0xa4020000 0 0x100000>; + no-map; + }; + }; + + sound-mqs { + compatible = "fsl,imx-audio-mqs"; + model = "mqs-audio"; + audio-cpu = <&sai1>; + audio-codec = <&mqs1>; + }; + + usdhc3_pwrseq: mmc-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pcal6524 12 GPIO_ACTIVE_LOW>; + }; +}; + +&adc1 { + vref-supply = <&buck5>; + status = "okay"; +}; + +&mu1 { + status = "okay"; +}; + +&cm33 { + mboxes = <&mu1 0 1>, + <&mu1 1 1>, + <&mu1 3 1>; + mbox-names = "tx", "rx", "rxdb"; + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; + status = "okay"; +}; + +&eqos { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_eqos>; + pinctrl-1 = <&pinctrl_eqos_sleep>; + phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy1: ethernet-phy@1 { + reg = <1>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; + realtek,clkout-disable; + }; + }; +}; + +&fec { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_fec>; + pinctrl-1 = <&pinctrl_fec_sleep>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy2>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy2: ethernet-phy@2 { + reg = <2>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>; + realtek,clkout-disable; + }; + }; +}; + +&flexcan2 { + phys = <&flexcan2_phy>; + pinctrl-0 = <&pinctrl_flexcan2>; + pinctrl-1 = <&pinctrl_flexcan2_sleep>; + pinctrl-names = "default", "sleep"; + status = "okay"; +}; + +&lpi2c1 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c1>; + pinctrl-names = "default"; + status = "okay"; + + pcal6408: gpio@20 { + compatible = "nxp,pcal6408"; + reg = <0x20>; + #gpio-cells = <2>; + gpio-controller; + reset-gpios = <&pcal6524 20 GPIO_ACTIVE_LOW>; + }; +}; + +&lpi2c2 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-names = "default"; + status = "okay"; + + pcal6524: gpio@22 { + compatible = "nxp,pcal6524"; + reg = <0x22>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + #gpio-cells = <2>; + gpio-controller; + pinctrl-0 = <&pinctrl_pcal6524>; + pinctrl-names = "default"; + /* does not boot with supplier set, because it is the bucks interrupt parent */ + /* vcc-supply = <&buck4>; */ + }; + + pmic@25 { + compatible = "nxp,pca9451a"; + reg = <0x25>; + interrupt-parent = <&pcal6524>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + + regulators { + + buck1: BUCK1 { + regulator-name = "VDD_SOC_0V8"; + regulator-min-microvolt = <610000>; + regulator-max-microvolt = <950000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "LPD4_x_VDDQ_0V6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <670000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <3125>; + }; + + buck4: BUCK4 { + regulator-name = "VDD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + buck5: BUCK5 { + regulator-name = "VDD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + buck6: BUCK6 { + regulator-name = "LPD4_x_VDD2_1V1"; + regulator-min-microvolt = <1060000>; + regulator-max-microvolt = <1140000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo1: LDO1 { + regulator-name = "NVCC_BBSM_1V8"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo4: LDO4 { + regulator-name = "VDD_ANA_0V8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <840000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo5: LDO5 { + regulator-name = "NVCC_SD"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + + eeprom: eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + pagesize = <64>; + vcc-supply = <&buck4>; + }; +}; + +&lpi2c3 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-names = "default"; + status = "okay"; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x50>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + + typec1_con: connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + op-sink-microwatt = <15000000>; + power-role = "dual"; + self-powered; + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) + PDO_VAR(5000, 20000, 3000)>; + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + try-power-role = "sink"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + }; + }; + }; + + pcf2131: rtc@53 { + compatible = "nxp,pcf2131"; + reg = <0x53>; + interrupt-parent = <&pcal6524>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&lpuart1 { /* console */ + pinctrl-0 = <&pinctrl_uart1>; + pinctrl-names = "default"; + status = "okay"; +}; + +&lpuart5 { + pinctrl-0 = <&pinctrl_uart5>; + pinctrl-names = "default"; + status = "okay"; + + uart-has-rtscts; + + bluetooth { + compatible = "nxp,88w8987-bt"; + device-wakeup-gpios = <&pcal6408 3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pcal6524 19 GPIO_ACTIVE_LOW>; + vcc-supply = <®_usdhc3_vmmc>; + }; +}; + +&mqs1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mqs1>; + clocks = <&clk IMX93_CLK_MQS1_GATE>; + clock-names = "mclk"; + status = "okay"; +}; + +&sai1 { + #sound-dai-cells = <0>; + clocks = <&clk IMX93_CLK_SAI1_IPG>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_SAI1_GATE>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_AUDIO_PLL>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k"; + assigned-clocks = <&clk IMX93_CLK_SAI1>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <24576000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&usbotg1 { + adp-disable; + disable-over-current; + dr_mode = "otg"; + hnp-disable; + srp-disable; + usb-role-switch; + samsung,picophy-dc-vol-level-adjust = <7>; + samsung,picophy-pre-emp-curr-control = <3>; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&usbotg2 { + disable-over-current; + dr_mode = "host"; + samsung,picophy-dc-vol-level-adjust = <7>; + samsung,picophy-pre-emp-curr-control = <3>; + status = "okay"; +}; + +&usdhc1 { + bus-width = <8>; + non-removable; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + vmmc-supply = <&buck4>; + status = "okay"; +}; + +&usdhc2 { + bus-width = <4>; + cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; + no-mmc; + no-sdio; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usdhc3 { + bus-width = <4>; + keep-power-in-suspend; + mmc-pwrseq = <&usdhc3_pwrseq>; + non-removable; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + pinctrl-3 = <&pinctrl_usdhc3_sleep>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + vmmc-supply = <®_usdhc3_vmmc>; + status = "okay"; +}; + +&wdog3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e + MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e + MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e + MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e + MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x58e + MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e + MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e + MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e + MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e + MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e + MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_eqos_sleep: eqossleepgrp { + fsl,pins = < + MX93_PAD_ENET1_MDC__GPIO4_IO00 0x31e + MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x31e + MX93_PAD_ENET1_RD0__GPIO4_IO10 0x31e + MX93_PAD_ENET1_RD1__GPIO4_IO11 0x31e + MX93_PAD_ENET1_RD2__GPIO4_IO12 0x31e + MX93_PAD_ENET1_RD3__GPIO4_IO13 0x31e + MX93_PAD_ENET1_RXC__GPIO4_IO09 0x31e + MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 0x31e + MX93_PAD_ENET1_TD0__GPIO4_IO05 0x31e + MX93_PAD_ENET1_TD1__GPIO4_IO04 0x31e + MX93_PAD_ENET1_TD2__GPIO4_IO03 0x31e + MX93_PAD_ENET1_TD3__GPIO4_IO02 0x31e + MX93_PAD_ENET1_TXC__GPIO4_IO07 0x31e + MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 0x31e + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e + MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e + MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e + MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e + MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e + MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e + MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x58e + MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e + MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e + MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e + MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e + MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e + MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x58e + MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_fec_sleep: fecsleepgrp { + fsl,pins = < + MX93_PAD_ENET2_MDC__GPIO4_IO14 0x51e + MX93_PAD_ENET2_MDIO__GPIO4_IO15 0x51e + MX93_PAD_ENET2_RD0__GPIO4_IO24 0x51e + MX93_PAD_ENET2_RD1__GPIO4_IO25 0x51e + MX93_PAD_ENET2_RD2__GPIO4_IO26 0x51e + MX93_PAD_ENET2_RD3__GPIO4_IO27 0x51e + MX93_PAD_ENET2_RXC__GPIO4_IO23 0x51e + MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e + MX93_PAD_ENET2_TD0__GPIO4_IO19 0x51e + MX93_PAD_ENET2_TD1__GPIO4_IO18 0x51e + MX93_PAD_ENET2_TD2__GPIO4_IO17 0x51e + MX93_PAD_ENET2_TD3__GPIO4_IO16 0x51e + MX93_PAD_ENET2_TXC__GPIO4_IO21 0x51e + MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX93_PAD_GPIO_IO25__CAN2_TX 0x139e + MX93_PAD_GPIO_IO27__CAN2_RX 0x139e + >; + }; + + pinctrl_flexcan2_sleep: flexcan2sleepgrp { + fsl,pins = < + MX93_PAD_GPIO_IO25__GPIO2_IO25 0x31e + MX93_PAD_GPIO_IO27__GPIO2_IO27 0x31e + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e + MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e + MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_mqs1: mqs1grp { + fsl,pins = < + MX93_PAD_PDM_CLK__MQS1_LEFT 0x31e + MX93_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x31e + >; + }; + + pinctrl_pcal6524: pcal6524grp { + fsl,pins = < + MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e + MX93_PAD_UART1_TXD__LPUART1_TX 0x31e + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e + MX93_PAD_DAP_TDI__LPUART5_RX 0x31e + MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e + MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582 + MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382 + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382 + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382 + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382 + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382 + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382 + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382 + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382 + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382 + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e + MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe + MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e + >; + }; + + pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp { + fsl,pins = < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x51e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582 + MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382 + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382 + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382 + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382 + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382 + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe + MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_sleep: usdhc2-sleepgrp { + fsl,pins = < + MX93_PAD_SD2_CLK__GPIO3_IO01 0x51e + MX93_PAD_SD2_CMD__GPIO3_IO02 0x51e + MX93_PAD_SD2_DATA0__GPIO3_IO03 0x51e + MX93_PAD_SD2_DATA1__GPIO3_IO04 0x51e + MX93_PAD_SD2_DATA2__GPIO3_IO05 0x51e + MX93_PAD_SD2_DATA3__GPIO3_IO06 0x51e + MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x51e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX93_PAD_SD3_CLK__USDHC3_CLK 0x1582 + MX93_PAD_SD3_CMD__USDHC3_CMD 0x40001382 + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x40001382 + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x40001382 + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x40001382 + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x40001382 + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX93_PAD_SD3_CLK__USDHC3_CLK 0x158e + MX93_PAD_SD3_CMD__USDHC3_CMD 0x4000138e + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x4000138e + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x4000138e + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x4000138e + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x4000138e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX93_PAD_SD3_CLK__USDHC3_CLK 0x15fe + MX93_PAD_SD3_CMD__USDHC3_CMD 0x400013fe + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x400013fe + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x400013fe + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x400013fe + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x400013fe + >; + }; + + pinctrl_usdhc3_sleep: usdhc3grpsleepgrp { + fsl,pins = < + MX93_PAD_SD3_CLK__GPIO3_IO20 0x31e + MX93_PAD_SD3_CMD__GPIO3_IO21 0x31e + MX93_PAD_SD3_DATA0__GPIO3_IO22 0x31e + MX93_PAD_SD3_DATA1__GPIO3_IO23 0x31e + MX93_PAD_SD3_DATA2__GPIO3_IO24 0x31e + MX93_PAD_SD3_DATA3__GPIO3_IO25 0x31e + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts b/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts index f9eebd27d640..61843b2c1b1b 100644 --- a/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts @@ -27,6 +27,11 @@ serial0 = &lpuart1; }; + bt_sco_codec: bt-sco-codec { + compatible = "linux,bt-sco"; + #sound-dai-cells = <1>; + }; + chosen { stdout-path = &lpuart1; }; @@ -168,6 +173,38 @@ regulator-max-microvolt = <1800000>; }; + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + simple-audio-card,codec { + sound-dai = <&bt_sco_codec 1>; + }; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + }; + + sound-xcvr { + compatible = "fsl,imx-audio-card"; + model = "imx-audio-xcvr"; + + pri-dai-link { + link-name = "XCVR PCM"; + + cpu { + sound-dai = <&xcvr>; + }; + }; + }; + usdhc3_pwrseq: usdhc3_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&pcal6524 12 GPIO_ACTIVE_LOW>; @@ -371,6 +408,16 @@ status = "okay"; }; +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clk IMX93_CLK_SAI1>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + &usbotg1 { dr_mode = "otg"; hnp-disable; @@ -434,6 +481,17 @@ status = "okay"; }; +&xcvr { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif>; + assigned-clocks = <&clk IMX93_CLK_SPDIF>, + <&clk IMX93_CLK_AUDIO_XCVR>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <12288000>, <200000000>; + status = "okay"; +}; + &iomuxc { pinctrl_flexcan1: flexcan1grp { fsl,pins = < @@ -568,6 +626,22 @@ >; }; + pinctrl_sai1: sai1grp { + fsl,pins = < + MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e + MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e + MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x31e + MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x31e + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX93_PAD_GPIO_IO22__SPDIF_IN 0x31e + MX93_PAD_GPIO_IO23__SPDIF_OUT 0x31e + >; + }; + pinctrl_usdhc2_gpio: usdhc2gpiogrp { fsl,pins = < MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e diff --git a/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-can1.dtso b/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-can1.dtso new file mode 100644 index 000000000000..0bf1e9d4bad2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-can1.dtso @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 NXP + */ + +#include <dt-bindings/gpio/gpio.h> +#include "imx93-pinfunc.h" + +/dts-v1/; +/plugin/; + +&{/} { + flexcan_phy: can-phy { + compatible = "nxp,tja1057"; + #phy-cells = <0>; + max-bitrate = <5000000>; + silent-gpios = <&pcal6524 23 GPIO_ACTIVE_HIGH>; + }; +}; + +&flexcan1 { + phys = <&flexcan_phy>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&iomuxc { + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX93_PAD_PDM_CLK__CAN1_TX 0x139e + MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e + >; + }; +}; + +/* micfi1 use the A port, conflict with can1 */ +&micfil { + status = "disabled"; +}; + +&pcal6524 { + /* + * mic-can-sel-hog have property 'output-low', dt overlay don't + * support /delete-property/. Both 'output-low' and 'output-high' + * will be exist under hog nodes if overlay file set 'output-high'. + * Workaround is disable this hog and create new hog with + * 'output-high'. + */ + mic-can-sel-hog { + status = "disabled"; + }; + + /* + * Config the MIC/CAN_SEL to high, chose B + * port, connect to CAN. + */ + mic-can-high-sel-hog { + gpio-hog; + gpios = <0x11 0x00>; + output-high; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts index c789c1f24bdc..c0842fb3cfa3 100644 --- a/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts @@ -20,6 +20,8 @@ gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &pca9534; i2c0 = &lpi2c1; i2c1 = &lpi2c2; i2c2 = &lpi2c3; @@ -206,6 +208,21 @@ sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; status = "okay"; + /* Capacitive touch controller */ + ft5x06_ts: touchscreen@38 { + compatible = "edt,edt-ft5206"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_captouch>; + interrupt-parent = <&gpio2>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + touchscreen-inverted-x; + touchscreen-inverted-y; + wakeup-source; + }; + /* DS1337 RTC module */ rtc@68 { compatible = "dallas,ds1337"; @@ -234,6 +251,22 @@ #gpio-cells = <2>; wakeup-source; }; + + /* USB Type-C Controller */ + ptn5150: typec@3d { + compatible = "nxp,ptn5150"; + reg = <0x3d>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ptn5150>; + interrupt-parent = <&gpio1>; + interrupts = <10 IRQ_TYPE_NONE>; + + port { + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + }; }; /* Console */ @@ -243,6 +276,13 @@ status = "okay"; }; +&lpspi6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi6>; + cs-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + /* J18.7, J18.9 */ &lpuart6 { pinctrl-names = "default"; @@ -250,6 +290,29 @@ status = "okay"; }; +&usbotg1 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + /* SD */ &usdhc2 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; @@ -270,6 +333,12 @@ }; &iomuxc { + pinctrl_captouch: captouchgrp { + fsl,pins = < + MX93_PAD_GPIO_IO25__GPIO2_IO25 0x31e + >; + }; + pinctrl_fec: fecgrp { fsl,pins = < MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e @@ -322,12 +391,27 @@ >; }; + pinctrl_lpspi6: lpspi6grp { + fsl,pins = < + MX93_PAD_GPIO_IO00__GPIO2_IO00 0x31e + MX93_PAD_GPIO_IO01__LPSPI6_SIN 0x31e + MX93_PAD_GPIO_IO02__LPSPI6_SOUT 0x31e + MX93_PAD_GPIO_IO03__LPSPI6_SCK 0x31e + >; + }; + pinctrl_pca9534: pca9534grp { fsl,pins = < MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e >; }; + pinctrl_ptn5150: ptn5150grp { + fsl,pins = < + MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX93_PAD_UART1_RXD__LPUART1_RX 0x31e diff --git a/arch/arm64/boot/dts/freescale/imx93-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-var-som.dtsi index 2dc8b18ae91e..24063bf8183d 100644 --- a/arch/arm64/boot/dts/freescale/imx93-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93-var-som.dtsi @@ -131,7 +131,7 @@ regulator-ramp-delay = <3125>; }; - buck4: BUCK4{ + buck4: BUCK4 { regulator-name = "BUCK4"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <3400000>; @@ -139,7 +139,7 @@ regulator-always-on; }; - buck5: BUCK5{ + buck5: BUCK5 { regulator-name = "BUCK5"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <3400000>; diff --git a/arch/arm64/boot/dts/freescale/imx94.dtsi b/arch/arm64/boot/dts/freescale/imx94.dtsi index 73184f03f8a3..d2f31c8caf6e 100644 --- a/arch/arm64/boot/dts/freescale/imx94.dtsi +++ b/arch/arm64/boot/dts/freescale/imx94.dtsi @@ -629,7 +629,7 @@ compatible = "fsl,aips-bus", "simple-bus"; reg = <0 0x42800000 0 0x800000>; ranges = <0x42800000 0x0 0x42800000 0x800000>, - <0x28000000 0x0 0x28000000 0x1000000>; + <0x24000000 0x0 0x24000000 0xc000000>; #address-cells = <1>; #size-cells = <1>; @@ -785,6 +785,38 @@ #mbox-cells = <2>; status = "disabled"; }; + + xspi1: spi@42b90000 { + compatible = "nxp,imx94-xspi"; + reg = <0x42b90000 0x50000>, <0x28000000 0x08000000>; + reg-names = "base", "mmap"; + interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, // EENV0 + <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, // EENV1 + <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>, // EENV2 + <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, // EENV3 + <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>; // EENV4 + #address-cells = <1>; + #size-cells = <0>; + clocks = <&scmi_clk IMX94_CLK_XSPI1>; + clock-names = "per"; + status = "disabled"; + }; + + xspi2: spi@42be0000 { + compatible = "nxp,imx94-xspi"; + reg = <0x42be0000 0x50000>, <0x24000000 0x04000000>; + reg-names = "base", "mmap"; + interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, // EENV0 + <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, // EENV1 + <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, // EENV2 + <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, // EENV3 + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>; // EENV4 + #address-cells = <1>; + #size-cells = <0>; + clocks = <&scmi_clk IMX94_CLK_XSPI2>; + clock-names = "per"; + status = "disabled"; + }; }; gpio2: gpio@43810000 { @@ -1191,6 +1223,144 @@ }; }; + netc_blk_ctrl: system-controller@4ceb0000 { + compatible = "nxp,imx94-netc-blk-ctrl"; + reg = <0x0 0x4ceb0000 0x0 0x10000>, + <0x0 0x4cec0000 0x0 0x10000>, + <0x0 0x4c810000 0x0 0x7C>; + reg-names = "ierb", "prb", "netcmix"; + ranges; + #address-cells = <2>; + #size-cells = <2>; + clocks = <&scmi_clk IMX94_CLK_ENET>; + clock-names = "ipg"; + power-domains = <&scmi_devpd IMX94_PD_NETC>; + status = "disabled"; + + netc_bus0: pcie@4ca00000 { + compatible = "pci-host-ecam-generic"; + reg = <0x0 0x4ca00000 0x0 0x100000>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x0 0x0>; + msi-map = <0x00 &its 0x68 0x1>, //ENETC3 PF + <0x01 &its 0x61 0x1>, //Timer0 + <0x02 &its 0x64 0x1>, //Switch + <0x40 &its 0x69 0x1>, //ENETC3 VF0 + <0x80 &its 0x6a 0x1>, //ENETC3 VF1 + <0xC0 &its 0x6b 0x1>; //ENETC3 VF2 + /* Switch BAR0 - non-prefetchable memory */ + ranges = <0x02000000 0x0 0x4cc00000 0x0 0x4cc00000 0x0 0x80000 + /* ENETC 3 and Timer 0 BAR0 - non-prefetchable memory */ + 0x02000000 0x0 0x4cd40000 0x0 0x4cd40000 0x0 0x60000 + /* Switch and Timer 0 BAR2 - prefetchable memory */ + 0x42000000 0x0 0x4ce00000 0x0 0x4ce00000 0x0 0x20000 + /* ENETC 3 VF0-2 BAR0 - non-prefetchable memory */ + 0x02000000 0x0 0x4ce50000 0x0 0x4ce50000 0x0 0x30000 + /* ENETC 3 VF0-2 BAR2 - prefetchable memory */ + 0x42000000 0x0 0x4ce80000 0x0 0x4ce80000 0x0 0x30000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 + GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + + enetc3: ethernet@0,0 { + compatible = "pci1131,e110"; + reg = <0x0 0 0 0 0>; + phy-mode = "internal"; + status = "disabled"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + netc_timer0: ptp-timer@0,1 { + compatible = "pci1131,ee02"; + reg = <0x100 0 0 0 0>; + status = "disabled"; + }; + + rcec@1,0 { + reg = <0x800 0 0 0 0>; + interrupts = <1>; + }; + }; + + netc_bus1: pcie@4cb00000 { + compatible = "pci-host-ecam-generic"; + reg = <0x0 0x4cb00000 0x0 0x100000>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + linux,pci-domain = <1>; + bus-range = <0x1 0x1>; + msi-map = <0x100 &its 0x65 0x1>, //ENETC0 PF + <0x101 &its 0x62 0x1>, //Timer1 + <0x140 &its 0x66 0x1>, //ENETC1 PF + <0x180 &its 0x67 0x1>, //ENETC2 PF + <0x181 &its 0x63 0x1>, //Timer2 + <0x1C0 &its 0x60 0x1>; //EMDIO + /* ENETC 0-2 BAR0 - non-prefetchable memory */ + ranges = <0x02000000 0x0 0x4cC80000 0x0 0x4cc80000 0x0 0xc0000 + /* Timer 1-2 and EMDIO BAR0 - non-prefetchable memory */ + 0x02000000 0x0 0x4cda0000 0x0 0x4cda0000 0x0 0x60000 + /* Timer 1-2 and EMDIO BAR2 - prefetchable memory */ + 0x42000000 0x0 0x4ce20000 0x0 0x4ce20000 0x0 0x30000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 + GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; + + enetc0: ethernet@0,0 { + compatible = "pci1131,e101"; + reg = <0x10000 0 0 0 0>; + status = "disabled"; + }; + + netc_timer1: ptp-timer@0,1 { + compatible = "pci1131,ee02"; + reg = <0x10100 0 0 0 0>; + status = "disabled"; + }; + + rcec@1,0 { + reg = <0x10800 0 0 0 0>; + interrupts = <1>; + }; + + enetc1: ethernet@8,0 { + compatible = "pci1131,e101"; + reg = <0x14000 0 0 0 0>; + status = "disabled"; + }; + + enetc2: ethernet@10,0 { + compatible = "pci1131,e101"; + reg = <0x18000 0 0 0 0>; + status = "disabled"; + }; + + netc_timer2: ptp-timer@10,1 { + compatible = "pci1131,ee02"; + reg = <0x18100 0 0 0 0>; + status = "disabled"; + }; + + netc_emdio: mdio@18,0 { + compatible = "pci1131,ee00"; + reg = <0x1c000 0 0 0 0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + }; + ddr-pmu@4e090dc0 { compatible = "fsl,imx94-ddr-pmu", "fsl,imx93-ddr-pmu"; reg = <0x0 0x4e090dc0 0x0 0x200>; diff --git a/arch/arm64/boot/dts/freescale/imx943-evk.dts b/arch/arm64/boot/dts/freescale/imx943-evk.dts index c8c3eff9df1a..31fa9675cee1 100644 --- a/arch/arm64/boot/dts/freescale/imx943-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx943-evk.dts @@ -12,6 +12,9 @@ model = "NXP i.MX943 EVK board"; aliases { + ethernet0 = &enetc3; + ethernet1 = &enetc1; + ethernet2 = &enetc2; i2c2 = &lpi2c3; i2c3 = &lpi2c4; i2c5 = &lpi2c6; @@ -25,6 +28,22 @@ #sound-dai-cells = <1>; }; + flexcan2_phy: can-phy0 { + compatible = "nxp,tjr1443"; + #phy-cells = <0>; + enable-gpios = <&pcal6416_i2c6_u50 3 GPIO_ACTIVE_HIGH>; + max-bitrate = <8000000>; + standby-gpios = <&pcal6416_i2c6_u50 4 GPIO_ACTIVE_LOW>; + }; + + flexcan4_phy: can-phy1 { + compatible = "nxp,tjr1443"; + #phy-cells = <0>; + enable-gpios = <&pcal6416_i2c3_u171 0 GPIO_ACTIVE_HIGH>; + max-bitrate = <8000000>; + standby-gpios = <&pcal6416_i2c3_u171 1 GPIO_ACTIVE_LOW>; + }; + chosen { stdout-path = &lpuart1; }; @@ -127,6 +146,44 @@ }; }; +&enetc1 { + clocks = <&scmi_clk IMX94_CLK_MAC4>; + clock-names = "ref"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth3>; + phy-handle = <ðphy3>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&enetc2 { + clocks = <&scmi_clk IMX94_CLK_MAC5>; + clock-names = "ref"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth4>; + phy-handle = <ðphy4>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&enetc3 { + status = "okay"; +}; + +&flexcan2 { + phys = <&flexcan2_phy>; + pinctrl-0 = <&pinctrl_flexcan2>; + pinctrl-names = "default"; + status = "okay"; +}; + +&flexcan4 { + phys = <&flexcan4_phy>; + pinctrl-0 = <&pinctrl_flexcan4>; + pinctrl-names = "default"; + status = "okay"; +}; + &lpi2c3 { clock-frequency = <400000>; pinctrl-0 = <&pinctrl_lpi2c3>; @@ -396,6 +453,39 @@ status = "okay"; }; +&netc_blk_ctrl { + assigned-clocks = <&scmi_clk IMX94_CLK_MAC4>, + <&scmi_clk IMX94_CLK_MAC5>; + assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD0>, + <&scmi_clk IMX94_CLK_SYSPLL1_PFD0>; + assigned-clock-rates = <250000000>, <250000000>; + status = "okay"; +}; + +&netc_emdio { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_emdio>; + status = "okay"; + + ethphy3: ethernet-phy@6 { + reg = <0x6>; + realtek,clkout-disable; + }; + + ethphy4: ethernet-phy@7 { + reg = <0x7>; + realtek,clkout-disable; + }; +}; + +&netc_timer0 { + status = "okay"; +}; + +&netc_timer1 { + status = "okay"; +}; + &sai1 { assigned-clocks = <&scmi_clk IMX94_CLK_AUDIOPLL1_VCO>, <&scmi_clk IMX94_CLK_AUDIOPLL2_VCO>, @@ -431,6 +521,60 @@ }; &scmi_iomuxc { + pinctrl_emdio: emdiogrp { + fsl,pins = < + IMX94_PAD_ETH4_MDC_GPIO1__NETC_EMDC 0x57e + IMX94_PAD_ETH4_MDIO_GPIO2__NETC_EMDIO 0x97e + >; + }; + + pinctrl_eth3: eth3grp { + fsl,pins = < + IMX94_PAD_ETH3_TXD3__NETC_PINMUX_ETH3_TXD3 0x50e + IMX94_PAD_ETH3_TXD2__NETC_PINMUX_ETH3_TXD2 0x50e + IMX94_PAD_ETH3_TXD1__NETC_PINMUX_ETH3_TXD1 0x50e + IMX94_PAD_ETH3_TXD0__NETC_PINMUX_ETH3_TXD0 0x50e + IMX94_PAD_ETH3_TX_CTL__NETC_PINMUX_ETH3_TX_CTL 0x51e + IMX94_PAD_ETH3_TX_CLK__NETC_PINMUX_ETH3_TX_CLK 0x59e + IMX94_PAD_ETH3_RX_CTL__NETC_PINMUX_ETH3_RX_CTL 0x51e + IMX94_PAD_ETH3_RX_CLK__NETC_PINMUX_ETH3_RX_CLK 0x59e + IMX94_PAD_ETH3_RXD0__NETC_PINMUX_ETH3_RXD0 0x51e + IMX94_PAD_ETH3_RXD1__NETC_PINMUX_ETH3_RXD1 0x51e + IMX94_PAD_ETH3_RXD2__NETC_PINMUX_ETH3_RXD2 0x51e + IMX94_PAD_ETH3_RXD3__NETC_PINMUX_ETH3_RXD3 0x51e + >; + }; + + pinctrl_eth4: eth4grp { + fsl,pins = < + IMX94_PAD_ETH4_TXD3__NETC_PINMUX_ETH4_TXD3 0x50e + IMX94_PAD_ETH4_TXD2__NETC_PINMUX_ETH4_TXD2 0x50e + IMX94_PAD_ETH4_TXD1__NETC_PINMUX_ETH4_TXD1 0x50e + IMX94_PAD_ETH4_TXD0__NETC_PINMUX_ETH4_TXD0 0x50e + IMX94_PAD_ETH4_TX_CTL__NETC_PINMUX_ETH4_TX_CTL 0x51e + IMX94_PAD_ETH4_TX_CLK__NETC_PINMUX_ETH4_TX_CLK 0x59e + IMX94_PAD_ETH4_RX_CTL__NETC_PINMUX_ETH4_RX_CTL 0x51e + IMX94_PAD_ETH4_RX_CLK__NETC_PINMUX_ETH4_RX_CLK 0x59e + IMX94_PAD_ETH4_RXD0__NETC_PINMUX_ETH4_RXD0 0x51e + IMX94_PAD_ETH4_RXD1__NETC_PINMUX_ETH4_RXD1 0x51e + IMX94_PAD_ETH4_RXD2__NETC_PINMUX_ETH4_RXD2 0x51e + IMX94_PAD_ETH4_RXD3__NETC_PINMUX_ETH4_RXD3 0x51e + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + IMX94_PAD_GPIO_IO34__CAN2_TX 0x39e + IMX94_PAD_GPIO_IO35__CAN2_RX 0x39e + >; + }; + + pinctrl_flexcan4: flexcan4grp { + fsl,pins = < + IMX94_PAD_GPIO_IO36__CAN4_TX 0x39e + IMX94_PAD_GPIO_IO37__CAN4_RX 0x39e + >; + }; pinctrl_ioexpander_int2: ioexpanderint2grp { fsl,pins = < @@ -594,6 +738,22 @@ IMX94_PAD_SD2_RESET_B__GPIO4_IO27 0x31e >; }; + + pinctrl_xspi1: xspi1grp { + fsl,pins = < + IMX94_PAD_XSPI1_SCLK__XSPI1_A_SCLK 0x3fe + IMX94_PAD_XSPI1_SS0_B__XSPI1_A_SS0_B 0x3fe + IMX94_PAD_XSPI1_DATA0__XSPI1_A_DATA0 0x3fe + IMX94_PAD_XSPI1_DATA1__XSPI1_A_DATA1 0x3fe + IMX94_PAD_XSPI1_DATA2__XSPI1_A_DATA2 0x3fe + IMX94_PAD_XSPI1_DATA3__XSPI1_A_DATA3 0x3fe + IMX94_PAD_XSPI1_DATA4__XSPI1_A_DATA4 0x3fe + IMX94_PAD_XSPI1_DATA5__XSPI1_A_DATA5 0x3fe + IMX94_PAD_XSPI1_DATA6__XSPI1_A_DATA6 0x3fe + IMX94_PAD_XSPI1_DATA7__XSPI1_A_DATA7 0x3fe + IMX94_PAD_XSPI1_DQS__XSPI1_A_DQS 0x3fe + >; + }; }; &usdhc1 { @@ -625,3 +785,21 @@ fsl,ext-reset-output; status = "okay"; }; + +&xspi1 { + pinctrl-0 = <&pinctrl_xspi1>; + pinctrl-1 = <&pinctrl_xspi1>; + pinctrl-names = "default", "sleep"; + status = "okay"; + + mt35xu512aba: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + reset-gpios = <&pcal6416_i2c6_u50 15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + spi-max-frequency = <200000000>; + spi-rx-bus-width = <8>; + spi-tx-bus-width = <8>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts index c1e245ecea9c..d4184fb8b28c 100644 --- a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts @@ -107,12 +107,11 @@ gpio = <&pcal6524 0 GPIO_ACTIVE_LOW>; }; - reg_can2_stby: regulator-can2-stby { - compatible = "regulator-fixed"; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "can2-stby"; - gpio = <&pcal6524 14 GPIO_ACTIVE_LOW>; + flexcan2_phy: can-phy { + compatible = "nxp,tja1051"; + #phy-cells = <0>; + max-bitrate = <5000000>; + silent-gpios = <&pcal6524 14 GPIO_ACTIVE_HIGH>; }; reg_m2_pwr: regulator-m2-pwr { @@ -179,7 +178,7 @@ linux_cma: linux,cma { compatible = "shared-dma-pool"; - alloc-ranges = <0 0x80000000 0 0x7F000000>; + alloc-ranges = <0 0x80000000 0 0x7f000000>; reusable; size = <0 0x3c000000>; linux,cma-default; @@ -216,7 +215,7 @@ no-map; }; - vpu_boot: vpu_boot@a0000000 { + vpu_boot: vpu-boot@a0000000 { reg = <0 0xa0000000 0 0x100000>; no-map; }; @@ -318,7 +317,7 @@ &flexcan2 { pinctrl-0 = <&pinctrl_flexcan2>; pinctrl-names = "default"; - xceiver-supply = <®_can2_stby>; + phys = <&flexcan2_phy>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts b/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts new file mode 100644 index 000000000000..ca1c4966c867 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts @@ -0,0 +1,964 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 NXP + */ + +/dts-v1/; + +#include <dt-bindings/leds/common.h> +#include <dt-bindings/phy/phy-imx8-pcie.h> +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/usb/pd.h> +#include "imx95.dtsi" + +#define BRD_SM_CTRL_SD3_WAKE 0x8000 /*!< PCAL6408A-0 */ +#define BRD_SM_CTRL_PCIE1_WAKE 0x8001 /*!< PCAL6408A-4 */ +#define BRD_SM_CTRL_BT_WAKE 0x8002 /*!< PCAL6408A-5 */ +#define BRD_SM_CTRL_PCIE2_WAKE 0x8003 /*!< PCAL6408A-6 */ +#define BRD_SM_CTRL_BUTTON 0x8004 /*!< PCAL6408A-7 */ + +/ { + compatible = "fsl,imx95-15x15-frdm", "fsl,imx95"; + model = "NXP i.MX95 15X15 FRDM board"; + + aliases { + ethernet0 = &enetc_port0; + ethernet1 = &enetc_port1; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + i2c3 = &lpi2c4; + i2c4 = &lpi2c5; + i2c5 = &lpi2c6; + i2c6 = &lpi2c7; + i2c7 = &lpi2c8; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + serial0 = &lpuart1; + serial4 = &lpuart5; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + stdout-path = &lpuart1; + }; + + dmic: dmic { + compatible = "dmic-codec"; + #sound-dai-cells = <0>; + num-channels = <2>; + }; + + flexcan2_phy: can-phy { + compatible = "nxp,tja1051"; + #phy-cells = <0>; + max-bitrate = <5000000>; + /* + * Shared SILENT GPIO: CAN PHYs enter silent mode + * together (hardware design). + */ + silent-gpios = <&pcal6524 7 GPIO_ACTIVE_HIGH>; + }; + + flexcan5_phy: can-phy { + compatible = "nxp,tja1051"; + #phy-cells = <0>; + max-bitrate = <5000000>; + silent-gpios = <&pcal6524 7 GPIO_ACTIVE_HIGH>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V1.8_SW"; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_SW"; + }; + + reg_5p0v: regulator-5p0v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "+V5.0_SW"; + }; + + reg_ext_3v3: regulator-ext-3v3 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VCCEXT_3V3"; + }; + + reg_ext_5v: regulator-ext-5v { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "VCCEXT_5V"; + gpio = <&pcal6524 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_m2_ekey_pwr: regulator-m2-pwr { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "M.2-power-ekey"; + gpio = <&pcal6524 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_m2_mkey_pwr: regulator-m2-mkey-pwr { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "M.2-mkey-power"; + gpio = <&pcal6524 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + off-on-delay-us = <12000>; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VDD_SD2_3V3"; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc3_vmmc: regulator-usdhc3 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "WLAN_EN"; + vin-supply = <®_m2_ekey_pwr>; + gpio = <&pcal6524 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + /* + * IW612 wifi chip needs more delay than other wifi chips to complete + * the host interface initialization after power up, otherwise the + * internal state of IW612 may be unstable, resulting in the failure of + * the SDIO3.0 switch voltage. + */ + startup-delay-us = <20000>; + }; + + reg_usb_vbus: regulator-vbus { + compatible = "regulator-fixed"; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "USB_VBUS"; + gpio = <&pcal6524 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vref_1v8"; + }; + + reserved-memory { + ranges; + #address-cells = <2>; + #size-cells = <2>; + + linux_cma: linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x80000000 0 0x7F000000>; + reusable; + size = <0 0x3c000000>; + linux,cma-default; + }; + + vdev0vring0: memory@88000000 { + reg = <0 0x88000000 0 0x8000>; + no-map; + }; + + vdev0vring1: memory@88008000 { + reg = <0 0x88008000 0 0x8000>; + no-map; + }; + + vdev1vring0: memory@88010000 { + reg = <0 0x88010000 0 0x8000>; + no-map; + }; + + vdev1vring1: memory@88018000 { + reg = <0 0x88018000 0 0x8000>; + no-map; + }; + + vdevbuffer: memory@88020000 { + compatible = "shared-dma-pool"; + reg = <0 0x88020000 0 0x100000>; + no-map; + }; + + rsc_table: memory@88220000 { + reg = <0 0x88220000 0 0x1000>; + no-map; + }; + + vpu_boot: memory@a0000000 { + reg = <0 0xa0000000 0 0x100000>; + no-map; + }; + }; + + sound-micfil { + compatible = "fsl,imx-audio-card"; + model = "micfil-audio"; + + pri-dai-link { + link-name = "micfil hifi"; + format = "i2s"; + + cpu { + sound-dai = <&micfil>; + }; + + codec { + sound-dai = <&dmic>; + }; + }; + }; + + usdhc3_pwrseq: usdhc3-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pcal6524 8 GPIO_ACTIVE_LOW>; + }; + + memory@80000000 { + reg = <0x0 0x80000000 0 0x80000000>; + device_type = "memory"; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&enetc_port0 { + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; + pinctrl-0 = <&pinctrl_enetc0>; + pinctrl-names = "default"; + status = "okay"; +}; + +&enetc_port1 { + phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; + pinctrl-0 = <&pinctrl_enetc1>; + pinctrl-names = "default"; + status = "okay"; +}; + +&flexcan2 { + pinctrl-0 = <&pinctrl_flexcan2>; + pinctrl-names = "default"; + phys = <&flexcan2_phy>; + status = "okay"; +}; + +&flexcan5 { + pinctrl-0 = <&pinctrl_flexcan5>; + pinctrl-names = "default"; + phys = <&flexcan5_phy>; + status = "okay"; +}; + +&lpi2c2 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-names = "default"; + status = "okay"; + + pcal6524: gpio@22 { + compatible = "nxp,pcal6524"; + reg = <0x22>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&gpio5>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; + #gpio-cells = <2>; + gpio-controller; + pinctrl-0 = <&pinctrl_pcal6524>; + pinctrl-names = "default"; + gpio-line-names = "ENET1 PHY reset", + "ENET2 PHY reset", + "SPI3/GPIO select", + "UART3/GPIO select", + "CAN2&5/GPIO select", + "PWM/GPIO select", + "Watch dog enable", + "CAN1&2&5 silent", + "SDIO_nRST", + "WL_nDISABLE1", + "WL_nDISABLE2", + "M.2 Mkey NC06", + "EXT_5V0_PWR_EN", + "EXT_3V3_PWR_EN", + "Mkey power control", + "USB2 power control", + "Ekey power control", + "MIPI-DSICSI reset", + "MIPI-DSI IO2", + "MIPI-CSI reset", + "LVDS TP reset", + "LVDS BL enable", + "LVDS BL power enable", + "IT6263 reset"; + + lpspi-gpio-sel-hog { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + output-low; + }; + + lpuart-gpio-sel-hog { + gpio-hog; + gpios = <3 GPIO_ACTIVE_HIGH>; + output-low; + }; + + can-gpio-sel-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; + output-low; + }; + + pwm-gpio-sel-hog { + gpio-hog; + gpios = <5 GPIO_ACTIVE_HIGH>; + output-high; + }; + }; +}; + +&lpi2c3 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-names = "default"; + status = "okay"; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x50>; + interrupt-parent = <&gpio5>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_ptn5110>; + pinctrl-names = "default"; + + typec_con: connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + op-sink-microwatt = <15000000>; + power-role = "dual"; + self-powered; + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) + PDO_VAR(5000, 20000, 3000)>; + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + try-power-role = "sink"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec_con_hs: endpoint { + remote-endpoint = <&usb3_data_hs>; + }; + }; + + port@1 { + reg = <1>; + + typec_con_ss: endpoint { + remote-endpoint = <&usb3_data_ss>; + }; + }; + }; + }; + }; +}; + +&lpi2c4 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c4>; + pinctrl-names = "default"; + status = "okay"; + + pca9632: led-controller@62 { + compatible = "nxp,pca9632"; + reg = <0x62>; + #address-cells = <1>; + #size-cells = <0>; + nxp,inverted-out; + + led_backlight0: led@0 { + reg = <0>; + color = <LED_COLOR_ID_WHITE>; + function = LED_FUNCTION_BACKLIGHT; + function-enumerator = <0>; + }; + + led_backlight1: led@1 { + reg = <1>; + color = <LED_COLOR_ID_WHITE>; + function = LED_FUNCTION_BACKLIGHT; + function-enumerator = <1>; + }; + }; +}; + +&lpuart1 { + pinctrl-0 = <&pinctrl_uart1>; + pinctrl-names = "default"; + status = "okay"; +}; + +&lpuart5 { + pinctrl-0 = <&pinctrl_uart5>; + pinctrl-names = "default"; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +&micfil { + assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_PDM>; + assigned-clock-parents = <0>, <0>, <0>, <0>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, + <3612672000>, <393216000>, + <361267200>, <49152000>; + #sound-dai-cells = <0>; + pinctrl-0 = <&pinctrl_pdm>; + pinctrl-names = "default"; + status = "okay"; +}; + +&mu7 { + status = "okay"; +}; + +&netc_blk_ctrl { + status = "okay"; +}; + +/* Configure MSI and IOMMU mappings specific to the i.MX95 15x15 FRDM board. */ +&netc_bus0 { + msi-map = <0x0 &its 0x60 0x1>, //ENETC0 PF + <0x10 &its 0x61 0x1>, //ENETC0 VF0 + <0x20 &its 0x62 0x1>, //ENETC0 VF1 + <0x40 &its 0x63 0x1>, //ENETC1 PF + <0x50 &its 0x65 0x1>, //ENETC1 VF0 + <0x60 &its 0x66 0x1>, //ENETC1 VF1 + <0x80 &its 0x64 0x1>, //ENETC2 PF + <0xc0 &its 0x67 0x1>; //NETC Timer + iommu-map = <0x0 &smmu 0x20 0x1>, + <0x10 &smmu 0x21 0x1>, + <0x20 &smmu 0x22 0x1>, + <0x40 &smmu 0x23 0x1>, + <0x50 &smmu 0x25 0x1>, + <0x60 &smmu 0x26 0x1>, + <0x80 &smmu 0x24 0x1>, + <0xc0 &smmu 0x27 0x1>; +}; + +&netc_emdio { + pinctrl-0 = <&pinctrl_emdio>; + pinctrl-names = "default"; + status = "okay"; + + ethphy0: ethernet-phy@1 { + reg = <1>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + reset-gpios = <&pcal6524 0 GPIO_ACTIVE_LOW>; + }; + + ethphy1: ethernet-phy@2 { + reg = <2>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + reset-gpios = <&pcal6524 1 GPIO_ACTIVE_LOW>; + }; +}; + +&netc_timer { + status = "okay"; +}; + +&netcmix_blk_ctrl { + status = "okay"; +}; + +&pcie0 { + pinctrl-0 = <&pinctrl_pcie0>; + pinctrl-names = "default"; + reset-gpio = <&gpio5 13 GPIO_ACTIVE_LOW>; + supports-clkreq; + vpcie-supply = <®_m2_mkey_pwr>; + status = "okay"; +}; + +&scmi_iomuxc { + pinctrl_emdio: emdiogrp { + fsl,pins = < + IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC 0x50e + IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO 0x90e + >; + }; + + pinctrl_enetc0: enetc0grp { + fsl,pins = < + IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x50e + IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x50e + IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x50e + IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x50e + IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e + IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e + IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e + IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e + IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e + IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e + IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e + IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e + >; + }; + + pinctrl_enetc1: enetc1grp { + fsl,pins = < + IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x50e + IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x50e + IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x50e + IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x50e + IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x57e + IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x58e + IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x57e + IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK 0x58e + IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0 0x57e + IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1 0x57e + IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2 0x57e + IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3 0x57e + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + IMX95_PAD_GPIO_IO25__CAN2_TX 0x39e + IMX95_PAD_GPIO_IO27__CAN2_RX 0x39e + >; + }; + + pinctrl_flexcan5: flexcan5grp { + fsl,pins = < + IMX95_PAD_GPIO_IO22__CAN5_TX 0x39e + IMX95_PAD_GPIO_IO23__CAN5_RX 0x39e + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + IMX95_PAD_I2C1_SCL__AONMIX_TOP_LPI2C1_SCL 0x40000b9e + IMX95_PAD_I2C1_SDA__AONMIX_TOP_LPI2C1_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x40000b9e + IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_lpi2c4: lpi2c4grp { + fsl,pins = < + IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40000b9e + IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40000b9e + >; + }; + + pinctrl_pcal6524: pcal6524grp { + fsl,pins = < + IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x31e + >; + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins = < + IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x40000b1e + IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13 0x31e + >; + }; + + pinctrl_pdm: pdmgrp { + fsl,pins = < + IMX95_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK 0x31e + IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_BIT0 0x31e + >; + }; + + pinctrl_ptn5110: ptn5110grp { + fsl,pins = < + IMX95_PAD_XSPI1_DATA3__GPIO5_IO_BIT3 0x31e + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e + IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + IMX95_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e + IMX95_PAD_DAP_TDI__LPUART5_RX 0x31e + IMX95_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e + IMX95_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e + IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e + IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e + IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e + IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e + IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e + IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e + IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e + IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e + IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e + IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + IMX95_PAD_SD3_CLK__USDHC3_CLK 0x15fe + IMX95_PAD_SD3_CMD__USDHC3_CMD 0x13fe + IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe + IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe + IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe + IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe + >; + }; +}; + +&scmi_misc { + nxp,ctrl-ids = <BRD_SM_CTRL_SD3_WAKE 1 + BRD_SM_CTRL_PCIE1_WAKE 1 + BRD_SM_CTRL_BT_WAKE 1 + BRD_SM_CTRL_PCIE2_WAKE 1 + BRD_SM_CTRL_BUTTON 1>; +}; + +&thermal_zones { + pf09-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 2>; + + trips { + pf09_alert: trip0 { + hysteresis = <2000>; + temperature = <140000>; + type = "passive"; + }; + + pf09_crit: trip1 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; + + pf53arm-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 4>; + + cooling-maps { + map0 { + cooling-device = <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + trip = <&pf5301_alert>; + }; + }; + + trips { + pf5301_alert: trip0 { + hysteresis = <2000>; + temperature = <140000>; + type = "passive"; + }; + + pf5301_crit: trip1 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; + + pf53soc-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 3>; + + trips { + pf5302_alert: trip0 { + hysteresis = <2000>; + temperature = <140000>; + type = "passive"; + }; + + pf5302_crit: trip1 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; +}; + +&usb2 { + disable-over-current; + dr_mode = "host"; + vbus-supply = <®_usb_vbus>; + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + adp-disable; + dr_mode = "otg"; + hnp-disable; + role-switch-default-mode = "peripheral"; + srp-disable; + usb-role-switch; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + status = "okay"; + + port { + usb3_data_hs: endpoint { + remote-endpoint = <&typec_con_hs>; + }; + }; +}; + +&usb3_phy { + orientation-switch; + fsl,phy-pcs-tx-deemph-3p5db-attenuation-db = <17>; + fsl,phy-pcs-tx-swing-full-percent = <100>; + fsl,phy-tx-preemp-amp-tune-microamp = <600>; + fsl,phy-tx-vboost-level-microvolt = <1156>; + fsl,phy-tx-vref-tune-percent = <100>; + status = "okay"; + + port { + usb3_data_ss: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; +}; + +&usdhc1 { + bus-width = <8>; + non-removable; + no-sd; + no-sdio; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pinctrl-3 = <&pinctrl_usdhc1>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + fsl,tuning-step = <1>; + status = "okay"; +}; + +&usdhc2 { + bus-width = <4>; + cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + vmmc-supply = <®_usdhc2_vmmc>; + fsl,tuning-step = <1>; + status = "okay"; +}; + +&usdhc3 { + bus-width = <4>; + keep-power-in-suspend; + mmc-pwrseq = <&usdhc3_pwrseq>; + non-removable; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + pinctrl-3 = <&pinctrl_usdhc3>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + vmmc-supply = <®_usdhc3_vmmc>; + wakeup-source; + status = "okay"; +}; + +&wdog3 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx95-clock.h b/arch/arm64/boot/dts/freescale/imx95-clock.h index e1f91203e794..22311612e440 100644 --- a/arch/arm64/boot/dts/freescale/imx95-clock.h +++ b/arch/arm64/boot/dts/freescale/imx95-clock.h @@ -183,5 +183,6 @@ #define IMX95_CLK_SEL_A55P (IMX95_CCM_NUM_CLK_SRC + 123 + 7) #define IMX95_CLK_SEL_DRAM (IMX95_CCM_NUM_CLK_SRC + 123 + 8) #define IMX95_CLK_SEL_TEMPSENSE (IMX95_CCM_NUM_CLK_SRC + 123 + 9) +#define IMX95_CLK_GPU_CGC (IMX95_CCM_NUM_CLK_SRC + 123 + 10) #endif /* __CLOCK_IMX95_H */ diff --git a/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi b/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi index 115a16e44a99..5932ba238a8a 100644 --- a/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi @@ -153,7 +153,7 @@ compatible = "shared-dma-pool"; reusable; size = <0 0x3c000000>; - alloc-ranges = <0 0x80000000 0 0x7F000000>; + alloc-ranges = <0 0x80000000 0 0x7f000000>; linux,cma-default; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx95-tqma9596sa.dtsi b/arch/arm64/boot/dts/freescale/imx95-tqma9596sa.dtsi index 43418844701b..456129f4a682 100644 --- a/arch/arm64/boot/dts/freescale/imx95-tqma9596sa.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95-tqma9596sa.dtsi @@ -40,7 +40,7 @@ linux,cma-default; }; - vpu_boot: vpu_boot@a0000000 { + vpu_boot: vpu-boot@a0000000 { reg = <0 0xa0000000 0 0x100000>; no-map; }; diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index a4d854817559..55e2da094c88 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -2164,7 +2164,7 @@ gpu: gpu@4d900000 { compatible = "nxp,imx95-mali", "arm,mali-valhall-csf"; reg = <0 0x4d900000 0 0x480000>; - clocks = <&scmi_clk IMX95_CLK_GPU>, <&scmi_clk IMX95_CLK_GPUAPB>; + clocks = <&scmi_clk IMX95_CLK_GPU_CGC>, <&scmi_clk IMX95_CLK_GPUAPB>; clock-names = "core", "coregroup"; interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm64/boot/dts/freescale/imx952-clock.h b/arch/arm64/boot/dts/freescale/imx952-clock.h new file mode 100644 index 000000000000..7d6f6635dc07 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx952-clock.h @@ -0,0 +1,215 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +/* + * Copyright 2025 NXP + */ + +#ifndef __CLOCK_IMX952_H__ +#define __CLOCK_IMX952_H__ + +/* Clock Source */ +#define IMX952_CLK_EXT 0 +#define IMX952_CLK_OSC32K 1 +#define IMX952_CLK_OSC24M 2 +#define IMX952_CLK_FRO 3 +#define IMX952_CLK_SYSPLL1_VCO 4 +#define IMX952_CLK_SYSPLL1_PFD0_UNGATED 5 +#define IMX952_CLK_SYSPLL1_PFD0 6 +#define IMX952_CLK_SYSPLL1_PFD0_DIV2 7 +#define IMX952_CLK_SYSPLL1_PFD1_UNGATED 8 +#define IMX952_CLK_SYSPLL1_PFD1 9 +#define IMX952_CLK_SYSPLL1_PFD1_DIV2 10 +#define IMX952_CLK_SYSPLL1_PFD2_UNGATED 11 +#define IMX952_CLK_SYSPLL1_PFD2 12 +#define IMX952_CLK_SYSPLL1_PFD2_DIV2 13 +#define IMX952_CLK_AUDIOPLL1_VCO 14 +#define IMX952_CLK_AUDIOPLL1 15 +#define IMX952_CLK_AUDIOPLL2_VCO 16 +#define IMX952_CLK_AUDIOPLL2 17 +#define IMX952_CLK_VIDEOPLL1_VCO 18 +#define IMX952_CLK_VIDEOPLL1 19 +#define IMX952_CLK_SRC_RESERVED20 20 +#define IMX952_CLK_SYSPLL1_PFD3_UNGATED 21 +#define IMX952_CLK_SYSPLL1_PFD3 22 +#define IMX952_CLK_SYSPLL1_PFD3_DIV2 23 +#define IMX952_CLK_ARMPLL_VCO 24 +#define IMX952_CLK_ARMPLL_PFD0_UNGATED 25 +#define IMX952_CLK_ARMPLL_PFD0 26 +#define IMX952_CLK_ARMPLL_PFD1_UNGATED 27 +#define IMX952_CLK_ARMPLL_PFD1 28 +#define IMX952_CLK_ARMPLL_PFD2_UNGATED 29 +#define IMX952_CLK_ARMPLL_PFD2 30 +#define IMX952_CLK_ARMPLL_PFD3_UNGATED 31 +#define IMX952_CLK_ARMPLL_PFD3 32 +#define IMX952_CLK_DRAMPLL_VCO 33 +#define IMX952_CLK_DRAMPLL 34 +#define IMX952_CLK_HSIOPLL_VCO 35 +#define IMX952_CLK_HSIOPLL 36 +#define IMX952_CLK_LDBPLL_VCO 37 +#define IMX952_CLK_LDBPLL 38 +#define IMX952_CLK_EXT1 39 +#define IMX952_CLK_EXT2 40 + +/* Clock ROOT */ +#define IMX952_CLK_ADC 41 +#define IMX952_CLK_RESERVED1 42 +#define IMX952_CLK_BUSAON 43 +#define IMX952_CLK_CAN1 44 +#define IMX952_CLK_RESERVED4 45 +#define IMX952_CLK_I3C1SLOW 46 +#define IMX952_CLK_LPI2C1 47 +#define IMX952_CLK_LPI2C2 48 +#define IMX952_CLK_LPSPI1 49 +#define IMX952_CLK_LPSPI2 50 +#define IMX952_CLK_LPTMR1 51 +#define IMX952_CLK_LPUART1 52 +#define IMX952_CLK_LPUART2 53 +#define IMX952_CLK_M33 54 +#define IMX952_CLK_M33SYSTICK 55 +#define IMX952_CLK_RESERVED15 56 +#define IMX952_CLK_PDM 57 +#define IMX952_CLK_SAI1 58 +#define IMX952_CLK_RESERVED18 59 +#define IMX952_CLK_TPM2 60 +#define IMX952_CLK_RESERVED20 61 +#define IMX952_CLK_CAMAPB 62 +#define IMX952_CLK_CAMAXI 63 +#define IMX952_CLK_CAMCM0 64 +#define IMX952_CLK_CAMISI 65 +#define IMX952_CLK_CAMPHYCFG 66 +#define IMX952_CLK_MIPIPHYPLLBYPASS 67 +#define IMX952_CLK_RESERVED27 68 +#define IMX952_CLK_MIPITESTBYTE 69 +#define IMX952_CLK_A55 70 +#define IMX952_CLK_A55MTRBUS 71 +#define IMX952_CLK_A55PERIPH 72 +#define IMX952_CLK_DRAMALT 73 +#define IMX952_CLK_DRAMAPB 74 +#define IMX952_CLK_DISPAPB 75 +#define IMX952_CLK_DISPAXI 76 +#define IMX952_CLK_DISPLPSPI 77 +#define IMX952_CLK_DISPOCRAM 78 +#define IMX952_CLK_DISPPHYCFG 79 +#define IMX952_CLK_DISP1PIX 80 +#define IMX952_CLK_DISPCDPHYAPB 81 +#define IMX952_CLK_RESERVED41 82 +#define IMX952_CLK_GPUAPB 83 +#define IMX952_CLK_GPU 84 +#define IMX952_CLK_HSIOACSCAN480M 85 +#define IMX952_CLK_HSIOACSCAN80M 86 +#define IMX952_CLK_HSIO 87 +#define IMX952_CLK_HSIOPCIEAUX 88 +#define IMX952_CLK_HSIOPCIETEST160M 89 +#define IMX952_CLK_HSIOPCIETEST400M 90 +#define IMX952_CLK_HSIOPCIETEST500M 91 +#define IMX952_CLK_HSIOUSBTEST50M 92 +#define IMX952_CLK_HSIOUSBTEST60M 93 +#define IMX952_CLK_BUSM7 94 +#define IMX952_CLK_M7 95 +#define IMX952_CLK_M7SYSTICK 96 +#define IMX952_CLK_BUSNETCMIX 97 +#define IMX952_CLK_ENET 98 +#define IMX952_CLK_ENETPHYTEST200M 99 +#define IMX952_CLK_ENETPHYTEST500M 100 +#define IMX952_CLK_ENETPHYTEST667M 101 +#define IMX952_CLK_ENETREF 102 +#define IMX952_CLK_ENETTIMER1 103 +#define IMX952_CLK_RESERVED63 104 +#define IMX952_CLK_SAI2 105 +#define IMX952_CLK_NOCAPB 106 +#define IMX952_CLK_NOC 107 +#define IMX952_CLK_NPUAPB 108 +#define IMX952_CLK_NPU 109 +#define IMX952_CLK_CCMCKO1 110 +#define IMX952_CLK_CCMCKO2 111 +#define IMX952_CLK_CCMCKO3 112 +#define IMX952_CLK_CCMCKO4 113 +#define IMX952_CLK_VPUAPB 114 +#define IMX952_CLK_VPU 115 +#define IMX952_CLK_RESERVED75 116 +#define IMX952_CLK_RESERVED76 117 +#define IMX952_CLK_AUDIOXCVR 118 +#define IMX952_CLK_BUSWAKEUP 119 +#define IMX952_CLK_CAN2 120 +#define IMX952_CLK_CAN3 121 +#define IMX952_CLK_CAN4 122 +#define IMX952_CLK_CAN5 123 +#define IMX952_CLK_FLEXIO1 124 +#define IMX952_CLK_FLEXIO2 125 +#define IMX952_CLK_XSPI1 126 +#define IMX952_CLK_RESERVED86 127 +#define IMX952_CLK_I3C2SLOW 128 +#define IMX952_CLK_LPI2C3 129 +#define IMX952_CLK_LPI2C4 130 +#define IMX952_CLK_LPI2C5 131 +#define IMX952_CLK_LPI2C6 132 +#define IMX952_CLK_LPI2C7 133 +#define IMX952_CLK_LPI2C8 134 +#define IMX952_CLK_LPSPI3 135 +#define IMX952_CLK_LPSPI4 136 +#define IMX952_CLK_LPSPI5 137 +#define IMX952_CLK_LPSPI6 138 +#define IMX952_CLK_LPSPI7 139 +#define IMX952_CLK_LPSPI8 140 +#define IMX952_CLK_LPTMR2 141 +#define IMX952_CLK_LPUART3 142 +#define IMX952_CLK_LPUART4 143 +#define IMX952_CLK_LPUART5 144 +#define IMX952_CLK_LPUART6 145 +#define IMX952_CLK_LPUART7 146 +#define IMX952_CLK_LPUART8 147 +#define IMX952_CLK_SAI3 148 +#define IMX952_CLK_SAI4 149 +#define IMX952_CLK_SAI5 150 +#define IMX952_CLK_SPDIF 151 +#define IMX952_CLK_SWOTRACE 152 +#define IMX952_CLK_TPM4 153 +#define IMX952_CLK_TPM5 154 +#define IMX952_CLK_TPM6 155 +#define IMX952_CLK_MIPIPHYDFT400 156 +#define IMX952_CLK_MIPIPHYDFT540 157 +#define IMX952_CLK_USDHC1 158 +#define IMX952_CLK_USDHC2 159 +#define IMX952_CLK_USDHC3 160 +#define IMX952_CLK_V2XPK 161 +#define IMX952_CLK_WAKEUPAXI 162 +#define IMX952_CLK_XSPISLVROOT 163 +#define IMX952_CLK_AUDMIX1 164 +#define IMX952_CLK_ASRC1 165 +#define IMX952_CLK_ASRC2 166 +#define IMX952_CLK_GPT1 167 +#define IMX952_CLK_GPT2 168 +#define IMX952_CLK_GPT3 169 +#define IMX952_CLK_GPT4 170 + +/* Clock GPR SEL */ +#define IMX952_CLK_GPR_SEL_EXT 171 +#define IMX952_CLK_GPR_SEL_A55C0 172 +#define IMX952_CLK_GPR_SEL_A55C1 173 +#define IMX952_CLK_GPR_SEL_A55C2 174 +#define IMX952_CLK_GPR_SEL_A55C3 175 +#define IMX952_CLK_GPR_SEL_A55P 176 +#define IMX952_CLK_GPR_SEL_DRAM 177 +#define IMX952_CLK_GPR_SEL_TEMPSENSE 178 + +/* Clock CGC */ +#define IMX952_CLK_CGC_NPU 179 +#define IMX952_CLK_CGC_GPU 180 +#define IMX952_CLK_CGC_CAMISI 181 +#define IMX952_CLK_CGC_CAMISP 182 +#define IMX952_CLK_CGC_CAMCSI0 183 +#define IMX952_CLK_CGC_CAMCSI1 184 +#define IMX952_CLK_CGC_CAMOCRAM 185 +#define IMX952_CLK_CGC_HSIOUSB 186 +#define IMX952_CLK_CGC_HSIOPCIE 187 +#define IMX952_CLK_CGC_DISPOCRAM 188 +#define IMX952_CLK_CGC_DISPSEERIS 189 +#define IMX952_CLK_CGC_DISPDSI 190 +#define IMX952_CLK_CGC_NOCGIC 191 +#define IMX952_CLK_CGC_NOCOCRAM 192 +#define IMX952_CLK_CGC_NETC 193 +#define IMX952_CLK_CGC_VPUENC 194 +#define IMX952_CLK_CGC_VPUJPEGENC 195 +#define IMX952_CLK_CGC_VPUJPEGDEC 196 +#define IMX952_CLK_CGC_VPUDEC 197 + +#endif diff --git a/arch/arm64/boot/dts/freescale/imx952-evk.dts b/arch/arm64/boot/dts/freescale/imx952-evk.dts new file mode 100644 index 000000000000..b838323468d4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx952-evk.dts @@ -0,0 +1,596 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025-2026 NXP + */ + +/dts-v1/; + +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/usb/pd.h> +#include "imx952.dtsi" + +#define FALLING_EDGE BIT(0) +#define RISING_EDGE BIT(1) + +#define BRD_SM_CTRL_SD3_WAKE 0x8000U /*!< PCAL6408A-0 */ +#define BRD_SM_CTRL_M2E_WAKE 0x8001U /*!< PCAL6408A-4 */ +#define BRD_SM_CTRL_BT_WAKE 0x8002U /*!< PCAL6408A-5 */ +#define BRD_SM_CTRL_M2M_WAKE 0x8003U /*!< PCAL6408A-6 */ +#define BRD_SM_CTRL_BUTTON 0x8004U /*!< PCAL6408A-7 */ + +/ { + model = "NXP i.MX952 EVK board"; + compatible = "fsl,imx952-evk", "fsl,imx952"; + + aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + i2c3 = &lpi2c4; + i2c4 = &lpi2c5; + i2c5 = &lpi2c6; + i2c6 = &lpi2c7; + i2c7 = &lpi2c8; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + serial0 = &lpuart1; + serial4 = &lpuart5; + spi6 = &lpspi7; + }; + + chosen { + stdout-path = &lpuart1; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0 0x80000000>; + }; + + fan0: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + pwms = <&tpm6 2 4000000 PWM_POLARITY_INVERTED>; + cooling-levels = <64 128 192 255>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux_cma: linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x80000000 0 0x7f000000>; + size = <0 0x3c000000>; + linux,cma-default; + reusable; + }; + }; + + flexcan1_phy: can-phy0 { + compatible = "nxp,tjr1443"; + #phy-cells = <0>; + max-bitrate = <8000000>; + enable-gpios = <&pcal6416 6 GPIO_ACTIVE_HIGH>; + standby-gpios = <&pcal6416 5 GPIO_ACTIVE_LOW>; + }; + + flexcan2_phy: can-phy1 { + compatible = "nxp,tjr1443"; + #phy-cells = <0>; + max-bitrate = <8000000>; + enable-gpios = <&i2c4_pcal6408 4 GPIO_ACTIVE_HIGH>; + standby-gpios = <&i2c4_pcal6408 3 GPIO_ACTIVE_LOW>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_SW"; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V1.8_SW"; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VDD_SD2_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us = <12000>; + }; + + reg_usb_vbus: regulator-vbus { + compatible = "regulator-fixed"; + regulator-name = "USB_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pcal6524 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + +}; + +/* pin conflict with PDM */ +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + phys = <&flexcan1_phy>; + status = "disabled"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + phys = <&flexcan2_phy>; + status = "okay"; +}; + +&lpi2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c2>; + status = "okay"; + + adp5585: io-expander@34 { + compatible = "adi,adp5585-00", "adi,adp5585"; + reg = <0x34>; + gpio-controller; + #gpio-cells = <2>; + gpio-reserved-ranges = <5 1>; + #pwm-cells = <3>; + }; +}; + +&lpi2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c3>; + status = "okay"; + + i2c3_pcal6408: gpio@20 { + compatible = "nxp,pcal6408"; + reg = <0x20>; + #gpio-cells = <2>; + gpio-controller; + vcc-supply = <®_3p3v>; + }; +}; + +&lpi2c4 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c4>; + status = "okay"; + + i2c4_pcal6408: gpio@21 { + compatible = "nxp,pcal6408"; + reg = <0x21>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio2>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4_pcal6408>; + vcc-supply = <®_3p3v>; + }; +}; + +&lpi2c6 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c6>; + status = "okay"; + + pcal6416: gpio@21 { + compatible = "nxp,pcal6416"; + #gpio-cells = <2>; + gpio-controller; + reg = <0x21>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio2>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcal6416>; + vcc-supply = <®_3p3v>; + + pdm-can-sel-hog { + gpio-hog; + gpios = <10 GPIO_ACTIVE_HIGH>; + output-low; + }; + + mqs-en-hog { + gpio-hog; + gpios = <15 GPIO_ACTIVE_HIGH>; + output-low; + }; + }; +}; + +&lpi2c7 { + clock-frequency = <1000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c7>; + status = "okay"; + + pcal6524: gpio@22 { + compatible = "nxp,pcal6524"; + reg = <0x22>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcal6524>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio5>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + }; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x50>; + interrupt-parent = <&gpio5>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ptn5110>; + + typec_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + sink-pdos = <PDO_FIXED(5000, 0, PDO_FIXED_USB_COMM)>; + op-sink-microwatt = <0>; + self-powered; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + }; + }; + }; +}; + +&lpuart1 { + /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&lpuart5 { + /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +&lpspi7 { + cs-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi7>; + status = "okay"; +}; + +&scmi_misc { + nxp,ctrl-ids = <BRD_SM_CTRL_SD3_WAKE 1 + BRD_SM_CTRL_M2E_WAKE 1 + BRD_SM_CTRL_BT_WAKE 1 + BRD_SM_CTRL_M2M_WAKE 1 + BRD_SM_CTRL_BUTTON 1>; +}; + +&tpm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm3>; + status = "okay"; +}; + +&tpm6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm6>; + status = "okay"; +}; + +&usb1 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&usb2 { + dr_mode = "host"; + disable-over-current; + vbus-supply = <®_usb_vbus>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pinctrl-3 = <&pinctrl_usdhc1>; + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; +}; + +&wdog3 { + fsl,ext-reset-output; + status = "okay"; +}; + +&scmi_iomuxc { + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + IMX952_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX 0x39e + IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX 0x39e + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_CAN2_TX 0x39e + IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_CAN2_RX 0x39e + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + IMX952_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x40000b9e + IMX952_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + IMX952_PAD_GPIO_IO00__WAKEUPMIX_TOP_LPI2C3_SDA 0x40000b9e + IMX952_PAD_GPIO_IO01__WAKEUPMIX_TOP_LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_lpi2c4: lpi2c4grp { + fsl,pins = < + IMX952_PAD_GPIO_IO30__WAKEUPMIX_TOP_LPI2C4_SDA 0x40000b9e + IMX952_PAD_GPIO_IO31__WAKEUPMIX_TOP_LPI2C4_SCL 0x40000b9e + >; + }; + + pinctrl_i2c4_pcal6408: i2c4pcal6408grp { + fsl,pins = < + IMX952_PAD_GPIO_IO18__WAKEUPMIX_TOP_GPIO2_IO_18 0x31e + >; + }; + + pinctrl_lpi2c6: lpi2c6grp { + fsl,pins = < + IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_LPI2C6_SDA 0x40000b9e + IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_LPI2C6_SCL 0x40000b9e + >; + }; + + pinctrl_lpi2c7: lpi2c7grp { + fsl,pins = < + IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_LPI2C7_SDA 0x40000b9e + IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_LPI2C7_SCL 0x40000b9e + >; + }; + + pinctrl_lpspi7: lpspi7grp { + fsl,pins = < + IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_GPIO2_IO_4 0x39e + IMX952_PAD_GPIO_IO05__WAKEUPMIX_TOP_LPSPI7_SIN 0x39e + IMX952_PAD_GPIO_IO06__WAKEUPMIX_TOP_LPSPI7_SOUT 0x39e + IMX952_PAD_GPIO_IO07__WAKEUPMIX_TOP_LPSPI7_SCK 0x39e + >; + }; + + pinctrl_pcal6416: pcal6416grp { + fsl,pins = < + IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_GPIO2_IO_10 0x31e + >; + }; + + pinctrl_pcal6524: pcal6524grp { + fsl,pins = < + IMX952_PAD_GPIO_IO36__WAKEUPMIX_TOP_GPIO5_IO_16 0x31e + >; + }; + + pinctrl_ptn5110: ptn5110grp { + fsl,pins = < + IMX952_PAD_GPIO_IO34__WAKEUPMIX_TOP_GPIO5_IO_14 0x31e + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + IMX952_PAD_SD2_RESET_B__WAKEUPMIX_TOP_GPIO3_IO_7 0x31e + >; + }; + + pinctrl_tpm3: tpm3grp { + fsl,pins = < + IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_TPM3_CH2 0x51e + >; + }; + + pinctrl_tpm6: tpm6grp { + fsl,pins = < + IMX952_PAD_GPIO_IO19__WAKEUPMIX_TOP_TPM6_CH2 0x51e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + IMX952_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e + IMX952_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + IMX952_PAD_DAP_TDO_TRACESWO__WAKEUPMIX_TOP_LPUART5_TX 0x31e + IMX952_PAD_DAP_TDI__WAKEUPMIX_TOP_LPUART5_RX 0x31e + IMX952_PAD_DAP_TMS_SWDIO__WAKEUPMIX_TOP_LPUART5_RTS_B 0x31e + IMX952_PAD_DAP_TCLK_SWCLK__WAKEUPMIX_TOP_LPUART5_CTS_B 0x31e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_USDHC1_CLK 0x158e + IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_USDHC1_CMD 0x138e + IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_USDHC1_DATA0 0x138e + IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_USDHC1_DATA1 0x138e + IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_USDHC1_DATA2 0x138e + IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_USDHC1_DATA3 0x138e + IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_USDHC1_DATA4 0x138e + IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_USDHC1_DATA5 0x138e + IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_USDHC1_DATA6 0x138e + IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_USDHC1_DATA7 0x138e + IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_USDHC1_CLK 0x158e + IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_USDHC1_CMD 0x138e + IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_USDHC1_DATA0 0x138e + IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_USDHC1_DATA1 0x138e + IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_USDHC1_DATA2 0x138e + IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_USDHC1_DATA3 0x138e + IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_USDHC1_DATA4 0x138e + IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_USDHC1_DATA5 0x138e + IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_USDHC1_DATA6 0x138e + IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_USDHC1_DATA7 0x138e + IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_USDHC1_CLK 0x159e + IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_USDHC1_CMD 0x139e + IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_USDHC1_DATA0 0x139e + IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_USDHC1_DATA1 0x139e + IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_USDHC1_DATA2 0x139e + IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_USDHC1_DATA3 0x139e + IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_USDHC1_DATA4 0x139e + IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_USDHC1_DATA5 0x139e + IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_USDHC1_DATA6 0x139e + IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_USDHC1_DATA7 0x139e + IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_USDHC1_STROBE 0x159e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_USDHC2_CLK 0x158e + IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_USDHC2_CMD 0x138e + IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_USDHC2_DATA0 0x138e + IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_USDHC2_DATA1 0x138e + IMX952_PAD_SD2_DATA2__WAKEUPMIX_TOP_USDHC2_DATA2 0x138e + IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_USDHC2_DATA3 0x138e + IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_USDHC2_CLK 0x158e + IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_USDHC2_CMD 0x138e + IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_USDHC2_DATA0 0x138e + IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_USDHC2_DATA1 0x138e + IMX952_PAD_SD2_DATA2__WAKEUPMIX_TOP_USDHC2_DATA2 0x138e + IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_USDHC2_DATA3 0x138e + IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_USDHC2_CLK 0x158e + IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_USDHC2_CMD 0x138e + IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_USDHC2_DATA0 0x138e + IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_USDHC2_DATA1 0x138e + IMX952_PAD_SD2_DATA2__WAKEUPMIX_TOP_USDHC2_DATA2 0x138e + IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_USDHC2_DATA3 0x138e + IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + IMX952_PAD_SD2_CD_B__WAKEUPMIX_TOP_GPIO3_IO_0 0x31e + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx952-pinfunc.h b/arch/arm64/boot/dts/freescale/imx952-pinfunc.h new file mode 100644 index 000000000000..debe6ede2d70 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx952-pinfunc.h @@ -0,0 +1,867 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright 2025 NXP + */ + +#ifndef __DTS_IMX952_PINFUNC_H__ +#define __DTS_IMX952_PINFUNC_H__ + +/* + * The pin function ID is a tuple of + * <mux_reg conf_reg input_reg mux_mode input_val> + */ +#define IMX952_PAD_DAP_TDI__WAKEUPMIX_TOP_TDI 0x0000 0x0230 0x05FC 0x00 0x00 +#define IMX952_PAD_DAP_TDI__NETCMIX_TOP_MQS2_LEFT 0x0000 0x0230 0x0000 0x01 0x00 +#define IMX952_PAD_DAP_TDI__NETCMIX_TOP_NETC_TMR_1588_ALARM1 0x0000 0x0230 0x0000 0x02 0x00 +#define IMX952_PAD_DAP_TDI__WAKEUPMIX_TOP_CAN2_TX 0x0000 0x0230 0x0000 0x03 0x00 +#define IMX952_PAD_DAP_TDI__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_30 0x0000 0x0230 0x0000 0x04 0x00 +#define IMX952_PAD_DAP_TDI__WAKEUPMIX_TOP_GPIO3_IO_28 0x0000 0x0230 0x0000 0x05 0x00 +#define IMX952_PAD_DAP_TDI__WAKEUPMIX_TOP_LPUART5_RX 0x0000 0x0230 0x059C 0x06 0x00 + +#define IMX952_PAD_DAP_TMS_SWDIO__WAKEUPMIX_TOP_TMS 0x0004 0x0234 0x0600 0x00 0x00 +#define IMX952_PAD_DAP_TMS_SWDIO__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_31 0x0004 0x0234 0x0000 0x04 0x00 +#define IMX952_PAD_DAP_TMS_SWDIO__WAKEUPMIX_TOP_GPIO3_IO_29 0x0004 0x0234 0x0000 0x05 0x00 +#define IMX952_PAD_DAP_TMS_SWDIO__WAKEUPMIX_TOP_LPUART5_RTS_B 0x0004 0x0234 0x0000 0x06 0x00 + +#define IMX952_PAD_DAP_TCLK_SWCLK__WAKEUPMIX_TOP_TCK 0x0008 0x0238 0x05F8 0x00 0x00 +#define IMX952_PAD_DAP_TCLK_SWCLK__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_30 0x0008 0x0238 0x04B4 0x04 0x00 +#define IMX952_PAD_DAP_TCLK_SWCLK__WAKEUPMIX_TOP_GPIO3_IO_30 0x0008 0x0238 0x0000 0x05 0x00 +#define IMX952_PAD_DAP_TCLK_SWCLK__WAKEUPMIX_TOP_LPUART5_CTS_B 0x0008 0x0238 0x0598 0x06 0x00 + +#define IMX952_PAD_DAP_TDO_TRACESWO__WAKEUPMIX_TOP_TDO 0x000C 0x023C 0x0000 0x00 0x00 +#define IMX952_PAD_DAP_TDO_TRACESWO__NETCMIX_TOP_MQS2_RIGHT 0x000C 0x023C 0x0000 0x01 0x00 +#define IMX952_PAD_DAP_TDO_TRACESWO__NETCMIX_TOP_NETC_TMR_1588_ALARM2 0x000C 0x023C 0x0000 0x02 0x00 +#define IMX952_PAD_DAP_TDO_TRACESWO__WAKEUPMIX_TOP_CAN2_RX 0x000C 0x023C 0x04A4 0x03 0x00 +#define IMX952_PAD_DAP_TDO_TRACESWO__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_31 0x000C 0x023C 0x04B8 0x04 0x00 +#define IMX952_PAD_DAP_TDO_TRACESWO__WAKEUPMIX_TOP_GPIO3_IO_31 0x000C 0x023C 0x0000 0x05 0x00 +#define IMX952_PAD_DAP_TDO_TRACESWO__WAKEUPMIX_TOP_LPUART5_TX 0x000C 0x023C 0x05A0 0x06 0x00 + +#define IMX952_PAD_GPIO_IO00__WAKEUPMIX_TOP_GPIO2_IO_0 0x0010 0x0240 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO00__WAKEUPMIX_TOP_LPI2C3_SDA 0x0010 0x0240 0x0530 0x01 0x00 +#define IMX952_PAD_GPIO_IO00__WAKEUPMIX_TOP_GPTMUX_INOUT0 0x0010 0x0240 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO00__WAKEUPMIX_TOP_LPSPI6_PCS0 0x0010 0x0240 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO00__WAKEUPMIX_TOP_LPUART5_TX 0x0010 0x0240 0x05A0 0x05 0x01 +#define IMX952_PAD_GPIO_IO00__WAKEUPMIX_TOP_LPI2C5_SDA 0x0010 0x0240 0x0540 0x06 0x00 +#define IMX952_PAD_GPIO_IO00__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_0 0x0010 0x0240 0x04BC 0x07 0x00 + +#define IMX952_PAD_GPIO_IO01__WAKEUPMIX_TOP_GPIO2_IO_1 0x0014 0x0244 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO01__WAKEUPMIX_TOP_LPI2C3_SCL 0x0014 0x0244 0x052C 0x01 0x00 +#define IMX952_PAD_GPIO_IO01__WAKEUPMIX_TOP_GPTMUX_INOUT1 0x0014 0x0244 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO01__WAKEUPMIX_TOP_LPSPI6_SIN 0x0014 0x0244 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO01__WAKEUPMIX_TOP_LPUART5_RX 0x0014 0x0244 0x059C 0x05 0x01 +#define IMX952_PAD_GPIO_IO01__WAKEUPMIX_TOP_LPI2C5_SCL 0x0014 0x0244 0x053C 0x06 0x00 +#define IMX952_PAD_GPIO_IO01__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_1 0x0014 0x0244 0x04C0 0x07 0x00 + +#define IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_GPIO2_IO_2 0x0018 0x0248 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_LPI2C4_SDA 0x0018 0x0248 0x0538 0x01 0x00 +#define IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_GPTMUX_INOUT2 0x0018 0x0248 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_LPSPI6_SOUT 0x0018 0x0248 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_LPUART5_CTS_B 0x0018 0x0248 0x0598 0x05 0x01 +#define IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_LPI2C6_SDA 0x0018 0x0248 0x0548 0x06 0x00 +#define IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_2 0x0018 0x0248 0x04C4 0x07 0x00 + +#define IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_GPIO2_IO_3 0x001C 0x024C 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_LPI2C4_SCL 0x001C 0x024C 0x0534 0x01 0x00 +#define IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_GPTMUX_INOUT3 0x001C 0x024C 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_LPSPI6_SCK 0x001C 0x024C 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_LPUART5_RTS_B 0x001C 0x024C 0x0000 0x05 0x00 +#define IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_LPI2C6_SCL 0x001C 0x024C 0x0544 0x06 0x00 +#define IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_3 0x001C 0x024C 0x04C8 0x07 0x00 + +#define IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_GPIO2_IO_4 0x0020 0x0250 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_TPM3_CH0 0x0020 0x0250 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO04__AONMIX_TOP_PDM_CLK 0x0020 0x0250 0x0000 0x02 0x00 +#define IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_GPTMUX_INOUT4 0x0020 0x0250 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_LPSPI7_PCS0 0x0020 0x0250 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_LPUART6_TX 0x0020 0x0250 0x05AC 0x05 0x00 +#define IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_LPI2C6_SDA 0x0020 0x0250 0x0548 0x06 0x01 +#define IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_4 0x0020 0x0250 0x04CC 0x07 0x00 + +#define IMX952_PAD_GPIO_IO05__WAKEUPMIX_TOP_GPIO2_IO_5 0x0024 0x0254 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO05__WAKEUPMIX_TOP_TPM4_CH0 0x0024 0x0254 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO05__AONMIX_TOP_PDM_BIT_STREAM_0 0x0024 0x0254 0x0464 0x02 0x01 +#define IMX952_PAD_GPIO_IO05__WAKEUPMIX_TOP_GPTMUX_INOUT5 0x0024 0x0254 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO05__WAKEUPMIX_TOP_LPSPI7_SIN 0x0024 0x0254 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO05__WAKEUPMIX_TOP_LPUART6_RX 0x0024 0x0254 0x05A8 0x05 0x00 +#define IMX952_PAD_GPIO_IO05__WAKEUPMIX_TOP_LPI2C6_SCL 0x0024 0x0254 0x0544 0x06 0x01 +#define IMX952_PAD_GPIO_IO05__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_5 0x0024 0x0254 0x04D0 0x07 0x00 + +#define IMX952_PAD_GPIO_IO06__WAKEUPMIX_TOP_GPIO2_IO_6 0x0028 0x0258 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO06__WAKEUPMIX_TOP_TPM5_CH0 0x0028 0x0258 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO06__AONMIX_TOP_PDM_BIT_STREAM_1 0x0028 0x0258 0x0468 0x02 0x01 +#define IMX952_PAD_GPIO_IO06__WAKEUPMIX_TOP_GPTMUX_INOUT6 0x0028 0x0258 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO06__WAKEUPMIX_TOP_LPSPI7_SOUT 0x0028 0x0258 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO06__WAKEUPMIX_TOP_LPUART6_CTS_B 0x0028 0x0258 0x05A4 0x05 0x00 +#define IMX952_PAD_GPIO_IO06__WAKEUPMIX_TOP_LPI2C7_SDA 0x0028 0x0258 0x0550 0x06 0x00 +#define IMX952_PAD_GPIO_IO06__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_6 0x0028 0x0258 0x04D4 0x07 0x00 + +#define IMX952_PAD_GPIO_IO07__WAKEUPMIX_TOP_GPIO2_IO_7 0x002C 0x025C 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO07__WAKEUPMIX_TOP_LPSPI3_PCS1 0x002C 0x025C 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO07__WAKEUPMIX_TOP_GPTMUX_INOUT7 0x002C 0x025C 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO07__WAKEUPMIX_TOP_LPSPI7_SCK 0x002C 0x025C 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO07__WAKEUPMIX_TOP_LPUART6_RTS_B 0x002C 0x025C 0x0000 0x05 0x00 +#define IMX952_PAD_GPIO_IO07__WAKEUPMIX_TOP_LPI2C7_SCL 0x002C 0x025C 0x054C 0x06 0x00 +#define IMX952_PAD_GPIO_IO07__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_7 0x002C 0x025C 0x04D8 0x07 0x00 + +#define IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_GPIO2_IO_8 0x0030 0x0260 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_LPSPI3_PCS0 0x0030 0x0260 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_GPTMUX_INOUT8 0x0030 0x0260 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_TPM6_CH0 0x0030 0x0260 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_LPUART7_TX 0x0030 0x0260 0x05B4 0x05 0x00 +#define IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_LPI2C7_SDA 0x0030 0x0260 0x0550 0x06 0x01 +#define IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_8 0x0030 0x0260 0x04DC 0x07 0x00 + +#define IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_GPIO2_IO_9 0x0034 0x0264 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_LPSPI3_SIN 0x0034 0x0264 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_GPTMUX_INOUT9 0x0034 0x0264 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_TPM3_EXTCLK 0x0034 0x0264 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_LPUART7_RX 0x0034 0x0264 0x05B0 0x05 0x00 +#define IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_LPI2C7_SCL 0x0034 0x0264 0x054C 0x06 0x01 +#define IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_9 0x0034 0x0264 0x04E0 0x07 0x00 + +#define IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_GPIO2_IO_10 0x0038 0x0268 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_LPSPI3_SOUT 0x0038 0x0268 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_GPTMUX_INOUT10 0x0038 0x0268 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_TPM4_EXTCLK 0x0038 0x0268 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_LPUART7_CTS_B 0x0038 0x0268 0x0000 0x05 0x00 +#define IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_LPI2C8_SDA 0x0038 0x0268 0x0558 0x06 0x00 +#define IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_10 0x0038 0x0268 0x04E4 0x07 0x00 + +#define IMX952_PAD_GPIO_IO11__WAKEUPMIX_TOP_GPIO2_IO_11 0x003C 0x026C 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO11__WAKEUPMIX_TOP_LPSPI3_SCK 0x003C 0x026C 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO11__WAKEUPMIX_TOP_GPTMUX_INOUT11 0x003C 0x026C 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO11__WAKEUPMIX_TOP_TPM5_EXTCLK 0x003C 0x026C 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO11__WAKEUPMIX_TOP_LPUART7_RTS_B 0x003C 0x026C 0x0000 0x05 0x00 +#define IMX952_PAD_GPIO_IO11__WAKEUPMIX_TOP_LPI2C8_SCL 0x003C 0x026C 0x0554 0x06 0x00 +#define IMX952_PAD_GPIO_IO11__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_11 0x003C 0x026C 0x04E8 0x07 0x00 + +#define IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_GPIO2_IO_12 0x0040 0x0270 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_TPM3_CH2 0x0040 0x0270 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO12__AONMIX_TOP_PDM_BIT_STREAM_2 0x0040 0x0270 0x046C 0x02 0x00 +#define IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_12 0x0040 0x0270 0x04EC 0x03 0x00 +#define IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_LPSPI8_PCS0 0x0040 0x0270 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_LPUART8_TX 0x0040 0x0270 0x0000 0x05 0x00 +#define IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_LPI2C8_SDA 0x0040 0x0270 0x0558 0x06 0x01 +#define IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_SAI3_RX_SYNC 0x0040 0x0270 0x05BC 0x07 0x00 + +#define IMX952_PAD_GPIO_IO13__WAKEUPMIX_TOP_GPIO2_IO_13 0x0044 0x0274 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO13__WAKEUPMIX_TOP_TPM4_CH2 0x0044 0x0274 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO13__AONMIX_TOP_PDM_BIT_STREAM_3 0x0044 0x0274 0x0470 0x02 0x00 +#define IMX952_PAD_GPIO_IO13__WAKEUPMIX_TOP_LPSPI8_SIN 0x0044 0x0274 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO13__WAKEUPMIX_TOP_LPUART8_RX 0x0044 0x0274 0x0000 0x05 0x00 +#define IMX952_PAD_GPIO_IO13__WAKEUPMIX_TOP_LPI2C8_SCL 0x0044 0x0274 0x0554 0x06 0x01 +#define IMX952_PAD_GPIO_IO13__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_13 0x0044 0x0274 0x04F0 0x07 0x00 + +#define IMX952_PAD_GPIO_IO14__WAKEUPMIX_TOP_GPIO2_IO_14 0x0048 0x0278 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO14__WAKEUPMIX_TOP_LPUART3_TX 0x0048 0x0278 0x0588 0x01 0x01 +#define IMX952_PAD_GPIO_IO14__WAKEUPMIX_TOP_LPSPI8_SOUT 0x0048 0x0278 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO14__WAKEUPMIX_TOP_LPUART8_CTS_B 0x0048 0x0278 0x0000 0x05 0x00 +#define IMX952_PAD_GPIO_IO14__WAKEUPMIX_TOP_LPUART4_TX 0x0048 0x0278 0x0594 0x06 0x01 +#define IMX952_PAD_GPIO_IO14__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_14 0x0048 0x0278 0x04F4 0x07 0x00 + +#define IMX952_PAD_GPIO_IO15__WAKEUPMIX_TOP_GPIO2_IO_15 0x004C 0x027C 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO15__WAKEUPMIX_TOP_LPUART3_RX 0x004C 0x027C 0x0584 0x01 0x01 +#define IMX952_PAD_GPIO_IO15__WAKEUPMIX_TOP_XSPI1_INTFA_B 0x004C 0x027C 0x0624 0x03 0x00 +#define IMX952_PAD_GPIO_IO15__WAKEUPMIX_TOP_LPSPI8_SCK 0x004C 0x027C 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO15__WAKEUPMIX_TOP_LPUART8_RTS_B 0x004C 0x027C 0x0000 0x05 0x00 +#define IMX952_PAD_GPIO_IO15__WAKEUPMIX_TOP_LPUART4_RX 0x004C 0x027C 0x0590 0x06 0x01 +#define IMX952_PAD_GPIO_IO15__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_15 0x004C 0x027C 0x04F8 0x07 0x00 + +#define IMX952_PAD_GPIO_IO16__WAKEUPMIX_TOP_GPIO2_IO_16 0x0050 0x0280 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO16__WAKEUPMIX_TOP_AUDMIX_TDM_OUT_TXBCLK 0x0050 0x0280 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO16__AONMIX_TOP_PDM_BIT_STREAM_2 0x0050 0x0280 0x046C 0x02 0x01 +#define IMX952_PAD_GPIO_IO16__WAKEUPMIX_TOP_LPUART3_CTS_B 0x0050 0x0280 0x0580 0x04 0x01 +#define IMX952_PAD_GPIO_IO16__WAKEUPMIX_TOP_LPSPI4_PCS2 0x0050 0x0280 0x0564 0x05 0x00 +#define IMX952_PAD_GPIO_IO16__WAKEUPMIX_TOP_LPUART4_CTS_B 0x0050 0x0280 0x058C 0x06 0x01 +#define IMX952_PAD_GPIO_IO16__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_16 0x0050 0x0280 0x04FC 0x07 0x00 + +#define IMX952_PAD_GPIO_IO17__WAKEUPMIX_TOP_GPIO2_IO_17 0x0054 0x0284 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO17__WAKEUPMIX_TOP_SAI3_MCLK 0x0054 0x0284 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO17__WAKEUPMIX_TOP_LPUART3_RTS_B 0x0054 0x0284 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO17__WAKEUPMIX_TOP_LPSPI4_PCS1 0x0054 0x0284 0x0560 0x05 0x00 +#define IMX952_PAD_GPIO_IO17__WAKEUPMIX_TOP_LPUART4_RTS_B 0x0054 0x0284 0x0000 0x06 0x00 +#define IMX952_PAD_GPIO_IO17__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_17 0x0054 0x0284 0x0500 0x07 0x00 + +#define IMX952_PAD_GPIO_IO18__WAKEUPMIX_TOP_GPIO2_IO_18 0x0058 0x0288 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO18__WAKEUPMIX_TOP_SAI3_RX_BCLK 0x0058 0x0288 0x05B8 0x01 0x00 +#define IMX952_PAD_GPIO_IO18__WAKEUPMIX_TOP_LPSPI5_PCS0 0x0058 0x0288 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO18__WAKEUPMIX_TOP_LPSPI4_PCS0 0x0058 0x0288 0x055C 0x05 0x00 +#define IMX952_PAD_GPIO_IO18__WAKEUPMIX_TOP_TPM5_CH2 0x0058 0x0288 0x0000 0x06 0x00 +#define IMX952_PAD_GPIO_IO18__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_18 0x0058 0x0288 0x0504 0x07 0x00 + +#define IMX952_PAD_GPIO_IO19__WAKEUPMIX_TOP_GPIO2_IO_19 0x005C 0x028C 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO19__WAKEUPMIX_TOP_SAI3_RX_SYNC 0x005C 0x028C 0x05BC 0x01 0x01 +#define IMX952_PAD_GPIO_IO19__AONMIX_TOP_PDM_BIT_STREAM_3 0x005C 0x028C 0x0470 0x02 0x01 +#define IMX952_PAD_GPIO_IO19__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_19 0x005C 0x028C 0x0508 0x03 0x00 +#define IMX952_PAD_GPIO_IO19__WAKEUPMIX_TOP_LPSPI5_SIN 0x005C 0x028C 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO19__WAKEUPMIX_TOP_LPSPI4_SIN 0x005C 0x028C 0x056C 0x05 0x00 +#define IMX952_PAD_GPIO_IO19__WAKEUPMIX_TOP_TPM6_CH2 0x005C 0x028C 0x0000 0x06 0x00 +#define IMX952_PAD_GPIO_IO19__WAKEUPMIX_TOP_AUDMIX_TDM_OUT_TXDATA 0x005C 0x028C 0x05F4 0x07 0x00 + +#define IMX952_PAD_GPIO_IO20__WAKEUPMIX_TOP_GPIO2_IO_20 0x0060 0x0290 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO20__WAKEUPMIX_TOP_SAI3_RX_DATA_0 0x0060 0x0290 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO20__AONMIX_TOP_PDM_BIT_STREAM_0 0x0060 0x0290 0x0464 0x02 0x02 +#define IMX952_PAD_GPIO_IO20__WAKEUPMIX_TOP_LPSPI5_SOUT 0x0060 0x0290 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO20__WAKEUPMIX_TOP_LPSPI4_SOUT 0x0060 0x0290 0x0570 0x05 0x00 +#define IMX952_PAD_GPIO_IO20__WAKEUPMIX_TOP_TPM3_CH1 0x0060 0x0290 0x0000 0x06 0x00 +#define IMX952_PAD_GPIO_IO20__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_20 0x0060 0x0290 0x050C 0x07 0x00 + +#define IMX952_PAD_GPIO_IO21__WAKEUPMIX_TOP_GPIO2_IO_21 0x0064 0x0294 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO21__WAKEUPMIX_TOP_AUDMIX_TDM_OUT_TXDATA 0x0064 0x0294 0x05F4 0x01 0x01 +#define IMX952_PAD_GPIO_IO21__AONMIX_TOP_PDM_CLK 0x0064 0x0294 0x0000 0x02 0x00 +#define IMX952_PAD_GPIO_IO21__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_21 0x0064 0x0294 0x0510 0x03 0x00 +#define IMX952_PAD_GPIO_IO21__WAKEUPMIX_TOP_LPSPI5_SCK 0x0064 0x0294 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO21__WAKEUPMIX_TOP_LPSPI4_SCK 0x0064 0x0294 0x0568 0x05 0x00 +#define IMX952_PAD_GPIO_IO21__WAKEUPMIX_TOP_TPM4_CH1 0x0064 0x0294 0x0000 0x06 0x00 +#define IMX952_PAD_GPIO_IO21__WAKEUPMIX_TOP_SAI3_RX_BCLK 0x0064 0x0294 0x05B8 0x07 0x01 + +#define IMX952_PAD_GPIO_IO22__WAKEUPMIX_TOP_GPIO2_IO_22 0x0068 0x0298 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO22__WAKEUPMIX_TOP_USDHC3_CLK 0x0068 0x0298 0x0604 0x01 0x00 +#define IMX952_PAD_GPIO_IO22__HSIOMIX_TOP_USB1_OTG_OC 0x0068 0x0298 0x047C 0x03 0x01 +#define IMX952_PAD_GPIO_IO22__WAKEUPMIX_TOP_TPM5_CH1 0x0068 0x0298 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO22__WAKEUPMIX_TOP_TPM6_EXTCLK 0x0068 0x0298 0x0000 0x05 0x00 +#define IMX952_PAD_GPIO_IO22__WAKEUPMIX_TOP_LPI2C5_SDA 0x0068 0x0298 0x0540 0x06 0x01 +#define IMX952_PAD_GPIO_IO22__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_22 0x0068 0x0298 0x0514 0x07 0x00 + +#define IMX952_PAD_GPIO_IO23__WAKEUPMIX_TOP_GPIO2_IO_23 0x006C 0x029C 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO23__WAKEUPMIX_TOP_USDHC3_CMD 0x006C 0x029C 0x0608 0x01 0x00 +#define IMX952_PAD_GPIO_IO23__HSIOMIX_TOP_USB2_OTG_OC 0x006C 0x029C 0x0480 0x03 0x01 +#define IMX952_PAD_GPIO_IO23__WAKEUPMIX_TOP_TPM6_CH1 0x006C 0x029C 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO23__WAKEUPMIX_TOP_LPI2C5_SCL 0x006C 0x029C 0x053C 0x06 0x01 +#define IMX952_PAD_GPIO_IO23__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_23 0x006C 0x029C 0x0518 0x07 0x00 + +#define IMX952_PAD_GPIO_IO24__WAKEUPMIX_TOP_GPIO2_IO_24 0x0070 0x02A0 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO24__WAKEUPMIX_TOP_USDHC3_DATA0 0x0070 0x02A0 0x060C 0x01 0x00 +#define IMX952_PAD_GPIO_IO24__HSIOMIX_TOP_USB1_OTG_PWR 0x0070 0x02A0 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO24__WAKEUPMIX_TOP_TPM3_CH3 0x0070 0x02A0 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO24__WAKEUPMIX_TOP_TDO 0x0070 0x02A0 0x0000 0x05 0x00 +#define IMX952_PAD_GPIO_IO24__WAKEUPMIX_TOP_LPSPI6_PCS1 0x0070 0x02A0 0x0000 0x06 0x00 +#define IMX952_PAD_GPIO_IO24__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_24 0x0070 0x02A0 0x051C 0x07 0x00 + +#define IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_GPIO2_IO_25 0x0074 0x02A4 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_USDHC3_DATA1 0x0074 0x02A4 0x0610 0x01 0x00 +#define IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_CAN2_TX 0x0074 0x02A4 0x0000 0x02 0x00 +#define IMX952_PAD_GPIO_IO25__HSIOMIX_TOP_USB2_OTG_PWR 0x0074 0x02A4 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_TPM4_CH3 0x0074 0x02A4 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_TCK 0x0074 0x02A4 0x05F8 0x05 0x01 +#define IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_LPSPI7_PCS1 0x0074 0x02A4 0x0000 0x06 0x00 +#define IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_25 0x0074 0x02A4 0x0520 0x07 0x00 + +#define IMX952_PAD_GPIO_IO26__WAKEUPMIX_TOP_GPIO2_IO_26 0x0078 0x02A8 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO26__WAKEUPMIX_TOP_USDHC3_DATA2 0x0078 0x02A8 0x0614 0x01 0x00 +#define IMX952_PAD_GPIO_IO26__AONMIX_TOP_PDM_BIT_STREAM_1 0x0078 0x02A8 0x0468 0x02 0x02 +#define IMX952_PAD_GPIO_IO26__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_26 0x0078 0x02A8 0x04AC 0x03 0x01 +#define IMX952_PAD_GPIO_IO26__WAKEUPMIX_TOP_TPM5_CH3 0x0078 0x02A8 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO26__WAKEUPMIX_TOP_TDI 0x0078 0x02A8 0x05FC 0x05 0x01 +#define IMX952_PAD_GPIO_IO26__WAKEUPMIX_TOP_LPSPI8_PCS1 0x0078 0x02A8 0x0000 0x06 0x00 +#define IMX952_PAD_GPIO_IO26__WAKEUPMIX_TOP_AUDMIX_TDM_OUT_TXSYNC 0x0078 0x02A8 0x0000 0x07 0x00 + +#define IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_GPIO2_IO_27 0x007C 0x02AC 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_USDHC3_DATA3 0x007C 0x02AC 0x0618 0x01 0x00 +#define IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_CAN2_RX 0x007C 0x02AC 0x04A4 0x02 0x02 +#define IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_TPM6_CH3 0x007C 0x02AC 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_TMS 0x007C 0x02AC 0x0600 0x05 0x01 +#define IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_LPSPI5_PCS1 0x007C 0x02AC 0x0000 0x06 0x00 +#define IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_27 0x007C 0x02AC 0x04B0 0x07 0x01 + +#define IMX952_PAD_GPIO_IO28__WAKEUPMIX_TOP_GPIO2_IO_28 0x0080 0x02B0 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO28__WAKEUPMIX_TOP_LPI2C3_SDA 0x0080 0x02B0 0x0530 0x01 0x01 +#define IMX952_PAD_GPIO_IO28__WAKEUPMIX_TOP_CAN3_TX 0x0080 0x02B0 0x0000 0x02 0x00 +#define IMX952_PAD_GPIO_IO28__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_28 0x0080 0x02B0 0x0000 0x07 0x00 + +#define IMX952_PAD_GPIO_IO29__WAKEUPMIX_TOP_GPIO2_IO_29 0x0084 0x02B4 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO29__WAKEUPMIX_TOP_LPI2C3_SCL 0x0084 0x02B4 0x052C 0x01 0x01 +#define IMX952_PAD_GPIO_IO29__WAKEUPMIX_TOP_CAN3_RX 0x0084 0x02B4 0x04A8 0x02 0x01 +#define IMX952_PAD_GPIO_IO29__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_29 0x0084 0x02B4 0x0000 0x07 0x00 + +#define IMX952_PAD_GPIO_IO30__WAKEUPMIX_TOP_GPIO2_IO_30 0x0088 0x02B8 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO30__WAKEUPMIX_TOP_LPI2C4_SDA 0x0088 0x02B8 0x0538 0x01 0x01 +#define IMX952_PAD_GPIO_IO30__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_30 0x0088 0x02B8 0x04B4 0x07 0x01 + +#define IMX952_PAD_GPIO_IO31__WAKEUPMIX_TOP_GPIO2_IO_31 0x008C 0x02BC 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO31__WAKEUPMIX_TOP_LPI2C4_SCL 0x008C 0x02BC 0x0534 0x01 0x01 +#define IMX952_PAD_GPIO_IO31__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_31 0x008C 0x02BC 0x04B8 0x07 0x01 + +#define IMX952_PAD_GPIO_IO32__WAKEUPMIX_TOP_GPIO5_IO_12 0x0090 0x02C0 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x0090 0x02C0 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO32__WAKEUPMIX_TOP_LPUART6_TX 0x0090 0x02C0 0x05AC 0x02 0x01 +#define IMX952_PAD_GPIO_IO32__WAKEUPMIX_TOP_LPSPI4_PCS2 0x0090 0x02C0 0x0564 0x04 0x01 + +#define IMX952_PAD_GPIO_IO33__WAKEUPMIX_TOP_GPIO5_IO_13 0x0094 0x02C4 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO33__WAKEUPMIX_TOP_LPUART6_RX 0x0094 0x02C4 0x05A8 0x02 0x01 +#define IMX952_PAD_GPIO_IO33__WAKEUPMIX_TOP_LPSPI4_PCS1 0x0094 0x02C4 0x0560 0x04 0x01 + +#define IMX952_PAD_GPIO_IO34__WAKEUPMIX_TOP_GPIO5_IO_14 0x0098 0x02C8 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO34__WAKEUPMIX_TOP_LPUART6_CTS_B 0x0098 0x02C8 0x05A4 0x02 0x01 +#define IMX952_PAD_GPIO_IO34__WAKEUPMIX_TOP_LPSPI4_PCS0 0x0098 0x02C8 0x055C 0x04 0x01 + +#define IMX952_PAD_GPIO_IO35__WAKEUPMIX_TOP_GPIO5_IO_15 0x009C 0x02CC 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO35__WAKEUPMIX_TOP_LPUART6_RTS_B 0x009C 0x02CC 0x0000 0x02 0x00 +#define IMX952_PAD_GPIO_IO35__WAKEUPMIX_TOP_LPSPI4_SIN 0x009C 0x02CC 0x056C 0x04 0x01 + +#define IMX952_PAD_GPIO_IO36__WAKEUPMIX_TOP_LPSPI4_SOUT 0x00A0 0x02D0 0x0570 0x04 0x01 +#define IMX952_PAD_GPIO_IO36__WAKEUPMIX_TOP_GPIO5_IO_16 0x00A0 0x02D0 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO36__WAKEUPMIX_TOP_LPUART7_TX 0x00A0 0x02D0 0x05B4 0x02 0x01 + +#define IMX952_PAD_GPIO_IO37__WAKEUPMIX_TOP_GPIO5_IO_17 0x00A4 0x02D4 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO37__WAKEUPMIX_TOP_LPUART7_RX 0x00A4 0x02D4 0x05B0 0x02 0x01 +#define IMX952_PAD_GPIO_IO37__WAKEUPMIX_TOP_LPSPI4_SCK 0x00A4 0x02D4 0x0568 0x04 0x01 + +#define IMX952_PAD_CCM_CLKO1__CCMSRCGPCMIX_TOP_CLKO_1 0x00D4 0x0304 0x0000 0x00 0x00 +#define IMX952_PAD_CCM_CLKO1__NETCMIX_TOP_NETC_TMR_1588_TRIG1 0x00D4 0x0304 0x0494 0x01 0x00 +#define IMX952_PAD_CCM_CLKO1__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_26 0x00D4 0x0304 0x04AC 0x04 0x00 +#define IMX952_PAD_CCM_CLKO1__WAKEUPMIX_TOP_GPIO3_IO_26 0x00D4 0x0304 0x0000 0x05 0x00 + +#define IMX952_PAD_CCM_CLKO2__WAKEUPMIX_TOP_GPIO3_IO_27 0x00D8 0x0308 0x0000 0x05 0x00 +#define IMX952_PAD_CCM_CLKO2__CCMSRCGPCMIX_TOP_CLKO_2 0x00D8 0x0308 0x0000 0x00 0x00 +#define IMX952_PAD_CCM_CLKO2__NETCMIX_TOP_NETC_TMR_1588_PP1 0x00D8 0x0308 0x0000 0x01 0x00 +#define IMX952_PAD_CCM_CLKO2__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_27 0x00D8 0x0308 0x04B0 0x04 0x00 + +#define IMX952_PAD_CCM_CLKO3__CCMSRCGPCMIX_TOP_CLKO_3 0x00DC 0x030C 0x0000 0x00 0x00 +#define IMX952_PAD_CCM_CLKO3__NETCMIX_TOP_NETC_TMR_1588_TRIG2 0x00DC 0x030C 0x0498 0x01 0x00 +#define IMX952_PAD_CCM_CLKO3__WAKEUPMIX_TOP_CAN3_TX 0x00DC 0x030C 0x0000 0x02 0x00 +#define IMX952_PAD_CCM_CLKO3__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_28 0x00DC 0x030C 0x0000 0x04 0x00 +#define IMX952_PAD_CCM_CLKO3__WAKEUPMIX_TOP_GPIO4_IO_28 0x00DC 0x030C 0x0000 0x05 0x00 + +#define IMX952_PAD_CCM_CLKO4__CCMSRCGPCMIX_TOP_CLKO_4 0x00E0 0x0310 0x0000 0x00 0x00 +#define IMX952_PAD_CCM_CLKO4__NETCMIX_TOP_NETC_TMR_1588_PP2 0x00E0 0x0310 0x0000 0x01 0x00 +#define IMX952_PAD_CCM_CLKO4__WAKEUPMIX_TOP_CAN3_RX 0x00E0 0x0310 0x04A8 0x02 0x00 +#define IMX952_PAD_CCM_CLKO4__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_29 0x00E0 0x0310 0x0000 0x04 0x00 +#define IMX952_PAD_CCM_CLKO4__WAKEUPMIX_TOP_GPIO4_IO_29 0x00E0 0x0310 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC 0x00E4 0x0314 0x0484 0x00 0x00 +#define IMX952_PAD_ENET1_MDC__WAKEUPMIX_TOP_LPUART3_DCD_B 0x00E4 0x0314 0x0000 0x01 0x00 +#define IMX952_PAD_ENET1_MDC__WAKEUPMIX_TOP_I3C2_SCL 0x00E4 0x0314 0x0524 0x02 0x00 +#define IMX952_PAD_ENET1_MDC__HSIOMIX_TOP_USB1_OTG_ID 0x00E4 0x0314 0x0000 0x03 0x00 +#define IMX952_PAD_ENET1_MDC__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_0 0x00E4 0x0314 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_MDC__WAKEUPMIX_TOP_GPIO4_IO_0 0x00E4 0x0314 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO 0x00E8 0x0318 0x0488 0x00 0x00 +#define IMX952_PAD_ENET1_MDIO__WAKEUPMIX_TOP_LPUART3_RIN_B 0x00E8 0x0318 0x0000 0x01 0x00 +#define IMX952_PAD_ENET1_MDIO__WAKEUPMIX_TOP_I3C2_SDA 0x00E8 0x0318 0x0528 0x02 0x00 +#define IMX952_PAD_ENET1_MDIO__HSIOMIX_TOP_USB1_OTG_PWR 0x00E8 0x0318 0x0000 0x03 0x00 +#define IMX952_PAD_ENET1_MDIO__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_1 0x00E8 0x0318 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_MDIO__WAKEUPMIX_TOP_GPIO4_IO_1 0x00E8 0x0318 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x00EC 0x031C 0x0000 0x00 0x00 +#define IMX952_PAD_ENET1_TD3__WAKEUPMIX_TOP_CAN2_TX 0x00EC 0x031C 0x0000 0x02 0x00 +#define IMX952_PAD_ENET1_TD3__HSIOMIX_TOP_USB2_OTG_ID 0x00EC 0x031C 0x0000 0x03 0x00 +#define IMX952_PAD_ENET1_TD3__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_2 0x00EC 0x031C 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_TD3__WAKEUPMIX_TOP_GPIO4_IO_2 0x00EC 0x031C 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x00F0 0x0320 0x0000 0x00 0x00 +#define IMX952_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RMII_REF50_CLK 0x00F0 0x0320 0x0000 0x01 0x00 +#define IMX952_PAD_ENET1_TD2__WAKEUPMIX_TOP_CAN2_RX 0x00F0 0x0320 0x04A4 0x02 0x01 +#define IMX952_PAD_ENET1_TD2__HSIOMIX_TOP_USB2_OTG_OC 0x00F0 0x0320 0x0480 0x03 0x00 +#define IMX952_PAD_ENET1_TD2__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_3 0x00F0 0x0320 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_TD2__WAKEUPMIX_TOP_GPIO4_IO_3 0x00F0 0x0320 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x00F4 0x0324 0x0000 0x00 0x00 +#define IMX952_PAD_ENET1_TD1__WAKEUPMIX_TOP_LPUART3_RTS_B 0x00F4 0x0324 0x0000 0x01 0x00 +#define IMX952_PAD_ENET1_TD1__WAKEUPMIX_TOP_I3C2_PUR 0x00F4 0x0324 0x0000 0x02 0x00 +#define IMX952_PAD_ENET1_TD1__HSIOMIX_TOP_USB1_OTG_OC 0x00F4 0x0324 0x047C 0x03 0x00 +#define IMX952_PAD_ENET1_TD1__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_4 0x00F4 0x0324 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_TD1__WAKEUPMIX_TOP_GPIO4_IO_4 0x00F4 0x0324 0x0000 0x05 0x00 +#define IMX952_PAD_ENET1_TD1__WAKEUPMIX_TOP_I3C2_PUR_B 0x00F4 0x0324 0x0000 0x06 0x00 +#define IMX952_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RMII_TXD1 0x00F4 0x0324 0x0000 0x07 0x00 + +#define IMX952_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x00F8 0x0328 0x0000 0x00 0x00 +#define IMX952_PAD_ENET1_TD0__WAKEUPMIX_TOP_LPUART3_TX 0x00F8 0x0328 0x0588 0x01 0x00 +#define IMX952_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RMII_TXD0 0x00F8 0x0328 0x0000 0x02 0x00 +#define IMX952_PAD_ENET1_TD0__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_5 0x00F8 0x0328 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_TD0__WAKEUPMIX_TOP_GPIO4_IO_5 0x00F8 0x0328 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x00FC 0x032C 0x0000 0x00 0x00 +#define IMX952_PAD_ENET1_TX_CTL__WAKEUPMIX_TOP_LPUART3_DTR_B 0x00FC 0x032C 0x0000 0x01 0x00 +#define IMX952_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RMII_TX_EN 0x00FC 0x032C 0x0000 0x02 0x00 +#define IMX952_PAD_ENET1_TX_CTL__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_6 0x00FC 0x032C 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_TX_CTL__WAKEUPMIX_TOP_GPIO4_IO_6 0x00FC 0x032C 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x0100 0x0330 0x0000 0x00 0x00 +#define IMX952_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RMII_REF50_CLK_OUT 0x0100 0x0330 0x0000 0x01 0x00 +#define IMX952_PAD_ENET1_TXC__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_7 0x0100 0x0330 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_TXC__WAKEUPMIX_TOP_GPIO4_IO_7 0x0100 0x0330 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x0104 0x0334 0x0000 0x00 0x00 +#define IMX952_PAD_ENET1_RX_CTL__WAKEUPMIX_TOP_LPUART3_DSR_B 0x0104 0x0334 0x0000 0x01 0x00 +#define IMX952_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RMII_CRS_DV 0x0104 0x0334 0x0000 0x02 0x00 +#define IMX952_PAD_ENET1_RX_CTL__HSIOMIX_TOP_USB2_OTG_PWR 0x0104 0x0334 0x0000 0x03 0x00 +#define IMX952_PAD_ENET1_RX_CTL__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_8 0x0104 0x0334 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_RX_CTL__WAKEUPMIX_TOP_GPIO4_IO_8 0x0104 0x0334 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x0108 0x0338 0x0000 0x00 0x00 +#define IMX952_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RMII_RX_ER 0x0108 0x0338 0x048C 0x01 0x00 +#define IMX952_PAD_ENET1_RXC__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_9 0x0108 0x0338 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_RXC__WAKEUPMIX_TOP_GPIO4_IO_9 0x0108 0x0338 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x010C 0x033C 0x0000 0x00 0x00 +#define IMX952_PAD_ENET1_RD0__WAKEUPMIX_TOP_LPUART3_RX 0x010C 0x033C 0x0584 0x01 0x00 +#define IMX952_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RMII_RXD0 0x010C 0x033C 0x0000 0x02 0x00 +#define IMX952_PAD_ENET1_RD0__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_10 0x010C 0x033C 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_RD0__WAKEUPMIX_TOP_GPIO4_IO_10 0x010C 0x033C 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x0110 0x0340 0x0000 0x00 0x00 +#define IMX952_PAD_ENET1_RD1__WAKEUPMIX_TOP_LPUART3_CTS_B 0x0110 0x0340 0x0580 0x01 0x00 +#define IMX952_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RMII_RXD1 0x0110 0x0340 0x0000 0x02 0x00 +#define IMX952_PAD_ENET1_RD1__WAKEUPMIX_TOP_LPTMR2_ALT0 0x0110 0x0340 0x0574 0x03 0x00 +#define IMX952_PAD_ENET1_RD1__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_11 0x0110 0x0340 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_RD1__WAKEUPMIX_TOP_GPIO4_IO_11 0x0110 0x0340 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x0114 0x0344 0x0000 0x00 0x00 +#define IMX952_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RMII_RX_ER 0x0114 0x0344 0x048C 0x02 0x01 +#define IMX952_PAD_ENET1_RD2__WAKEUPMIX_TOP_LPTMR2_ALT1 0x0114 0x0344 0x0578 0x03 0x00 +#define IMX952_PAD_ENET1_RD2__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_12 0x0114 0x0344 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_RD2__WAKEUPMIX_TOP_GPIO4_IO_12 0x0114 0x0344 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x0118 0x0348 0x0000 0x00 0x00 +#define IMX952_PAD_ENET1_RD3__WAKEUPMIX_TOP_LPTMR2_ALT2 0x0118 0x0348 0x057C 0x03 0x00 +#define IMX952_PAD_ENET1_RD3__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_13 0x0118 0x0348 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_RD3__WAKEUPMIX_TOP_GPIO4_IO_13 0x0118 0x0348 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC 0x011C 0x034C 0x0484 0x00 0x01 +#define IMX952_PAD_ENET2_MDC__WAKEUPMIX_TOP_LPUART4_DCD_B 0x011C 0x034C 0x0000 0x01 0x00 +#define IMX952_PAD_ENET2_MDC__NETCMIX_TOP_SAI2_RX_SYNC 0x011C 0x034C 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_MDC__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_14 0x011C 0x034C 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_MDC__WAKEUPMIX_TOP_GPIO4_IO_14 0x011C 0x034C 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO 0x0120 0x0350 0x0488 0x00 0x01 +#define IMX952_PAD_ENET2_MDIO__WAKEUPMIX_TOP_LPUART4_RIN_B 0x0120 0x0350 0x0000 0x01 0x00 +#define IMX952_PAD_ENET2_MDIO__NETCMIX_TOP_SAI2_RX_BCLK 0x0120 0x0350 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_MDIO__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_15 0x0120 0x0350 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_MDIO__WAKEUPMIX_TOP_GPIO4_IO_15 0x0120 0x0350 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET2_TD3__NETCMIX_TOP_SAI2_RX_DATA_0 0x0124 0x0354 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_TD3__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_16 0x0124 0x0354 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_TD3__WAKEUPMIX_TOP_GPIO4_IO_16 0x0124 0x0354 0x0000 0x05 0x00 +#define IMX952_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x0124 0x0354 0x0000 0x00 0x00 + +#define IMX952_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x0128 0x0358 0x0000 0x00 0x00 +#define IMX952_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RMII_REF50_CLK 0x0128 0x0358 0x0000 0x01 0x00 +#define IMX952_PAD_ENET2_TD2__NETCMIX_TOP_SAI2_RX_DATA_1 0x0128 0x0358 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_TD2__WAKEUPMIX_TOP_SAI4_TX_SYNC 0x0128 0x0358 0x05D0 0x03 0x00 +#define IMX952_PAD_ENET2_TD2__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_17 0x0128 0x0358 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_TD2__WAKEUPMIX_TOP_GPIO4_IO_17 0x0128 0x0358 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x012C 0x035C 0x0000 0x00 0x00 +#define IMX952_PAD_ENET2_TD1__WAKEUPMIX_TOP_LPUART4_RTS_B 0x012C 0x035C 0x0000 0x01 0x00 +#define IMX952_PAD_ENET2_TD1__NETCMIX_TOP_SAI2_RX_DATA_2 0x012C 0x035C 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_TD1__WAKEUPMIX_TOP_SAI4_TX_BCLK 0x012C 0x035C 0x05CC 0x03 0x00 +#define IMX952_PAD_ENET2_TD1__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_18 0x012C 0x035C 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_TD1__WAKEUPMIX_TOP_GPIO4_IO_18 0x012C 0x035C 0x0000 0x05 0x00 +#define IMX952_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RMII_TXD1 0x012C 0x035C 0x0000 0x06 0x00 + +#define IMX952_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x0130 0x0360 0x0000 0x00 0x00 +#define IMX952_PAD_ENET2_TD0__WAKEUPMIX_TOP_LPUART4_TX 0x0130 0x0360 0x0594 0x01 0x00 +#define IMX952_PAD_ENET2_TD0__NETCMIX_TOP_SAI2_RX_DATA_3 0x0130 0x0360 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_TD0__WAKEUPMIX_TOP_SAI4_TX_DATA_0 0x0130 0x0360 0x0000 0x03 0x00 +#define IMX952_PAD_ENET2_TD0__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_19 0x0130 0x0360 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_TD0__WAKEUPMIX_TOP_GPIO4_IO_19 0x0130 0x0360 0x0000 0x05 0x00 +#define IMX952_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RMII_TXD0 0x0130 0x0360 0x0000 0x06 0x00 + +#define IMX952_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x0134 0x0364 0x0000 0x00 0x00 +#define IMX952_PAD_ENET2_TX_CTL__WAKEUPMIX_TOP_LPUART4_DTR_B 0x0134 0x0364 0x0000 0x01 0x00 +#define IMX952_PAD_ENET2_TX_CTL__NETCMIX_TOP_SAI2_TX_SYNC 0x0134 0x0364 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RMII_TX_EN 0x0134 0x0364 0x0000 0x03 0x00 +#define IMX952_PAD_ENET2_TX_CTL__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_20 0x0134 0x0364 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_TX_CTL__WAKEUPMIX_TOP_GPIO4_IO_20 0x0134 0x0364 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x0138 0x0368 0x0000 0x00 0x00 +#define IMX952_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RMII_REF50_CLK_OUT 0x0138 0x0368 0x0000 0x01 0x00 +#define IMX952_PAD_ENET2_TXC__NETCMIX_TOP_SAI2_TX_BCLK 0x0138 0x0368 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_TXC__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_21 0x0138 0x0368 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_TXC__WAKEUPMIX_TOP_GPIO4_IO_21 0x0138 0x0368 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x013C 0x036C 0x0000 0x00 0x00 +#define IMX952_PAD_ENET2_RX_CTL__WAKEUPMIX_TOP_LPUART4_DSR_B 0x013C 0x036C 0x0000 0x01 0x00 +#define IMX952_PAD_ENET2_RX_CTL__NETCMIX_TOP_SAI2_TX_DATA_0 0x013C 0x036C 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_RX_CTL__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_22 0x013C 0x036C 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_RX_CTL__WAKEUPMIX_TOP_GPIO4_IO_22 0x013C 0x036C 0x0000 0x05 0x00 +#define IMX952_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RMII_CRS_DV 0x013C 0x036C 0x0000 0x06 0x00 + +#define IMX952_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK 0x0140 0x0370 0x0000 0x00 0x00 +#define IMX952_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RMII_RX_ER 0x0140 0x0370 0x0490 0x01 0x00 +#define IMX952_PAD_ENET2_RXC__NETCMIX_TOP_SAI2_TX_DATA_1 0x0140 0x0370 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_RXC__WAKEUPMIX_TOP_SAI4_RX_SYNC 0x0140 0x0370 0x05C8 0x03 0x00 +#define IMX952_PAD_ENET2_RXC__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_23 0x0140 0x0370 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_RXC__WAKEUPMIX_TOP_GPIO4_IO_23 0x0140 0x0370 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0 0x0144 0x0374 0x0000 0x00 0x00 +#define IMX952_PAD_ENET2_RD0__WAKEUPMIX_TOP_LPUART4_RX 0x0144 0x0374 0x0590 0x01 0x00 +#define IMX952_PAD_ENET2_RD0__NETCMIX_TOP_SAI2_TX_DATA_2 0x0144 0x0374 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_RD0__WAKEUPMIX_TOP_SAI4_RX_BCLK 0x0144 0x0374 0x05C0 0x03 0x00 +#define IMX952_PAD_ENET2_RD0__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_24 0x0144 0x0374 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_RD0__WAKEUPMIX_TOP_GPIO4_IO_24 0x0144 0x0374 0x0000 0x05 0x00 +#define IMX952_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RMII_RXD0 0x0144 0x0374 0x0000 0x06 0x00 + +#define IMX952_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1 0x0148 0x0378 0x0000 0x00 0x00 +#define IMX952_PAD_ENET2_RD1__NETCMIX_TOP_SAI2_TX_DATA_3 0x0148 0x0378 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_RD1__WAKEUPMIX_TOP_SAI4_RX_DATA_0 0x0148 0x0378 0x05C4 0x03 0x00 +#define IMX952_PAD_ENET2_RD1__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_25 0x0148 0x0378 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_RD1__WAKEUPMIX_TOP_GPIO4_IO_25 0x0148 0x0378 0x0000 0x05 0x00 +#define IMX952_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RMII_RXD1 0x0148 0x0378 0x0000 0x06 0x00 + +#define IMX952_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2 0x014C 0x037C 0x0000 0x00 0x00 +#define IMX952_PAD_ENET2_RD2__WAKEUPMIX_TOP_LPUART4_CTS_B 0x014C 0x037C 0x058C 0x01 0x00 +#define IMX952_PAD_ENET2_RD2__NETCMIX_TOP_SAI2_MCLK 0x014C 0x037C 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_RD2__NETCMIX_TOP_MQS2_RIGHT 0x014C 0x037C 0x0000 0x03 0x00 +#define IMX952_PAD_ENET2_RD2__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_26 0x014C 0x037C 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_RD2__WAKEUPMIX_TOP_GPIO4_IO_26 0x014C 0x037C 0x0000 0x05 0x00 +#define IMX952_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RMII_RX_ER 0x014C 0x037C 0x0490 0x06 0x01 + +#define IMX952_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3 0x0150 0x0380 0x0000 0x00 0x00 +#define IMX952_PAD_ENET2_RD3__NETCMIX_TOP_MQS2_LEFT 0x0150 0x0380 0x0000 0x03 0x00 +#define IMX952_PAD_ENET2_RD3__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_27 0x0150 0x0380 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_RD3__WAKEUPMIX_TOP_GPIO4_IO_27 0x0150 0x0380 0x0000 0x05 0x00 + +#define IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_8 0x0154 0x0384 0x04DC 0x04 0x01 +#define IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_GPIO3_IO_8 0x0154 0x0384 0x0000 0x05 0x00 +#define IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_USDHC1_CLK 0x0154 0x0384 0x0000 0x00 0x00 + +#define IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_USDHC1_CMD 0x0158 0x0388 0x0000 0x00 0x00 +#define IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_9 0x0158 0x0388 0x04E0 0x04 0x01 +#define IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_GPIO3_IO_9 0x0158 0x0388 0x0000 0x05 0x00 + +#define IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_USDHC1_DATA0 0x015C 0x038C 0x0000 0x00 0x00 +#define IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_10 0x015C 0x038C 0x04E4 0x04 0x01 +#define IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_GPIO3_IO_10 0x015C 0x038C 0x0000 0x05 0x00 + +#define IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_USDHC1_DATA1 0x0160 0x0390 0x0000 0x00 0x00 +#define IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_11 0x0160 0x0390 0x04E8 0x04 0x01 +#define IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_GPIO3_IO_11 0x0160 0x0390 0x0000 0x05 0x00 + +#define IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_USDHC1_DATA2 0x0164 0x0394 0x0000 0x00 0x00 +#define IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_XSPI1_INTFA_B 0x0164 0x0394 0x0624 0x01 0x01 +#define IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_12 0x0164 0x0394 0x04EC 0x04 0x01 +#define IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_GPIO3_IO_12 0x0164 0x0394 0x0000 0x05 0x00 +#define IMX952_PAD_SD1_DATA2__CCMSRCGPCMIX_TOP_PMIC_READY 0x0164 0x0394 0x0000 0x06 0x00 + +#define IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_USDHC1_DATA3 0x0168 0x0398 0x0000 0x00 0x00 +#define IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_XSPI1_A_SS1_B 0x0168 0x0398 0x064C 0x01 0x00 +#define IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_13 0x0168 0x0398 0x04F0 0x04 0x01 +#define IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_GPIO3_IO_13 0x0168 0x0398 0x0000 0x05 0x00 + +#define IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_USDHC1_DATA4 0x016C 0x039C 0x0000 0x00 0x00 +#define IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_XSPI1_A_DATA_4 0x016C 0x039C 0x0638 0x01 0x00 +#define IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_14 0x016C 0x039C 0x04F4 0x04 0x01 +#define IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_GPIO3_IO_14 0x016C 0x039C 0x0000 0x05 0x00 +#define IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_XSPI_SLV_DATA_4 0x016C 0x039C 0x066C 0x06 0x00 + +#define IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_USDHC1_DATA5 0x0170 0x03A0 0x0000 0x00 0x00 +#define IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_XSPI1_A_DATA_5 0x0170 0x03A0 0x063C 0x01 0x00 +#define IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_USDHC1_RESET_B 0x0170 0x03A0 0x0000 0x02 0x00 +#define IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_15 0x0170 0x03A0 0x04F8 0x04 0x01 +#define IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_GPIO3_IO_15 0x0170 0x03A0 0x0000 0x05 0x00 +#define IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_XSPI_SLV_DATA_5 0x0170 0x03A0 0x0670 0x06 0x00 + +#define IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_USDHC1_DATA6 0x0174 0x03A4 0x0000 0x00 0x00 +#define IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_XSPI1_A_DATA_6 0x0174 0x03A4 0x0640 0x01 0x00 +#define IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_USDHC1_CD_B 0x0174 0x03A4 0x0000 0x02 0x00 +#define IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_16 0x0174 0x03A4 0x04FC 0x04 0x01 +#define IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_GPIO3_IO_16 0x0174 0x03A4 0x0000 0x05 0x00 +#define IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_XSPI_SLV_DATA_6 0x0174 0x03A4 0x0674 0x06 0x00 + +#define IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_USDHC1_DATA7 0x0178 0x03A8 0x0000 0x00 0x00 +#define IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_XSPI1_A_DATA_7 0x0178 0x03A8 0x0644 0x01 0x00 +#define IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_USDHC1_WP 0x0178 0x03A8 0x0000 0x02 0x00 +#define IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_17 0x0178 0x03A8 0x0500 0x04 0x01 +#define IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_GPIO3_IO_17 0x0178 0x03A8 0x0000 0x05 0x00 +#define IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_XSPI_SLV_DATA_7 0x0178 0x03A8 0x0678 0x06 0x00 + +#define IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_USDHC1_STROBE 0x017C 0x03AC 0x0000 0x00 0x00 +#define IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_XSPI1_A_DQS 0x017C 0x03AC 0x0620 0x01 0x00 +#define IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_18 0x017C 0x03AC 0x0504 0x04 0x01 +#define IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_GPIO3_IO_18 0x017C 0x03AC 0x0000 0x05 0x00 +#define IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_XSPI_SLV_DQS 0x017C 0x03AC 0x0654 0x06 0x00 + +#define IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_USDHC2_VSELECT 0x0180 0x03B0 0x0000 0x00 0x00 +#define IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_USDHC2_WP 0x0180 0x03B0 0x0000 0x01 0x00 +#define IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_LPTMR2_ALT2 0x0180 0x03B0 0x057C 0x02 0x01 +#define IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_19 0x0180 0x03B0 0x0508 0x04 0x01 +#define IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_GPIO3_IO_19 0x0180 0x03B0 0x0000 0x05 0x00 +#define IMX952_PAD_SD2_VSELECT__CCMSRCGPCMIX_TOP_EXT_CLK1 0x0180 0x03B0 0x0478 0x06 0x01 + +#define IMX952_PAD_SD3_CLK__WAKEUPMIX_TOP_USDHC3_CLK 0x0184 0x03B4 0x0604 0x00 0x01 +#define IMX952_PAD_SD3_CLK__WAKEUPMIX_TOP_XSPI1_A_SCLK 0x0184 0x03B4 0x061C 0x01 0x00 +#define IMX952_PAD_SD3_CLK__WAKEUPMIX_TOP_SAI5_TX_DATA_1 0x0184 0x03B4 0x0000 0x02 0x00 +#define IMX952_PAD_SD3_CLK__WAKEUPMIX_TOP_SAI5_RX_DATA_0 0x0184 0x03B4 0x05D8 0x03 0x00 +#define IMX952_PAD_SD3_CLK__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_20 0x0184 0x03B4 0x050C 0x04 0x01 +#define IMX952_PAD_SD3_CLK__WAKEUPMIX_TOP_GPIO3_IO_20 0x0184 0x03B4 0x0000 0x05 0x00 +#define IMX952_PAD_SD3_CLK__WAKEUPMIX_TOP_XSPI_SLV_CLK 0x0184 0x03B4 0x0658 0x06 0x00 + +#define IMX952_PAD_SD3_CMD__WAKEUPMIX_TOP_USDHC3_CMD 0x0188 0x03B8 0x0608 0x00 0x01 +#define IMX952_PAD_SD3_CMD__WAKEUPMIX_TOP_XSPI1_A_SS0_B 0x0188 0x03B8 0x0648 0x01 0x00 +#define IMX952_PAD_SD3_CMD__WAKEUPMIX_TOP_SAI5_TX_DATA_2 0x0188 0x03B8 0x0000 0x02 0x00 +#define IMX952_PAD_SD3_CMD__WAKEUPMIX_TOP_SAI5_RX_SYNC 0x0188 0x03B8 0x05E8 0x03 0x00 +#define IMX952_PAD_SD3_CMD__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_21 0x0188 0x03B8 0x0510 0x04 0x01 +#define IMX952_PAD_SD3_CMD__WAKEUPMIX_TOP_GPIO3_IO_21 0x0188 0x03B8 0x0000 0x05 0x00 +#define IMX952_PAD_SD3_CMD__WAKEUPMIX_TOP_XSPI_SLV_CS 0x0188 0x03B8 0x0650 0x06 0x00 + +#define IMX952_PAD_SD3_DATA0__WAKEUPMIX_TOP_USDHC3_DATA0 0x018C 0x03BC 0x060C 0x00 0x01 +#define IMX952_PAD_SD3_DATA0__WAKEUPMIX_TOP_XSPI1_A_DATA_0 0x018C 0x03BC 0x0628 0x01 0x00 +#define IMX952_PAD_SD3_DATA0__WAKEUPMIX_TOP_SAI5_TX_DATA_3 0x018C 0x03BC 0x0000 0x02 0x00 +#define IMX952_PAD_SD3_DATA0__WAKEUPMIX_TOP_SAI5_RX_BCLK 0x018C 0x03BC 0x05D4 0x03 0x00 +#define IMX952_PAD_SD3_DATA0__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_22 0x018C 0x03BC 0x0514 0x04 0x01 +#define IMX952_PAD_SD3_DATA0__WAKEUPMIX_TOP_GPIO3_IO_22 0x018C 0x03BC 0x0000 0x05 0x00 +#define IMX952_PAD_SD3_DATA0__WAKEUPMIX_TOP_XSPI_SLV_DATA_0 0x018C 0x03BC 0x065C 0x06 0x00 + +#define IMX952_PAD_SD3_DATA1__WAKEUPMIX_TOP_USDHC3_DATA1 0x0190 0x03C0 0x0610 0x00 0x01 +#define IMX952_PAD_SD3_DATA1__WAKEUPMIX_TOP_XSPI1_A_DATA_1 0x0190 0x03C0 0x062C 0x01 0x00 +#define IMX952_PAD_SD3_DATA1__WAKEUPMIX_TOP_SAI5_RX_DATA_1 0x0190 0x03C0 0x05DC 0x02 0x00 +#define IMX952_PAD_SD3_DATA1__WAKEUPMIX_TOP_SAI5_TX_DATA_0 0x0190 0x03C0 0x0000 0x03 0x00 +#define IMX952_PAD_SD3_DATA1__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_23 0x0190 0x03C0 0x0518 0x04 0x01 +#define IMX952_PAD_SD3_DATA1__WAKEUPMIX_TOP_GPIO3_IO_23 0x0190 0x03C0 0x0000 0x05 0x00 +#define IMX952_PAD_SD3_DATA1__WAKEUPMIX_TOP_XSPI_SLV_DATA_1 0x0190 0x03C0 0x0660 0x06 0x00 + +#define IMX952_PAD_SD3_DATA2__WAKEUPMIX_TOP_USDHC3_DATA2 0x0194 0x03C4 0x0614 0x00 0x01 +#define IMX952_PAD_SD3_DATA2__WAKEUPMIX_TOP_XSPI1_A_DATA_2 0x0194 0x03C4 0x0630 0x01 0x00 +#define IMX952_PAD_SD3_DATA2__WAKEUPMIX_TOP_SAI5_RX_DATA_2 0x0194 0x03C4 0x05E0 0x02 0x00 +#define IMX952_PAD_SD3_DATA2__WAKEUPMIX_TOP_SAI5_TX_SYNC 0x0194 0x03C4 0x05F0 0x03 0x00 +#define IMX952_PAD_SD3_DATA2__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_24 0x0194 0x03C4 0x051C 0x04 0x01 +#define IMX952_PAD_SD3_DATA2__WAKEUPMIX_TOP_GPIO3_IO_24 0x0194 0x03C4 0x0000 0x05 0x00 +#define IMX952_PAD_SD3_DATA2__WAKEUPMIX_TOP_XSPI_SLV_DATA_2 0x0194 0x03C4 0x0664 0x06 0x00 + +#define IMX952_PAD_SD3_DATA3__WAKEUPMIX_TOP_USDHC3_DATA3 0x0198 0x03C8 0x0618 0x00 0x01 +#define IMX952_PAD_SD3_DATA3__WAKEUPMIX_TOP_XSPI1_A_DATA_3 0x0198 0x03C8 0x0634 0x01 0x00 +#define IMX952_PAD_SD3_DATA3__WAKEUPMIX_TOP_SAI5_RX_DATA_3 0x0198 0x03C8 0x05E4 0x02 0x00 +#define IMX952_PAD_SD3_DATA3__WAKEUPMIX_TOP_SAI5_TX_BCLK 0x0198 0x03C8 0x05EC 0x03 0x00 +#define IMX952_PAD_SD3_DATA3__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_25 0x0198 0x03C8 0x0520 0x04 0x01 +#define IMX952_PAD_SD3_DATA3__WAKEUPMIX_TOP_GPIO3_IO_25 0x0198 0x03C8 0x0000 0x05 0x00 +#define IMX952_PAD_SD3_DATA3__WAKEUPMIX_TOP_XSPI_SLV_DATA_3 0x0198 0x03C8 0x0668 0x06 0x00 + +#define IMX952_PAD_XSPI1_DATA0__WAKEUPMIX_TOP_XSPI1_A_DATA_0 0x019C 0x03CC 0x0628 0x00 0x01 +#define IMX952_PAD_XSPI1_DATA0__NETCMIX_TOP_SAI2_TX_DATA_4 0x019C 0x03CC 0x0000 0x01 0x00 +#define IMX952_PAD_XSPI1_DATA0__WAKEUPMIX_TOP_SAI4_TX_BCLK 0x019C 0x03CC 0x05CC 0x02 0x01 +#define IMX952_PAD_XSPI1_DATA0__WAKEUPMIX_TOP_SAI4_RX_DATA_1 0x019C 0x03CC 0x0000 0x03 0x00 +#define IMX952_PAD_XSPI1_DATA0__WAKEUPMIX_TOP_XSPI_SLV_DATA_0 0x019C 0x03CC 0x065C 0x04 0x01 +#define IMX952_PAD_XSPI1_DATA0__WAKEUPMIX_TOP_GPIO5_IO_0 0x019C 0x03CC 0x0000 0x05 0x00 + +#define IMX952_PAD_XSPI1_DATA1__WAKEUPMIX_TOP_XSPI1_A_DATA_1 0x01A0 0x03D0 0x062C 0x00 0x01 +#define IMX952_PAD_XSPI1_DATA1__NETCMIX_TOP_SAI2_TX_DATA_5 0x01A0 0x03D0 0x0000 0x01 0x00 +#define IMX952_PAD_XSPI1_DATA1__WAKEUPMIX_TOP_SAI4_TX_SYNC 0x01A0 0x03D0 0x05D0 0x02 0x01 +#define IMX952_PAD_XSPI1_DATA1__WAKEUPMIX_TOP_SAI4_TX_DATA_1 0x01A0 0x03D0 0x0000 0x03 0x00 +#define IMX952_PAD_XSPI1_DATA1__WAKEUPMIX_TOP_XSPI_SLV_DATA_1 0x01A0 0x03D0 0x0660 0x04 0x01 +#define IMX952_PAD_XSPI1_DATA1__WAKEUPMIX_TOP_GPIO5_IO_1 0x01A0 0x03D0 0x0000 0x05 0x00 + +#define IMX952_PAD_XSPI1_DATA2__WAKEUPMIX_TOP_XSPI1_A_DATA_2 0x01A4 0x03D4 0x0630 0x00 0x01 +#define IMX952_PAD_XSPI1_DATA2__NETCMIX_TOP_SAI2_TX_DATA_6 0x01A4 0x03D4 0x0000 0x01 0x00 +#define IMX952_PAD_XSPI1_DATA2__WAKEUPMIX_TOP_SAI4_TX_DATA_0 0x01A4 0x03D4 0x0000 0x02 0x00 +#define IMX952_PAD_XSPI1_DATA2__WAKEUPMIX_TOP_XSPI_SLV_DATA_2 0x01A4 0x03D4 0x0664 0x04 0x01 +#define IMX952_PAD_XSPI1_DATA2__WAKEUPMIX_TOP_GPIO5_IO_2 0x01A4 0x03D4 0x0000 0x05 0x00 + +#define IMX952_PAD_XSPI1_DATA3__WAKEUPMIX_TOP_XSPI1_A_DATA_3 0x01A8 0x03D8 0x0634 0x00 0x01 +#define IMX952_PAD_XSPI1_DATA3__NETCMIX_TOP_SAI2_TX_DATA_7 0x01A8 0x03D8 0x0000 0x01 0x00 +#define IMX952_PAD_XSPI1_DATA3__WAKEUPMIX_TOP_SAI4_RX_DATA_0 0x01A8 0x03D8 0x05C4 0x02 0x01 +#define IMX952_PAD_XSPI1_DATA3__WAKEUPMIX_TOP_XSPI_SLV_DATA_3 0x01A8 0x03D8 0x0668 0x04 0x01 +#define IMX952_PAD_XSPI1_DATA3__WAKEUPMIX_TOP_GPIO5_IO_3 0x01A8 0x03D8 0x0000 0x05 0x00 + +#define IMX952_PAD_XSPI1_DATA4__WAKEUPMIX_TOP_XSPI1_A_DATA_4 0x01AC 0x03DC 0x0638 0x00 0x01 +#define IMX952_PAD_XSPI1_DATA4__WAKEUPMIX_TOP_SAI5_TX_DATA_0 0x01AC 0x03DC 0x0000 0x01 0x00 +#define IMX952_PAD_XSPI1_DATA4__WAKEUPMIX_TOP_SAI5_RX_DATA_1 0x01AC 0x03DC 0x05DC 0x02 0x01 +#define IMX952_PAD_XSPI1_DATA4__WAKEUPMIX_TOP_XSPI_SLV_DATA_4 0x01AC 0x03DC 0x066C 0x04 0x01 +#define IMX952_PAD_XSPI1_DATA4__WAKEUPMIX_TOP_GPIO5_IO_4 0x01AC 0x03DC 0x0000 0x05 0x00 + +#define IMX952_PAD_XSPI1_DATA5__WAKEUPMIX_TOP_XSPI1_A_DATA_5 0x01B0 0x03E0 0x063C 0x00 0x01 +#define IMX952_PAD_XSPI1_DATA5__WAKEUPMIX_TOP_SAI5_TX_SYNC 0x01B0 0x03E0 0x05F0 0x01 0x01 +#define IMX952_PAD_XSPI1_DATA5__WAKEUPMIX_TOP_SAI5_RX_DATA_2 0x01B0 0x03E0 0x05E0 0x02 0x01 +#define IMX952_PAD_XSPI1_DATA5__NETCMIX_TOP_SAI2_RX_DATA_6 0x01B0 0x03E0 0x049C 0x03 0x00 +#define IMX952_PAD_XSPI1_DATA5__WAKEUPMIX_TOP_XSPI_SLV_DATA_5 0x01B0 0x03E0 0x0670 0x04 0x01 +#define IMX952_PAD_XSPI1_DATA5__WAKEUPMIX_TOP_GPIO5_IO_5 0x01B0 0x03E0 0x0000 0x05 0x00 + +#define IMX952_PAD_XSPI1_DATA6__WAKEUPMIX_TOP_XSPI1_A_DATA_6 0x01B4 0x03E4 0x0640 0x00 0x01 +#define IMX952_PAD_XSPI1_DATA6__WAKEUPMIX_TOP_SAI5_TX_BCLK 0x01B4 0x03E4 0x05EC 0x01 0x01 +#define IMX952_PAD_XSPI1_DATA6__WAKEUPMIX_TOP_SAI5_RX_DATA_3 0x01B4 0x03E4 0x05E4 0x02 0x01 +#define IMX952_PAD_XSPI1_DATA6__NETCMIX_TOP_SAI2_RX_DATA_7 0x01B4 0x03E4 0x04A0 0x03 0x00 +#define IMX952_PAD_XSPI1_DATA6__WAKEUPMIX_TOP_XSPI_SLV_DATA_6 0x01B4 0x03E4 0x0674 0x04 0x01 +#define IMX952_PAD_XSPI1_DATA6__WAKEUPMIX_TOP_GPIO5_IO_6 0x01B4 0x03E4 0x0000 0x05 0x00 + +#define IMX952_PAD_XSPI1_DATA7__WAKEUPMIX_TOP_XSPI1_A_DATA_7 0x01B8 0x03E8 0x0644 0x00 0x01 +#define IMX952_PAD_XSPI1_DATA7__WAKEUPMIX_TOP_SAI5_RX_DATA_0 0x01B8 0x03E8 0x05D8 0x01 0x01 +#define IMX952_PAD_XSPI1_DATA7__WAKEUPMIX_TOP_SAI5_TX_DATA_1 0x01B8 0x03E8 0x0000 0x02 0x00 +#define IMX952_PAD_XSPI1_DATA7__WAKEUPMIX_TOP_XSPI_SLV_DATA_7 0x01B8 0x03E8 0x0678 0x04 0x01 +#define IMX952_PAD_XSPI1_DATA7__WAKEUPMIX_TOP_GPIO5_IO_7 0x01B8 0x03E8 0x0000 0x05 0x00 + +#define IMX952_PAD_XSPI1_DQS__WAKEUPMIX_TOP_XSPI1_A_DQS 0x01BC 0x03EC 0x0620 0x00 0x01 +#define IMX952_PAD_XSPI1_DQS__WAKEUPMIX_TOP_SAI5_RX_SYNC 0x01BC 0x03EC 0x05E8 0x01 0x01 +#define IMX952_PAD_XSPI1_DQS__WAKEUPMIX_TOP_SAI5_TX_DATA_2 0x01BC 0x03EC 0x0000 0x02 0x00 +#define IMX952_PAD_XSPI1_DQS__NETCMIX_TOP_SAI2_RX_DATA_6 0x01BC 0x03EC 0x049C 0x03 0x01 +#define IMX952_PAD_XSPI1_DQS__WAKEUPMIX_TOP_XSPI_SLV_DQS 0x01BC 0x03EC 0x0654 0x04 0x01 +#define IMX952_PAD_XSPI1_DQS__WAKEUPMIX_TOP_GPIO5_IO_8 0x01BC 0x03EC 0x0000 0x05 0x00 + +#define IMX952_PAD_XSPI1_SCLK__WAKEUPMIX_TOP_XSPI1_A_SCLK 0x01C0 0x03F0 0x061C 0x00 0x01 +#define IMX952_PAD_XSPI1_SCLK__NETCMIX_TOP_SAI2_RX_DATA_4 0x01C0 0x03F0 0x0000 0x01 0x00 +#define IMX952_PAD_XSPI1_SCLK__WAKEUPMIX_TOP_SAI4_RX_SYNC 0x01C0 0x03F0 0x05C8 0x02 0x01 +#define IMX952_PAD_XSPI1_SCLK__WAKEUPMIX_TOP_XSPI_SLV_CLK 0x01C0 0x03F0 0x0658 0x04 0x01 +#define IMX952_PAD_XSPI1_SCLK__WAKEUPMIX_TOP_GPIO5_IO_9 0x01C0 0x03F0 0x0000 0x05 0x00 + +#define IMX952_PAD_XSPI1_SS0_B__WAKEUPMIX_TOP_XSPI1_A_SS0_B 0x01C4 0x03F4 0x0648 0x00 0x01 +#define IMX952_PAD_XSPI1_SS0_B__NETCMIX_TOP_SAI2_RX_DATA_5 0x01C4 0x03F4 0x0000 0x01 0x00 +#define IMX952_PAD_XSPI1_SS0_B__WAKEUPMIX_TOP_SAI4_RX_BCLK 0x01C4 0x03F4 0x05C0 0x02 0x01 +#define IMX952_PAD_XSPI1_SS0_B__WAKEUPMIX_TOP_XSPI_SLV_CS 0x01C4 0x03F4 0x0650 0x04 0x01 +#define IMX952_PAD_XSPI1_SS0_B__WAKEUPMIX_TOP_GPIO5_IO_10 0x01C4 0x03F4 0x0000 0x05 0x00 + +#define IMX952_PAD_XSPI1_SS1_B__WAKEUPMIX_TOP_XSPI1_A_SS1_B 0x01C8 0x03F8 0x064C 0x00 0x01 +#define IMX952_PAD_XSPI1_SS1_B__WAKEUPMIX_TOP_SAI5_RX_BCLK 0x01C8 0x03F8 0x05D4 0x01 0x01 +#define IMX952_PAD_XSPI1_SS1_B__WAKEUPMIX_TOP_SAI5_TX_DATA_3 0x01C8 0x03F8 0x0000 0x02 0x00 +#define IMX952_PAD_XSPI1_SS1_B__NETCMIX_TOP_SAI2_RX_DATA_7 0x01C8 0x03F8 0x04A0 0x03 0x01 +#define IMX952_PAD_XSPI1_SS1_B__WAKEUPMIX_TOP_GPIO5_IO_11 0x01C8 0x03F8 0x0000 0x05 0x00 + +#define IMX952_PAD_SD2_CD_B__WAKEUPMIX_TOP_USDHC2_CD_B 0x01CC 0x03FC 0x0000 0x00 0x00 +#define IMX952_PAD_SD2_CD_B__NETCMIX_TOP_NETC_TMR_1588_TRIG1 0x01CC 0x03FC 0x0494 0x01 0x01 +#define IMX952_PAD_SD2_CD_B__WAKEUPMIX_TOP_I3C2_SCL 0x01CC 0x03FC 0x0524 0x02 0x01 +#define IMX952_PAD_SD2_CD_B__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_0 0x01CC 0x03FC 0x04BC 0x04 0x01 +#define IMX952_PAD_SD2_CD_B__WAKEUPMIX_TOP_GPIO3_IO_0 0x01CC 0x03FC 0x0000 0x05 0x00 + +#define IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_USDHC2_CLK 0x01D0 0x0400 0x0000 0x00 0x00 +#define IMX952_PAD_SD2_CLK__NETCMIX_TOP_NETC_TMR_1588_PP1 0x01D0 0x0400 0x0000 0x01 0x00 +#define IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_I3C2_SDA 0x01D0 0x0400 0x0528 0x02 0x01 +#define IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_1 0x01D0 0x0400 0x04C0 0x04 0x01 +#define IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_GPIO3_IO_1 0x01D0 0x0400 0x0000 0x05 0x00 +#define IMX952_PAD_SD2_CLK__CCMSRCGPCMIX_TOP_OBSERVE_0 0x01D0 0x0400 0x0000 0x06 0x00 + +#define IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_USDHC2_CMD 0x01D4 0x0404 0x0000 0x00 0x00 +#define IMX952_PAD_SD2_CMD__NETCMIX_TOP_NETC_TMR_1588_TRIG2 0x01D4 0x0404 0x0498 0x01 0x01 +#define IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_I3C2_PUR 0x01D4 0x0404 0x0000 0x02 0x00 +#define IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_I3C2_PUR_B 0x01D4 0x0404 0x0000 0x03 0x00 +#define IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_2 0x01D4 0x0404 0x04C4 0x04 0x01 +#define IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_GPIO3_IO_2 0x01D4 0x0404 0x0000 0x05 0x00 +#define IMX952_PAD_SD2_CMD__CCMSRCGPCMIX_TOP_OBSERVE_1 0x01D4 0x0404 0x0000 0x06 0x00 + +#define IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_USDHC2_DATA0 0x01D8 0x0408 0x0000 0x00 0x00 +#define IMX952_PAD_SD2_DATA0__NETCMIX_TOP_NETC_TMR_1588_PP2 0x01D8 0x0408 0x0000 0x01 0x00 +#define IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_CAN2_TX 0x01D8 0x0408 0x0000 0x02 0x00 +#define IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_3 0x01D8 0x0408 0x04C8 0x04 0x01 +#define IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_GPIO3_IO_3 0x01D8 0x0408 0x0000 0x05 0x00 +#define IMX952_PAD_SD2_DATA0__CCMSRCGPCMIX_TOP_OBSERVE_2 0x01D8 0x0408 0x0000 0x06 0x00 + +#define IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_USDHC2_DATA1 0x01DC 0x040C 0x0000 0x00 0x00 +#define IMX952_PAD_SD2_DATA1__NETCMIX_TOP_NETC_TMR_1588_CLK 0x01DC 0x040C 0x0000 0x01 0x00 +#define IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_CAN2_RX 0x01DC 0x040C 0x04A4 0x02 0x03 +#define IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_4 0x01DC 0x040C 0x04CC 0x04 0x01 +#define IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_GPIO3_IO_4 0x01DC 0x040C 0x0000 0x05 0x00 + +#define IMX952_PAD_SD2_DATA2__WAKEUPMIX_TOP_USDHC2_DATA2 0x01E0 0x0410 0x0000 0x00 0x00 +#define IMX952_PAD_SD2_DATA2__NETCMIX_TOP_NETC_TMR_1588_PP3 0x01E0 0x0410 0x0000 0x01 0x00 +#define IMX952_PAD_SD2_DATA2__NETCMIX_TOP_MQS2_RIGHT 0x01E0 0x0410 0x0000 0x02 0x00 +#define IMX952_PAD_SD2_DATA2__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_5 0x01E0 0x0410 0x04D0 0x04 0x01 +#define IMX952_PAD_SD2_DATA2__WAKEUPMIX_TOP_GPIO3_IO_5 0x01E0 0x0410 0x0000 0x05 0x00 + +#define IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_USDHC2_DATA3 0x01E4 0x0414 0x0000 0x00 0x00 +#define IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_LPTMR2_ALT0 0x01E4 0x0414 0x0574 0x01 0x01 +#define IMX952_PAD_SD2_DATA3__NETCMIX_TOP_MQS2_LEFT 0x01E4 0x0414 0x0000 0x02 0x00 +#define IMX952_PAD_SD2_DATA3__NETCMIX_TOP_NETC_TMR_1588_ALARM1 0x01E4 0x0414 0x0000 0x03 0x00 +#define IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_6 0x01E4 0x0414 0x04D4 0x04 0x01 +#define IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_GPIO3_IO_6 0x01E4 0x0414 0x0000 0x05 0x00 + +#define IMX952_PAD_SD2_RESET_B__WAKEUPMIX_TOP_USDHC2_RESET_B 0x01E8 0x0418 0x0000 0x00 0x00 +#define IMX952_PAD_SD2_RESET_B__WAKEUPMIX_TOP_LPTMR2_ALT1 0x01E8 0x0418 0x0578 0x01 0x01 +#define IMX952_PAD_SD2_RESET_B__NETCMIX_TOP_NETC_TMR_1588_GCLK 0x01E8 0x0418 0x0000 0x03 0x00 +#define IMX952_PAD_SD2_RESET_B__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_7 0x01E8 0x0418 0x04D8 0x04 0x01 +#define IMX952_PAD_SD2_RESET_B__WAKEUPMIX_TOP_GPIO3_IO_7 0x01E8 0x0418 0x0000 0x05 0x00 + +#define IMX952_PAD_I2C1_SCL__AONMIX_TOP_LPI2C1_SCL 0x01EC 0x041C 0x0000 0x00 0x00 +#define IMX952_PAD_I2C1_SCL__AONMIX_TOP_I3C1_SCL 0x01EC 0x041C 0x0000 0x01 0x00 +#define IMX952_PAD_I2C1_SCL__AONMIX_TOP_LPUART1_DCD_B 0x01EC 0x041C 0x0000 0x02 0x00 +#define IMX952_PAD_I2C1_SCL__AONMIX_TOP_TPM2_CH0 0x01EC 0x041C 0x0000 0x03 0x00 +#define IMX952_PAD_I2C1_SCL__VPUMIX_TOP_UART_RX 0x01EC 0x041C 0x0000 0x04 0x00 +#define IMX952_PAD_I2C1_SCL__AONMIX_TOP_GPIO1_IO_0 0x01EC 0x041C 0x0000 0x05 0x00 + +#define IMX952_PAD_I2C1_SDA__AONMIX_TOP_LPI2C1_SDA 0x01F0 0x0420 0x0000 0x00 0x00 +#define IMX952_PAD_I2C1_SDA__AONMIX_TOP_I3C1_SDA 0x01F0 0x0420 0x0000 0x01 0x00 +#define IMX952_PAD_I2C1_SDA__AONMIX_TOP_LPUART1_RIN_B 0x01F0 0x0420 0x0000 0x02 0x00 +#define IMX952_PAD_I2C1_SDA__AONMIX_TOP_TPM2_CH1 0x01F0 0x0420 0x0000 0x03 0x00 +#define IMX952_PAD_I2C1_SDA__VPUMIX_TOP_UART_TX 0x01F0 0x0420 0x0000 0x04 0x00 +#define IMX952_PAD_I2C1_SDA__AONMIX_TOP_GPIO1_IO_1 0x01F0 0x0420 0x0000 0x05 0x00 + +#define IMX952_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x01F4 0x0424 0x0000 0x00 0x00 +#define IMX952_PAD_I2C2_SCL__AONMIX_TOP_I3C1_PUR 0x01F4 0x0424 0x0000 0x01 0x00 +#define IMX952_PAD_I2C2_SCL__AONMIX_TOP_LPUART2_DCD_B 0x01F4 0x0424 0x0000 0x02 0x00 +#define IMX952_PAD_I2C2_SCL__AONMIX_TOP_TPM2_CH2 0x01F4 0x0424 0x0000 0x03 0x00 +#define IMX952_PAD_I2C2_SCL__AONMIX_TOP_SAI1_RX_SYNC 0x01F4 0x0424 0x0000 0x04 0x00 +#define IMX952_PAD_I2C2_SCL__AONMIX_TOP_GPIO1_IO_2 0x01F4 0x0424 0x0000 0x05 0x00 +#define IMX952_PAD_I2C2_SCL__AONMIX_TOP_I3C1_PUR_B 0x01F4 0x0424 0x0000 0x06 0x00 + +#define IMX952_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x01F8 0x0428 0x0000 0x00 0x00 +#define IMX952_PAD_I2C2_SDA__AONMIX_TOP_LPUART2_RIN_B 0x01F8 0x0428 0x0000 0x02 0x00 +#define IMX952_PAD_I2C2_SDA__AONMIX_TOP_TPM2_CH3 0x01F8 0x0428 0x0000 0x03 0x00 +#define IMX952_PAD_I2C2_SDA__AONMIX_TOP_SAI1_RX_BCLK 0x01F8 0x0428 0x0000 0x04 0x00 +#define IMX952_PAD_I2C2_SDA__AONMIX_TOP_GPIO1_IO_3 0x01F8 0x0428 0x0000 0x05 0x00 + +#define IMX952_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x01FC 0x042C 0x0000 0x00 0x00 +#define IMX952_PAD_UART1_RXD__AONMIX_TOP_UART_CSSI_RX 0x01FC 0x042C 0x0000 0x01 0x00 +#define IMX952_PAD_UART1_RXD__AONMIX_TOP_LPSPI2_SIN 0x01FC 0x042C 0x0000 0x02 0x00 +#define IMX952_PAD_UART1_RXD__AONMIX_TOP_TPM1_CH0 0x01FC 0x042C 0x0000 0x03 0x00 +#define IMX952_PAD_UART1_RXD__AONMIX_TOP_GPIO1_IO_4 0x01FC 0x042C 0x0000 0x05 0x00 + +#define IMX952_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x0200 0x0430 0x0000 0x00 0x00 +#define IMX952_PAD_UART1_TXD__AONMIX_TOP_UART_CSSI_TX 0x0200 0x0430 0x0000 0x01 0x00 +#define IMX952_PAD_UART1_TXD__AONMIX_TOP_LPSPI2_PCS0 0x0200 0x0430 0x0000 0x02 0x00 +#define IMX952_PAD_UART1_TXD__AONMIX_TOP_TPM1_CH1 0x0200 0x0430 0x0000 0x03 0x00 +#define IMX952_PAD_UART1_TXD__AONMIX_TOP_GPIO1_IO_5 0x0200 0x0430 0x0000 0x05 0x00 + +#define IMX952_PAD_UART2_RXD__AONMIX_TOP_LPUART2_RX 0x0204 0x0434 0x0000 0x00 0x00 +#define IMX952_PAD_UART2_RXD__AONMIX_TOP_LPUART1_CTS_B 0x0204 0x0434 0x0000 0x01 0x00 +#define IMX952_PAD_UART2_RXD__AONMIX_TOP_LPSPI2_SOUT 0x0204 0x0434 0x0000 0x02 0x00 +#define IMX952_PAD_UART2_RXD__AONMIX_TOP_TPM1_CH2 0x0204 0x0434 0x0000 0x03 0x00 +#define IMX952_PAD_UART2_RXD__AONMIX_TOP_SAI1_MCLK 0x0204 0x0434 0x0474 0x04 0x00 +#define IMX952_PAD_UART2_RXD__AONMIX_TOP_GPIO1_IO_6 0x0204 0x0434 0x0000 0x05 0x00 + +#define IMX952_PAD_UART2_TXD__AONMIX_TOP_LPUART2_TX 0x0208 0x0438 0x0000 0x00 0x00 +#define IMX952_PAD_UART2_TXD__AONMIX_TOP_LPUART1_RTS_B 0x0208 0x0438 0x0000 0x01 0x00 +#define IMX952_PAD_UART2_TXD__AONMIX_TOP_LPSPI2_SCK 0x0208 0x0438 0x0000 0x02 0x00 +#define IMX952_PAD_UART2_TXD__AONMIX_TOP_TPM1_CH3 0x0208 0x0438 0x0000 0x03 0x00 +#define IMX952_PAD_UART2_TXD__AONMIX_TOP_GPIO1_IO_7 0x0208 0x0438 0x0000 0x05 0x00 + +#define IMX952_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK 0x020C 0x043C 0x0000 0x00 0x00 +#define IMX952_PAD_PDM_CLK__AONMIX_TOP_MQS1_LEFT 0x020C 0x043C 0x0000 0x01 0x00 +#define IMX952_PAD_PDM_CLK__AONMIX_TOP_LPTMR1_ALT0 0x020C 0x043C 0x0000 0x04 0x00 +#define IMX952_PAD_PDM_CLK__AONMIX_TOP_GPIO1_IO_8 0x020C 0x043C 0x0000 0x05 0x00 +#define IMX952_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX 0x020C 0x043C 0x0000 0x06 0x00 + +#define IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_0 0x0210 0x0440 0x0464 0x00 0x00 +#define IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_MQS1_RIGHT 0x0210 0x0440 0x0000 0x01 0x00 +#define IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_LPSPI1_PCS1 0x0210 0x0440 0x0000 0x02 0x00 +#define IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_TPM1_EXTCLK 0x0210 0x0440 0x0000 0x03 0x00 +#define IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_LPTMR1_ALT1 0x0210 0x0440 0x0000 0x04 0x00 +#define IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_GPIO1_IO_9 0x0210 0x0440 0x0000 0x05 0x00 +#define IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX 0x0210 0x0440 0x0460 0x06 0x00 + +#define IMX952_PAD_PDM_BIT_STREAM1__AONMIX_TOP_PDM_BIT_STREAM_1 0x0214 0x0444 0x0468 0x00 0x00 +#define IMX952_PAD_PDM_BIT_STREAM1__AONMIX_TOP_NMI 0x0214 0x0444 0x0000 0x01 0x00 +#define IMX952_PAD_PDM_BIT_STREAM1__AONMIX_TOP_LPSPI2_PCS1 0x0214 0x0444 0x0000 0x02 0x00 +#define IMX952_PAD_PDM_BIT_STREAM1__AONMIX_TOP_TPM2_EXTCLK 0x0214 0x0444 0x0000 0x03 0x00 +#define IMX952_PAD_PDM_BIT_STREAM1__AONMIX_TOP_LPTMR1_ALT2 0x0214 0x0444 0x0000 0x04 0x00 +#define IMX952_PAD_PDM_BIT_STREAM1__AONMIX_TOP_GPIO1_IO_10 0x0214 0x0444 0x0000 0x05 0x00 +#define IMX952_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_TOP_EXT_CLK1 0x0214 0x0444 0x0478 0x06 0x00 + +#define IMX952_PAD_SAI1_TXFS__AONMIX_TOP_SAI1_TX_SYNC 0x0218 0x0448 0x0000 0x00 0x00 +#define IMX952_PAD_SAI1_TXFS__AONMIX_TOP_SAI1_TX_DATA_1 0x0218 0x0448 0x0000 0x01 0x00 +#define IMX952_PAD_SAI1_TXFS__AONMIX_TOP_LPSPI1_PCS0 0x0218 0x0448 0x0000 0x02 0x00 +#define IMX952_PAD_SAI1_TXFS__AONMIX_TOP_LPUART2_DTR_B 0x0218 0x0448 0x0000 0x03 0x00 +#define IMX952_PAD_SAI1_TXFS__AONMIX_TOP_MQS1_LEFT 0x0218 0x0448 0x0000 0x04 0x00 +#define IMX952_PAD_SAI1_TXFS__AONMIX_TOP_GPIO1_IO_11 0x0218 0x0448 0x0000 0x05 0x00 + +#define IMX952_PAD_SAI1_TXC__AONMIX_TOP_SAI1_TX_BCLK 0x021C 0x044C 0x0000 0x00 0x00 +#define IMX952_PAD_SAI1_TXC__AONMIX_TOP_LPUART2_CTS_B 0x021C 0x044C 0x0000 0x01 0x00 +#define IMX952_PAD_SAI1_TXC__AONMIX_TOP_LPSPI1_SIN 0x021C 0x044C 0x0000 0x02 0x00 +#define IMX952_PAD_SAI1_TXC__AONMIX_TOP_LPUART1_DSR_B 0x021C 0x044C 0x0000 0x03 0x00 +#define IMX952_PAD_SAI1_TXC__AONMIX_TOP_CAN1_RX 0x021C 0x044C 0x0460 0x04 0x01 +#define IMX952_PAD_SAI1_TXC__AONMIX_TOP_GPIO1_IO_12 0x021C 0x044C 0x0000 0x05 0x00 + +#define IMX952_PAD_SAI1_TXD0__AONMIX_TOP_SAI1_TX_DATA_0 0x0220 0x0450 0x0000 0x00 0x00 +#define IMX952_PAD_SAI1_TXD0__AONMIX_TOP_LPUART2_RTS_B 0x0220 0x0450 0x0000 0x01 0x00 +#define IMX952_PAD_SAI1_TXD0__AONMIX_TOP_LPSPI1_SCK 0x0220 0x0450 0x0000 0x02 0x00 +#define IMX952_PAD_SAI1_TXD0__AONMIX_TOP_LPUART1_DTR_B 0x0220 0x0450 0x0000 0x03 0x00 +#define IMX952_PAD_SAI1_TXD0__AONMIX_TOP_CAN1_TX 0x0220 0x0450 0x0000 0x04 0x00 +#define IMX952_PAD_SAI1_TXD0__AONMIX_TOP_GPIO1_IO_13 0x0220 0x0450 0x0000 0x05 0x00 + +#define IMX952_PAD_SAI1_RXD0__AONMIX_TOP_SAI1_RX_DATA_0 0x0224 0x0454 0x0000 0x00 0x00 +#define IMX952_PAD_SAI1_RXD0__AONMIX_TOP_SAI1_MCLK 0x0224 0x0454 0x0474 0x01 0x01 +#define IMX952_PAD_SAI1_RXD0__AONMIX_TOP_LPSPI1_SOUT 0x0224 0x0454 0x0000 0x02 0x00 +#define IMX952_PAD_SAI1_RXD0__AONMIX_TOP_LPUART2_DSR_B 0x0224 0x0454 0x0000 0x03 0x00 +#define IMX952_PAD_SAI1_RXD0__AONMIX_TOP_MQS1_RIGHT 0x0224 0x0454 0x0000 0x04 0x00 +#define IMX952_PAD_SAI1_RXD0__AONMIX_TOP_GPIO1_IO_14 0x0224 0x0454 0x0000 0x05 0x00 + +#define IMX952_PAD_WDOG_ANY__AONMIX_TOP_WDOG_ANY 0x0228 0x0458 0x0000 0x00 0x00 +#define IMX952_PAD_WDOG_ANY__AONMIX_TOP_FCCU_EOUT1 0x0228 0x0458 0x0000 0x01 0x00 +#define IMX952_PAD_WDOG_ANY__AONMIX_TOP_GPIO1_IO_15 0x0228 0x0458 0x0000 0x05 0x00 +#endif /* __DTS_IMX952_PINFUNC_H__ */ diff --git a/arch/arm64/boot/dts/freescale/imx952-power.h b/arch/arm64/boot/dts/freescale/imx952-power.h new file mode 100644 index 000000000000..1d0fb8c93e24 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx952-power.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright 2025 NXP + */ + +#ifndef __IMX952_POWER_H__ +#define __IMX952_POWER_H__ + +#define IMX952_PD_ANA 0 +#define IMX952_PD_AON 1 +#define IMX952_PD_BBSM 2 +#define IMX952_PD_CAMERA 3 +#define IMX952_PD_CCMSRCGPC 4 +#define IMX952_PD_A55C0 5 +#define IMX952_PD_A55C1 6 +#define IMX952_PD_A55C2 7 +#define IMX952_PD_A55C3 8 +#define IMX952_PD_A55P 9 +#define IMX952_PD_DDR 10 +#define IMX952_PD_DISPLAY 11 +#define IMX952_PD_GPU 12 +#define IMX952_PD_HSIO_TOP 13 +#define IMX952_PD_HSIO_WAON 14 +#define IMX952_PD_M7 15 +#define IMX952_PD_NETC 16 +#define IMX952_PD_NOC 17 +#define IMX952_PD_NPU 18 +#define IMX952_PD_VPU 19 +#define IMX952_PD_WAKEUP 20 + +#define IMX952_PERF_M33 0 +#define IMX952_PERF_WAKEUP 1 +#define IMX952_PERF_M7 2 +#define IMX952_PERF_DRAM 3 +#define IMX952_PERF_HSIO 4 +#define IMX952_PERF_NPU 5 +#define IMX952_PERF_NOC 6 +#define IMX952_PERF_A55 7 +#define IMX952_PERF_GPU 8 +#define IMX952_PERF_VPU 9 +#define IMX952_PERF_CAM 10 +#define IMX952_PERF_DISP 11 + +#endif diff --git a/arch/arm64/boot/dts/freescale/imx952.dtsi b/arch/arm64/boot/dts/freescale/imx952.dtsi new file mode 100644 index 000000000000..91fe4916ac04 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx952.dtsi @@ -0,0 +1,1266 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) +/* + * Copyright 2025-2026 NXP + */ + +#include <dt-bindings/dma/fsl-edma.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +#include "imx952-clock.h" +#include "imx952-pinfunc.h" +#include "imx952-power.h" + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + clk_ext1: clock-ext1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext1"; + }; + + clk_dummy: clock-dummy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "dummy"; + }; + + clk_ldb_pll_pixel: clock-ldb-pll-div7 { + compatible = "fixed-factor-clock"; + clocks = <&scmi_clk IMX952_CLK_LDBPLL>; + #clock-cells = <0>; + clock-div = <7>; + clock-mult = <1>; + clock-output-names = "ldb_pll_div7"; + }; + + clk_osc_24m: clock-osc-24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc_24m"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + idle-states { + entry-method = "psci"; + + cpu_pd_wait: cpu-pd-wait { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010033>; + local-timer-stop; + entry-latency-us = <1000>; + exit-latency-us = <700>; + min-residency-us = <2700>; + wakeup-latency-us = <1500>; + }; + }; + + A55_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0>; + enable-method = "psci"; + #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; + power-domains = <&scmi_perf IMX952_PERF_A55>; + power-domain-names = "perf"; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l0>; + }; + + A55_1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; + power-domains = <&scmi_perf IMX952_PERF_A55>; + power-domain-names = "perf"; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l1>; + }; + + A55_2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x200>; + enable-method = "psci"; + #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; + power-domains = <&scmi_perf IMX952_PERF_A55>; + power-domain-names = "perf"; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l2>; + }; + + A55_3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x300>; + enable-method = "psci"; + #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; + power-domains = <&scmi_perf IMX952_PERF_A55>; + power-domain-names = "perf"; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l3>; + }; + + l2_cache_l0: l2-cache-l0 { + compatible = "cache"; + cache-size = <65536>; + cache-line-size = <64>; + cache-sets = <256>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_l1: l2-cache-l1 { + compatible = "cache"; + cache-size = <65536>; + cache-line-size = <64>; + cache-sets = <256>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_l2: l2-cache-l2 { + compatible = "cache"; + cache-size = <65536>; + cache-line-size = <64>; + cache-sets = <256>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_l3: l2-cache-l3 { + compatible = "cache"; + cache-size = <65536>; + cache-line-size = <64>; + cache-sets = <256>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l3_cache: l3-cache { + compatible = "cache"; + cache-size = <524288>; + cache-line-size = <64>; + cache-sets = <512>; + cache-level = <3>; + cache-unified; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&A55_0>; + }; + + core1 { + cpu = <&A55_1>; + }; + + core2 { + cpu = <&A55_2>; + }; + + core3 { + cpu = <&A55_3>; + }; + }; + }; + }; + + firmware { + scmi { + compatible = "arm,scmi"; + mboxes = <&mu2 5 0>, <&mu2 3 0>, <&mu2 3 1>, <&mu2 5 1>; + shmem = <&scmi_buf0>, <&scmi_buf1>; + #address-cells = <1>; + #size-cells = <0>; + arm,max-rx-timeout-ms = <5000>; + + scmi_devpd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi_sys_power: protocol@12 { + reg = <0x12>; + }; + + scmi_perf: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi_sensor: protocol@15 { + reg = <0x15>; + #thermal-sensor-cells = <1>; + }; + + scmi_iomuxc: protocol@19 { + reg = <0x19>; + }; + + scmi_lmm: protocol@80 { + reg = <0x80>; + }; + + scmi_bbm: protocol@81 { + reg = <0x81>; + }; + + scmi_cpu: protocol@82 { + reg = <0x82>; + }; + + scmi_misc: protocol@84 { + reg = <0x84>; + }; + }; + }; + + gic: interrupt-controller@48000000 { + compatible = "arm,gic-v3"; + reg = <0 0x48000000 0 0x10000>, + <0 0x48060000 0 0xc0000>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <3>; + dma-noncoherent; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + its: msi-controller@48040000 { + compatible = "arm,gic-v3-its"; + reg = <0 0x48040000 0 0x20000>; + msi-controller; + #msi-cells = <1>; + dma-noncoherent; + }; + }; + + pmu { + compatible = "arm,cortex-a55-pmu"; + interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; + clock-frequency = <24000000>; + arm,no-tick-in-suspend; + interrupt-parent = <&gic>; + }; + + usbphynop1: usbphynop1 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + clocks = <&clk_dummy>; + clock-names = "main_clk"; + }; + + usbphynop2: usbphynop2 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + clocks = <&clk_dummy>; + clock-names = "main_clk"; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0x0 0x0 0x80000000>, + <0x0 0x28000000 0x0 0x28000000 0x0 0x10000000>; + + aips2: bus@42000000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x0 0x42000000 0x0 0x800000>; + ranges = <0x42000000 0x0 0x42000000 0x8000000>, + <0x28000000 0x0 0x28000000 0x10000000>; + #address-cells = <1>; + #size-cells = <1>; + + mu7: mailbox@42050000 { + compatible = "fsl,imx95-mu"; + reg = <0x42050000 0x10000>; + interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>; + #mbox-cells = <2>; + status = "disabled"; + }; + + wdog3: watchdog@420b0000 { + compatible = "fsl,imx93-wdt"; + reg = <0x420b0000 0x10000>; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>; + timeout-sec = <40>; + status = "disabled"; + }; + + tpm3: pwm@42100000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x42100000 0x1000>; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>; + #pwm-cells = <3>; + status = "disabled"; + }; + + tpm4: pwm@42110000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x42110000 0x1000>; + clocks = <&scmi_clk IMX952_CLK_TPM4>; + #pwm-cells = <3>; + status = "disabled"; + }; + + tpm5: pwm@42120000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x42120000 0x1000>; + clocks = <&scmi_clk IMX952_CLK_TPM5>; + #pwm-cells = <3>; + status = "disabled"; + }; + + tpm6: pwm@42130000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x42130000 0x1000>; + clocks = <&scmi_clk IMX952_CLK_TPM6>; + #pwm-cells = <3>; + status = "disabled"; + }; + + i3c2: i3c@42140000 { + compatible = "silvaco,i3c-master-v1"; + reg = <0x42140000 0x10000>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <3>; + #size-cells = <0>; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, + <&scmi_clk IMX952_CLK_I3C2SLOW>, + <&clk_dummy>; + clock-names = "pclk", "fast_clk", "slow_clk"; + status = "disabled"; + }; + + lpi2c3: i2c@42150000 { + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x42150000 0x10000>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk IMX952_CLK_LPI2C3>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&edma2 8 0 0>, <&edma2 9 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpi2c4: i2c@42160000 { + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x42160000 0x10000>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk IMX952_CLK_LPI2C4>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&edma2 10 0 0>, <&edma2 11 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi3: spi@42170000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg = <0x42170000 0x10000>; + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk IMX952_CLK_LPSPI3>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 12 0 0>, <&edma2 13 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi4: spi@42180000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg = <0x42180000 0x10000>; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk IMX952_CLK_LPSPI4>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 14 0 0>, <&edma2 15 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpuart3: serial@42190000 { + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x42190000 0x1000>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk IMX952_CLK_LPUART3>; + clock-names = "ipg"; + dmas = <&edma2 18 0 FSL_EDMA_RX>, <&edma2 17 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lpuart4: serial@421a0000 { + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x421a0000 0x1000>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk IMX952_CLK_LPUART4>; + clock-names = "ipg"; + dmas = <&edma2 20 0 FSL_EDMA_RX>, <&edma2 19 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lpuart5: serial@421b0000 { + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x421b0000 0x1000>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk IMX952_CLK_LPUART5>; + clock-names = "ipg"; + dmas = <&edma2 22 0 FSL_EDMA_RX>, <&edma2 21 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lpuart6: serial@421c0000 { + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x421c0000 0x1000>; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk IMX952_CLK_LPUART6>; + clock-names = "ipg"; + dmas = <&edma2 24 0 FSL_EDMA_RX>, <&edma2 23 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + flexcan2: can@421d0000 { + compatible = "fsl,imx95-flexcan"; + reg = <0x421d0000 0x10000>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, + <&scmi_clk IMX952_CLK_CAN2>; + clock-names = "ipg", "per"; + assigned-clocks = <&scmi_clk IMX952_CLK_CAN2>; + assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD1_DIV2>; + assigned-clock-rates = <40000000>; + fsl,clk-source = /bits/ 8 <0>; + status = "disabled"; + }; + + flexcan3: can@42220000 { + compatible = "fsl,imx95-flexcan"; + reg = <0x42220000 0x10000>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, + <&scmi_clk IMX952_CLK_CAN3>; + clock-names = "ipg", "per"; + assigned-clocks = <&scmi_clk IMX952_CLK_CAN3>; + assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD1_DIV2>; + assigned-clock-rates = <40000000>; + fsl,clk-source = /bits/ 8 <0>; + status = "disabled"; + }; + + lpuart7: serial@422b0000 { + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x422b0000 0x1000>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk IMX952_CLK_LPUART7>; + clock-names = "ipg"; + dmas = <&edma2 88 0 FSL_EDMA_RX>, <&edma2 87 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lpuart8: serial@422c0000 { + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x422c0000 0x1000>; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk IMX952_CLK_LPUART8>; + clock-names = "ipg"; + dmas = <&edma2 90 0 FSL_EDMA_RX>, <&edma2 89 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lpi2c5: i2c@422d0000 { + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x422d0000 0x10000>; + interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk IMX952_CLK_LPI2C5>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&edma2 71 0 0>, <&edma2 72 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpi2c6: i2c@422e0000 { + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x422e0000 0x10000>; + interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk IMX952_CLK_LPI2C6>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&edma2 73 0 0>, <&edma2 74 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpi2c7: i2c@422f0000 { + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x422f0000 0x10000>; + interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk IMX952_CLK_LPI2C7>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&edma2 75 0 0>, <&edma2 76 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpi2c8: i2c@42300000 { + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x42300000 0x10000>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk IMX952_CLK_LPI2C8>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&edma2 77 0 0>, <&edma2 78 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi5: spi@42310000 { + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg = <0x42310000 0x10000>; + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&scmi_clk IMX952_CLK_LPSPI5>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 79 0 0>, <&edma2 80 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi6: spi@42320000 { + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg = <0x42320000 0x10000>; + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&scmi_clk IMX952_CLK_LPSPI6>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 81 0 0>, <&edma2 82 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi7: spi@42330000 { + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg = <0x42330000 0x10000>; + interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&scmi_clk IMX952_CLK_LPSPI7>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 83 0 0>, <&edma2 84 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi8: spi@42340000 { + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg = <0x42340000 0x10000>; + interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&scmi_clk IMX952_CLK_LPSPI8>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 85 0 0>, <&edma2 86 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + mu8: mailbox@42350000 { + compatible = "fsl,imx95-mu"; + reg = <0x42350000 0x10000>; + interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>; + #mbox-cells = <2>; + status = "disabled"; + }; + }; + + aips3: bus@42800000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0 0x42800000 0 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x42800000 0x0 0x42800000 0x800000>; + + edma2: dma-controller@42800000 { + compatible = "fsl,imx95-edma5"; + reg = <0x42800000 0x210000>; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "dma"; + #dma-cells = <3>; + dma-channels = <64>; + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; //error irq + }; + + usdhc1: mmc@42c20000 { + compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x42c20000 0x10000>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, + <&scmi_clk IMX952_CLK_WAKEUPAXI>, + <&scmi_clk IMX952_CLK_USDHC1>; + clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&scmi_clk IMX952_CLK_USDHC1>; + assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD1>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + fsl,tuning-start-tap = <1>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + usdhc2: mmc@42c30000 { + compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x42c30000 0x10000>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, + <&scmi_clk IMX952_CLK_WAKEUPAXI>, + <&scmi_clk IMX952_CLK_USDHC2>; + clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&scmi_clk IMX952_CLK_USDHC2>; + assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD1>; + assigned-clock-rates = <200000000>; + bus-width = <4>; + fsl,tuning-start-tap = <1>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + usdhc3: mmc@42c40000 { + compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x42c40000 0x10000>; + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, + <&scmi_clk IMX952_CLK_WAKEUPAXI>, + <&scmi_clk IMX952_CLK_USDHC3>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + fsl,tuning-start-tap = <1>; + fsl,tuning-step = <2>; + status = "disabled"; + }; + }; + + gpio2: gpio@43810000 { + compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; + reg = <0x0 0x43810000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "gpio", "port"; + gpio-ranges = <&scmi_iomuxc 0 4 32>; + ngpios = <32>; + }; + + gpio3: gpio@43820000 { + compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; + reg = <0x0 0x43820000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "gpio", "port"; + gpio-ranges = <&scmi_iomuxc 0 115 8>, <&scmi_iomuxc 8 85 18>, + <&scmi_iomuxc 26 53 2>, <&scmi_iomuxc 28 0 4>; + ngpios = <32>; + }; + + gpio4: gpio@43840000 { + compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; + reg = <0x0 0x43840000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "gpio", "port"; + gpio-ranges = <&scmi_iomuxc 0 57 28>, <&scmi_iomuxc 28 55 2>; + ngpios = <30>; + }; + + gpio5: gpio@43850000 { + compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; + reg = <0x0 0x43850000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "gpio", "port"; + gpio-ranges = <&scmi_iomuxc 0 103 12>, <&scmi_iomuxc 12 36 6>; + ngpios = <18>; + }; + + aips1: bus@44000000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x0 0x44000000 0x0 0x800000>; + ranges = <0x44000000 0x0 0x44000000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + + edma1: dma-controller@44000000 { + compatible = "fsl,imx93-edma3"; + reg = <0x44000000 0x210000>; + clocks = <&scmi_clk IMX952_CLK_BUSAON>; + clock-names = "dma"; + #dma-cells = <3>; + dma-channels = <32>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; //error irq + }; + + mu1: mailbox@44220000 { + compatible = "fsl,imx95-mu"; + reg = <0x44220000 0x10000>; + interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk IMX952_CLK_BUSAON>; + #mbox-cells = <2>; + status = "disabled"; + }; + + system_counter: timer@44290000 { + compatible = "nxp,imx95-sysctr-timer"; + reg = <0x44290000 0x30000>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_osc_24m>; + clock-names = "per"; + nxp,no-divider; + }; + + i3c1: i3c@44330000 { + compatible = "silvaco,i3c-master-v1"; + reg = <0x44330000 0x10000>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <3>; + #size-cells = <0>; + clocks = <&scmi_clk IMX952_CLK_BUSAON>, + <&scmi_clk IMX952_CLK_I3C1SLOW>, + <&clk_dummy>; + clock-names = "pclk", "fast_clk", "slow_clk"; + status = "disabled"; + }; + + lpi2c1: i2c@44340000 { + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x44340000 0x10000>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk IMX952_CLK_LPI2C1>, + <&scmi_clk IMX952_CLK_BUSAON>; + clock-names = "per", "ipg"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&edma1 12 0 0>, <&edma1 13 0 FSL_EDMA_RX> ; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpi2c2: i2c@44350000 { + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x44350000 0x10000>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk IMX952_CLK_LPI2C2>, + <&scmi_clk IMX952_CLK_BUSAON>; + clock-names = "per", "ipg"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&edma1 14 0 0>, <&edma1 15 0 FSL_EDMA_RX> ; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi1: spi@44360000 { + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg = <0x44360000 0x10000>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk IMX952_CLK_LPSPI1>, + <&scmi_clk IMX952_CLK_BUSAON>; + clock-names = "per", "ipg"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&edma1 16 0 FSL_EDMA_RX>, <&edma1 17 0 0> ; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi2: spi@44370000 { + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg = <0x44370000 0x10000>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk IMX952_CLK_LPSPI2>, + <&scmi_clk IMX952_CLK_BUSAON>; + clock-names = "per", "ipg"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&edma1 18 0 FSL_EDMA_RX>, <&edma1 19 0 0> ; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpuart1: serial@44380000 { + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x44380000 0x1000>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk IMX952_CLK_LPUART1>; + clock-names = "ipg"; + dmas = <&edma1 21 0 FSL_EDMA_RX>, <&edma1 20 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lpuart2: serial@44390000 { + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x44390000 0x1000>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk IMX952_CLK_LPUART2>; + clock-names = "ipg"; + dmas = <&edma1 23 0 FSL_EDMA_RX>, <&edma1 22 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + flexcan1: can@443a0000 { + compatible = "fsl,imx95-flexcan"; + reg = <0x443a0000 0x10000>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk IMX952_CLK_BUSAON>, + <&scmi_clk IMX952_CLK_CAN1>; + clock-names = "ipg", "per"; + assigned-clocks = <&scmi_clk IMX952_CLK_CAN1>; + assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD1_DIV2>; + assigned-clock-rates = <40000000>; + fsl,clk-source = /bits/ 8 <0>; + status = "disabled"; + }; + + adc1: adc@44530000 { + compatible = "nxp,imx93-adc"; + reg = <0x44530000 0x10000>; + interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk IMX952_CLK_ADC>; + clock-names = "ipg"; + #io-channel-cells = <1>; + status = "disabled"; + }; + + mu2: mailbox@445b0000 { + compatible = "fsl,imx95-mu"; + reg = <0x445b0000 0x1000>; + ranges; + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <1>; + #mbox-cells = <2>; + + sram0: sram@445b1000 { + compatible = "mmio-sram"; + reg = <0x445b1000 0x400>; + ranges = <0x0 0x445b1000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + + scmi_buf0: scmi-sram-section@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x80>; + }; + + scmi_buf1: scmi-sram-section@80 { + compatible = "arm,scmi-shmem"; + reg = <0x80 0x80>; + }; + }; + + }; + + mu3: mailbox@445d0000 { + compatible = "fsl,imx95-mu"; + reg = <0x445d0000 0x10000>; + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk IMX952_CLK_BUSAON>; + #mbox-cells = <2>; + status = "disabled"; + }; + + mu4: mailbox@445f0000 { + compatible = "fsl,imx95-mu"; + reg = <0x445f0000 0x10000>; + interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk IMX952_CLK_BUSAON>; + #mbox-cells = <2>; + status = "disabled"; + }; + + mu5: mailbox@44610000 { + compatible = "fsl,imx95-mu"; + reg = <0x44610000 0x10000>; + interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk IMX952_CLK_BUSAON>; + #mbox-cells = <2>; + status = "disabled"; + }; + + mu6: mailbox@44630000 { + compatible = "fsl,imx95-mu"; + reg = <0x44630000 0x10000>; + interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk IMX952_CLK_BUSAON>; + #mbox-cells = <2>; + status = "disabled"; + }; + }; + + v2x_mu0: mailbox@47300000 { + compatible = "fsl,imx95-mu-v2x"; + reg = <0x0 0x47300000 0x0 0x10000>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + }; + + v2x_mu2: mailbox@47320000 { + compatible = "fsl,imx95-mu-v2x"; + reg = <0x0 0x47320000 0x0 0x10000>; + interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + }; + + v2x_mu3: mailbox@47330000 { + compatible = "fsl,imx95-mu-v2x"; + reg = <0x0 0x47330000 0x0 0x10000>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + }; + + v2x_mu4: mailbox@47340000 { + compatible = "fsl,imx95-mu-v2x"; + reg = <0x0 0x47340000 0x0 0x10000>; + interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + }; + + v2x_mu: mailbox@47350000 { + compatible = "fsl,imx95-mu-v2x"; + reg = <0x0 0x47350000 0x0 0x10000>; + interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + }; + + /* GPIO1 is under exclusive control of System Manager */ + gpio1: gpio@47400000 { + compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; + reg = <0x0 0x47400000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk IMX952_CLK_M33>, + <&scmi_clk IMX952_CLK_M33>; + clock-names = "gpio", "port"; + gpio-ranges = <&scmi_iomuxc 0 123 16>; + ngpios = <16>; + status = "disabled"; + }; + + elemu0: mailbox@47520000 { + compatible = "fsl,imx95-mu-ele"; + reg = <0x0 0x47520000 0x0 0x10000>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + status = "disabled"; + }; + + elemu1: mailbox@47530000 { + compatible = "fsl,imx95-mu-ele"; + reg = <0x0 0x47530000 0x0 0x10000>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + status = "disabled"; + }; + + elemu2: mailbox@47540000 { + compatible = "fsl,imx95-mu-ele"; + reg = <0x0 0x47540000 0x0 0x10000>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + status = "disabled"; + }; + + elemu3: mailbox@47550000 { + compatible = "fsl,imx95-mu-ele"; + reg = <0x0 0x47550000 0x0 0x10000>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + }; + + elemu4: mailbox@47560000 { + compatible = "fsl,imx95-mu-ele"; + reg = <0x0 0x47560000 0x0 0x10000>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + status = "disabled"; + }; + + elemu5: mailbox@47570000 { + compatible = "fsl,imx95-mu-ele"; + reg = <0x0 0x47570000 0x0 0x10000>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + status = "disabled"; + }; + + usb1: usb@4c100000 { + compatible = "fsl,imx95-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x0 0x4c100000 0x0 0x200>; + interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk IMX952_CLK_CGC_HSIOUSB>, + <&scmi_clk IMX952_CLK_OSC32K>; + clock-names = "usb_ctrl_root", "usb_wakeup"; + power-domains = <&scmi_devpd IMX952_PD_HSIO_TOP>; + phys = <&usbphynop1>; + fsl,usbmisc = <&usbmisc1 0>; + status = "disabled"; + }; + + usbmisc1: usbmisc@4c100200 { + compatible = "fsl,imx95-usbmisc", "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; + #index-cells = <1>; + reg = <0x0 0x4c100200 0x0 0x200>, + <0x0 0x4c010010 0x0 0x4>; + }; + + usb2: usb@4c200000 { + compatible = "fsl,imx95-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x0 0x4c200000 0x0 0x200>; + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk IMX952_CLK_CGC_HSIOUSB>, + <&scmi_clk IMX952_CLK_OSC32K>; + clock-names = "usb_ctrl_root", "usb_wakeup"; + power-domains = <&scmi_devpd IMX952_PD_HSIO_TOP>; + phys = <&usbphynop2>; + fsl,usbmisc = <&usbmisc2 0>; + status = "disabled"; + }; + + usbmisc2: usbmisc@4c200200 { + compatible = "fsl,imx95-usbmisc", "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; + #index-cells = <1>; + reg = <0x0 0x4c200200 0x0 0x200>, + <0x0 0x4c010014 0x0 0x4>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/mba8xx.dtsi b/arch/arm64/boot/dts/freescale/mba8xx.dtsi index f534dab44e8e..e32519b156d9 100644 --- a/arch/arm64/boot/dts/freescale/mba8xx.dtsi +++ b/arch/arm64/boot/dts/freescale/mba8xx.dtsi @@ -232,7 +232,7 @@ tlv320aic3x04: audio-codec@18 { compatible = "ti,tlv320aic32x4"; reg = <0x18>; - clocks = <&mclkout0_lpcg 0>; + clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>; clock-names = "mclk"; iov-supply = <®_1v8>; ldoin-supply = <®_3v3>; @@ -343,7 +343,7 @@ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, - <&sai1_lpcg 0>; + <&sai1_lpcg IMX_LPCG_CLK_0>; assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai1>; diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi index eff7673e7f34..e314f3c7d61d 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -641,9 +641,9 @@ status = "disabled"; }; - swt7: watchdog@4020C000 { + swt7: watchdog@4020c000 { compatible = "nxp,s32g3-swt", "nxp,s32g2-swt"; - reg = <0x4020C000 0x1000>; + reg = <0x4020c000 0x1000>; clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; clock-names = "counter", "module", "register"; status = "disabled"; diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi index f1969cdcef19..803ff4531077 100644 --- a/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi +++ b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi @@ -197,16 +197,16 @@ }; dspi1-grp3 { - pinmux = <0x5F0>; + pinmux = <0x5f0>; input-enable; slew-rate = <150>; bias-pull-up; }; dspi1-grp4 { - pinmux = <0x3D92>, - <0x3DA2>, - <0x3DB2>; + pinmux = <0x3d92>, + <0x3da2>, + <0x3db2>; }; }; @@ -219,26 +219,26 @@ }; dspi5-grp1 { - pinmux = <0xA0>; + pinmux = <0xa0>; input-enable; slew-rate = <150>; bias-pull-up; }; dspi5-grp2 { - pinmux = <0x3ED2>, - <0x3EE2>, - <0x3EF2>; + pinmux = <0x3ed2>, + <0x3ee2>, + <0x3ef2>; }; dspi5-grp3 { - pinmux = <0xB3>; + pinmux = <0xb3>; output-enable; slew-rate = <150>; }; dspi5-grp4 { - pinmux = <0xC3>; + pinmux = <0xc3>; output-enable; input-enable; slew-rate = <150>; diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi index 3bc3335c9248..979868f6d2c5 100644 --- a/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi +++ b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi @@ -151,16 +151,16 @@ }; dspi1-grp3 { - pinmux = <0x5F0>; + pinmux = <0x5f0>; input-enable; slew-rate = <150>; bias-pull-up; }; dspi1-grp4 { - pinmux = <0x3D92>, - <0x3DA2>, - <0x3DB2>; + pinmux = <0x3d92>, + <0x3da2>, + <0x3db2>; }; }; @@ -173,26 +173,26 @@ }; dspi5-grp1 { - pinmux = <0xA0>; + pinmux = <0xa0>; input-enable; slew-rate = <150>; bias-pull-up; }; dspi5-grp2 { - pinmux = <0x3ED2>, - <0x3EE2>, - <0x3EF2>; + pinmux = <0x3ed2>, + <0x3ee2>, + <0x3ef2>; }; dspi5-grp3 { - pinmux = <0xB3>; + pinmux = <0xb3>; output-enable; slew-rate = <150>; }; dspi5-grp4 { - pinmux = <0xC3>; + pinmux = <0xc3>; output-enable; input-enable; slew-rate = <150>; diff --git a/arch/arm64/boot/dts/freescale/tqma8xxs-mb-smarc-2.dtsi b/arch/arm64/boot/dts/freescale/tqma8xxs-mb-smarc-2.dtsi index 3d20e3bf32ce..050ae23c4dc1 100644 --- a/arch/arm64/boot/dts/freescale/tqma8xxs-mb-smarc-2.dtsi +++ b/arch/arm64/boot/dts/freescale/tqma8xxs-mb-smarc-2.dtsi @@ -126,11 +126,17 @@ status = "okay"; }; +&hsio_phy { + fsl,hsio-cfg = "pciea-x2-pcieb"; + fsl,refclk-pad-mode = "input"; + status = "okay"; +}; + &i2c0 { tlv320aic3x04: audio-codec@18 { compatible = "ti,tlv320aic32x4"; reg = <0x18>; - clocks = <&mclkout0_lpcg 0>; + clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>; clock-names = "mclk"; iov-supply = <®_1v8>; ldoin-supply = <®_3v3>; @@ -156,6 +162,10 @@ status = "okay"; }; +&pcieb { + status = "okay"; +}; + ®_sdvmmc { off-on-delay-us = <200000>; status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/tqma8xxs.dtsi b/arch/arm64/boot/dts/freescale/tqma8xxs.dtsi index 2d0a329c2fa5..bfc918f18d01 100644 --- a/arch/arm64/boot/dts/freescale/tqma8xxs.dtsi +++ b/arch/arm64/boot/dts/freescale/tqma8xxs.dtsi @@ -402,11 +402,19 @@ status = "okay"; }; +&pcieb { + phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; + phy-names = "pcie-phy"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; +}; + &sai1 { assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, - <&sai1_lpcg 0>; + <&sai1_lpcg IMX_LPCG_CLK_0>; assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai1>; @@ -646,9 +654,9 @@ }; pinctrl_pcieb: pcieagrp { - fsl,pins = <IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000041>, - <IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000041>, - <IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000041>; + fsl,pins = <IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000041>, + <IMX8QXP_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B 0x06000041>, + <IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000041>; }; pinctrl_pwm_mipi_lvds0: mipi-lvds0-pwmgrp { diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile index a117268267ee..33fcc55d0cb9 100644 --- a/arch/arm64/boot/dts/intel/Makefile +++ b/arch/arm64/boot/dts/intel/Makefile @@ -1,10 +1,12 @@ # SPDX-License-Identifier: GPL-2.0-only dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \ socfpga_agilex_socdk.dtb \ + socfpga_agilex_socdk_emmc.dtb \ socfpga_agilex_socdk_nand.dtb \ socfpga_agilex3_socdk.dtb \ socfpga_agilex5_socdk.dtb \ socfpga_agilex5_socdk_013b.dtb \ + socfpga_agilex5_socdk_modular.dtb \ socfpga_agilex5_socdk_nand.dtb \ socfpga_n5x_socdk.dtb dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi index a5c2025a616e..352c96d144a8 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi @@ -312,6 +312,7 @@ clock-names = "nf_clk"; cdns,board-delay-ps = <4830>; iommus = <&smmu 4>; + dma-coherent; status = "disabled"; }; @@ -323,40 +324,50 @@ #size-cells = <1>; }; - dmac0: dma-controller@10db0000 { - compatible = "snps,axi-dma-1.01a"; - reg = <0x10db0000 0x500>; - clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>, - <&clkmgr AGILEX5_L4_MP_CLK>; - clock-names = "core-clk", "cfgr-clk"; - interrupt-parent = <&intc>; - interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - dma-channels = <4>; - snps,dma-masters = <1>; - snps,data-width = <2>; - snps,block-size = <32767 32767 32767 32767>; - snps,priority = <0 1 2 3>; - snps,axi-max-burst-len = <8>; - iommus = <&smmu 8>; - }; - - dmac1: dma-controller@10dc0000 { - compatible = "snps,axi-dma-1.01a"; - reg = <0x10dc0000 0x500>; - clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>, - <&clkmgr AGILEX5_L4_MP_CLK>; - clock-names = "core-clk", "cfgr-clk"; - interrupt-parent = <&intc>; - interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - dma-channels = <4>; - snps,dma-masters = <1>; - snps,data-width = <2>; - snps,block-size = <32767 32767 32767 32767>; - snps,priority = <0 1 2 3>; - snps,axi-max-burst-len = <8>; - iommus = <&smmu 9>; + dma: dma-bus@10db0000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <2>; + ranges = <0x00 0x10db0000 0x00 0x20000>; + dma-ranges = <0x00 0x00 0x100 0x00>; + + dmac0: dma-controller@0 { + compatible = "altr,agilex5-axi-dma", + "snps,axi-dma-1.01a"; + reg = <0x0 0x0 0x500>; + clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>, + <&clkmgr AGILEX5_L4_MP_CLK>; + clock-names = "core-clk", "cfgr-clk"; + interrupt-parent = <&intc>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + dma-channels = <4>; + snps,dma-masters = <1>; + snps,data-width = <2>; + snps,block-size = <32767 32767 32767 32767>; + snps,priority = <0 1 2 3>; + snps,axi-max-burst-len = <8>; + iommus = <&smmu 8>; + }; + + dmac1: dma-controller@10000 { + compatible = "altr,agilex5-axi-dma", + "snps,axi-dma-1.01a"; + reg = <0x10000 0x0 0x500>; + clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>, + <&clkmgr AGILEX5_L4_MP_CLK>; + clock-names = "core-clk", "cfgr-clk"; + interrupt-parent = <&intc>; + interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + dma-channels = <4>; + snps,dma-masters = <1>; + snps,data-width = <2>; + snps,block-size = <32767 32767 32767 32767>; + snps,priority = <0 1 2 3>; + snps,axi-max-burst-len = <8>; + iommus = <&smmu 9>; + }; }; rst: rstmgr@10d11000 { @@ -565,6 +576,7 @@ snps,tso; altr,sysmgr-syscon = <&sysmgr 0x44 0>; snps,clk-csr = <0>; + iommus = <&smmu 1>; status = "disabled"; stmmac_axi_emac0_setup: stmmac-axi-config { @@ -618,31 +630,31 @@ snps,dcb-algorithm; }; queue1 { - snps,weight = <0x0A>; + snps,weight = <0x0a>; snps,dcb-algorithm; }; queue2 { - snps,weight = <0x0B>; + snps,weight = <0x0b>; snps,coe-unsupported; snps,dcb-algorithm; }; queue3 { - snps,weight = <0x0C>; + snps,weight = <0x0c>; snps,coe-unsupported; snps,dcb-algorithm; }; queue4 { - snps,weight = <0x0D>; + snps,weight = <0x0d>; snps,coe-unsupported; snps,dcb-algorithm; }; queue5 { - snps,weight = <0x0E>; + snps,weight = <0x0e>; snps,coe-unsupported; snps,dcb-algorithm; }; queue6 { - snps,weight = <0x0F>; + snps,weight = <0x0f>; snps,coe-unsupported; snps,dcb-algorithm; }; @@ -677,6 +689,7 @@ snps,tso; altr,sysmgr-syscon = <&sysmgr 0x48 0>; snps,clk-csr = <0>; + iommus = <&smmu 2>; status = "disabled"; stmmac_axi_emac1_setup: stmmac-axi-config { @@ -730,31 +743,31 @@ snps,dcb-algorithm; }; queue1 { - snps,weight = <0x0A>; + snps,weight = <0x0a>; snps,dcb-algorithm; }; queue2 { - snps,weight = <0x0B>; + snps,weight = <0x0b>; snps,coe-unsupported; snps,dcb-algorithm; }; queue3 { - snps,weight = <0x0C>; + snps,weight = <0x0c>; snps,coe-unsupported; snps,dcb-algorithm; }; queue4 { - snps,weight = <0x0D>; + snps,weight = <0x0d>; snps,coe-unsupported; snps,dcb-algorithm; }; queue5 { - snps,weight = <0x0E>; + snps,weight = <0x0e>; snps,coe-unsupported; snps,dcb-algorithm; }; queue6 { - snps,weight = <0x0F>; + snps,weight = <0x0f>; snps,coe-unsupported; snps,dcb-algorithm; }; @@ -789,6 +802,7 @@ snps,tso; altr,sysmgr-syscon = <&sysmgr 0x4c 0>; snps,clk-csr = <0>; + iommus = <&smmu 3>; status = "disabled"; stmmac_axi_emac2_setup: stmmac-axi-config { @@ -842,31 +856,31 @@ snps,dcb-algorithm; }; queue1 { - snps,weight = <0x0A>; + snps,weight = <0x0a>; snps,dcb-algorithm; }; queue2 { - snps,weight = <0x0B>; + snps,weight = <0x0b>; snps,coe-unsupported; snps,dcb-algorithm; }; queue3 { - snps,weight = <0x0C>; + snps,weight = <0x0c>; snps,coe-unsupported; snps,dcb-algorithm; }; queue4 { - snps,weight = <0x0D>; + snps,weight = <0x0d>; snps,coe-unsupported; snps,dcb-algorithm; }; queue5 { - snps,weight = <0x0E>; + snps,weight = <0x0e>; snps,coe-unsupported; snps,dcb-algorithm; }; queue6 { - snps,weight = <0x0F>; + snps,weight = <0x0f>; snps,coe-unsupported; snps,dcb-algorithm; }; @@ -912,24 +926,24 @@ pmu0_tbu3: pmu@160a2000 { compatible = "arm,smmu-v3-pmcg"; - reg = <0x160A2000 0x1000>, - <0x160B2000 0x1000>; + reg = <0x160a2000 0x1000>, + <0x160b2000 0x1000>; interrupt-parent = <&intc>; interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; }; pmu0_tbu4: pmu@160c2000 { compatible = "arm,smmu-v3-pmcg"; - reg = <0x160C2000 0x1000>, - <0x160D2000 0x1000>; + reg = <0x160c2000 0x1000>, + <0x160d2000 0x1000>; interrupt-parent = <&intc>; interrupts = <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>; }; pmu0_tbu5: pmu@160e2000 { compatible = "arm,smmu-v3-pmcg"; - reg = <0x160E2000 0x1000>, - <0x160F2000 0x1000>; + reg = <0x160e2000 0x1000>, + <0x160f2000 0x1000>; interrupt-parent = <&intc>; interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>; }; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts new file mode 100644 index 000000000000..1831402d8808 --- /dev/null +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2025, Altera Corporation + */ +#include "socfpga_agilex5.dtsi" + +/ { + model = "SoCFPGA Agilex5 SoCDK - Modular development kit"; + compatible = "intel,socfpga-agilex5-socdk-modular", "intel,socfpga-agilex5"; + + aliases { + serial0 = &uart0; + ethernet2 = &gmac2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led0 { + label = "hps_led0"; + gpios = <&porta 0x0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the reg */ + reg = <0x0 0x80000000 0x0 0x0>; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gmac2 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <&emac2_phy0>; + max-frame-size = <9000>; + + mdio0 { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + emac2_phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&osc1 { + clock-frequency = <25000000>; +}; + +&qspi { + status = "okay"; + flash@0 { + compatible = "micron,mt25qu02g", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <100000000>; + m25p,fast-read; + cdns,read-delay = <2>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + qspi_boot: partition@0 { + label = "u-boot"; + reg = <0x0 0x04200000>; + }; + + root: partition@4200000 { + label = "root"; + reg = <0x04200000 0x0be00000>; + }; + }; + }; +}; + +&smmu { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&watchdog0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts index 9ee312bae8d2..8f8a5423ba02 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts @@ -131,7 +131,7 @@ root: partition@4200000 { label = "Root Filesystem - UBIFS"; - reg = <0x04200000 0x0BE00000>; + reg = <0x04200000 0x0be00000>; }; }; }; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_emmc.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_emmc.dts new file mode 100644 index 000000000000..1d3a2d7d48c0 --- /dev/null +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_emmc.dts @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2026, Altera Corporation + */ +#include "socfpga_agilex.dtsi" + +/ { + model = "SoCFPGA Agilex SoCDK eMMC daughter board"; + compatible = "intel,socfpga-agilex-socdk-emmc", "intel,socfpga-agilex"; + + aliases { + serial0 = &uart0; + ethernet0 = &gmac0; + ethernet1 = &gmac1; + ethernet2 = &gmac2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + led0 { + label = "hps_led0"; + gpios = <&portb 20 GPIO_ACTIVE_HIGH>; + }; + + led1 { + label = "hps_led1"; + gpios = <&portb 19 GPIO_ACTIVE_HIGH>; + }; + + led2 { + label = "hps_led2"; + gpios = <&portb 21 GPIO_ACTIVE_HIGH>; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the reg */ + reg = <0 0x80000000 0 0>; + }; +}; + +&gpio1 { + status = "okay"; +}; + +&gmac2 { + status = "okay"; + /* PHY delays is configured via skew properties */ + phy-mode = "rgmii"; + phy-handle = <&phy0>; + + max-frame-size = <9000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@4 { + reg = <4>; + + txd0-skew-ps = <0>; /* -420ps */ + txd1-skew-ps = <0>; /* -420ps */ + txd2-skew-ps = <0>; /* -420ps */ + txd3-skew-ps = <0>; /* -420ps */ + rxd0-skew-ps = <420>; /* 0ps */ + rxd1-skew-ps = <420>; /* 0ps */ + rxd2-skew-ps = <420>; /* 0ps */ + rxd3-skew-ps = <420>; /* 0ps */ + txen-skew-ps = <0>; /* -420ps */ + txc-skew-ps = <900>; /* 0ps */ + rxdv-skew-ps = <420>; /* 0ps */ + rxc-skew-ps = <1680>; /* 780ps */ + }; + }; +}; + +&mmc { + status = "okay"; + cap-mmc-highspeed; + broken-cd; + bus-width = <4>; + clk-phase-sd-hs = <0>, <135>; +}; + +&osc1 { + clock-frequency = <25000000>; +}; + +&uart0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + disable-over-current; +}; + +&watchdog0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts index 0034a4897220..d7d500f50a07 100644 --- a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts @@ -103,12 +103,12 @@ qspi_boot: partition@0 { label = "Boot and fpga data"; - reg = <0x0 0x03FE0000>; + reg = <0x0 0x03fe0000>; }; qspi_rootfs: partition@3fe0000 { label = "Root Filesystem - JFFS2"; - reg = <0x03FE0000 0x0C020000>; + reg = <0x03fe0000 0x0c020000>; }; }; }; diff --git a/arch/arm64/boot/dts/lg/lg131x.dtsi b/arch/arm64/boot/dts/lg/lg131x.dtsi index 4cb1e4510897..90988770cb5c 100644 --- a/arch/arm64/boot/dts/lg/lg131x.dtsi +++ b/arch/arm64/boot/dts/lg/lg131x.dtsi @@ -102,7 +102,7 @@ clock-output-names = "BUSCLK"; }; - amba { + amba-bus { #address-cells = <2>; #size-cells = <1>; diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile index a774bc74a0a0..09d1544041af 100644 --- a/arch/arm64/boot/dts/marvell/Makefile +++ b/arch/arm64/boot/dts/marvell/Makefile @@ -11,6 +11,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin-v7-emmc.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-gl-mv1000.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-turris-mox.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-uDPU.dtb +dtb-$(CONFIG_ARCH_MVEBU) += db-falcon-carrier-a7k.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-7040-db.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-7040-mochabin.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-clearfog-gt-8k.dtb diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts b/arch/arm64/boot/dts/marvell/armada-3720-db.dts index bd4e61d5448e..06d4a3a93f84 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts @@ -41,6 +41,7 @@ usb3_phy: usb3-phy { compatible = "usb-nop-xceiv"; + #phy-cells = <0>; vcc-supply = <&exp_usb3_vbus>; }; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts index 97a180c8dcd9..0ab33aa928e7 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts @@ -37,11 +37,11 @@ usb3_phy: usb3-phy { compatible = "usb-nop-xceiv"; + #phy-cells = <0>; vcc-supply = <®_usb3_vbus>; }; gpio-leds { - pinctrl-names = "default"; compatible = "gpio-leds"; /* No assigned functions to the LEDs by default */ led1 { diff --git a/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts b/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts index 9f4bafeddd82..a881a3326dba 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts @@ -26,16 +26,11 @@ }; vcc_sd_reg1: regulator { - compatible = "regulator-gpio"; + compatible = "regulator-fixed"; regulator-name = "vcc_sd1"; - regulator-min-microvolt = <1800000>; + regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-boot-on; - - gpios-states = <0>; - states = <1800000 0x1 - 3300000 0x0>; - enable-active-high; }; keys { diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index c612317043ea..87f9367aec12 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -427,7 +427,8 @@ }; crypto: crypto@90000 { - compatible = "inside-secure,safexcel-eip97ies"; + compatible = "marvell,armada-3700-crypto", + "inside-secure,safexcel-eip97ies"; reg = <0x90000 0x20000>; interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm64/boot/dts/marvell/armada-7020-comexpress.dtsi b/arch/arm64/boot/dts/marvell/armada-7020-comexpress.dtsi new file mode 100644 index 000000000000..2b5ec4a451e3 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/armada-7020-comexpress.dtsi @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 Marvell Technology Group Ltd. + * + * Device Tree file for Marvell Armada 7020 Com Express CPU module board. + */ + +#include "armada-7020.dtsi" + +/ { + model = "Marvell Armada-7020 COMEXPRESS board setup"; + compatible = "marvell,armada7020-cpu-module", "marvell,armada7020", + "marvell,armada-ap806-dual", "marvell,armada-ap806"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x2 0x00000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + ethernet0 = &cp0_eth0; + ethernet1 = &cp0_eth1; + }; +}; + +&ap_clk { + status = "okay"; +}; + +&gic { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <100000>; +}; + +&spi0 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&cp0_mdio { + status = "okay"; + + phy0: ethernet-phy@10 { + reg = <0x10>; + }; +}; + +&cp0_ethernet { + status = "okay"; +}; + +&cp0_eth0 { + status = "okay"; + phy-mode = "10gbase-r"; + managed = "in-band-status"; + /* Generic PHY, providing serdes lanes */ + phys = <&cp0_comphy4 0>; +}; + +&cp0_eth1 { + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; +}; + +&cp0_usb3_0 { + status = "okay"; +}; + +&cp0_usb3_1 { + status = "okay"; +}; + +&cp0_clk { + status = "okay"; +}; + +&cp0_i2c0 { + status = "okay"; + clock-frequency = <100000>; +}; + +&cp0_nand_controller { + status = "okay"; + + nand@0 { + reg = <0>; + label = "main-storage"; + nand-rb = <0>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0 0x400000>; + }; + partition@200000 { + label = "Linux"; + reg = <0x400000 0x100000>; + }; + partition@1000000 { + label = "Filesystem"; + reg = <0x500000 0x1e00000>; + }; + }; + }; +}; + +&cp0_pcie0 { + status = "okay"; + num-lanes = <4>; + num-viewport = <8>; + + ranges = <0x81000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x00010000 + 0x82000000 0x0 0x00000000 0x0 0xc0000000 0x0 0x30000000>; + + /* Generic PHY, providing serdes lanes */ + phys = <&cp0_comphy0 0 + &cp0_comphy1 0 + &cp0_comphy2 0 + &cp0_comphy3 0>; +}; + +&cp0_sata0 { + /* CPM Lane 0 - U29 */ + status = "okay"; + + sata-port@1 { + status = "okay"; + /* Generic PHY, providing serdes lanes */ + phys = <&cp0_comphy5 1>; + }; +}; + +&cp0_sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&sdhci_pins>; + status = "okay"; + bus-width = <4>; + no-1-8-v; + broken-cd; +}; + diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi index df939426d258..36e0a8a0ade3 100644 --- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi @@ -47,6 +47,13 @@ cp0_pinctrl: pinctrl { compatible = "marvell,armada-7k-pinctrl"; + + sdhci_pins: sdhci-pins { + marvell,pins = "mpp56", "mpp57", "mpp58", + "mpp59", "mpp60", "mpp61", "mpp62"; + marvell,function = "sdio"; + }; + nand_pins: nand-pins { marvell,pins = "mpp15", "mpp16", "mpp17", "mpp18", diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts b/arch/arm64/boot/dts/marvell/armada-8040-db.dts index 21ecb9c12505..c7102f74d4d5 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts @@ -51,6 +51,7 @@ cp0_usb3_0_phy: cp0-usb3-0-phy { compatible = "usb-nop-xceiv"; + #phy-cells = <0>; vcc-supply = <&cp0_reg_usb3_0_vbus>; }; @@ -65,6 +66,7 @@ cp1_usb3_0_phy: cp1-usb3-0-phy { compatible = "usb-nop-xceiv"; + #phy-cells = <0>; vcc-supply = <&cp1_reg_usb3_0_vbus>; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi index 82f4dedfc25e..0868d59d561b 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi @@ -54,7 +54,7 @@ }; thermal-zones { - /delete-node/ ap-thermal-cpu2; - /delete-node/ ap-thermal-cpu3; + /delete-node/ ap-cpu2-thermal; + /delete-node/ ap-cpu3-thermal; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi index d9d409eac259..39599171d51b 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi @@ -512,7 +512,8 @@ }; CP11X_LABEL(crypto): crypto@800000 { - compatible = "inside-secure,safexcel-eip197b"; + compatible = "marvell,armada-cp110-crypto", + "inside-secure,safexcel-eip197b"; reg = <0x800000 0x200000>; interrupts = <88 IRQ_TYPE_LEVEL_HIGH>, <89 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm64/boot/dts/marvell/cn9130-cf-base.dts b/arch/arm64/boot/dts/marvell/cn9130-cf-base.dts index 788a5c302b17..212865f6cf6a 100644 --- a/arch/arm64/boot/dts/marvell/cn9130-cf-base.dts +++ b/arch/arm64/boot/dts/marvell/cn9130-cf-base.dts @@ -137,7 +137,7 @@ &cp0_pinctrl { pinctrl-0 = <&sim_select_pins>; - pintrl-names = "default"; + pinctrl-names = "default"; rear_button_pins: cp0-rear-button-pins { marvell,pins = "mpp31"; diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi index 5e7d6de3cdde..c9050e707a60 100644 --- a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi @@ -47,10 +47,12 @@ cp0_usb3_0_phy0: usb-phy-1 { compatible = "usb-nop-xceiv"; + #phy-cells = <0>; }; cp0_usb3_0_phy1: usb-phy-2 { compatible = "usb-nop-xceiv"; + #phy-cells = <0>; vcc-supply = <&cp0_reg_usb3_vbus1>; }; @@ -91,7 +93,6 @@ /* on-board eMMC U6 */ &ap_sdhci0 { - pinctrl-names = "default"; bus-width = <8>; status = "okay"; mmc-ddr-1_8v; diff --git a/arch/arm64/boot/dts/marvell/cn9130-db.dtsi b/arch/arm64/boot/dts/marvell/cn9130-db.dtsi index 3cc320f569ad..8e413286e019 100644 --- a/arch/arm64/boot/dts/marvell/cn9130-db.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9130-db.dtsi @@ -50,6 +50,7 @@ cp0_usb3_0_phy0: usb-phy-1 { compatible = "usb-nop-xceiv"; + #phy-cells = <0>; vcc-supply = <&cp0_reg_usb3_vbus0>; }; @@ -64,6 +65,7 @@ cp0_usb3_0_phy1: usb-phy-2 { compatible = "usb-nop-xceiv"; + #phy-cells = <0>; vcc-supply = <&cp0_reg_usb3_vbus1>; }; @@ -109,7 +111,6 @@ /* on-board eMMC - U9 */ &ap_sdhci0 { - pinctrl-names = "default"; bus-width = <8>; vqmmc-supply = <&ap0_reg_sd_vccq>; status = "okay"; @@ -164,7 +165,6 @@ /* U36 */ expander0: pca953x@21 { compatible = "nxp,pca9555"; - pinctrl-names = "default"; gpio-controller; #gpio-cells = <2>; reg = <0x21>; diff --git a/arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts b/arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts index 338853d3b179..b6aeba7d0a61 100644 --- a/arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts +++ b/arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts @@ -202,6 +202,8 @@ expander0: gpio@41 { compatible = "nxp,pca9536"; reg = <0x41>; + gpio-controller; + #gpio-cells = <2>; usb-a-vbus0-ilimit-hog { gpio-hog; diff --git a/arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dtsi b/arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dtsi index 6f3914bcfd01..71c225221617 100644 --- a/arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dtsi @@ -15,8 +15,9 @@ }; &ap0_reg_sd_vccq { + compatible = "regulator-fixed"; regulator-max-microvolt = <1800000>; - states = <1800000 0x1 1800000 0x0>; + /delete-property/ states; /delete-property/ gpios; }; diff --git a/arch/arm64/boot/dts/marvell/cn9131-db.dtsi b/arch/arm64/boot/dts/marvell/cn9131-db.dtsi index 626042fce7e2..26dc91c88677 100644 --- a/arch/arm64/boot/dts/marvell/cn9131-db.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9131-db.dtsi @@ -31,6 +31,7 @@ cp1_usb3_0_phy0: usb-phy-3 { compatible = "usb-nop-xceiv"; + #phy-cells = <0>; vcc-supply = <&cp1_reg_usb3_vbus0>; }; diff --git a/arch/arm64/boot/dts/marvell/cn9132-db.dtsi b/arch/arm64/boot/dts/marvell/cn9132-db.dtsi index f91fc69905b8..98eee9e4e10b 100644 --- a/arch/arm64/boot/dts/marvell/cn9132-db.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9132-db.dtsi @@ -28,6 +28,7 @@ cp2_usb3_0_phy0: usb-phy-4 { compatible = "usb-nop-xceiv"; + #phy-cells = <0>; vcc-supply = <&cp2_reg_usb3_vbus0>; }; @@ -42,6 +43,7 @@ cp2_usb3_0_phy1: usb-phy-5 { compatible = "usb-nop-xceiv"; + #phy-cells = <0>; vcc-supply = <&cp2_reg_usb3_vbus1>; }; @@ -140,7 +142,6 @@ /* U12 */ cp2_module_expander1: pca9555@21 { compatible = "nxp,pca9555"; - pinctrl-names = "default"; gpio-controller; #gpio-cells = <2>; reg = <0x21>; diff --git a/arch/arm64/boot/dts/marvell/db-falcon-carrier-a7k.dts b/arch/arm64/boot/dts/marvell/db-falcon-carrier-a7k.dts new file mode 100644 index 000000000000..5d1ae7b35b62 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/db-falcon-carrier-a7k.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 Marvell International Ltd. + * + * Device tree for the Falcon DB Type 7 Com Express carrier board, + * Utilizing the Armada 7020 COM Express CPU module board. + * This specific carrier board (DB-98CX8540/80) + * only maintains a PCIe link with the CPU module, + * which does not require any special DTS definitions. + * + * There is no Linux CPU booting in this mode on the carrier, only on the + * Armada 7020 COM Express CPU module. + * What runs the Linux is the Armada 7020 on the COM Express CPU module, + * And it accesses the switch end-point on the Falcon DB portion of the carrier + * via PCIe. + */ + +#include "armada-7020-comexpress.dtsi" +#include "db-falcon-carrier.dtsi" + +/ { + model = "Marvell Falcon DB COM EXPRESS type 7 carrier board with Armada 7020 CPU module"; + compatible = "marvell,armada7020-falcon-carrier", "marvell,db-falcon-carrier", + "marvell,armada7020-cpu-module", "marvell,armada7020", + "marvell,armada-ap806-dual", "marvell,armada-ap806"; + +}; diff --git a/arch/arm64/boot/dts/marvell/db-falcon-carrier.dtsi b/arch/arm64/boot/dts/marvell/db-falcon-carrier.dtsi new file mode 100644 index 000000000000..c85ad1547ec5 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/db-falcon-carrier.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 Marvell International Ltd. + * + * Device tree for the Falcon DB Type 7 Com Express carrier board, + * This (DB-98CX8540/80) specific carrier board only maintains + * a PCIe link with the COM Express CPU module, which does not + * require any special DTS definitions. + * + * The board contains the 98CX8540/80 Switch, which connects by + * PCIe to the COM Express CPU module. + * This CPU module can be any standard COM Express CPU module with + * PCIe support. + * + * There is no Linux CPU booting in this mode on the carrier, + * only on the COM Express CPU module. + */ + +/ { + model = "Marvell Armada Falcon DB COM EXPRESS type 7 carrier board"; + compatible = "marvell,db-falcon-carrier"; +}; diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 3f76d9ce9879..387faa9c2a09 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -159,10 +159,12 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8365-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8370-genio-510-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8370-grinn-genio-510-sbc.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8370-tungsten-smarc.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-genio-1200-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-genio-1200-evk-ufs.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-genio-700-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-grinn-genio-700-sbc.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-tungsten-smarc.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-kontron-3-5-sbc-i1200.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-radxa-nio-12l.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-radxa-nio-12l-8-hd-panel.dtbo diff --git a/arch/arm64/boot/dts/mediatek/mt6331.dtsi b/arch/arm64/boot/dts/mediatek/mt6331.dtsi index 243afbffa21f..7e7b96e8ca6f 100644 --- a/arch/arm64/boot/dts/mediatek/mt6331.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6331.dtsi @@ -217,7 +217,7 @@ }; mt6331_vcamio_reg: ldo-vcamio { - regulator-name = "vcam_io"; + regulator-name = "vcamio"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1800000>; regulator-ramp-delay = <0>; diff --git a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts index fccb948cfa45..0e086dd487d9 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts +++ b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts @@ -227,8 +227,9 @@ &mmc1 { /* MicroSD card slot */ - pinctrl-names = "default"; + pinctrl-names = "default", "state_uhs"; pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_uhs>; vmmc-supply = <&mt6331_vmc_reg>; vqmmc-supply = <&mt6331_vmch_reg>; status = "okay"; @@ -236,8 +237,9 @@ &mmc2 { /* SDIO WiFi on MMC2 */ - pinctrl-names = "default"; + pinctrl-names = "default", "state_uhs"; pinctrl-0 = <&mmc2_pins_default>; + pinctrl-1 = <&mmc2_pins_uhs>; vmmc-supply = <&mt6331_vmc_reg>; vqmmc-supply = <&mt6331_vmch_reg>; status = "okay"; @@ -324,11 +326,32 @@ <PINMUX_GPIO170__FUNC_MSDC1_CMD>; input-enable; bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + drive-strength = <4>; }; pins-clk { pinmux = <PINMUX_GPIO175__FUNC_MSDC1_CLK>; bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + drive-strength = <4>; + }; + }; + + mmc1_pins_uhs: microsd-uhs-pins { + pins-cmd-dat { + pinmux = <PINMUX_GPIO171__FUNC_MSDC1_DAT0>, + <PINMUX_GPIO172__FUNC_MSDC1_DAT1>, + <PINMUX_GPIO173__FUNC_MSDC1_DAT2>, + <PINMUX_GPIO174__FUNC_MSDC1_DAT3>, + <PINMUX_GPIO170__FUNC_MSDC1_CMD>; + input-enable; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + drive-strength = <6>; + }; + + pins-clk { + pinmux = <PINMUX_GPIO175__FUNC_MSDC1_CLK>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + drive-strength = <8>; }; }; @@ -341,11 +364,32 @@ <PINMUX_GPIO105__FUNC_MSDC2_CMD>; input-enable; bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + drive-strength = <4>; + }; + + pins-clk { + pinmux = <PINMUX_GPIO104__FUNC_MSDC2_CLK>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + drive-strength = <4>; + }; + }; + + mmc2_pins_uhs: sdio-uhs-pins { + pins-cmd-dat { + pinmux = <PINMUX_GPIO100__FUNC_MSDC2_DAT0>, + <PINMUX_GPIO101__FUNC_MSDC2_DAT1>, + <PINMUX_GPIO102__FUNC_MSDC2_DAT2>, + <PINMUX_GPIO103__FUNC_MSDC2_DAT3>, + <PINMUX_GPIO105__FUNC_MSDC2_CMD>; + input-enable; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + drive-strength = <8>; }; pins-clk { pinmux = <PINMUX_GPIO104__FUNC_MSDC2_CLK>; bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + drive-strength = <8>; }; }; @@ -463,7 +507,7 @@ */ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; - mt6332-led { + leds { compatible = "mediatek,mt6332-led"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index 58833e5135c8..ae2aaa51c9ad 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -287,9 +287,8 @@ }; scpsys: syscon@10006000 { - compatible = "syscon", "simple-mfd"; + compatible = "mediatek,mt6795-scpsys", "syscon", "simple-mfd"; reg = <0 0x10006000 0 0x1000>; - #power-domain-cells = <1>; /* System Power Manager */ spm: power-controller { diff --git a/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts b/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts index 2e39e7287730..b7ff7b8e1375 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts +++ b/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts @@ -12,6 +12,8 @@ model = "OpenWrt One"; aliases { + ethernet0 = &gmac1; + ethernet1 = &gmac0; serial0 = &uart0; }; @@ -67,9 +69,94 @@ linux,default-trigger = "netdev"; }; }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "fixed-5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +ð { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + /* WAN interface */ + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + nvmem-cells = <&wan_factory_mac 0>; + nvmem-cell-names = "mac-address"; + phy-mode = "2500base-x"; + phy-handle = <&phy15>; + }; + + /* LAN interface */ + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "gmii"; + phy-handle = <&int_gbe_phy>; + }; +}; + +&mdio_bus { + phy15: ethernet-phy@f { + compatible = "ethernet-phy-id03a2.a411"; + reg = <0xf>; + interrupt-parent = <&pio>; + interrupts = <38 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&pio 39 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <20000>; + airoha,pnswap-rx; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + function = LED_FUNCTION_WAN; + color = <LED_COLOR_ID_AMBER>; + }; + + led@1 { + reg = <1>; + function = LED_FUNCTION_WAN; + color = <LED_COLOR_ID_GREEN>; + }; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pins>; + status = "okay"; }; &pio { + pcie_pins: pcie-pins { + mux { + function = "pcie"; + groups = "pcie_pereset"; + }; + }; + pwm_pins: pwm-pins { mux { function = "pwm"; @@ -95,6 +182,22 @@ pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; }; }; + + wifi_dbdc_pins: wifi-dbdc-pins { + mux { + function = "eth"; + groups = "wf0_mode1"; + }; + + conf { + pins = "WF_HB1", "WF_HB2", "WF_HB3", "WF_HB4", + "WF_HB0", "WF_HB0_B", "WF_HB5", "WF_HB6", + "WF_HB7", "WF_HB8", "WF_HB9", "WF_HB10", + "WF_TOP_CLK", "WF_TOP_DATA", "WF_XO_REQ", + "WF_CBA_RESETB", "WF_DIG_RESETB"; + drive-strength = <4>; + }; + }; }; &pwm { @@ -112,8 +215,6 @@ compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <40000000>; - #address-cells = <1>; - #size-cells = <1>; partitions { compatible = "fixed-partitions"; @@ -160,6 +261,30 @@ }; }; +&sgmiisys0 { + mediatek,pnswap; +}; + &uart0 { status = "okay"; }; + +&usb_phy { + status = "okay"; +}; + +&wifi { + nvmem-cells = <&wifi_factory_calibration>; + nvmem-cell-names = "eeprom"; + pinctrl-names = "dbdc"; + pinctrl-0 = <&wifi_dbdc_pins>; + status = "okay"; +}; + +&xhci { + phys = <&u2port0 PHY_TYPE_USB2>; + vusb33-supply = <®_3p3v>; + vbus-supply = <®_5v>; + mediatek,u3p-dis-msk = <0x01>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi index 416096b80770..4084f4dfa3e5 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi @@ -2,6 +2,8 @@ #include <dt-bindings/clock/mediatek,mt7981-clk.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/phy/phy.h> #include <dt-bindings/reset/mt7986-resets.h> / { @@ -46,11 +48,41 @@ #size-cells = <2>; ranges; + wo_boot: wo-boot@15194000 { + reg = <0 0x15194000 0 0x1000>; + no-map; + }; + + wo_ilm0: wo-ilm@151e0000 { + reg = <0 0x151e0000 0 0x8000>; + no-map; + }; + + wo_dlm0: wo-dlm@151e8000 { + reg = <0 0x151e8000 0 0x2000>; + no-map; + }; + /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ secmon_reserved: secmon@43000000 { reg = <0 0x43000000 0 0x30000>; no-map; }; + + wmcpu_emi: wmcpu-reserved@47c80000 { + reg = <0 0x47c80000 0 0x100000>; + no-map; + }; + + wo_emi0: wo-emi@47d80000 { + reg = <0 0x47d80000 0 0x40000>; + no-map; + }; + + wo_data: wo-data@47dc0000 { + reg = <0 0x47dc0000 0 0x240000>; + no-map; + }; }; soc { @@ -106,6 +138,18 @@ #pwm-cells = <2>; }; + sgmiisys0: syscon@10060000 { + compatible = "mediatek,mt7981-sgmiisys_0", "syscon"; + reg = <0 0x10060000 0 0x1000>; + #clock-cells = <1>; + }; + + sgmiisys1: syscon@10070000 { + compatible = "mediatek,mt7981-sgmiisys_1", "syscon"; + reg = <0 0x10070000 0 0x1000>; + #clock-cells = <1>; + }; + uart0: serial@11002000 { compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart"; reg = <0 0x11002000 0 0x100>; @@ -223,6 +267,55 @@ status = "disabled"; }; + xhci: usb@11200000 { + compatible = "mediatek,mt7986-xhci", "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x2e00>, <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>, + <&infracfg CLK_INFRA_IUSB_CK>, + <&infracfg CLK_INFRA_IUSB_133_CK>, + <&infracfg CLK_INFRA_IUSB_66M_CK>, + <&topckgen CLK_TOP_U2U3_XHCI_SEL>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; + phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; + status = "disabled"; + }; + + pcie: pcie@11280000 { + compatible = "mediatek,mt7981-pcie", + "mediatek,mt8192-pcie"; + reg = <0 0x11280000 0 0x4000>; + reg-names = "pcie-mac"; + ranges = <0x82000000 0 0x20000000 + 0x0 0x20000000 0 0x10000000>; + bus-range = <0x00 0xff>; + clocks = <&infracfg CLK_INFRA_IPCIE_CK>, + <&infracfg CLK_INFRA_IPCIE_PIPE_CK>, + <&infracfg CLK_INFRA_IPCIER_CK>, + <&infracfg CLK_INFRA_IPCIEB_CK>; + clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m"; + device_type = "pci"; + phys = <&u3port0 PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + #address-cells = <3>; + #interrupt-cells = <1>; + #size-cells = <2>; + status = "disabled"; + + pcie_intc: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + pio: pinctrl@11d00000 { compatible = "mediatek,mt7981-pinctrl"; reg = <0 0x11d00000 0 0x1000>, @@ -252,6 +345,36 @@ }; }; + topmisc: topmisc@11d10000 { + compatible = "mediatek,mt7981-topmisc", "syscon"; + reg = <0 0x11d10000 0 0x10000>; + #clock-cells = <1>; + }; + + usb_phy: t-phy@11e10000 { + compatible = "mediatek,mt7981-tphy", + "mediatek,generic-tphy-v2"; + ranges = <0 0 0x11e10000 0x1700>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + u2port0: usb-phy@0 { + reg = <0x0 0x700>; + clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>; + clock-names = "ref"; + #phy-cells = <1>; + }; + + u3port0: usb-phy@700 { + reg = <0x700 0x900>; + clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>; + clock-names = "ref"; + #phy-cells = <1>; + mediatek,syscon-type = <&topmisc 0x218 0>; + }; + }; + efuse@11f20000 { compatible = "mediatek,mt7981-efuse", "mediatek,efuse"; reg = <0 0x11f20000 0 0x1000>; @@ -265,16 +388,107 @@ thermal_calibration: thermal-calib@274 { reg = <0x274 0xc>; }; + + phy_calibration: phy-calib@8dc { + reg = <0x8dc 0x10>; + }; }; - clock-controller@15000000 { + ethsys: clock-controller@15000000 { compatible = "mediatek,mt7981-ethsys", "syscon"; reg = <0 0x15000000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; }; - wifi@18000000 { + wed: wed@15010000 { + compatible = "mediatek,mt7981-wed", + "syscon"; + reg = <0 0x15010000 0 0x1000>; + interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; + memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>, + <&wo_data>, <&wo_boot>; + memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", + "wo-data", "wo-boot"; + mediatek,wo-ccif = <&wo_ccif0>; + }; + + eth: ethernet@15100000 { + compatible = "mediatek,mt7981-eth"; + reg = <0 0x15100000 0 0x40000>; + assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, + <&topckgen CLK_TOP_SGM_325M_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_800M>, + <&topckgen CLK_TOP_CB_SGM_325M>; + clocks = <ðsys CLK_ETH_FE_EN>, + <ðsys CLK_ETH_GP2_EN>, + <ðsys CLK_ETH_GP1_EN>, + <ðsys CLK_ETH_WOCPU0_EN>, + <&topckgen CLK_TOP_SGM_REG>, + <&sgmiisys0 CLK_SGM0_TX_EN>, + <&sgmiisys0 CLK_SGM0_RX_EN>, + <&sgmiisys0 CLK_SGM0_CK0_EN>, + <&sgmiisys0 CLK_SGM0_CDR_CK0_EN>, + <&sgmiisys1 CLK_SGM1_TX_EN>, + <&sgmiisys1 CLK_SGM1_RX_EN>, + <&sgmiisys1 CLK_SGM1_CK1_EN>, + <&sgmiisys1 CLK_SGM1_CDR_CK1_EN>, + <&topckgen CLK_TOP_NETSYS_SEL>, + <&topckgen CLK_TOP_NETSYS_500M_SEL>; + clock-names = "fe", "gp2", "gp1", "wocpu0", + "sgmii_ck", + "sgmii_tx250m", "sgmii_rx250m", + "sgmii_cdr_ref", "sgmii_cdr_fb", + "sgmii2_tx250m", "sgmii2_rx250m", + "sgmii2_cdr_ref", "sgmii2_cdr_fb", + "netsys0", "netsys1"; + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "fe0", "fe1", "fe2", "fe3", "pdma0", + "pdma1", "pdma2", "pdma3"; + sram = <ð_sram>; + mediatek,ethsys = <ðsys>; + mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; + mediatek,infracfg = <&topmisc>; + mediatek,wed = <&wed>; + status = "disabled"; + + mdio_bus: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + int_gbe_phy: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + phy-mode = "gmii"; + phy-is-integrated; + nvmem-cells = <&phy_calibration>; + nvmem-cell-names = "phy-cal-data"; + }; + }; + }; + + eth_sram: sram@15140000 { + compatible = "mmio-sram"; + reg = <0 0x15140000 0 0x40000>; + ranges = <0 0x15140000 0 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + wo_ccif0: syscon@151a5000 { + compatible = "mediatek,mt7986-wo-ccif", "syscon"; + reg = <0 0x151a5000 0 0x1000>; + interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; + }; + + wifi: wifi@18000000 { compatible = "mediatek,mt7981-wmac"; reg = <0 0x18000000 0 0x1000000>, <0 0x10003000 0 0x1000>, @@ -286,8 +500,10 @@ clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>, <&topckgen CLK_TOP_AP2CNN_HOST_SEL>; clock-names = "mcu", "ap2conn"; + memory-region = <&wmcpu_emi>; resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>; reset-names = "consys"; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi index 7790601586cc..9693f62fd013 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -231,7 +231,7 @@ }; crypto: crypto@10320000 { - compatible = "inside-secure,safexcel-eip97"; + compatible = "mediatek,mt7986-crypto", "inside-secure,safexcel-eip97ies"; reg = <0 0x10320000 0 0x40000>; interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index bec590d26659..8c9a5aba2579 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -629,20 +629,20 @@ tphy: t-phy@11c50000 { compatible = "mediatek,mt7986-tphy", "mediatek,generic-tphy-v2"; - #address-cells = <2>; - #size-cells = <2>; - ranges; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11c50000 0x1000>; status = "disabled"; - tphyu2port0: usb-phy@11c50000 { - reg = <0 0x11c50000 0 0x700>; + tphyu2port0: usb-phy@0 { + reg = <0 0x700>; clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>; clock-names = "ref"; #phy-cells = <1>; }; - tphyu3port0: usb-phy@11c50700 { - reg = <0 0x11c50700 0 0x900>; + tphyu3port0: usb-phy@700 { + reg = <0x700 0x900>; clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>; clock-names = "ref"; #phy-cells = <1>; @@ -659,20 +659,20 @@ xsphy: xs-phy@11e10000 { compatible = "mediatek,mt7988-xsphy", "mediatek,xsphy"; - #address-cells = <2>; - #size-cells = <2>; - ranges; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11e10000 0x3900>; status = "disabled"; - xphyu2port0: usb-phy@11e10000 { - reg = <0 0x11e10000 0 0x400>; + xphyu2port0: usb-phy@0 { + reg = <0 0x400>; clocks = <&infracfg CLK_INFRA_USB_UTMI>; clock-names = "ref"; #phy-cells = <1>; }; - xphyu3port0: usb-phy@11e13000 { - reg = <0 0x11e13400 0 0x500>; + xphyu3port0: usb-phy@3400 { + reg = <0x3400 0x500>; clocks = <&infracfg CLK_INFRA_USB_PIPE>; clock-names = "ref"; #phy-cells = <1>; diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi index dfc5c2f0ddef..1004eb8ea52c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi @@ -5,6 +5,14 @@ #include "mt8173-elm.dtsi" +&hdmi_mux_pins { + pins-mux { + pinmux = <MT8173_PIN_98_URTS1__FUNC_GPIO98>; + bias-pull-up; + output-high; + }; +}; + &i2c0 { clock-frequency = <200000>; }; @@ -67,26 +75,16 @@ }; }; -&mmc1 { - wp-gpios = <&pio 42 GPIO_ACTIVE_HIGH>; -}; - -&pio { - hdmi_mux_pins: hdmi_mux_pins { - pins2 { - pinmux = <MT8173_PIN_98_URTS1__FUNC_GPIO98>; - bias-pull-up; - output-high; - }; +&mmc1_pins_default { + pins-wp { + pinmux = <MT8173_PIN_42_DSI_TE__FUNC_GPIO42>; + input-enable; + bias-pull-up; }; +}; - mmc1_pins_default: mmc1default { - pins_wp { - pinmux = <MT8173_PIN_42_DSI_TE__FUNC_GPIO42>; - input-enable; - bias-pull-up; - }; - }; +&mmc1 { + wp-gpios = <&pio 42 GPIO_ACTIVE_HIGH>; }; &touchscreen { diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi index 0d995b342d46..a0573bc359fb 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi @@ -206,11 +206,9 @@ &dsi0 { status = "okay"; - ports { - port { - dsi0_out: endpoint { - remote-endpoint = <&ps8640_in>; - }; + port { + dsi0_out: endpoint { + remote-endpoint = <&ps8640_in>; }; }; }; @@ -432,20 +430,20 @@ #address-cells = <1>; #size-cells = <0>; - btmrvl: btmrvl@2 { + mwifiex: wifi@1 { + compatible = "marvell,sd8897"; + reg = <1>; + interrupts-extended = <&pio 38 IRQ_TYPE_LEVEL_LOW>; + marvell,wakeup-pin = <3>; + }; + + btmrvl: bluetooth@2 { compatible = "marvell,sd8897-bt"; reg = <2>; interrupts-extended = <&pio 119 IRQ_TYPE_LEVEL_LOW>; marvell,wakeup-pin = /bits/ 16 <0x0d>; marvell,wakeup-gap-ms = /bits/ 16 <0x64>; }; - - mwifiex: mwifiex@1 { - compatible = "marvell,sd8897"; - reg = <1>; - interrupts-extended = <&pio 38 IRQ_TYPE_LEVEL_LOW>; - marvell,wakeup-pin = <3>; - }; }; &nor_flash { @@ -601,8 +599,8 @@ "SOC_I2C4_1V8_SDA_400K", "SOC_I2C4_1V8_SCL_400K"; - aud_i2s2: aud_i2s2 { - pins1 { + aud_i2s2: aud-i2s2-pins { + pins-bus { pinmux = <MT8173_PIN_128_I2S0_LRCK__FUNC_I2S1_WS>, <MT8173_PIN_129_I2S0_BCK__FUNC_I2S1_BCK>, <MT8173_PIN_130_I2S0_MCK__FUNC_I2S1_MCK>, @@ -614,55 +612,55 @@ }; }; - bl_fixed_pins: bl_fixed_pins { - pins1 { + bl_fixed_pins: backlight-pins { + pins-blon { pinmux = <MT8173_PIN_32_UTXD2__FUNC_GPIO32>; output-low; }; }; - bt_wake_pins: bt_wake_pins { - pins1 { + bt_wake_pins: bt-pins { + pins-wake { pinmux = <MT8173_PIN_119_KPROW0__FUNC_GPIO119>; bias-pull-up; }; }; - disp_pwm0_pins: disp_pwm0_pins { + disp_pwm0_pins: disp-pwm0-pins { pins1 { pinmux = <MT8173_PIN_87_DISP_PWM0__FUNC_DISP_PWM0>; output-low; }; }; - gpio_keys_pins: gpio_keys_pins { - volume_pins { + gpio_keys_pins: gpio-keys-pins { + pins-volumeupdn { pinmux = <MT8173_PIN_123_KPCOL1__FUNC_GPIO123>, <MT8173_PIN_124_KPCOL2__FUNC_GPIO124>; bias-pull-up; }; - tablet_mode_pins { + pins-tabletmode { pinmux = <MT8173_PIN_121_KPROW2__FUNC_GPIO121>; bias-pull-up; }; }; - hdmi_mux_pins: hdmi_mux_pins { - pins1 { + hdmi_mux_pins: hdmi-pins { + pins-mux { pinmux = <MT8173_PIN_36_DAISYNC__FUNC_GPIO36>; }; }; - i2c1_pins_a: i2c1 { - da9211_pins { + i2c1_pins_a: i2c1-pins { + pins-da9211 { pinmux = <MT8173_PIN_15_EINT15__FUNC_GPIO15>; bias-pull-up; }; }; - mmc0_pins_default: mmc0default { - pins_cmd_dat { + mmc0_pins_default: mmc0-default-pins { + pins-cmd-dat { pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>, <MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1>, <MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2>, @@ -675,68 +673,68 @@ bias-pull-up; }; - pins_clk { + pins-clk { pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>; bias-pull-down; }; - pins_rst { + pins-rst { pinmux = <MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB>; bias-pull-up; }; }; - mmc1_pins_default: mmc1default { - pins_cmd_dat { + mmc1_pins_default: mmc1-default-pins { + pins-cmd-dat { pinmux = <MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0>, <MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1>, <MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2>, <MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3>, <MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD>; input-enable; - drive-strength = <MTK_DRIVE_4mA>; + drive-strength = <4>; bias-pull-up = <MTK_PUPD_SET_R1R0_10>; }; - pins_clk { + pins-clk { pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>; bias-pull-down; - drive-strength = <MTK_DRIVE_4mA>; + drive-strength = <4>; }; - pins_insert { + pins-insert { pinmux = <MT8173_PIN_1_EINT1__FUNC_GPIO1>; bias-pull-up; }; }; - mmc3_pins_default: mmc3default { - pins_dat { + mmc3_pins_default: mmc3-default-pins { + pins-dat { pinmux = <MT8173_PIN_22_MSDC3_DAT0__FUNC_MSDC3_DAT0>, <MT8173_PIN_23_MSDC3_DAT1__FUNC_MSDC3_DAT1>, <MT8173_PIN_24_MSDC3_DAT2__FUNC_MSDC3_DAT2>, <MT8173_PIN_25_MSDC3_DAT3__FUNC_MSDC3_DAT3>; input-enable; - drive-strength = <MTK_DRIVE_8mA>; + drive-strength = <8>; bias-pull-up = <MTK_PUPD_SET_R1R0_10>; }; - pins_cmd { + pins-cmd { pinmux = <MT8173_PIN_27_MSDC3_CMD__FUNC_MSDC3_CMD>; input-enable; - drive-strength = <MTK_DRIVE_8mA>; + drive-strength = <8>; bias-pull-up = <MTK_PUPD_SET_R1R0_10>; }; - pins_clk { + pins-clk { pinmux = <MT8173_PIN_26_MSDC3_CLK__FUNC_MSDC3_CLK>; bias-pull-down; - drive-strength = <MTK_DRIVE_8mA>; + drive-strength = <8>; }; }; - mmc0_pins_uhs: mmc0 { - pins_cmd_dat { + mmc0_pins_uhs: mmc0-uhs-pins { + pins-cmd-dat { pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>, <MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1>, <MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2>, @@ -747,109 +745,109 @@ <MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7>, <MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD>; input-enable; - drive-strength = <MTK_DRIVE_6mA>; + drive-strength = <6>; bias-pull-up = <MTK_PUPD_SET_R1R0_01>; }; - pins_clk { + pins-clk { pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>; - drive-strength = <MTK_DRIVE_6mA>; + drive-strength = <6>; bias-pull-down = <MTK_PUPD_SET_R1R0_01>; }; - pins_ds { + pins-ds { pinmux = <MT8173_PIN_67_MSDC0_DSL__FUNC_MSDC0_DSL>; drive-strength = <MTK_DRIVE_10mA>; bias-pull-down = <MTK_PUPD_SET_R1R0_01>; }; - pins_rst { + pins-rst { pinmux = <MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB>; bias-pull-up; }; }; - mmc1_pins_uhs: mmc1 { - pins_cmd_dat { + mmc1_pins_uhs: mmc1-pins { + pins-cmd-dat { pinmux = <MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0>, <MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1>, <MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2>, <MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3>, <MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD>; input-enable; - drive-strength = <MTK_DRIVE_6mA>; + drive-strength = <6>; bias-pull-up = <MTK_PUPD_SET_R1R0_10>; }; - pins_clk { + pins-clk { pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>; - drive-strength = <MTK_DRIVE_8mA>; + drive-strength = <8>; bias-pull-down = <MTK_PUPD_SET_R1R0_10>; }; }; - mmc3_pins_uhs: mmc3 { - pins_dat { + mmc3_pins_uhs: mmc3-pins { + pins-dat { pinmux = <MT8173_PIN_22_MSDC3_DAT0__FUNC_MSDC3_DAT0>, <MT8173_PIN_23_MSDC3_DAT1__FUNC_MSDC3_DAT1>, <MT8173_PIN_24_MSDC3_DAT2__FUNC_MSDC3_DAT2>, <MT8173_PIN_25_MSDC3_DAT3__FUNC_MSDC3_DAT3>; input-enable; - drive-strength = <MTK_DRIVE_8mA>; + drive-strength = <8>; bias-pull-up = <MTK_PUPD_SET_R1R0_10>; }; - pins_cmd { + pins-cmd { pinmux = <MT8173_PIN_27_MSDC3_CMD__FUNC_MSDC3_CMD>; input-enable; - drive-strength = <MTK_DRIVE_8mA>; + drive-strength = <8>; bias-pull-up = <MTK_PUPD_SET_R1R0_10>; }; - pins_clk { + pins-clk { pinmux = <MT8173_PIN_26_MSDC3_CLK__FUNC_MSDC3_CLK>; - drive-strength = <MTK_DRIVE_8mA>; + drive-strength = <8>; bias-pull-down = <MTK_PUPD_SET_R1R0_10>; }; }; - nor_gpio1_pins: nor { + nor_gpio1_pins: nor-pins { pins1 { pinmux = <MT8173_PIN_6_EINT6__FUNC_SFCS0>, <MT8173_PIN_7_EINT7__FUNC_SFHOLD>, <MT8173_PIN_8_EINT8__FUNC_SFIN>; input-enable; - drive-strength = <MTK_DRIVE_4mA>; + drive-strength = <4>; bias-pull-up; }; pins2 { pinmux = <MT8173_PIN_5_EINT5__FUNC_SFOUT>; - drive-strength = <MTK_DRIVE_4mA>; + drive-strength = <4>; bias-pull-up; }; - pins_clk { + pins-clk { pinmux = <MT8173_PIN_9_EINT9__FUNC_SFCK>; input-enable; - drive-strength = <MTK_DRIVE_4mA>; + drive-strength = <4>; bias-pull-up; }; }; - panel_backlight_en_pins: panel_backlight_en_pins { + panel_backlight_en_pins: panel-backlight-en-pins { pins1 { pinmux = <MT8173_PIN_95_PCM_TX__FUNC_GPIO95>; }; }; - panel_fixed_pins: panel_fixed_pins { + panel_fixed_pins: panel-fixed-pins { pins1 { pinmux = <MT8173_PIN_41_CMMCLK__FUNC_GPIO41>; }; }; - ps8640_pins: ps8640_pins { + ps8640_pins: ps8640-pins { pins1 { pinmux = <MT8173_PIN_92_PCM_CLK__FUNC_GPIO92>, <MT8173_PIN_115_URTS0__FUNC_GPIO115>, @@ -857,33 +855,33 @@ }; }; - ps8640_fixed_pins: ps8640_fixed_pins { + ps8640_fixed_pins: ps8640-fixed-pins { pins1 { pinmux = <MT8173_PIN_30_URTS2__FUNC_GPIO30>; }; }; - rt5650_irq: rt5650_irq { - pins1 { + rt5650_irq: rt5650-pins { + pins-intn { pinmux = <MT8173_PIN_3_EINT3__FUNC_GPIO3>; bias-pull-down; }; }; - sdio_fixed_3v3_pins: sdio_fixed_3v3_pins { + sdio_fixed_3v3_pins: sdio-vreg-3v3-pins { pins1 { pinmux = <MT8173_PIN_85_AUD_DAT_MOSI__FUNC_GPIO85>; output-low; }; }; - spi_pins_a: spi1 { + spi_pins_a: spi1-pins { pins1 { pinmux = <MT8173_PIN_0_EINT0__FUNC_GPIO0>; bias-pull-up; }; - pins_spi { + pins-spi { pinmux = <MT8173_PIN_102_MSDC2_DAT2__FUNC_SPI_CK_1_>, <MT8173_PIN_103_MSDC2_DAT3__FUNC_SPI_MI_1_>, <MT8173_PIN_104_MSDC2_CLK__FUNC_SPI_MO_1_>, @@ -892,15 +890,15 @@ }; }; - trackpad_irq: trackpad_irq { - pins1 { + trackpad_irq: trackpad-pins { + pins-intn { pinmux = <MT8173_PIN_117_URXD3__FUNC_GPIO117>; input-enable; bias-pull-up; }; }; - usb_pins: usb { + usb_pins: usb-pins { pins1 { pinmux = <MT8173_PIN_101_MSDC2_DAT1__FUNC_GPIO101>; output-high; @@ -908,8 +906,8 @@ }; }; - wifi_wake_pins: wifi_wake_pins { - pins1 { + wifi_wake_pins: wifi-pins { + pins-wake { pinmux = <MT8173_PIN_38_CONN_RST__FUNC_GPIO38>; bias-pull-up; }; @@ -1149,11 +1147,6 @@ status = "okay"; }; -&thermal { - bank0-supply = <&mt6397_vpca15_reg>; - bank1-supply = <&da9211_vcpu_reg>; -}; - &uart0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts index 9fffed0ef4bf..1049877e6cda 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts @@ -117,6 +117,7 @@ buck: da9211@68 { compatible = "dlg,da9211"; reg = <0x68>; + interrupts-extended = <&pio 15 IRQ_TYPE_LEVEL_LOW>; regulators { da9211_vcpu_reg: BUCKA { @@ -172,15 +173,22 @@ }; &pio { - disp_pwm0_pins: disp_pwm0_pins { + disp_pwm0_pins: disp-pwm0-pins { pins1 { pinmux = <MT8173_PIN_87_DISP_PWM0__FUNC_DISP_PWM0>; output-low; }; }; - mmc0_pins_default: mmc0default { - pins_cmd_dat { + i2c1_pins_a: i2c1-pins { + pins-da9211 { + pinmux = <MT8173_PIN_15_EINT15__FUNC_GPIO15>; + bias-pull-up; + }; + }; + + mmc0_pins_default: mmc0-default-pins { + pins-cmd-dat { pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>, <MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1>, <MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2>, @@ -194,19 +202,19 @@ bias-pull-up; }; - pins_clk { + pins-clk { pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>; bias-pull-down; }; - pins_rst { + pins-rst { pinmux = <MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB>; bias-pull-up; }; }; - mmc1_pins_default: mmc1default { - pins_cmd_dat { + mmc1_pins_default: mmc1-default-pins { + pins-cmd-dat { pinmux = <MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0>, <MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1>, <MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2>, @@ -217,20 +225,20 @@ bias-pull-up = <MTK_PUPD_SET_R1R0_10>; }; - pins_clk { + pins-clk { pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>; bias-pull-down; drive-strength = <4>; }; - pins_insert { + pins-insert { pinmux = <MT8173_PIN_132_I2S0_DATA1__FUNC_GPIO132>; bias-pull-up; }; }; - mmc0_pins_uhs: mmc0 { - pins_cmd_dat { + mmc0_pins_uhs: mmc0-uhs-pins { + pins-cmd-dat { pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>, <MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1>, <MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2>, @@ -245,20 +253,29 @@ bias-pull-up = <MTK_PUPD_SET_R1R0_01>; }; - pins_clk { + pins-clk { pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>; drive-strength = <2>; bias-pull-down = <MTK_PUPD_SET_R1R0_01>; }; - pins_rst { + pins-rst { pinmux = <MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB>; bias-pull-up; }; }; - mmc1_pins_uhs: mmc1 { - pins_cmd_dat { + spi_pins_a: spi0-pins { + pins-bus { + pinmux = <MT8173_PIN_69_SPI_CK__FUNC_SPI_CK_0_>, + <MT8173_PIN_70_SPI_MI__FUNC_SPI_MI_0_>, + <MT8173_PIN_71_SPI_MO__FUNC_SPI_MO_0_>, + <MT8173_PIN_72_SPI_CS__FUNC_SPI_CS_0_>; + }; + }; + + mmc1_pins_uhs: mmc1-uhs-pins { + pins-cmd-dat { pinmux = <MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0>, <MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1>, <MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2>, @@ -269,22 +286,22 @@ bias-pull-up = <MTK_PUPD_SET_R1R0_10>; }; - pins_clk { + pins-clk { pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>; drive-strength = <4>; bias-pull-down = <MTK_PUPD_SET_R1R0_10>; }; }; - usb_id_pins_float: usb_iddig_pull_up { - pins_iddig { + usb_id_pins_float: usb-iddig-pu-pins { + pins-iddig-pu { pinmux = <MT8173_PIN_16_IDDIG__FUNC_IDDIG>; bias-pull-up; }; }; - usb_id_pins_ground: usb_iddig_pull_down { - pins_iddig { + usb_id_pins_ground: usb-iddig-pd-pins { + pins-iddig-pd { pinmux = <MT8173_PIN_16_IDDIG__FUNC_IDDIG>; bias-pull-down; }; @@ -473,17 +490,6 @@ }; }; -&pio { - spi_pins_a: spi0 { - pins_spi { - pinmux = <MT8173_PIN_69_SPI_CK__FUNC_SPI_CK_0_>, - <MT8173_PIN_70_SPI_MI__FUNC_SPI_MI_0_>, - <MT8173_PIN_71_SPI_MO__FUNC_SPI_MO_0_>, - <MT8173_PIN_72_SPI_CS__FUNC_SPI_CS_0_>; - }; - }; -}; - &spi { pinctrl-names = "default"; pinctrl-0 = <&spi_pins_a>; diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 122a57c3780b..78c2ccd5be13 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -391,58 +391,58 @@ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; - hdmi_pin: xxx { + hdmi_pin: hdmi-hotplug-pins { /*hdmi htplg pin*/ - pins1 { + pins-htplg { pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>; input-enable; bias-pull-down; }; }; - i2c0_pins_a: i2c0 { - pins1 { + i2c0_pins_a: i2c0-pins { + pins-bus { pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>, <MT8173_PIN_46_SCL0__FUNC_SCL0>; bias-disable; }; }; - i2c1_pins_a: i2c1 { - pins1 { + i2c1_pins_a: i2c1-pins { + pins-bus { pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>, <MT8173_PIN_126_SCL1__FUNC_SCL1>; bias-disable; }; }; - i2c2_pins_a: i2c2 { - pins1 { + i2c2_pins_a: i2c2-pins { + pins-bus { pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>, <MT8173_PIN_44_SCL2__FUNC_SCL2>; bias-disable; }; }; - i2c3_pins_a: i2c3 { - pins1 { + i2c3_pins_a: i2c3-pins { + pins-bus { pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>, <MT8173_PIN_107_SCL3__FUNC_SCL3>; bias-disable; }; }; - i2c4_pins_a: i2c4 { - pins1 { + i2c4_pins_a: i2c4-pins { + pins-bus { pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>, <MT8173_PIN_134_SCL4__FUNC_SCL4>; bias-disable; }; }; - i2c6_pins_a: i2c6 { - pins1 { + i2c6_pins_a: i2c6-pins { + pins-bus { pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>, <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>; bias-disable; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts index f04baea5d6cb..acfdd5fb041f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts @@ -38,7 +38,7 @@ }; }; - thermal-sensor { + thermistor { compatible = "murata,ncp03wf104"; pullup-uv = <1800000>; pullup-ohm = <390000>; @@ -155,7 +155,7 @@ }; &pio { - i2c_pins_0: i2c0 { + i2c_pins_0: i2c0-pins { pins_i2c { pinmux = <PINMUX_GPIO82__FUNC_SDA0>, <PINMUX_GPIO83__FUNC_SCL0>; @@ -163,7 +163,7 @@ }; }; - i2c_pins_1: i2c1 { + i2c_pins_1: i2c1-pins { pins_i2c { pinmux = <PINMUX_GPIO81__FUNC_SDA1>, <PINMUX_GPIO84__FUNC_SCL1>; @@ -171,7 +171,7 @@ }; }; - i2c_pins_2: i2c2 { + i2c_pins_2: i2c2-pins { pins_i2c { pinmux = <PINMUX_GPIO103__FUNC_SCL2>, <PINMUX_GPIO104__FUNC_SDA2>; @@ -179,7 +179,7 @@ }; }; - i2c_pins_3: i2c3 { + i2c_pins_3: i2c3-pins { pins_i2c { pinmux = <PINMUX_GPIO50__FUNC_SCL3>, <PINMUX_GPIO51__FUNC_SDA3>; @@ -187,7 +187,7 @@ }; }; - i2c_pins_4: i2c4 { + i2c_pins_4: i2c4-pins { pins_i2c { pinmux = <PINMUX_GPIO105__FUNC_SCL4>, <PINMUX_GPIO106__FUNC_SDA4>; @@ -195,7 +195,7 @@ }; }; - i2c_pins_5: i2c5 { + i2c_pins_5: i2c5-pins { pins_i2c { pinmux = <PINMUX_GPIO48__FUNC_SCL5>, <PINMUX_GPIO49__FUNC_SDA5>; @@ -203,7 +203,7 @@ }; }; - spi_pins_0: spi0 { + spi_pins_0: spi0-pins { pins_spi { pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>, <PINMUX_GPIO86__FUNC_SPI0_CSB>, @@ -213,7 +213,7 @@ }; }; - mmc0_pins_default: mmc0default { + mmc0_pins_default: mmc0-default-pins { pins_cmd_dat { pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, @@ -239,7 +239,7 @@ }; }; - mmc0_pins_uhs: mmc0 { + mmc0_pins_uhs: mmc0-uhs-pins { pins_cmd_dat { pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, @@ -274,7 +274,7 @@ }; }; - mmc1_pins_default: mmc1default { + mmc1_pins_default: mmc1-default-pins { pins_cmd_dat { pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, @@ -298,7 +298,7 @@ }; }; - mmc1_pins_uhs: mmc1 { + mmc1_pins_uhs: mmc1-pins { pins_cmd_dat { pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, @@ -318,7 +318,7 @@ }; }; - spi_pins_1: spi1 { + spi_pins_1: spi1-pins { pins_spi { pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>, <PINMUX_GPIO162__FUNC_SPI1_A_CSB>, @@ -328,7 +328,7 @@ }; }; - spi_pins_2: spi2 { + spi_pins_2: spi2-pins { pins_spi { pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>, <PINMUX_GPIO1__FUNC_SPI2_MO>, @@ -338,7 +338,7 @@ }; }; - spi_pins_3: spi3 { + spi_pins_3: spi3-pins { pins_spi { pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>, <PINMUX_GPIO22__FUNC_SPI3_CSB>, @@ -348,7 +348,7 @@ }; }; - spi_pins_4: spi4 { + spi_pins_4: spi4-pins { pins_spi { pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>, <PINMUX_GPIO18__FUNC_SPI4_CSB>, @@ -358,7 +358,7 @@ }; }; - spi_pins_5: spi5 { + spi_pins_5: spi5-pins { pins_spi { pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>, <PINMUX_GPIO14__FUNC_SPI5_CSB>, @@ -368,7 +368,7 @@ }; }; - pwm_pins_1: pwm1 { + pwm_pins_1: pwm1-pins { pins_pwm { pinmux = <PINMUX_GPIO90__FUNC_PWM_A>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico6.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico6.dts index cce326aec1aa..40af5656d6f1 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico6.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico6.dts @@ -91,7 +91,7 @@ &pio { bt_pins_wakeup: bt-pins-wakeup { - piins-bt-wakeup { + pins-bt-wakeup { pinmux = <PINMUX_GPIO42__FUNC_GPIO42>; input-enable; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index 4b87d4940c8c..a8e257b21a88 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -44,10 +44,10 @@ clock-output-names = "clk32k"; }; - it6505_pp18_reg: regulator0 { + pp1800_it6505: regulator0 { compatible = "regulator-fixed"; - regulator-name = "it6505_pp18"; - gpio = <&pio 178 0>; + regulator-name = "pp1800_it6505"; + gpios = <&pio 178 GPIO_ACTIVE_HIGH>; enable-active-high; vin-supply = <&pp1800_alw>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts index f60ef3e53a09..e47955602c83 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts @@ -241,7 +241,7 @@ }; &pio { - i2c_pins_0: i2c0 { + i2c_pins_0: i2c0-pins { pins_i2c { pinmux = <PINMUX_GPIO82__FUNC_SDA0>, <PINMUX_GPIO83__FUNC_SCL0>; @@ -249,7 +249,7 @@ }; }; - i2c_pins_1: i2c1 { + i2c_pins_1: i2c1-pins { pins_i2c { pinmux = <PINMUX_GPIO81__FUNC_SDA1>, <PINMUX_GPIO84__FUNC_SCL1>; @@ -257,7 +257,7 @@ }; }; - i2c_pins_2: i2c2 { + i2c_pins_2: i2c2-pins { pins_i2c { pinmux = <PINMUX_GPIO103__FUNC_SCL2>, <PINMUX_GPIO104__FUNC_SDA2>; @@ -265,7 +265,7 @@ }; }; - i2c_pins_3: i2c3 { + i2c_pins_3: i2c3-pins { pins_i2c { pinmux = <PINMUX_GPIO50__FUNC_SCL3>, <PINMUX_GPIO51__FUNC_SDA3>; @@ -273,7 +273,7 @@ }; }; - i2c_pins_4: i2c4 { + i2c_pins_4: i2c4-pins { pins_i2c { pinmux = <PINMUX_GPIO105__FUNC_SCL4>, <PINMUX_GPIO106__FUNC_SDA4>; @@ -281,7 +281,7 @@ }; }; - i2c_pins_5: i2c5 { + i2c_pins_5: i2c5-pins { pins_i2c { pinmux = <PINMUX_GPIO48__FUNC_SCL5>, <PINMUX_GPIO49__FUNC_SDA5>; @@ -289,7 +289,7 @@ }; }; - i2c6_pins: i2c6 { + i2c6_pins: i2c6-pins { pins_cmd_dat { pinmux = <PINMUX_GPIO113__FUNC_SCL6>, <PINMUX_GPIO114__FUNC_SDA6>; @@ -297,7 +297,7 @@ }; }; - keyboard_pins: keyboard { + keyboard_pins: keyboard-pins { pins_keyboard { pinmux = <PINMUX_GPIO91__FUNC_KPROW1>, <PINMUX_GPIO92__FUNC_KPROW0>, diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 4e20a8f2eb25..95cc06799533 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1812,15 +1812,23 @@ #size-cells = <0>; port@0 { + #address-cells = <1>; + #size-cells = <0>; reg = <0>; - ovl_2l1_in: endpoint { + + ovl_2l1_in: endpoint@1 { + reg = <1>; remote-endpoint = <&mmsys_ep_ext>; }; }; port@1 { + #address-cells = <1>; + #size-cells = <0>; reg = <1>; - ovl_2l1_out: endpoint { + + ovl_2l1_out: endpoint@1 { + reg = <1>; remote-endpoint = <&rdma1_in>; }; }; @@ -1872,15 +1880,23 @@ #size-cells = <0>; port@0 { + #address-cells = <1>; + #size-cells = <0>; reg = <0>; - rdma1_in: endpoint { + + rdma1_in: endpoint@1 { + reg = <1>; remote-endpoint = <&ovl_2l1_out>; }; }; port@1 { + #address-cells = <1>; + #size-cells = <0>; reg = <1>; - rdma1_out: endpoint { + + rdma1_out: endpoint@1 { + reg = <1>; remote-endpoint = <&dpi_in>; }; }; @@ -2076,15 +2092,24 @@ #size-cells = <0>; port@0 { + #address-cells = <1>; + #size-cells = <0>; reg = <0>; - dpi_in: endpoint { + + dpi_in: endpoint@1 { + reg = <1>; remote-endpoint = <&rdma1_out>; }; }; port@1 { + #address-cells = <1>; + #size-cells = <0>; reg = <1>; - dpi_out: endpoint { }; + + dpi_out: endpoint@1 { + reg = <1>; + }; }; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts index 2667a7424200..a941a931a07c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts @@ -22,6 +22,19 @@ device_type = "memory"; reg = <0 0x40000000 0 0x80000000>; }; + + vproc: regulator-vproc12 { + compatible = "regulator-fixed"; + regulator-name = "vproc12"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; +}; + +&cci { + proc-supply = <&vproc>; }; &i2c0 { diff --git a/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi b/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi index 7fedbacdac44..8e423504ec05 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi @@ -1166,7 +1166,6 @@ &scp_c0 { pinctrl-names = "default"; pinctrl-0 = <&scp_pins>; - firmware-name = "mediatek/mt8188/scp.img"; memory-region = <&scp_mem_reserved>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi index 90c388f1890f..75133794cec3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -26,6 +26,7 @@ aliases { dp-intf0 = &dp_intf0; dp-intf1 = &dp_intf1; + dpi1 = &dpi1; dsc0 = &dsc0; ethdr0 = ðdr0; gce0 = &gce0; @@ -1800,7 +1801,7 @@ compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc"; reg = <0 0x11230000 0 0x10000>, <0 0x11f50000 0 0x1000>; - interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>; + interrupts-extended = <&gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&topckgen CLK_TOP_MSDC50_0>, <&infracfg_ao CLK_INFRA_AO_MSDC0>, <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>, @@ -1813,7 +1814,7 @@ compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc"; reg = <0 0x11240000 0 0x1000>, <0 0x11eb0000 0 0x1000>; - interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>; + interrupts-extended = <&gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&topckgen CLK_TOP_MSDC30_1>, <&infracfg_ao CLK_INFRA_AO_MSDC1>, <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; @@ -1827,7 +1828,7 @@ compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc"; reg = <0 0x11250000 0 0x1000>, <0 0x11e60000 0 0x1000>; - interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>; + interrupts-extended = <&gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&topckgen CLK_TOP_MSDC30_2>, <&infracfg_ao CLK_INFRA_AO_MSDC2>, <&infracfg_ao CLK_INFRA_AO_MSDC30_2>; @@ -2038,6 +2039,19 @@ }; }; + hdmi_phy: hdmi-phy@11d5f000 { + compatible = "mediatek,mt8188-hdmi-phy", "mediatek,mt8195-hdmi-phy"; + reg = <0 0x11d5f000 0 0x100>; + clocks = <&infracfg_ao CLK_INFRA_AO_HDMI_26M>; + clock-names = "pll_ref"; + clock-output-names = "hdmi_txpll"; + #clock-cells = <0>; + #phy-cells = <0>; + mediatek,ibias = <0xa>; + mediatek,ibias_up = <0x1c>; + status = "disabled"; + }; + mipi_tx_config0: dsi-phy@11c80000 { compatible = "mediatek,mt8188-mipi-tx", "mediatek,mt8183-mipi-tx"; reg = <0 0x11c80000 0 0x1000>; @@ -3406,6 +3420,34 @@ mediatek,merge-fifo-en; }; + dpi1: dpi@1c112000 { + compatible = "mediatek,mt8188-dpi", "mediatek,mt8195-dpi"; + reg = <0 0x1c112000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_DPI1>, + <&vdosys1 CLK_VDO1_DPI1_MM>, + <&vdosys1 CLK_VDO1_DPI1_HDMI>; + clock-names = "pixel", "engine", "pll"; + interrupts = <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + resets = <&vdosys1 MT8188_VDO1_RST_DPI1_MM_CK>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpi1_in: endpoint { }; + }; + + port@1 { + reg = <1>; + dpi1_out: endpoint { }; + }; + }; + }; + dp_intf1: dp-intf@1c113000 { compatible = "mediatek,mt8188-dp-intf"; reg = <0 0x1c113000 0 0x1000>; @@ -3530,6 +3572,46 @@ mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x4000 0x1000>; }; + hdmi: hdmi@1c300000 { + compatible = "mediatek,mt8188-hdmi-tx"; + #sound-dai-cells = <1>; + reg = <0 0x1c300000 0 0x1000>; + clocks = <&topckgen CLK_TOP_HDMI_APB>, + <&topckgen CLK_TOP_HDCP>, + <&topckgen CLK_TOP_HDCP_24M>, + <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>; + clock-names = "bus", "hdcp", "hdcp24m", "hdmi-split"; + assigned-clocks = <&topckgen CLK_TOP_HDCP>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4_D8>; + interrupts = <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8188_POWER_DOMAIN_HDMI_TX>; + phys = <&hdmi_phy>; + phy-names = "hdmi"; + status = "disabled"; + + hdmi_ddc: i2c { + compatible = "mediatek,mt8188-hdmi-ddc", + "mediatek,mt8195-hdmi-ddc"; + clocks = <&clk26m>; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + hdmi0_in: endpoint { }; + }; + + port@1 { + reg = <1>; + hdmi0_out: endpoint { }; + }; + }; + }; + + edp_tx: edp-tx@1c500000 { compatible = "mediatek,mt8188-edp-tx"; reg = <0 0x1c500000 0 0x8000>; diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index 0b4664f044a1..eadf1b2d156f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -344,7 +344,6 @@ status = "okay"; clock-frequency = <400000>; - clock-stretch-ns = <12600>; pinctrl-names = "default"; pinctrl-0 = <&i2c2_pins>; diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 47dea10dd3b8..9f8f115edd4c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -973,7 +973,7 @@ reg = <0 0x11210000 0 0x2000>; #clock-cells = <1>; - afe: mt8192-afe-pcm { + afe: audio-controller { compatible = "mediatek,mt8192-audio"; interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>; resets = <&watchdog 17>; diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index c7adafaa8328..c72e34c57629 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -26,8 +26,10 @@ aliases { dp-intf0 = &dp_intf0; dp-intf1 = &dp_intf1; + dpi1 = &dpi1; gce0 = &gce0; gce1 = &gce1; + hdmi0 = &hdmi; ethdr0 = ðdr0; mutex0 = &mutex; mutex1 = &mutex1; @@ -1857,6 +1859,23 @@ #clock-cells = <1>; }; + hdmi_phy: hdmi-phy@11d5f000 { + compatible = "mediatek,mt8195-hdmi-phy"; + reg = <0 0x11d5f000 0 0x100>; + clocks = <&topckgen CLK_TOP_HDMI_XTAL>, + <&infracfg_ao CLK_INFRA_AO_HDMI_26M>, + <&apmixedsys CLK_APMIXED_HDMIPLL1>, + <&apmixedsys CLK_APMIXED_HDMIPLL2>; + clock-names = "pll_ref", "26m", "pll1", "pll2"; + clock-output-names = "hdmi_txpll"; + + #clock-cells = <0>; + #phy-cells = <0>; + mediatek,ibias = <0xa>; + mediatek,ibias_up = <0x1c>; + status = "disabled"; + }; + i2c0: i2c@11e00000 { compatible = "mediatek,mt8195-i2c", "mediatek,mt8192-i2c"; @@ -3670,6 +3689,34 @@ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>; }; + dpi1: dpi@1c112000 { + compatible = "mediatek,mt8195-dpi"; + reg = <0 0x1c112000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_DPI1>, + <&vdosys1 CLK_VDO1_DPI1_MM>, + <&vdosys1 CLK_VDO1_DPI1_HDMI>; + clock-names = "pixel", "engine", "pll"; + interrupts = <GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_DPI1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpi1_in: endpoint { }; + }; + + port@1 { + reg = <1>; + dpi1_out: endpoint { }; + }; + }; + }; + dp_intf1: dp-intf@1c113000 { compatible = "mediatek,mt8195-dp-intf"; reg = <0 0x1c113000 0 0x1000>; @@ -3730,6 +3777,44 @@ "gfx_fe1_async", "vdo_be_async"; }; + hdmi: hdmi-tx@1c300000 { + compatible = "mediatek,mt8195-hdmi-tx"; + #sound-dai-cells = <1>; + reg = <0 0x1c300000 0 0x1000>; + clocks = <&topckgen CLK_TOP_HDMI_APB>, + <&topckgen CLK_TOP_HDCP>, + <&topckgen CLK_TOP_HDCP_24M>, + <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>; + clock-names = "bus", "hdcp", "hdcp24m", "hdmi-split"; + assigned-clocks = <&topckgen CLK_TOP_HDCP>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4_D8>; + interrupts = <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8195_POWER_DOMAIN_HDMI_TX>; + phys = <&hdmi_phy>; + phy-names = "hdmi"; + status = "disabled"; + + hdmitx_ddc: i2c { + compatible = "mediatek,mt8195-hdmi-ddc"; + clocks = <&clk26m>; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + hdmi0_in: endpoint { }; + }; + + port@1 { + reg = <1>; + hdmi0_out: endpoint { }; + }; + }; + }; + edp_tx: edp-tx@1c500000 { compatible = "mediatek,mt8195-edp-tx"; reg = <0 0x1c500000 0 0x8000>; diff --git a/arch/arm64/boot/dts/mediatek/mt8370-tungsten-smarc.dts b/arch/arm64/boot/dts/mediatek/mt8370-tungsten-smarc.dts new file mode 100644 index 000000000000..4c3a7c4579c8 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8370-tungsten-smarc.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 Ezurio LLC + * Author: Gary Bisson <bisson.gary@gmail.com> + */ +/dts-v1/; +#include "mt8370.dtsi" +#include "mt8390-tungsten-smarc.dtsi" + +/ { + model = "Ezurio Tungsten510 SMARC (MT8370)"; + compatible = "ezurio,mt8370-tungsten-smarc", "mediatek,mt8370", + "mediatek,mt8188"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi index a2cdecd2b903..2062506f6cc5 100644 --- a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi @@ -55,6 +55,20 @@ wakeup-delay-ms = <30>; }; + connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + ddc-i2c-bus = <&hdmi_ddc>; + hdmi-pwr-supply = <&hdmi_phy>; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi0_out>; + }; + }; + }; + firmware { optee { compatible = "linaro,optee-tz"; @@ -328,6 +342,18 @@ remote-endpoint = <&dsi0_in>; }; +&dpi1 { + status = "okay"; +}; + +&dpi1_in { + remote-endpoint = <&merge5_out>; +}; + +&dpi1_out { + remote-endpoint = <&hdmi0_in>; +}; + &gamma0_out { remote-endpoint = <&postmask0_in>; }; @@ -337,6 +363,55 @@ status = "okay"; }; +ðdr0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + ethdr0_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&vdosys1_ep_ext>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + ethdr0_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&merge5_in>; + }; + }; + }; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pins>; + status = "okay"; +}; + +&hdmi0_in { + remote-endpoint = <&dpi1_out>; +}; + +&hdmi0_out { + remote-endpoint = <&hdmi_connector_in>; +}; + +&hdmi_phy { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_vreg_pins>; + status = "okay"; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; @@ -475,6 +550,35 @@ status = "okay"; }; +&merge5 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + merge5_in: endpoint@1 { + reg = <1>; + remote-endpoint = <ðdr0_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + merge5_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&dpi1_in>; + }; + }; + }; +}; + &mfg0 { domain-supply = <&mt6359_vproc2_buck_reg>; }; @@ -727,6 +831,31 @@ }; }; + hdmi_vreg_pins: hdmi-vreg-pins { + pins-pwr { + pinmux = <PINMUX_GPIO50__FUNC_O_HDMITX20_PWR5V>; + bias-disable; + }; + }; + + hdmi_pins: hdmi-pins { + pins-hotplug { + pinmux = <PINMUX_GPIO51__FUNC_I0_HDMITX20_HTPLG>; + bias-pull-down; + }; + + pins-cec { + pinmux = <PINMUX_GPIO52__FUNC_B1_HDMITX20_CEC>; + bias-disable; + }; + + pins-ddc { + pinmux = <PINMUX_GPIO53__FUNC_B1_HDMITX20_SCL>, + <PINMUX_GPIO54__FUNC_B1_HDMITX20_SDA>; + drive-strength = <10>; + }; + }; + i2c0_pins: i2c0-pins { pins { pinmux = <PINMUX_GPIO56__FUNC_B1_SDA0>, @@ -1215,6 +1344,15 @@ sound-dai = <&dmic_codec>; }; }; + + dai-link-2 { + link-name = "ETDM3_OUT_BE"; + + codec { + sound-dai = <&hdmi 0>; + }; + }; + }; &spi2 { @@ -1286,6 +1424,18 @@ }; }; +&vdosys1 { + port { + #address-cells = <1>; + #size-cells = <0>; + + vdosys1_ep_ext: endpoint@1 { + reg = <1>; + remote-endpoint = <ðdr0_in>; + }; + }; +}; + &xhci0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dts b/arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dts new file mode 100644 index 000000000000..7580f9e2f20d --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 Ezurio LLC + * Author: Gary Bisson <bisson.gary@gmail.com> + */ +/dts-v1/; +#include "mt8188.dtsi" +#include "mt8390-tungsten-smarc.dtsi" + +/ { + model = "Ezurio Tungsten700 SMARC (MT8390)"; + compatible = "ezurio,mt8390-tungsten-smarc", "mediatek,mt8390", + "mediatek,mt8188"; +}; + +&cpu4 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu5 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dtsi b/arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dtsi new file mode 100644 index 000000000000..40b381d4cc35 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dtsi @@ -0,0 +1,1489 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 Ezurio LLC + * Author: Gary Bisson <bisson.gary@gmail.com> + */ + +#include "mt6359.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/net/microchip-lan78xx.h> +#include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h> +#include <dt-bindings/spmi/spmi.h> +#include <dt-bindings/usb/pd.h> + +/ { + aliases { + dsi0 = &disp_dsi0; + ethernet0 = ð + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + mmc0 = &mmc0; + mmc1 = &mmc1; + mmc2 = &mmc2; + rtc0 = &rv3028; + rtc1 = &mt6359rtc; + serial0 = &uart0; + }; + + backlight_lcd0: backlight-lcd0 { + compatible = "pwm-backlight"; + brightness-levels = <0 1023>; + default-brightness-level = <768>; + num-interpolated-steps = <1023>; + enable-gpios = <&pio 30 GPIO_ACTIVE_HIGH>; + pwms = <&disp_pwm0 0 30000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0x1 0x00000000>; + }; + + panel-dsi0 { + compatible = "tianma,tm070jdhg30"; + backlight = <&backlight_lcd0>; + power-supply = <®_5v>; + + port { + dsi0_panel_in: endpoint { + remote-endpoint = <&sn65dsi84_bridge_out>; + }; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * 12 MiB reserved for OP-TEE (BL32) + * +-----------------------+ 0x43e0_0000 + * | SHMEM 2MiB | + * +-----------------------+ 0x43c0_0000 + * | | TA_RAM 8MiB | + * + TZDRAM +--------------+ 0x4340_0000 + * | | TEE_RAM 2MiB | + * +-----------------------+ 0x4320_0000 + */ + optee_reserved: optee@43200000 { + no-map; + reg = <0 0x43200000 0 0x00c00000>; + }; + + scp_mem: memory@50000000 { + compatible = "shared-dma-pool"; + reg = <0 0x50000000 0 0x2900000>; + no-map; + }; + + /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ + bl31_secmon_reserved: memory@54600000 { + no-map; + reg = <0 0x54600000 0x0 0x200000>; + }; + + apu_mem: memory@55000000 { + compatible = "shared-dma-pool"; + reg = <0 0x55000000 0 0x1400000>; /* 20 MB */ + }; + + vpu_mem: memory@57000000 { + compatible = "shared-dma-pool"; + reg = <0 0x57000000 0 0x1400000>; /* 20 MB */ + }; + + adsp_mem: memory@60000000 { + compatible = "shared-dma-pool"; + reg = <0 0x60000000 0 0xf00000>; + no-map; + }; + + afe_dma_mem: memory@60f00000 { + compatible = "shared-dma-pool"; + reg = <0 0x60f00000 0 0x100000>; + no-map; + }; + + adsp_dma_mem: memory@61000000 { + compatible = "shared-dma-pool"; + reg = <0 0x61000000 0 0x100000>; + no-map; + }; + }; + + regulator-efuse { + compatible = "regulator-output"; + vout-supply = <&mt6359_vefuse_ldo_reg>; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "reg_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "reg_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "reg_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + sdcard_en_3v3: regulator-sdcard-en { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-name = "sdcard_en_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pio 111 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usb_p0_vbus: regulator-usb-p0-vbus { + compatible = "regulator-fixed"; + regulator-name = "vbus_p0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 84 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usb_p1_vbus: regulator-usb-p1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&usb1_hub_pins>; + regulator-name = "vbus_p1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&pio 147 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usb_p2_vbus: regulator-usb-p2-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&usb2_eth_pins>; + regulator-name = "vbus_p2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&pio 80 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_pwrseq_pins>; + post-power-on-delay-ms = <200>; + reset-gpios = <&pio 89 GPIO_ACTIVE_LOW>; + }; +}; + +&adsp { + memory-region = <&adsp_dma_mem>, <&adsp_mem>; + status = "okay"; +}; + +&afe { + memory-region = <&afe_dma_mem>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu1 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu2 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu3 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu6 { + cpu-supply = <&mt6315_6_vbuck1>; +}; + +&cpu7 { + cpu-supply = <&mt6315_6_vbuck1>; +}; + +&disp_pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&disp_pwm0_pins>; + status = "okay"; +}; + +&disp_dsi0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dither0_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + remote-endpoint = <&sn65dsi84_bridge_in>; + }; + }; + }; +}; + +&dither0_in { + remote-endpoint = <&postmask0_out>; +}; + +&dither0_out { + remote-endpoint = <&dsi0_in>; +}; + +ð { + phy-mode ="rgmii-id"; + phy-handle = <ðernet_phy0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <ð_default_pins>; + pinctrl-1 = <ð_sleep_pins>; + mediatek,mac-wol; + snps,reset-gpio = <&pio 27 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 11000 1000>; + status = "okay"; +}; + +ð_mdio { + ethernet_phy0: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x7>; + interrupts-extended = <&pio 148 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&gamma0_out { + remote-endpoint = <&postmask0_in>; +}; + +&gpu { + mali-supply = <&mt6359_vproc2_buck_reg>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <100000>; + status = "okay"; + + i2c-mux@73 { + compatible = "nxp,pca9546"; + reg = <0x73>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_mux_pins>; + reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>; + #address-cells = <1>; + #size-cells = <0>; + + i2c_mux_gp_0: i2c@0 { + reg = <0>; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c_mux_gp_1: i2c@1 { + reg = <1>; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c_mux_gp_2: i2c@2 { + reg = <2>; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c_mux_gp_3: i2c@3 { + reg = <3>; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + clock-frequency = <400000>; + status = "okay"; + + i2c-mux@73 { + compatible = "nxp,pca9546"; + reg = <0x73>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_mux_smarc_lcd_pins>; + reset-gpios = <&pio 5 GPIO_ACTIVE_LOW>; + #address-cells = <1>; + #size-cells = <0>; + + i2c_mux_lcd_0: i2c@0 { + reg = <0>; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c_mux_lcd_1: i2c@1 { + reg = <1>; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c_mux_lcd_2: i2c@2 { + reg = <2>; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c_mux_lcd_3: i2c@3 { + reg = <3>; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c_mux_gp_0 { + rv3028: rtc@52 { + compatible = "microcrystal,rv3028"; + reg = <0x52>; + interrupts-extended = <&pio 42 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&rv3028_pins>; + #clock-cells = <0>; + wakeup-source; + }; +}; + +&i2c_mux_gp_1 { + usb-typec@60 { + compatible = "ti,hd3ss3220"; + reg = <0x60>; + interrupts-extended = <&pio 45 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hd3ss3220_pins>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + hd3ss3220_in_ep: endpoint { + remote-endpoint = <&ss_ep>; + }; + }; + + port@1 { + reg = <1>; + hd3ss3220_out_ep: endpoint { + remote-endpoint = <&usb_role_switch>; + }; + }; + }; + }; +}; + +&i2c_mux_gp_2 { + codec@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&topckgen CLK_TOP_I2SO1>; + AVDD-supply = <®_1v8>; + CPVDD-supply = <®_1v8>; + DBVDD-supply = <®_3v3>; + DCVDD-supply = <®_1v8>; + MICVDD-supply = <®_3v3>; + PLLVDD-supply = <®_1v8>; + SPKVDD1-supply = <®_5v>; + SPKVDD2-supply = <®_5v>; + gpio-cfg = < + 0x0000 /* n/c */ + 0x0000 /* gpio2: */ + 0x0000 /* gpio3: */ + 0x0000 /* n/c */ + 0x8081 /* gpio5:HP detect */ + 0x8095 /* gpio6:Mic detect */ + >; + }; +}; + +&i2c_mux_lcd_2 { + bridge@2c { + compatible = "ti,sn65dsi84"; + reg = <0x2c>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi0_sn65dsi84_pins>; + enable-gpios = <&pio 25 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sn65dsi84_bridge_in: endpoint { + remote-endpoint = <&dsi0_out>; + data-lanes = <1 2 3 4>; + }; + }; + + port@2 { + reg = <2>; + + sn65dsi84_bridge_out: endpoint { + remote-endpoint = <&dsi0_panel_in>; + }; + }; + }; + }; + + touchscren@5d { + compatible = "goodix,gt911"; + reg = <0x5d>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_dsi0_goodix_pins>; + interrupts-extended = <&pio 146 IRQ_TYPE_LEVEL_HIGH>; + irq-gpios = <&pio 146 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>; + }; +}; + +&mfg0 { + domain-supply = <&mt6359_vproc2_buck_reg>; +}; + +&mfg1 { + domain-supply = <&mt6359_vsram_others_ldo_reg>; +}; + +&mmc0 { + bus-width = <8>; + cap-mmc-highspeed; + cap-mmc-hw-reset; + hs400-ds-delay = <0x1481b>; + max-frequency = <200000000>; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + non-removable; + no-sd; + no-sdio; + supports-cqe; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_default_pins>; + pinctrl-1 = <&mmc0_uhs_pins>; + vmmc-supply = <&mt6359_vemc_1_ldo_reg>; + vqmmc-supply = <&mt6359_vufs_ldo_reg>; + status = "okay"; +}; + +&mmc1 { + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <200000000>; + sd-uhs-sdr104; + sd-uhs-sdr50; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc1_default_pins>; + pinctrl-1 = <&mmc1_uhs_pins>; + cd-gpios = <&pio 2 GPIO_ACTIVE_LOW>; + vqmmc-supply = <&mt6359_vsim1_ldo_reg>; + vmmc-supply = <&sdcard_en_3v3>; + status = "okay"; +}; + +&mmc2 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + max-frequency = <200000000>; + no-mmc; + non-removable; + no-sd; + sd-uhs-sdr104; + wakeup-source; + pinctrl-names = "default", "state_uhs", "state_eint"; + pinctrl-0 = <&mmc2_default_pins>; + pinctrl-1 = <&mmc2_uhs_pins>; + pinctrl-2 = <&mmc2_eint_pins>; + interrupt-names = "msdc", "sdio_wakeup"; + interrupts-extended = <&gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>, + <&pio 172 IRQ_TYPE_LEVEL_LOW>; + vmmc-supply = <&mt6359_vcn33_2_bt_ldo_reg>; + vqmmc-supply = <&mt6359_vcn18_ldo_reg>; + mmc-pwrseq = <&wifi_pwrseq>; + status = "okay"; +}; + +&mipi_tx_config0 { + status = "okay"; +}; + +&mt6359codec { + mediatek,mic-type-0 = <1>; + mediatek,mic-type-1 = <3>; +}; + +&mt6359_vbbck_ldo_reg { + regulator-always-on; +}; + +&mt6359_vcn18_ldo_reg { + regulator-name = "vcn18_pmu"; + regulator-always-on; + regulator-boot-on; +}; + +&mt6359_vcn33_1_bt_ldo_reg { + regulator-name = "vcn33_1_pmu"; + regulator-always-on; +}; + +&mt6359_vcn33_2_bt_ldo_reg { + regulator-name = "vcn33_2_pmu"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; +}; + +&mt6359_vcore_buck_reg { + regulator-name = "dvdd_proc_l"; + regulator-always-on; +}; + +&mt6359_vemc_1_ldo_reg { + regulator-always-on; +}; + +&mt6359_vgpu11_buck_reg { + regulator-name = "dvdd_core"; + regulator-always-on; +}; + +&mt6359_vmodem_buck_reg { + regulator-always-on; +}; + +&mt6359_vpa_buck_reg { + regulator-name = "vpa_pmu"; + regulator-always-on; +}; + +&mt6359_vproc2_buck_reg { + /* The name "vgpu" is required by mtk-regulator-coupler */ + regulator-name = "vgpu"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <800000>; + regulator-coupled-with = <&mt6359_vsram_others_ldo_reg>; + regulator-coupled-max-spread = <225000>; +}; + +&mt6359_vs2_buck_reg { + regulator-min-microvolt = <1600000>; + regulator-boot-on; +}; + +&mt6359_vpu_buck_reg { + regulator-name = "dvdd_adsp"; + regulator-always-on; +}; + +&mt6359_vrf12_ldo_reg { + regulator-name = "va12_abb2_pmu"; + regulator-always-on; +}; + +&mt6359_vsram_md_ldo_reg { + regulator-always-on; +}; + +&mt6359_vsram_others_ldo_reg { + /* The name "vsram_gpu" is required by mtk-regulator-coupler */ + regulator-name = "vsram_gpu"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <800000>; + regulator-coupled-with = <&mt6359_vproc2_buck_reg>; + regulator-coupled-max-spread = <225000>; +}; + +&mt6359_vsim1_ldo_reg { + regulator-name = "vsim1_pmu"; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <480>; +}; + +&mt6359_vufs_ldo_reg { + regulator-name = "vufs18_pmu"; + regulator-always-on; +}; + +&ovl0_in { + remote-endpoint = <&vdosys0_ep_main>; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_default_pins>; + status = "okay"; +}; + +&pciephy { + status = "okay"; +}; + +&pmic { + interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; + + keys { + compatible = "mediatek,mt6359-keys"; + mediatek,long-press-mode = <1>; + power-off-time-sec = <0>; + + power-key { + linux,keycodes = <KEY_POWER>; + wakeup-source; + }; + }; +}; + +&postmask0_in { + remote-endpoint = <&gamma0_out>; +}; + +&postmask0_out { + remote-endpoint = <&dither0_in>; +}; + +&scp_cluster { + status = "okay"; +}; + +&scp_c0 { + memory-region = <&scp_mem>; + status = "okay"; +}; + +&spi0 { + pinctrl-0 = <&spi0_pins>; + pinctrl-names = "default"; + mediatek,pad-select = <0>; + status = "okay"; +}; + +&spi1 { + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; + mediatek,pad-select = <0>; + status = "okay"; +}; + +&spmi { + #address-cells = <2>; + #size-cells = <0>; + + mt6315_6: pmic@6 { + compatible = "mediatek,mt6315-regulator"; + reg = <0x6 SPMI_USID>; + + regulators { + mt6315_6_vbuck1: vbuck1 { + regulator-name = "vbuck1"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1193750>; + regulator-enable-ramp-delay = <256>; + regulator-allowed-modes = <0 1 2>; + regulator-always-on; + }; + + mt6315_6_vbuck3: vbuck3 { + regulator-name = "vbuck3"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1193750>; + regulator-enable-ramp-delay = <256>; + regulator-allowed-modes = <0 1 2>; + regulator-always-on; + }; + + mt6315_6_vbuck4: vbuck4 { + regulator-name = "vbuck4"; + regulator-min-microvolt = <1193750>; + regulator-max-microvolt = <1193750>; + regulator-enable-ramp-delay = <256>; + regulator-allowed-modes = <0 1 2>; + regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1193750>; + }; + }; + }; + }; +}; + +&uart0 { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart1 { + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&ssusb0 { + dr_mode = "otg"; + maximum-speed = "high-speed"; + usb-role-switch; + wakeup-source; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + pinctrl-0 = <&usbotg_pins>; + pinctrl-names = "default"; + status = "okay"; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + hs_ep: endpoint { + remote-endpoint = <&usb_hs_ep>; + }; + }; + + port@1 { + reg = <1>; + ss_ep: endpoint { + remote-endpoint = <&hd3ss3220_in_ep>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usb_hs_ep: endpoint { + remote-endpoint = <&hs_ep>; + }; + }; + + port@1 { + reg = <1>; + usb_role_switch: endpoint { + remote-endpoint = <&hd3ss3220_out_ep>; + }; + }; + }; +}; + +&u2port0 { + status = "okay"; +}; + +&u3phy0 { + status = "okay"; +}; + +&xhci0 { + vbus-supply = <&usb_p0_vbus>; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +&ssusb1 { + dr_mode = "host"; + wakeup-source; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + pinctrl-0 = <&usb1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&u2port1 { + status = "okay"; +}; + +&u3port1 { + status = "okay"; +}; + +&u3phy1 { + status = "okay"; +}; + +&xhci1 { + vbus-supply = <&usb_p1_vbus>; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +&ssusb2 { + dr_mode = "host"; + maximum-speed = "high-speed"; + wakeup-source; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +&u2port2 { + status = "okay"; +}; + +&u3phy2 { + status = "okay"; +}; + +&xhci2 { + vbus-supply = <&usb_p2_vbus>; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ethernet@1 { + compatible = "usb424,7850"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@1 { + reg = <1>; + microchip,led-modes = < + LAN78XX_LINK_1000_ACTIVITY + LAN78XX_LINK_10_ACTIVITY + LAN78XX_LINK_10_100_ACTIVITY + LAN78XX_LINK_ACTIVITY + >; + }; + }; + }; +}; + +&vdosys0 { + port { + #address-cells = <1>; + #size-cells = <0>; + + vdosys0_ep_main: endpoint@0 { + reg = <0>; + remote-endpoint = <&ovl0_in>; + }; + }; +}; + +&watchdog { + pinctrl-names = "default"; + pinctrl-0 = <&watchdog_pins>; +}; + +&pio { + audio_pins: audio-pins { + pins-aud-pmic { + pinmux = <PINMUX_GPIO101__FUNC_O_AUD_CLK_MOSI + PINMUX_GPIO102__FUNC_O_AUD_SYNC_MOSI + PINMUX_GPIO103__FUNC_O_AUD_DAT_MOSI0 + PINMUX_GPIO104__FUNC_O_AUD_DAT_MOSI1 + PINMUX_GPIO105__FUNC_I0_AUD_DAT_MISO0 + PINMUX_GPIO106__FUNC_I0_AUD_DAT_MISO1>; + }; + + pins-pcm-wifi { + pinmux = <PINMUX_GPIO121__FUNC_B0_PCM_CLK + PINMUX_GPIO122__FUNC_B0_PCM_SYNC + PINMUX_GPIO123__FUNC_O_PCM_DO + PINMUX_GPIO124__FUNC_I0_PCM_DI>; + }; + + pins-i2s { + pinmux = <PINMUX_GPIO119__FUNC_O_I2SO1_MCK + PINMUX_GPIO112__FUNC_O_I2SO1_WS + PINMUX_GPIO120__FUNC_O_I2SO1_BCK + PINMUX_GPIO113__FUNC_O_I2SO1_D0 + PINMUX_GPIO110__FUNC_I0_I2SIN_D0>; + }; + }; + + disp_pwm0_pins: disp-pwm0-pins { + pins { + pinmux = <PINMUX_GPIO29__FUNC_O_DISP_PWM0>; + bias-pull-down; + }; + }; + + dsi0_sn65dsi84_pins: dsi0-sn65dsi84-pins { + pins-irq { + pinmux = <PINMUX_GPIO128__FUNC_B_GPIO128>; + bias-pull-down; + input-enable; + }; + + pins-enable { + pinmux = <PINMUX_GPIO25__FUNC_B_GPIO25>; + bias-pull-down; + }; + }; + + eth_default_pins: eth-default-pins { + pins-txd { + pinmux = <PINMUX_GPIO131__FUNC_O_GBE_TXD3>, + <PINMUX_GPIO132__FUNC_O_GBE_TXD2>, + <PINMUX_GPIO133__FUNC_O_GBE_TXD1>, + <PINMUX_GPIO134__FUNC_O_GBE_TXD0>; + drive-strength = <8>; + }; + pins-cc { + pinmux = <PINMUX_GPIO139__FUNC_B0_GBE_TXC>, + <PINMUX_GPIO142__FUNC_O_GBE_TXEN>, + <PINMUX_GPIO141__FUNC_I0_GBE_RXDV>; + drive-strength = <8>; + }; + pins-rxd { + pinmux = <PINMUX_GPIO135__FUNC_I0_GBE_RXD3>, + <PINMUX_GPIO136__FUNC_I0_GBE_RXD2>, + <PINMUX_GPIO137__FUNC_I0_GBE_RXD1>, + <PINMUX_GPIO138__FUNC_I0_GBE_RXD0>, + <PINMUX_GPIO140__FUNC_I0_GBE_RXC>; + drive-strength = <8>; + bias-pull-up = <MTK_PUPD_SET_R1R0_10>; + }; + pins-mdio { + pinmux = <PINMUX_GPIO143__FUNC_O_GBE_MDC>, + <PINMUX_GPIO144__FUNC_B1_GBE_MDIO>; + drive-strength = <8>; + input-enable; + }; + pins-power { + pinmux = <PINMUX_GPIO27__FUNC_B_GPIO27>; /* GP_EQOS_RESET */ + output-high; + }; + pins-intr { + pinmux = <PINMUX_GPIO148__FUNC_B_GPIO148>; /* GPIRQ_EQOS_PHY */ + bias-pull-up = <MTK_PUPD_SET_R1R0_10>; + input-enable; + }; + }; + + eth_sleep_pins: eth-sleep-pins { + pins-txd { + pinmux = <PINMUX_GPIO131__FUNC_B_GPIO131>, + <PINMUX_GPIO132__FUNC_B_GPIO132>, + <PINMUX_GPIO133__FUNC_B_GPIO133>, + <PINMUX_GPIO134__FUNC_B_GPIO134>; + }; + pins-cc { + pinmux = <PINMUX_GPIO139__FUNC_B_GPIO139>, + <PINMUX_GPIO142__FUNC_B_GPIO142>, + <PINMUX_GPIO141__FUNC_B_GPIO141>, + <PINMUX_GPIO140__FUNC_B_GPIO140>; + }; + pins-rxd { + pinmux = <PINMUX_GPIO135__FUNC_B_GPIO135>, + <PINMUX_GPIO136__FUNC_B_GPIO136>, + <PINMUX_GPIO137__FUNC_B_GPIO137>, + <PINMUX_GPIO138__FUNC_B_GPIO138>; + }; + pins-mdio { + pinmux = <PINMUX_GPIO143__FUNC_B_GPIO143>, + <PINMUX_GPIO144__FUNC_B_GPIO144>; + input-disable; + bias-disable; + }; + }; + + gpio_keys_pins: gpio-keys-pins { + pins-keys { + pinmux = <PINMUX_GPIO129__FUNC_B_GPIO129>, + <PINMUX_GPIO65__FUNC_B_GPIO65>, + <PINMUX_GPIO66__FUNC_B_GPIO66>; + bias-pull-up; + }; + }; + + hd3ss3220_pins: hd3ss3320-pins { + pins-irq { + pinmux = <PINMUX_GPIO45__FUNC_B_GPIO45>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + input-enable; + }; + }; + + hdmi_vreg_pins: hdmi-vreg-pins { + pins-pwr { + pinmux = <PINMUX_GPIO50__FUNC_O_HDMITX20_PWR5V>; + bias-disable; + }; + }; + + hdmi_pins: hdmi-pins { + pins-hotplug { + pinmux = <PINMUX_GPIO51__FUNC_I0_HDMITX20_HTPLG>; + bias-pull-down; + }; + + pins-cec { + pinmux = <PINMUX_GPIO52__FUNC_B1_HDMITX20_CEC>; + bias-disable; + }; + + pins-ddc { + pinmux = <PINMUX_GPIO53__FUNC_B1_HDMITX20_SCL>, + <PINMUX_GPIO54__FUNC_B1_HDMITX20_SDA>; + drive-strength = <10>; + }; + }; + + i2c0_pins: i2c0-pins { + pins-bus { + pinmux = <PINMUX_GPIO56__FUNC_B1_SDA0>, + <PINMUX_GPIO55__FUNC_B1_SCL0>; + bias-pull-up = <MTK_PULL_SET_RSEL_011>; + drive-strength-microamp = <1000>; + }; + }; + + i2c0_mux_pins: i2c0-mux-pins { + pins-reset { + pinmux = <PINMUX_GPIO6__FUNC_B_GPIO6>; + bias-pull-up; + }; + }; + + i2c1_pins: i2c1-pins { + pins-bus { + pinmux = <PINMUX_GPIO58__FUNC_B1_SDA1>, + <PINMUX_GPIO57__FUNC_B1_SCL1>; + bias-pull-up = <MTK_PULL_SET_RSEL_011>; + drive-strength-microamp = <1000>; + }; + }; + + i2c2_pins: i2c2-pins { + pins-bus { + pinmux = <PINMUX_GPIO60__FUNC_B1_SDA2>, + <PINMUX_GPIO59__FUNC_B1_SCL2>; + bias-pull-up = <MTK_PULL_SET_RSEL_011>; + drive-strength-microamp = <1000>; + }; + }; + + i2c3_pins: i2c3-pins { + pins-bus { + pinmux = <PINMUX_GPIO62__FUNC_B1_SDA3>, + <PINMUX_GPIO61__FUNC_B1_SCL3>; + bias-pull-up = <MTK_PULL_SET_RSEL_011>; + drive-strength-microamp = <1000>; + }; + }; + + i2c4_pins: i2c4-pins { + pins-bus { + pinmux = <PINMUX_GPIO64__FUNC_B1_SDA4>, + <PINMUX_GPIO63__FUNC_B1_SCL4>; + bias-pull-up = <MTK_PULL_SET_RSEL_011>; + drive-strength-microamp = <1000>; + }; + }; + + i2c_mux_smarc_lcd_pins: i2c-mux-smarc-lcd-pins { + pins-reset { + pinmux = <PINMUX_GPIO5__FUNC_B_GPIO5>; + bias-pull-down; + }; + }; + + mmc0_default_pins: mmc0-default-pins { + pins-cmd-dat { + pinmux = <PINMUX_GPIO161__FUNC_B1_MSDC0_DAT0>, + <PINMUX_GPIO160__FUNC_B1_MSDC0_DAT1>, + <PINMUX_GPIO159__FUNC_B1_MSDC0_DAT2>, + <PINMUX_GPIO158__FUNC_B1_MSDC0_DAT3>, + <PINMUX_GPIO154__FUNC_B1_MSDC0_DAT4>, + <PINMUX_GPIO153__FUNC_B1_MSDC0_DAT5>, + <PINMUX_GPIO152__FUNC_B1_MSDC0_DAT6>, + <PINMUX_GPIO151__FUNC_B1_MSDC0_DAT7>, + <PINMUX_GPIO156__FUNC_B1_MSDC0_CMD>; + input-enable; + drive-strength = <6>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-clk { + pinmux = <PINMUX_GPIO157__FUNC_B1_MSDC0_CLK>; + drive-strength = <6>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-rst { + pinmux = <PINMUX_GPIO155__FUNC_O_MSDC0_RSTB>; + drive-strength = <6>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + }; + + mmc0_uhs_pins: mmc0-uhs-pins { + pins-cmd-dat { + pinmux = <PINMUX_GPIO161__FUNC_B1_MSDC0_DAT0>, + <PINMUX_GPIO160__FUNC_B1_MSDC0_DAT1>, + <PINMUX_GPIO159__FUNC_B1_MSDC0_DAT2>, + <PINMUX_GPIO158__FUNC_B1_MSDC0_DAT3>, + <PINMUX_GPIO154__FUNC_B1_MSDC0_DAT4>, + <PINMUX_GPIO153__FUNC_B1_MSDC0_DAT5>, + <PINMUX_GPIO152__FUNC_B1_MSDC0_DAT6>, + <PINMUX_GPIO151__FUNC_B1_MSDC0_DAT7>, + <PINMUX_GPIO156__FUNC_B1_MSDC0_CMD>; + input-enable; + drive-strength = <8>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-clk { + pinmux = <PINMUX_GPIO157__FUNC_B1_MSDC0_CLK>; + drive-strength = <8>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-ds { + pinmux = <PINMUX_GPIO162__FUNC_B0_MSDC0_DSL>; + drive-strength = <8>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-rst { + pinmux = <PINMUX_GPIO155__FUNC_O_MSDC0_RSTB>; + drive-strength = <8>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + }; + + mmc1_default_pins: mmc1-default-pins { + pins-cmd-dat { + pinmux = <PINMUX_GPIO163__FUNC_B1_MSDC1_CMD>, + <PINMUX_GPIO165__FUNC_B1_MSDC1_DAT0>, + <PINMUX_GPIO166__FUNC_B1_MSDC1_DAT1>, + <PINMUX_GPIO167__FUNC_B1_MSDC1_DAT2>, + <PINMUX_GPIO168__FUNC_B1_MSDC1_DAT3>; + input-enable; + drive-strength = <6>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-pwr { + pinmux = <PINMUX_GPIO111__FUNC_B_GPIO111>; + bias-pull-down; + }; + + pins-pullup { + pinmux = <PINMUX_GPIO11__FUNC_B_GPIO11>; + bias-pull-up; + }; + + pins-clk { + pinmux = <PINMUX_GPIO164__FUNC_B1_MSDC1_CLK>; + drive-strength = <6>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-insert { + pinmux = <PINMUX_GPIO2__FUNC_B_GPIO2>; + bias-pull-up; + }; + }; + + mmc1_uhs_pins: mmc1-uhs-pins { + pins-cmd-dat { + pinmux = <PINMUX_GPIO163__FUNC_B1_MSDC1_CMD>, + <PINMUX_GPIO165__FUNC_B1_MSDC1_DAT0>, + <PINMUX_GPIO166__FUNC_B1_MSDC1_DAT1>, + <PINMUX_GPIO167__FUNC_B1_MSDC1_DAT2>, + <PINMUX_GPIO168__FUNC_B1_MSDC1_DAT3>; + input-enable; + drive-strength = <6>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-clk { + pinmux = <PINMUX_GPIO164__FUNC_B1_MSDC1_CLK>; + drive-strength = <6>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + }; + + mmc2_default_pins: mmc2-default-pins { + pins-clk { + pinmux = <PINMUX_GPIO170__FUNC_B1_MSDC2_CLK>; + drive-strength = <4>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-cmd-dat { + pinmux = <PINMUX_GPIO169__FUNC_B1_MSDC2_CMD>, + <PINMUX_GPIO171__FUNC_B1_MSDC2_DAT0>, + <PINMUX_GPIO172__FUNC_B1_MSDC2_DAT1>, + <PINMUX_GPIO173__FUNC_B1_MSDC2_DAT2>, + <PINMUX_GPIO174__FUNC_B1_MSDC2_DAT3>; + input-enable; + drive-strength = <6>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + }; + + mmc2_uhs_pins: mmc2-uhs-pins { + pins-clk { + pinmux = <PINMUX_GPIO170__FUNC_B1_MSDC2_CLK>; + drive-strength = <4>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-cmd-dat { + pinmux = <PINMUX_GPIO169__FUNC_B1_MSDC2_CMD>, + <PINMUX_GPIO171__FUNC_B1_MSDC2_DAT0>, + <PINMUX_GPIO172__FUNC_B1_MSDC2_DAT1>, + <PINMUX_GPIO173__FUNC_B1_MSDC2_DAT2>, + <PINMUX_GPIO174__FUNC_B1_MSDC2_DAT3>; + input-enable; + drive-strength = <6>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + }; + + mmc2_eint_pins: mmc2-eint-pins { + pins-dat1 { + pinmux = <PINMUX_GPIO172__FUNC_B_GPIO172>; + input-enable; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + }; + + rv3028_pins: rv3028-pins { + pins-irq { + pinmux = <PINMUX_GPIO42__FUNC_B_GPIO42>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + input-enable; + }; + }; + + spi0_pins: spi0-pins { + pins-spi { + pinmux = <PINMUX_GPIO69__FUNC_O_SPIM0_CSB>, + <PINMUX_GPIO70__FUNC_O_SPIM0_CLK>, + <PINMUX_GPIO71__FUNC_B0_SPIM0_MOSI>, + <PINMUX_GPIO72__FUNC_B0_SPIM0_MISO>; + bias-disable; + }; + }; + + spi1_pins: spi1-pins { + pins-spi { + pinmux = <PINMUX_GPIO75__FUNC_O_SPIM1_CSB>, + <PINMUX_GPIO76__FUNC_O_SPIM1_CLK>, + <PINMUX_GPIO77__FUNC_B0_SPIM1_MOSI>, + <PINMUX_GPIO78__FUNC_B0_SPIM1_MISO>; + bias-disable; + }; + }; + + pcie_default_pins: pcie-default-pins { + pins { + pinmux = <PINMUX_GPIO47__FUNC_I1_WAKEN>, + <PINMUX_GPIO48__FUNC_O_PERSTN>, + <PINMUX_GPIO49__FUNC_B1_CLKREQN>; + bias-pull-up; + }; + }; + + ts_dsi0_goodix_pins: ts-dsi0-goodix-pins { + pins-irq { + pinmux = <PINMUX_GPIO146__FUNC_B_GPIO146>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + input-enable; + }; + + pins-reset { + pinmux = <PINMUX_GPIO7__FUNC_B_GPIO7>; + bias-pull-down; + }; + }; + + uart0_pins: uart0-pins { + pins { + pinmux = <PINMUX_GPIO31__FUNC_O_UTXD0>, + <PINMUX_GPIO32__FUNC_I1_URXD0>; + bias-pull-up; + }; + }; + + uart1_pins: uart1-pins { + pins { + pinmux = <PINMUX_GPIO33__FUNC_O_UTXD1>, + <PINMUX_GPIO34__FUNC_I1_URXD1>; + bias-pull-up; + }; + }; + + uart2_pins: uart2-pins { + pins { + pinmux = <PINMUX_GPIO35__FUNC_O_UTXD2>, + <PINMUX_GPIO36__FUNC_I1_URXD2>; + bias-pull-up; + }; + }; + + usbotg_pins: usbotg-pins { + pins-iddig { + pinmux = <PINMUX_GPIO83__FUNC_B_GPIO83>; + input-enable; + bias-pull-up; + }; + + pins-valid { + pinmux = <PINMUX_GPIO85__FUNC_I0_VBUSVALID>; + input-enable; + }; + + pins-vbus { + pinmux = <PINMUX_GPIO84__FUNC_O_USB_DRVVBUS>; + output-high; + }; + }; + + usb1_hub_pins: usb1-hub-pins { + pins { + pinmux = <PINMUX_GPIO147__FUNC_B_GPIO147>; + output-low; + }; + }; + + usb1_pins: usb1-pins { + pins { + pinmux = <PINMUX_GPIO88__FUNC_I0_VBUSVALID_1P>; + input-enable; + }; + }; + + usb2_eth_pins: usb2-eth-pins { + pins { + pinmux = <PINMUX_GPIO80__FUNC_B_GPIO80>; + output-low; + }; + }; + + wifi_pwrseq_pins: wifi-pwrseq-pins { + pins { + pinmux = <PINMUX_GPIO89__FUNC_B_GPIO89>; + output-low; + }; + }; + + watchdog_pins: watchdog-pins { + pins { + pinmux = <PINMUX_GPIO100__FUNC_O_WATCHDOG>; + bias-pull-up; + }; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi index 2b7167804e71..d849af4d3613 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi @@ -26,6 +26,20 @@ stdout-path = "serial0:921600n8"; }; + connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + ddc-i2c-bus = <&hdmitx_ddc>; + hdmi-pwr-supply = <&hdmi_phy>; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi0_out>; + }; + }; + }; + firmware { optee { compatible = "linaro,optee-tz"; @@ -247,6 +261,18 @@ wakeup-delay-ms = <200>; }; +&dpi1 { + status = "okay"; +}; + +&dpi1_in { + remote-endpoint = <&merge5_out>; +}; + +&dpi1_out { + remote-endpoint = <&hdmi0_in>; +}; + &dsi0 { #address-cells = <1>; #size-cells = <0>; @@ -313,6 +339,35 @@ }; }; +ðdr0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + ethdr0_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&vdosys1_ep_ext>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + ethdr0_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&merge5_in>; + }; + }; + }; +}; + &gamma0_out { remote-endpoint = <&dither0_in>; }; @@ -329,6 +384,27 @@ status = "okay"; }; +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pins>; + status = "okay"; +}; + +&hdmi0_in { + remote-endpoint = <&dpi1_out>; +}; + +&hdmi0_out { + remote-endpoint = <&hdmi_connector_in>; +}; + +&hdmi_phy { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_vreg_pins>; + + status = "okay"; +}; + &i2c1 { clock-frequency = <400000>; pinctrl-0 = <&i2c1_pins>; @@ -533,6 +609,35 @@ }; }; +&merge5 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + merge5_in: endpoint@1 { + reg = <1>; + remote-endpoint = <ðdr0_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + merge5_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&dpi1_in>; + }; + }; + }; +}; + &mfg0 { domain-supply = <&mt6315_7_vbuck1>; }; @@ -762,6 +867,31 @@ }; }; + hdmi_vreg_pins: hdmi-vreg-pins { + pins-pwr { + pinmux = <PINMUX_GPIO31__FUNC_HDMITX20_PWR5V>; + bias-disable; + }; + }; + + hdmi_pins: hdmi-pins { + pins-hotplug { + pinmux = <PINMUX_GPIO32__FUNC_HDMITX20_HTPLG>; + bias-pull-down; + }; + + pins-ddc { + pinmux = <PINMUX_GPIO34__FUNC_HDMITX20_SCL>, + <PINMUX_GPIO35__FUNC_HDMITX20_SDA>; + drive-strength = <10>; + }; + + pins-cec { + pinmux = <PINMUX_GPIO33__FUNC_HDMITX20_CEC>; + bias-disable; + }; + }; + i2c0_pins: i2c0-pins { pins { pinmux = <PINMUX_GPIO8__FUNC_SDA0>, @@ -1059,6 +1189,14 @@ sound-dai = <&pmic 0>; }; }; + + hdmi-dai-link { + link-name = "ETDM3_OUT_BE"; + + codec { + sound-dai = <&hdmi 0>; + }; + }; }; &spi1 { @@ -1212,6 +1350,18 @@ }; }; +&vdosys1 { + port { + #address-cells = <1>; + #size-cells = <0>; + + vdosys1_ep_ext: endpoint@1 { + reg = <1>; + remote-endpoint = <ðdr0_in>; + }; + }; +}; + &xhci0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts index d32f973f5e05..1cd4b84e9861 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts +++ b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts @@ -37,6 +37,20 @@ stdout-path = "serial0:921600n8"; }; + connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + ddc-i2c-bus = <&hdmitx_ddc>; + hdmi-pwr-supply = <&hdmi_phy>; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi0_out>; + }; + }; + }; + firmware { optee { compatible = "linaro,optee-tz"; @@ -245,6 +259,18 @@ }; }; +&dpi1 { + status = "okay"; +}; + +&dpi1_in { + remote-endpoint = <&merge5_out>; +}; + +&dpi1_out { + remote-endpoint = <&hdmi0_in>; +}; + ð { phy-mode = "rgmii-rxid"; phy-handle = <&rgmii_phy>; @@ -265,11 +291,61 @@ }; }; +ðdr0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + ethdr0_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&vdosys1_ep_ext>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + ethdr0_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&merge5_in>; + }; + }; + }; +}; + &gpu { mali-supply = <&mt6315_7_vbuck1>; status = "okay"; }; +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pins>; + status = "okay"; +}; + +&hdmi0_in { + remote-endpoint = <&dpi1_out>; +}; + +&hdmi0_out { + remote-endpoint = <&hdmi_connector_in>; +}; + +&hdmi_phy { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_vreg_pins>; + + status = "okay"; +}; + &i2c2 { clock-frequency = <400000>; pinctrl-0 = <&i2c2_pins>; @@ -448,6 +524,35 @@ }; }; +&merge5 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + merge5_in: endpoint@1 { + reg = <1>; + remote-endpoint = <ðdr0_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + merge5_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&dpi1_in>; + }; + }; + }; +}; + &mfg0 { domain-supply = <&mt6315_7_vbuck1>; }; @@ -647,6 +752,31 @@ }; }; + hdmi_vreg_pins: hdmi-vreg-pins { + pins-pwr { + pinmux = <PINMUX_GPIO31__FUNC_HDMITX20_PWR5V>; + bias-disable; + }; + }; + + hdmi_pins: hdmi-pins { + pins-hotplug { + pinmux = <PINMUX_GPIO32__FUNC_HDMITX20_HTPLG>; + bias-pull-down; + }; + + pins-ddc { + pinmux = <PINMUX_GPIO34__FUNC_HDMITX20_SCL>, + <PINMUX_GPIO35__FUNC_HDMITX20_SDA>; + drive-strength = <10>; + }; + + pins-cec { + pinmux = <PINMUX_GPIO33__FUNC_HDMITX20_CEC>; + bias-disable; + }; + }; + i2c2_pins: i2c2-pins { pins-bus { pinmux = <PINMUX_GPIO12__FUNC_SDA2>, @@ -942,6 +1072,14 @@ sound-dai = <&pmic 0>; }; }; + + hdmi-dai-link { + link-name = "ETDM3_OUT_BE"; + + codec { + sound-dai = <&hdmi 0>; + }; + }; }; &spi1 { @@ -1058,6 +1196,18 @@ status = "okay"; }; +&vdosys1 { + port { + #address-cells = <1>; + #size-cells = <0>; + + vdosys1_ep_ext: endpoint@1 { + reg = <1>; + remote-endpoint = <ðdr0_in>; + }; + }; +}; + &xhci0 { vbus-supply = <&otg_vbus_regulator>; status = "okay"; diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts index 2638ee1c3846..5edf5d13342d 100644 --- a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts @@ -17,6 +17,7 @@ }; memory@0 { + device_type = "memory"; reg = <0x0 0x0 0x0 0x40000000>; }; diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi index 383938dcd3ce..8239d9a9f0d2 100644 --- a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi @@ -64,8 +64,8 @@ }; psci { - compatible = "arm,psci-1.0"; - method = "smc"; + compatible = "arm,psci-1.0"; + method = "smc"; }; timer { diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index b00630451909..705af0373a09 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -120,7 +120,6 @@ iommus = <&smmu TEGRA186_SID_GPCDMA_0>; dma-coherent; dma-channel-mask = <0xfffffffe>; - status = "okay"; }; aconnect@2900000 { @@ -608,7 +607,6 @@ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - status = "okay"; }; uarta: serial@3100000 { diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index b782f8db1288..849694f751d9 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -97,7 +97,6 @@ <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; nvidia,axi2apb = <&axi2apb>; nvidia,apbmisc = <&apbmisc>; - status = "okay"; }; axi2apb: axi2apb@2390000 { @@ -108,13 +107,11 @@ <0x0 0x23c0000 0x0 0x1000>, <0x0 0x23d0000 0x0 0x1000>, <0x0 0x23e0000 0x0 0x1000>; - status = "okay"; }; pinmux: pinmux@2430000 { compatible = "nvidia,tegra194-pinmux"; reg = <0x0 0x2430000 0x0 0x17000>; - status = "okay"; pex_clkreq_c5_bi_dir_state: pinmux-pex-clkreq-c5-bi-dir { clkreq { @@ -208,7 +205,6 @@ iommus = <&smmu TEGRA194_SID_GPCDMA_0>; dma-coherent; dma-channel-mask = <0xfffffffe>; - status = "okay"; }; aconnect@2900000 { @@ -737,7 +733,6 @@ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - status = "okay"; }; uarta: serial@3100000 { @@ -1359,7 +1354,6 @@ nvidia,int-threshold = <1>; nvidia,slices = <11>; #timestamp-cells = <1>; - status = "okay"; }; hsp_top0: hsp@3c00000 { @@ -1547,7 +1541,6 @@ <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; nvidia,axi2apb = <&axi2apb>; nvidia,apbmisc = <&apbmisc>; - status = "okay"; }; rce-noc@be00000 { @@ -1557,7 +1550,6 @@ <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; nvidia,axi2apb = <&axi2apb>; nvidia,apbmisc = <&apbmisc>; - status = "okay"; }; hsp_aon: hsp@c150000 { @@ -1582,7 +1574,6 @@ nvidia,int-threshold = <1>; nvidia,slices = <3>; #timestamp-cells = <1>; - status = "okay"; }; gen2_i2c: i2c@c240000 { @@ -1668,8 +1659,6 @@ pinmux_aon: pinmux@c300000 { compatible = "nvidia,tegra194-pinmux-aon"; reg = <0x0 0xc300000 0x0 0x4000>; - - status = "okay"; }; pwm4: pwm@c340000 { @@ -1722,7 +1711,6 @@ interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; nvidia,apbmisc = <&apbmisc>; - status = "okay"; }; bpmp-noc@d600000 { @@ -1732,7 +1720,6 @@ <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; nvidia,axi2apb = <&axi2apb>; nvidia,apbmisc = <&apbmisc>; - status = "okay"; }; iommu@10000000 { @@ -1886,7 +1873,6 @@ #iommu-cells = <1>; nvidia,memory-controller = <&mc>; - status = "okay"; }; host1x@13e00000 { @@ -3106,7 +3092,6 @@ psci { compatible = "arm,psci-1.0"; - status = "okay"; method = "smc"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index 5aa6afd56cbc..b88428aa831e 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -31,6 +31,11 @@ }; host1x@50000000 { + dpaux1: dpaux@54040000 { + vdd-supply = <&pp3300>; + status = "okay"; + }; + dsia: dsi@54300000 { avdd-dsi-csi-supply = <&vdd_dsi_csi>; status = "okay"; @@ -58,6 +63,13 @@ }; }; + sor1: sor@54580000 { + avdd-io-hdmi-dp-supply = <&pp1800>; + vdd-hdmi-dp-pll-supply = <&avddio_1v05>; + nvidia,dpaux = <&dpaux1>; + status = "okay"; + }; + dpaux: dpaux@545c0000 { status = "okay"; }; @@ -1809,6 +1821,8 @@ status = "okay"; vbus-supply = <&usbc_vbus>; mode = "otg"; + usb-role-switch; + role-switch-default-mode = "host"; }; usb3-0 { @@ -1843,6 +1857,17 @@ status = "okay"; }; + usb@700d0000 { + phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, + <&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>; + phy-names = "usb2-0", "usb3-0"; + + avddio-usb-supply = <&avddio_1v05>; + hvdd-usb-supply = <&pp3300>; + + status = "okay"; + }; + clock@70110000 { status = "okay"; nvidia,cf = <6>; diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 827dbb420826..850c473235e3 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -40,7 +40,6 @@ compatible = "nvidia,tegra234-misc"; reg = <0x0 0x00100000 0x0 0xf000>, <0x0 0x0010f000 0x0 0x1000>; - status = "okay"; }; timer@2080000 { @@ -62,7 +61,6 @@ <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; - status = "okay"; }; gpio: gpio@2200000 { @@ -2780,7 +2778,6 @@ "ch11", "ch12", "ch13", "ch14", "ch15"; interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; #interconnect-cells = <1>; - status = "okay"; #address-cells = <2>; #size-cells = <2>; @@ -2812,7 +2809,6 @@ interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA234_CLK_EMC>; clock-names = "emc"; - status = "okay"; #interconnect-cells = <0>; @@ -3888,7 +3884,6 @@ #iommu-cells = <1>; nvidia,memory-controller = <&mc>; - status = "okay"; }; sce-fabric@b600000 { @@ -3902,7 +3897,6 @@ compatible = "nvidia,tegra234-rce-fabric"; reg = <0x0 0xbe00000 0x0 0x40000>; interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; - status = "okay"; }; hsp_aon: hsp@c150000 { @@ -4064,28 +4058,24 @@ compatible = "nvidia,tegra234-aon-fabric"; reg = <0x0 0xc600000 0x0 0x40000>; interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; - status = "okay"; }; bpmp-fabric@d600000 { compatible = "nvidia,tegra234-bpmp-fabric"; reg = <0x0 0xd600000 0x0 0x40000>; interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; - status = "okay"; }; dce-fabric@de00000 { compatible = "nvidia,tegra234-dce-fabric"; reg = <0x0 0xde00000 0x0 0x40000>; interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>; - status = "okay"; }; ccplex@e000000 { compatible = "nvidia,tegra234-ccplex-cluster"; reg = <0x0 0x0e000000 0x0 0x5ffff>; nvidia,bpmp = <&bpmp>; - status = "okay"; }; gic: interrupt-controller@f400000 { @@ -4239,7 +4229,6 @@ #iommu-cells = <1>; nvidia,memory-controller = <&mc>; - status = "okay"; }; smmu_niso0: iommu@12000000 { @@ -4381,14 +4370,12 @@ #iommu-cells = <1>; nvidia,memory-controller = <&mc>; - status = "okay"; }; cbb-fabric@13a00000 { compatible = "nvidia,tegra234-cbb-fabric"; reg = <0x0 0x13a00000 0x0 0x400000>; interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; - status = "okay"; }; host1x@13e00000 { @@ -5804,12 +5791,10 @@ pmu { compatible = "arm,cortex-a78-pmu"; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; - status = "okay"; }; psci { compatible = "arm,psci-1.0"; - status = "okay"; method = "smc"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi b/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi index 06795c82427a..7e2c3e66c2ab 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi @@ -23,8 +23,16 @@ status = "okay"; }; + cmdqv@5200000 { + status = "okay"; + }; + iommu@6000000 { status = "okay"; }; + + cmdqv@6200000 { + status = "okay"; + }; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi index f137565da804..7644a41d5f72 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi @@ -3361,7 +3361,7 @@ <0x02 0x00000000 0xd0 0x00000000 0x08 0x80000000>; /* ECAM, prefetchable memory, I/O */ smmu1: iommu@5000000 { - compatible = "arm,smmu-v3"; + compatible = "nvidia,tegra264-smmu", "arm,smmu-v3"; reg = <0x00 0x5000000 0x0 0x200000>; interrupts = <GIC_SPI 12 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 13 IRQ_TYPE_EDGE_RISING>; @@ -3370,10 +3370,18 @@ #iommu-cells = <1>; dma-coherent; + nvidia,cmdqv = <&cmdqv1>; + }; + + cmdqv1: cmdqv@5200000 { + compatible = "nvidia,tegra264-cmdqv"; + reg = <0x00 0x5200000 0x0 0x830000>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; }; smmu2: iommu@6000000 { - compatible = "arm,smmu-v3"; + compatible = "nvidia,tegra264-smmu", "arm,smmu-v3"; reg = <0x00 0x6000000 0x0 0x200000>; interrupts = <GIC_SPI 1 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>; @@ -3382,6 +3390,14 @@ #iommu-cells = <1>; dma-coherent; + nvidia,cmdqv = <&cmdqv2>; + }; + + cmdqv2: cmdqv@6200000 { + compatible = "nvidia,tegra264-cmdqv"; + reg = <0x00 0x6200000 0x0 0x830000>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; }; mc: memory-controller@8020000 { @@ -3428,8 +3444,9 @@ reg = <0x00 0x8800000 0x0 0x20000>, <0x00 0x8890000 0x0 0x20000>; interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&bpmp TEGRA264_CLK_EMC>; - clock-names = "emc"; + clocks = <&bpmp TEGRA264_CLK_EMC>, + <&bpmp TEGRA264_CLK_DBB_UPHY0>; + clock-names = "emc", "dbb"; #interconnect-cells = <0>; nvidia,bpmp = <&bpmp>; @@ -3437,7 +3454,7 @@ }; smmu0: iommu@a000000 { - compatible = "arm,smmu-v3"; + compatible = "nvidia,tegra264-smmu", "arm,smmu-v3"; reg = <0x00 0xa000000 0x0 0x200000>; interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; @@ -3446,10 +3463,18 @@ #iommu-cells = <1>; dma-coherent; + nvidia,cmdqv = <&cmdqv0>; + }; + + cmdqv0: cmdqv@a200000 { + compatible = "nvidia,tegra264-cmdqv"; + reg = <0x00 0xa200000 0x0 0x830000>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; }; smmu4: iommu@b000000 { - compatible = "arm,smmu-v3"; + compatible = "nvidia,tegra264-smmu", "arm,smmu-v3"; reg = <0x00 0xb000000 0x0 0x200000>; interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>; @@ -3458,6 +3483,14 @@ #iommu-cells = <1>; dma-coherent; + nvidia,cmdqv = <&cmdqv4>; + }; + + cmdqv4: cmdqv@b200000 { + compatible = "nvidia,tegra264-cmdqv"; + reg = <0x00 0xb200000 0x0 0x830000>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; }; i2c14: i2c@c410000 { @@ -3690,7 +3723,7 @@ ranges = <0x00 0x00000000 0x88 0x00000000 0x01 0x00000000>; smmu3: iommu@6000000 { - compatible = "arm,smmu-v3"; + compatible = "nvidia,tegra264-smmu", "arm,smmu-v3"; reg = <0x00 0x6000000 0x0 0x200000>; interrupts = <GIC_SPI 225 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 226 IRQ_TYPE_EDGE_RISING>; @@ -3699,6 +3732,14 @@ #iommu-cells = <1>; dma-coherent; + nvidia,cmdqv = <&cmdqv3>; + }; + + cmdqv3: cmdqv@6200000 { + compatible = "nvidia,tegra264-cmdqv"; + reg = <0x00 0x6200000 0x0 0x830000>; + interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; }; hda@90b0000 { @@ -3733,10 +3774,9 @@ #size-cells = <0>; cpu0: cpu@0 { - compatible = "arm,armv8"; + compatible = "arm,neoverse-v3ae"; device_type = "cpu"; reg = <0x00000>; - status = "okay"; enable-method = "psci"; @@ -3749,10 +3789,9 @@ }; cpu1: cpu@1 { - compatible = "arm,armv8"; + compatible = "arm,neoverse-v3ae"; device_type = "cpu"; reg = <0x10000>; - status = "okay"; enable-method = "psci"; @@ -3790,12 +3829,10 @@ pmu { compatible = "arm,armv8-pmuv3"; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; - status = "okay"; }; psci { compatible = "arm,psci-1.0"; - status = "okay"; method = "smc"; }; @@ -3822,6 +3859,5 @@ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; - status = "okay"; }; }; diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 6f34d5ed331c..f80b5d9cf1e8 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -30,6 +30,8 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp433.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp449.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp453.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp454.dtb +dtb-$(CONFIG_ARCH_QCOM) += kaanapali-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM) += kaanapali-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) += lemans-evk.dtb lemans-evk-camera-csi1-imx577-dtbs := lemans-evk.dtb lemans-evk-camera-csi1-imx577.dtbo @@ -37,6 +39,11 @@ lemans-evk-camera-dtbs := lemans-evk.dtb lemans-evk-camera.dtbo dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-camera-csi1-imx577.dtb dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-camera.dtb + +lemans-evk-el2-dtbs := lemans-evk.dtb lemans-el2.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-el2.dtb +dtb-$(CONFIG_ARCH_QCOM) += milos-fairphone-fp6.dtb dtb-$(CONFIG_ARCH_QCOM) += monaco-evk.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8216-samsung-fortuna3g.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-acer-a1-724.dtb @@ -138,12 +145,25 @@ qcs6490-rb3gen2-industrial-mezzanine-dtbs := qcs6490-rb3gen2.dtb qcs6490-rb3gen2 dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-industrial-mezzanine.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-vision-mezzanine.dtb +dtb-$(CONFIG_ARCH_QCOM) += qcs6490-thundercomm-rubikpi3.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs8300-ride.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride-r3.dtb + +qcs9100-ride-el2-dtbs := qcs9100-ride.dtb lemans-el2.dtbo +qcs9100-ride-r3-el2-dtbs := qcs9100-ride-r3.dtb lemans-el2.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride-el2.dtb +dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride-r3-el2.dtb dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb +dtb-$(CONFIG_ARCH_QCOM) += qrb2210-arduino-imola.dtb dtb-$(CONFIG_ARCH_QCOM) += qrb2210-rb1.dtb + +qrb2210-rb1-vision-mezzanine-dtbs := qrb2210-rb1.dtb qrb2210-rb1-vision-mezzanine.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += qrb2210-rb1-vision-mezzanine.dtb + dtb-$(CONFIG_ARCH_QCOM) += qrb4210-rb2.dtb dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb @@ -250,6 +270,8 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb sdm845-db845c-navigation-mezzanine-dtbs := sdm845-db845c.dtb sdm845-db845c-navigation-mezzanine.dtbo dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c-navigation-mezzanine.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm845-google-crosshatch.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm845-google-blueline.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-lg-judyln.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-lg-judyp.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb @@ -315,8 +337,12 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8550-samsung-q5q.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-sony-xperia-yodo-pdx234.dtb sm8650-hdk-display-card-dtbs := sm8650-hdk.dtb sm8650-hdk-display-card.dtbo +sm8650-hdk-display-card-rear-camera-card-dtbs := sm8650-hdk.dtb sm8650-hdk-display-card.dtbo sm8650-hdk-rear-camera-card.dtbo +sm8650-hdk-rear-camera-card-dtbs := sm8650-hdk.dtb sm8650-hdk-rear-camera-card.dtbo +dtb-$(CONFIG_ARCH_QCOM) += sm8650-hdk-display-card-rear-camera-card.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8650-hdk-display-card.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8650-hdk-rear-camera-card.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8650-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8650-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8650-qrd.dtb @@ -346,6 +372,8 @@ x1e80100-hp-omnibook-x14-el2-dtbs := x1e80100-hp-omnibook-x14.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1e80100-hp-omnibook-x14.dtb x1e80100-hp-omnibook-x14-el2.dtb x1e80100-lenovo-yoga-slim7x-el2-dtbs := x1e80100-lenovo-yoga-slim7x.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1e80100-lenovo-yoga-slim7x.dtb x1e80100-lenovo-yoga-slim7x-el2.dtb +x1e80100-medion-sprchrgd-14-s1-el2-dtbs := x1e80100-medion-sprchrgd-14-s1.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1e80100-medion-sprchrgd-14-s1.dtb x1e80100-medion-sprchrgd-14-s1-el2.dtb x1e80100-microsoft-romulus13-el2-dtbs := x1e80100-microsoft-romulus13.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1e80100-microsoft-romulus13.dtb x1e80100-microsoft-romulus13-el2.dtb x1e80100-microsoft-romulus15-el2-dtbs := x1e80100-microsoft-romulus15.dtb x1-el2.dtbo @@ -362,3 +390,5 @@ x1p42100-hp-omnibook-x14-el2-dtbs := x1p42100-hp-omnibook-x14.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1p42100-hp-omnibook-x14.dtb x1p42100-hp-omnibook-x14-el2.dtb x1p42100-lenovo-thinkbook-16-el2-dtbs := x1p42100-lenovo-thinkbook-16.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1p42100-lenovo-thinkbook-16.dtb x1p42100-lenovo-thinkbook-16-el2.dtb +x1p64100-microsoft-denali-el2-dtbs := x1p64100-microsoft-denali.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1p64100-microsoft-denali.dtb x1p64100-microsoft-denali-el2.dtb diff --git a/arch/arm64/boot/dts/qcom/agatti.dtsi b/arch/arm64/boot/dts/qcom/agatti.dtsi index 8bf5c5583fc2..76b93b7bd50f 100644 --- a/arch/arm64/boot/dts/qcom/agatti.dtsi +++ b/arch/arm64/boot/dts/qcom/agatti.dtsi @@ -562,6 +562,13 @@ bias-disable; }; + qup_uart2_default: qup-uart2-default-state { + pins = "gpio6", "gpio7", "gpio71", "gpio80"; + function = "qup2"; + drive-strength = <2>; + bias-disable; + }; + qup_uart3_default: qup-uart3-default-state { pins = "gpio8", "gpio9", "gpio10", "gpio11"; function = "qup3"; @@ -597,6 +604,34 @@ bias-disable; }; + mclk0_default: mclk0-default-state { + pins = "gpio20"; + function = "cam_mclk"; + drive-strength = <16>; + bias-disable; + }; + + mclk1_default: mclk1-default-state { + pins = "gpio21"; + function = "cam_mclk"; + drive-strength = <16>; + bias-disable; + }; + + mclk2_default: mclk2-default-state { + pins = "gpio27"; + function = "cam_mclk"; + drive-strength = <16>; + bias-disable; + }; + + mclk3_default: mclk3-default-state { + pins = "gpio28"; + function = "cam_mclk"; + drive-strength = <16>; + bias-disable; + }; + sdc1_state_on: sdc1-on-state { clk-pins { pins = "sdc1_clk"; @@ -1315,6 +1350,23 @@ status = "disabled"; }; + uart2: serial@4a88000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x04a88000 0x0 0x4000>; + interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_uart2_default>; + pinctrl-names = "default"; + interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG + &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + status = "disabled"; + }; + i2c3: i2c@4a8c000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x04a8c000 0x0 0x4000>; @@ -1591,8 +1643,12 @@ gpu: gpu@5900000 { compatible = "qcom,adreno-07000200", "qcom,adreno"; - reg = <0x0 0x05900000 0x0 0x40000>; - reg-names = "kgsl_3d0_reg_memory"; + reg = <0x0 0x05900000 0x0 0x40000>, + <0x0 0x0599e000 0x0 0x1000>, + <0x0 0x05961000 0x0 0x800>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; @@ -2235,6 +2291,47 @@ }; }; }; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "adsp"; + + qcom,non-secure-domain; + + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x1c3 0x0>; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x1c4 0x0>; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x1c5 0x0>; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x1c6 0x0>; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x1c7 0x0>; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/glymur-ipcc.h b/arch/arm64/boot/dts/qcom/glymur-ipcc.h new file mode 100644 index 000000000000..700cd7114909 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/glymur-ipcc.h @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __DTS_GLYMUR_MAILBOX_IPCC_H +#define __DTS_GLYMUR_MAILBOX_IPCC_H + +/* Glymur physical client IDs */ +#define IPCC_MPROC_AOP 0 +#define IPCC_MPROC_TZ 1 +#define IPCC_MPROC_MPSS 2 +#define IPCC_MPROC_LPASS 3 +#define IPCC_MPROC_SLPI 4 +#define IPCC_MPROC_SDC 5 +#define IPCC_MPROC_CDSP 6 +#define IPCC_MPROC_NPU 7 +#define IPCC_MPROC_APSS 8 +#define IPCC_MPROC_GPU 9 +#define IPCC_MPROC_ICP 11 +#define IPCC_MPROC_VPU 12 +#define IPCC_MPROC_PCIE0 13 +#define IPCC_MPROC_PCIE1 14 +#define IPCC_MPROC_PCIE2 15 +#define IPCC_MPROC_SPSS 16 +#define IPCC_MPROC_PCIE3 19 +#define IPCC_MPROC_PCIE4 20 +#define IPCC_MPROC_PCIE5 21 +#define IPCC_MPROC_PCIE6 22 +#define IPCC_MPROC_TME 23 +#define IPCC_MPROC_WPSS 24 +#define IPCC_MPROC_PCIE7 44 +#define IPCC_MPROC_SOCCP 46 + +#define IPCC_COMPUTE_L0_LPASS 0 +#define IPCC_COMPUTE_L0_CDSP 1 +#define IPCC_COMPUTE_L0_APSS 2 +#define IPCC_COMPUTE_L0_GPU 3 +#define IPCC_COMPUTE_L0_CVP 6 +#define IPCC_COMPUTE_L0_ICP 7 +#define IPCC_COMPUTE_L0_VPU 8 +#define IPCC_COMPUTE_L0_DPU 9 +#define IPCC_COMPUTE_L0_SOCCP 11 + +#define IPCC_COMPUTE_L1_LPASS 0 +#define IPCC_COMPUTE_L1_CDSP 1 +#define IPCC_COMPUTE_L1_APSS 2 +#define IPCC_COMPUTE_L1_GPU 3 +#define IPCC_COMPUTE_L1_CVP 6 +#define IPCC_COMPUTE_L1_ICP 7 +#define IPCC_COMPUTE_L1_VPU 8 +#define IPCC_COMPUTE_L1_DPU 9 +#define IPCC_COMPUTE_L1_SOCCP 11 + +#define IPCC_PERIPH_LPASS 0 +#define IPCC_PERIPH_APSS 1 +#define IPCC_PERIPH_PCIE0 2 +#define IPCC_PERIPH_PCIE1 3 +#define IPCC_PERIPH_PCIE2 6 +#define IPCC_PERIPH_PCIE3 7 +#define IPCC_PERIPH_PCIE4 8 +#define IPCC_PERIPH_PCIE5 9 +#define IPCC_PERIPH_PCIE6 10 +#define IPCC_PERIPH_PCIE7 11 +#define IPCC_PERIPH_SOCCP 13 +#define IPCC_PERIPH_WPSS 16 + +#endif diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts index 36dd6599402b..2390648a248f 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts @@ -5,7 +5,9 @@ /dts-v1/; +#include <dt-bindings/leds/common.h> #include "hamoa-iot-som.dtsi" +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> / { model = "Qualcomm Technologies, Inc. Hamoa IoT EVK"; @@ -17,6 +19,16 @@ serial1 = &uart14; }; + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pmk8550_pwm 0 5000000>; + enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>; + power-supply = <&vreg_edp_bl>; + + pinctrl-0 = <&edp_bl_en>, <&edp_bl_pwm>; + pinctrl-names = "default"; + }; + wcd938x: audio-codec { compatible = "qcom,wcd9385-codec"; @@ -48,6 +60,32 @@ stdout-path = "serial0:115200n8"; }; + connector3 { + compatible = "usb-a-connector"; + label = "USB-3-Type-A"; + power-role = "source"; + + vbus-supply = <®ulator_usb3_vbus>; + + port { + connector_3_in: endpoint { + }; + }; + }; + + connector6 { + compatible = "usb-a-connector"; + label = "USB-6-Type-A"; + power-role = "source"; + + vbus-supply = <®ulator_usb6_vbus>; + + port { + connector_4_in: endpoint { + }; + }; + }; + pmic-glink { compatible = "qcom,x1e80100-pmic-glink", "qcom,sm8550-pmic-glink", @@ -183,6 +221,22 @@ regulator-boot-on; }; + vreg_edp_bl: regulator-edp-bl { + compatible = "regulator-fixed"; + + regulator-name = "VBL9"; + regulator-min-microvolt = <3600000>; + regulator-max-microvolt = <3600000>; + + gpio = <&pmc8380_3_gpios 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_bl_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + vreg_nvme: regulator-nvme { compatible = "regulator-fixed"; @@ -199,6 +253,48 @@ regulator-boot-on; }; + vreg_pcie_12v: regulator-pcie-12v { + compatible = "regulator-fixed"; + + regulator-name = "VREG_PCIE_12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + + gpio = <&pm8550ve_8_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&pcie_x8_12v>; + pinctrl-names = "default"; + }; + + vreg_pcie_3v3: regulator-pcie-3v3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_PCIE_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmc8380_3_gpios 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&pm_sde7_main_3p3_en>; + pinctrl-names = "default"; + }; + + vreg_pcie_3v3_aux: regulator-pcie-3v3-aux { + compatible = "regulator-fixed"; + + regulator-name = "VREG_PCIE_3P3_AUX"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmc8380_3_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&pm_sde7_aux_3p3_en>; + pinctrl-names = "default"; + }; + /* Left unused as the retimer is not used on this board. */ vreg_rtmr0_1p15: regulator-rtmr0-1p15 { compatible = "regulator-fixed"; @@ -344,6 +440,26 @@ regulator-boot-on; }; + regulator_usb3_vbus: regulator-usb3-vbus { + compatible = "regulator-fixed"; + regulator-name = "USB3_VBUS"; + gpio = <&pm8550ve_9_gpios 4 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&usb3_en>; + pinctrl-names = "default"; + enable-active-high; + regulator-always-on; + }; + + regulator_usb6_vbus: regulator-usb6-vbus { + compatible = "regulator-fixed"; + regulator-name = "USB6_VBUS"; + gpio = <&pm8550ve_9_gpios 5 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&usb6_en>; + pinctrl-names = "default"; + enable-active-high; + regulator-always-on; + }; + vph_pwr: regulator-vph-pwr { compatible = "regulator-fixed"; @@ -534,7 +650,7 @@ bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&wcn_bt_en>; + pinctrl-0 = <&wcn_bt_en>, <&wcn_wlan_en>; pinctrl-names = "default"; regulators { @@ -819,6 +935,8 @@ aux-bus { panel { compatible = "edp-panel"; + + backlight = <&backlight>; power-supply = <&vreg_edp_3p3>; port { @@ -844,10 +962,53 @@ status = "okay"; }; +&pcie3_port0 { + vpcie12v-supply = <&vreg_pcie_12v>; + vpcie3v3-supply = <&vreg_pcie_3v3>; + vpcie3v3aux-supply = <&vreg_pcie_3v3_aux>; + + reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; +}; + +&pcie4_port0 { + reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; +}; + +&pcie5 { + vddpe-3v3-supply = <&vreg_wwan>; +}; + +&pcie5_port0 { + reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; +}; + &pcie6a { vddpe-3v3-supply = <&vreg_nvme>; }; +&pcie6a_port0 { + reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; +}; + &pm8550_gpios { rtmr0_default: rtmr0-reset-n-active-state { pins = "gpio10"; @@ -868,6 +1029,17 @@ }; }; +&pm8550ve_8_gpios { + pcie_x8_12v: pcie-12v-default-state { + pins = "gpio8"; + function = "normal"; + output-enable; + output-high; + bias-pull-down; + power-source = <0>; + }; +}; + &pm8550ve_9_gpios { usb0_1p8_reg_en: usb0-1p8-reg-en-state { pins = "gpio8"; @@ -877,6 +1049,77 @@ input-disable; output-enable; }; + + usb3_en: usb3-en-state { + pins = "gpio4"; + function = "normal"; + qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>; + output-enable; + power-source = <0>; + }; + + usb6_en: usb6-en-state { + pins = "gpio5"; + function = "normal"; + qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>; + output-enable; + power-source = <0>; + }; +}; + +&pm8550_pwm { + status = "okay"; + + multi-led { + color = <LED_COLOR_ID_MULTI>; + function = LED_FUNCTION_STATUS; + + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = <LED_COLOR_ID_RED>; + }; + + led@2 { + reg = <2>; + color = <LED_COLOR_ID_GREEN>; + }; + }; +}; + +&pmc8380_3_gpios { + edp_bl_en: edp-bl-en-state { + pins = "gpio4"; + function = "normal"; + power-source = <1>; + input-disable; + output-enable; + }; + + edp_bl_reg_en: edp-bl-reg-en-state { + pins = "gpio10"; + function = "normal"; + }; +}; + +&pmc8380_3_gpios { + pm_sde7_aux_3p3_en: pcie-aux-3p3-default-state { + pins = "gpio8"; + function = "normal"; + output-enable; + bias-pull-down; + power-source = <0>; + }; + + pm_sde7_main_3p3_en: pcie-main-3p3-default-state { + pins = "gpio6"; + function = "normal"; + output-enable; + bias-pull-down; + power-source = <0>; + }; }; &pmc8380_5_gpios { @@ -890,6 +1133,17 @@ }; }; +&pmk8550_gpios { + edp_bl_pwm: edp-bl-pwm-state { + pins = "gpio5"; + function = "func3"; + }; +}; + +&pmk8550_pwm { + status = "okay"; +}; + &smb2360_0 { status = "okay"; }; @@ -917,6 +1171,16 @@ vdd3-supply = <&vreg_l8b_3p0>; }; +&spi11 { + status = "okay"; + + tpm@0 { + compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi"; + reg = <0>; + spi-max-frequency = <20000000>; + }; +}; + &swr0 { status = "okay"; @@ -1143,6 +1407,13 @@ bias-disable; }; + wcn_wlan_en: wcn-wlan-en-state { + pins = "gpio117"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + wwan_sw_en: wwan-sw-en-state { pins = "gpio221"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi index 4a69852e9176..b8e3e04a6fbd 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi @@ -390,10 +390,21 @@ firmware-name = "qcom/x1e80100/gen70500_zap.mbn"; }; -&pcie4 { - perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; +&pcie3 { + pinctrl-0 = <&pcie3_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie3_phy { + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + status = "okay"; +}; + +&pcie4 { pinctrl-0 = <&pcie4_default>; pinctrl-names = "default"; @@ -407,10 +418,21 @@ status = "okay"; }; -&pcie6a { - perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; +&pcie5 { + pinctrl-0 = <&pcie5_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie5_phy { + vdda-phy-supply = <&vreg_l3i_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + status = "okay"; +}; + +&pcie6a { pinctrl-0 = <&pcie6a_default>; pinctrl-names = "default"; @@ -453,6 +475,29 @@ &tlmm { gpio-reserved-ranges = <34 2>; /* TPM LP & INT */ + pcie3_default: pcie3-default-state { + clkreq-n-pins { + pins = "gpio144"; + function = "pcie3_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio143"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio145"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + pcie4_default: pcie4-default-state { clkreq-n-pins { pins = "gpio147"; @@ -476,6 +521,29 @@ }; }; + pcie5_default: pcie5-default-state { + clkreq-n-pins { + pins = "gpio150"; + function = "pcie5_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio149"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio151"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + pcie6a_default: pcie6a-default-state { clkreq-n-pins { pins = "gpio153"; diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index a17900eacb20..db65c392e618 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -791,8 +791,8 @@ #address-cells = <2>; #size-cells = <2>; - dma-ranges = <0 0 0 0 0x10 0>; - ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x100 0>; + ranges = <0 0 0 0 0x100 0>; gcc: clock-controller@100000 { compatible = "qcom,x1e80100-gcc"; @@ -834,6 +834,9 @@ <0>, <0>, <0>, + <0>, + <0>, + <0>, <0>; power-domains = <&rpmhpd RPMHPD_CX>; @@ -2937,7 +2940,7 @@ reg = <0 0x00fda000 0 0x4000>; clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, - <&rpmhcc RPMH_CXO_CLK>, + <&tcsr TCSR_USB4_1_CLKREF_EN>, <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; clock-names = "aux", @@ -3008,7 +3011,7 @@ reg = <0 0x00fdf000 0 0x4000>; clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>, - <&rpmhcc RPMH_CXO_CLK>, + <&tcsr TCSR_USB4_2_CLKREF_EN>, <&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>, <&gcc GCC_USB3_TERT_PHY_PIPE_CLK>; clock-names = "aux", @@ -3060,6 +3063,11 @@ }; }; + rng: rng@10c3000 { + compatible = "qcom,x1e80100-trng", "qcom,trng"; + reg = <0x0 0x010c3000 0x0 0x1000>; + }; + cnoc_main: interconnect@1500000 { compatible = "qcom,x1e80100-cnoc-main"; reg = <0 0x01500000 0 0x14400>; @@ -3161,7 +3169,7 @@ mmss_noc: interconnect@1780000 { compatible = "qcom,x1e80100-mmss-noc"; - reg = <0 0x01780000 0 0x5B800>; + reg = <0 0x01780000 0 0x5b800>; qcom,bcm-voters = <&apps_bcm_voter>; @@ -3253,9 +3261,6 @@ power-domains = <&gcc GCC_PCIE_3_GDSC>; - phys = <&pcie3_phy>; - phy-names = "pciephy"; - eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555 0x5555 0x5555 0x5555 0x5555>; eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55>; @@ -3396,12 +3401,14 @@ }; }; - pcie3_port: pcie@0 { + pcie3_port0: pcie@0 { device_type = "pci"; compatible = "pciclass,0604"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; + phys = <&pcie3_phy>; + #address-cells = <3>; #size-cells = <2>; ranges; @@ -3530,13 +3537,22 @@ power-domains = <&gcc GCC_PCIE_6A_GDSC>; required-opps = <&rpmhpd_opp_nom>; - phys = <&pcie6a_phy>; - phy-names = "pciephy"; - eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; status = "disabled"; + + pcie6a_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + phys = <&pcie6a_phy>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie6a_phy: phy@1bfc000 { @@ -3662,12 +3678,21 @@ power-domains = <&gcc GCC_PCIE_5_GDSC>; required-opps = <&rpmhpd_opp_nom>; - phys = <&pcie5_phy>; - phy-names = "pciephy"; - eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; status = "disabled"; + + pcie5_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + phys = <&pcie5_phy>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie5_phy: phy@1c06000 { @@ -3792,9 +3817,6 @@ power-domains = <&gcc GCC_PCIE_4_GDSC>; required-opps = <&rpmhpd_opp_nom>; - phys = <&pcie4_phy>; - phy-names = "pciephy"; - eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; status = "disabled"; @@ -3804,6 +3826,8 @@ reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; + phys = <&pcie4_phy>; + #address-cells = <3>; #size-cells = <2>; ranges; @@ -3845,6 +3869,32 @@ status = "disabled"; }; + cryptobam: dma-controller@1dc4000 { + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg = <0x0 0x01dc4000 0x0 0x28000>; + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + iommus = <&apps_smmu 0x480 0x0>, + <&apps_smmu 0x481 0x0>; + qcom,ee = <0>; + qcom,controlled-remotely; + num-channels = <20>; + qcom,num-ees = <4>; + }; + + crypto: crypto@1dfa000 { + compatible = "qcom,x1e80100-qce", "qcom,sm8150-qce", "qcom,qce"; + reg = <0x0 0x01dfa000 0x0 0x6000>; + dmas = <&cryptobam 4>, <&cryptobam 5>; + dma-names = "rx", + "tx"; + iommus = <&apps_smmu 0x480 0x0>, + <&apps_smmu 0x481 0x0>; + interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "memory"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0 0x01f40000 0 0x20000>; @@ -4136,7 +4186,7 @@ nsp_noc: interconnect@320c0000 { compatible = "qcom,x1e80100-nsp-noc"; - reg = <0 0x320C0000 0 0xe080>; + reg = <0 0x320c0000 0 0xe080>; qcom,bcm-voters = <&apps_bcm_voter>; @@ -4647,7 +4697,7 @@ lpass_lpicx_noc: interconnect@7430000 { compatible = "qcom,x1e80100-lpass-lpicx-noc"; - reg = <0 0x07430000 0 0x3A200>; + reg = <0 0x07430000 0 0x3a200>; qcom,bcm-voters = <&apps_bcm_voter>; @@ -5579,6 +5629,7 @@ phy-names = "dp"; #sound-dai-cells = <0>; + sound-name-prefix = "DisplayPort0"; status = "disabled"; @@ -5667,6 +5718,7 @@ phy-names = "dp"; #sound-dai-cells = <0>; + sound-name-prefix = "DisplayPort1"; status = "disabled"; @@ -5755,6 +5807,7 @@ phy-names = "dp"; #sound-dai-cells = <0>; + sound-name-prefix = "DisplayPort2"; status = "disabled"; @@ -5838,6 +5891,7 @@ phy-names = "dp"; #sound-dai-cells = <0>; + sound-name-prefix = "DisplayPort3"; status = "disabled"; @@ -5896,9 +5950,11 @@ <0 0x0aec2000 0 0x1c8>; clocks = <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>; + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&tcsr TCSR_EDP_CLKREF_EN>; clock-names = "aux", - "cfg_ahb"; + "cfg_ahb", + "ref"; power-domains = <&rpmhpd RPMHPD_MX>; @@ -5916,9 +5972,11 @@ <0 0x0aec5000 0 0x1c8>; clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>; + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&tcsr TCSR_EDP_CLKREF_EN>; clock-names = "aux", - "cfg_ahb"; + "cfg_ahb", + "ref"; power-domains = <&rpmhpd RPMHPD_MX>; @@ -8302,6 +8360,14 @@ }; }; + apss_watchdog: watchdog@17410000 { + compatible = "qcom,apss-wdt-x1e80100", "qcom,kpss-wdt"; + reg = <0x0 0x17410000 0x0 0x1000>; + clocks = <&sleep_clk>; + interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; + status = "reserved"; /* Reserved by Gunyah */ + }; + cpucp_mbox: mailbox@17430000 { compatible = "qcom,x1e80100-cpucp-mbox"; reg = <0 0x17430000 0 0x10000>, <0 0x18830000 0 0x10000>; diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi index f024b3cba33f..6f8004a22a1f 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -340,7 +340,7 @@ }; tsens: thermal-sensor@4a9000 { - compatible = "qcom,ipq5018-tsens", "qcom,tsens-v1"; + compatible = "qcom,ipq5018-tsens"; reg = <0x004a9000 0x1000>, <0x004a8000 0x1000>; @@ -571,8 +571,12 @@ compatible = "qcom,ipq5018-dwc3", "qcom,dwc3"; reg = <0x08af8800 0x400>; - interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hs_phy_irq"; + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq"; clocks = <&gcc GCC_USB0_MASTER_CLK>, <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 86c9cb9fffc9..d7278f2137ac 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -765,8 +765,14 @@ assigned-clock-rates = <200000000>, <24000000>; - interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "pwr_event"; + interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "qusb2_phy", + "dm_hs_phy_irq", + "dp_hs_phy_irq"; resets = <&gcc GCC_USB_BCR>; status = "disabled"; diff --git a/arch/arm64/boot/dts/qcom/kaanapali-ipcc.h b/arch/arm64/boot/dts/qcom/kaanapali-ipcc.h new file mode 100644 index 000000000000..125375a4aac0 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/kaanapali-ipcc.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __DTS_KAANAPALI_MAILBOX_IPCC_H +#define __DTS_KAANAPALI_MAILBOX_IPCC_H + +/* Physical client IDs */ +#define IPCC_MPROC_AOP 0 +#define IPCC_MPROC_TZ 1 +#define IPCC_MPROC_MPSS 2 +#define IPCC_MPROC_LPASS 3 +#define IPCC_MPROC_SDC 4 +#define IPCC_MPROC_CDSP 5 +#define IPCC_MPROC_APSS 6 +#define IPCC_MPROC_SOCCP 13 +#define IPCC_MPROC_DCP 14 +#define IPCC_MPROC_SPSS 15 +#define IPCC_MPROC_TME 16 +#define IPCC_MPROC_WPSS 17 + +#define IPCC_COMPUTE_L0_CDSP 2 +#define IPCC_COMPUTE_L0_APSS 3 +#define IPCC_COMPUTE_L0_GPU 4 +#define IPCC_COMPUTE_L0_CVP 8 +#define IPCC_COMPUTE_L0_CAM 9 +#define IPCC_COMPUTE_L0_CAM1 10 +#define IPCC_COMPUTE_L0_DCP 11 +#define IPCC_COMPUTE_L0_VPU 12 +#define IPCC_COMPUTE_L0_SOCCP 16 + +#define IPCC_COMPUTE_L1_CDSP 2 +#define IPCC_COMPUTE_L1_APSS 3 +#define IPCC_COMPUTE_L1_GPU 4 +#define IPCC_COMPUTE_L1_CVP 8 +#define IPCC_COMPUTE_L1_CAM 9 +#define IPCC_COMPUTE_L1_CAM1 10 +#define IPCC_COMPUTE_L1_DCP 11 +#define IPCC_COMPUTE_L1_VPU 12 +#define IPCC_COMPUTE_L1_SOCCP 16 + +#define IPCC_PERIPH_CDSP 2 +#define IPCC_PERIPH_APSS 3 +#define IPCC_PERIPH_PCIE0 4 +#define IPCC_PERIPH_PCIE1 5 + +#define IPCC_FENCE_CDSP 2 +#define IPCC_FENCE_APSS 3 +#define IPCC_FENCE_GPU 4 +#define IPCC_FENCE_CVP 8 +#define IPCC_FENCE_CAM 8 +#define IPCC_FENCE_CAM1 10 +#define IPCC_FENCE_DCP 11 +#define IPCC_FENCE_VPU 20 +#define IPCC_FENCE_SOCCP 24 + +#endif diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts new file mode 100644 index 000000000000..32a082598434 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts @@ -0,0 +1,754 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include "kaanapali.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kaanapali MTP"; + compatible = "qcom,kaanapali-mtp", "qcom,kaanapali"; + chassis-type = "handset"; + + aliases { + serial0 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <76800000>; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32764>; + #clock-cells = <0>; + }; + + bi_tcxo_div2: bi-tcxo-div2-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-mult = <1>; + clock-div = <2>; + }; + + bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + + clocks = <&rpmhcc RPMH_CXO_CLK_A>; + clock-mult = <1>; + clock-div = <2>; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pmh0101-rpmh-regulators"; + qcom,pmic-id = "B_E0"; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <4000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <3552000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name = "vreg_l1b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3048000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + + vreg_l4b_1p8: ldo4 { + regulator-name = "vreg_l4b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + + vreg_l5b_3p1: ldo5 { + regulator-name = "vreg_l5b_3p1"; + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3148000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + + vreg_l7b_1p8: ldo7 { + regulator-name = "vreg_l7b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + + vreg_l8b_1p8: ldo8 { + regulator-name = "vreg_l8b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l10b_1p8: ldo10 { + regulator-name = "vreg_l10b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + + vreg_l11b_1p0: ldo11 { + regulator-name = "vreg_l11b_1p0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1292000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + + vreg_l12b_1p8: ldo12 { + regulator-name = "vreg_l12b_1p8"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + + vreg_l14b_3p2: ldo14 { + regulator-name = "vreg_l14b_3p2"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name = "vreg_l17b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l18b_1p2: ldo18 { + regulator-name = "vreg_l18b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + }; + + regulators-1 { + compatible = "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id = "D_E0"; + + vreg_s10d_1p0: smps10 { + regulator-name = "vreg_s10d_1p0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1d_1p2: ldo1 { + regulator-name = "vreg_l1d_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1256000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + + vreg_l2d_0p9: ldo2 { + regulator-name = "vreg_l2d_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <958000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + + vreg_l3d_0p8: ldo3 { + regulator-name = "vreg_l3d_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + + vreg_l4d_1p2: ldo4 { + regulator-name = "vreg_l4d_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + }; + + regulators-2 { + compatible = "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id = "F_E0"; + + vreg_s6f_0p5: smps6 { + regulator-name = "vreg_s6f_0p5"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <570000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s7f_1p2: smps7 { + regulator-name = "vreg_s7f_1p2"; + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1372000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s8f_1p8: smps8 { + regulator-name = "vreg_s8f_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1f_1p2: ldo1 { + regulator-name = "vreg_l1f_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + + vreg_l2f_1p2: ldo2 { + regulator-name = "vreg_l2f_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + + vreg_l3f_0p8: ldo3 { + regulator-name = "vreg_l3f_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <936000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + + vreg_l4f_0p8: ldo4 { + regulator-name = "vreg_l4f_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + }; + + regulators-3 { + compatible = "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id = "G_E0"; + + vreg_s7g_0p9: smps7 { + regulator-name = "vreg_s7g_0p9"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s9g_1p0: smps9 { + regulator-name = "vreg_s9g_1p0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1g_1p2: ldo1 { + regulator-name = "vreg_l1g_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + + vreg_l2g_1p8: ldo2 { + regulator-name = "vreg_l2g_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + + vreg_l3g_1p2: ldo3 { + regulator-name = "vreg_l3g_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + + vreg_l4g_0p9: ldo4 { + regulator-name = "vreg_l4g_0p9"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + }; + + regulators-4 { + compatible = "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id = "I_E0"; + + vreg_s7i_0p9: smps7 { + regulator-name = "vreg_s7i_0p9"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <972000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2i_1p2: ldo2 { + regulator-name = "vreg_l2i_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + + vreg_l3i_0p8: ldo3 { + regulator-name = "vreg_l3i_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + }; + + regulators-5 { + compatible = "qcom,pmh0104-rpmh-regulators"; + qcom,pmic-id = "J_E1"; + + vreg_s1j_0p8: smps1 { + regulator-name = "vreg_s1j_0p8"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s2j_0p8: smps2 { + regulator-name = "vreg_s2j_0p8"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s3j_1p2: smps3 { + regulator-name = "vreg_s3j_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s4j_0p7: smps4 { + regulator-name = "vreg_s4j_0p7"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-6 { + compatible = "qcom,pmr735d-rpmh-regulators"; + qcom,pmic-id = "K_E1"; + + vreg_l1k_0p8: ldo1 { + regulator-name = "vreg_l1k_0p8"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2k_0p7: ldo2 { + regulator-name = "vreg_l2k_0p7"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3k_1p2: ldo3 { + regulator-name = "vreg_l3k_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4k_1p0: ldo4 { + regulator-name = "vreg_l4k_1p0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5k_0p7: ldo5 { + regulator-name = "vreg_l5k_0p7"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6k_1p7: ldo6 { + regulator-name = "vreg_l6k_1p7"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7k_0p7: ldo7 { + regulator-name = "vreg_l7k_0p7"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <848000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-7 { + compatible = "qcom,pm8010-rpmh-regulators"; + qcom,pmic-id = "M_E1"; + + vreg_l1m_1p0: ldo1 { + regulator-name = "vreg_l1m_1p0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2m_1p0: ldo2 { + regulator-name = "vreg_l2m_1p0"; + regulator-min-microvolt = <1096000>; + regulator-max-microvolt = <1104000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3m_2p8: ldo3 { + regulator-name = "vreg_l3m_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2900000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4m_2p2: ldo4 { + regulator-name = "vreg_l4m_2p2"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6m_2p8: ldo6 { + regulator-name = "vreg_l6m_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7m_2p8: ldo7 { + regulator-name = "vreg_l7m_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-8 { + compatible = "qcom,pm8010-rpmh-regulators"; + qcom,pmic-id = "N_E1"; + + vreg_l1n_1p1: ldo1 { + regulator-name = "vreg_l1n_1p1"; + regulator-min-microvolt = <1096000>; + regulator-max-microvolt = <1104000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2n_1p2: ldo2 { + regulator-name = "vreg_l2n_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3n_1p8: ldo3 { + regulator-name = "vreg_l3n_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4n_1p8: ldo4 { + regulator-name = "vreg_l4n_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5n_2p8: ldo5 { + regulator-name = "vreg_l5n_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6n_2p8: ldo6 { + regulator-name = "vreg_l6n_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7n_3p3: ldo7 { + regulator-name = "vreg_l7n_3p3"; + regulator-min-microvolt = <3304000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; +}; + +&pcie0 { + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l3i_0p8>; + vdda-pll-supply = <&vreg_l1d_1p2>; + + status = "okay"; +}; + +&pcie_port0 { + wake-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>; + reset-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>; +}; + +&sdhc_2 { + cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>; + + vmmc-supply = <&vreg_l9b_2p9>; + vqmmc-supply = <&vreg_l8b_1p8>; + + bus-width = <4>; + no-sdio; + no-mmc; + + pinctrl-0 = <&sdc2_default>; + pinctrl-1 = <&sdc2_sleep>; + pinctrl-names = "default", "sleep"; + + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <36 4>, /* NFC eSE SPI */ + <74 1>, /* eSE */ + <119 2>, /* SoCCP */ + <144 4>; /* CXM UART */ + + pcie0_default_state: pcie0-default-state { + perst-n-pins { + pins = "gpio102"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + clkreq-n-pins { + pins = "gpio103"; + function = "pcie0_clk_req_n"; + drive-strength = <2>; + bias-pull-up; + }; + + wake-n-pins { + pins = "gpio104"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; +}; + +&uart7 { + status = "okay"; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 217 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l17b_2p5>; + vcc-max-microamp = <1200000>; + vccq-supply = <&vreg_l4d_1p2>; + vccq-max-microamp = <1200000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l4g_0p9>; + vdda-pll-supply = <&vreg_l1d_1p2>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts b/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts new file mode 100644 index 000000000000..66b423a497b3 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts @@ -0,0 +1,712 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include "kaanapali.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kaanapali QRD"; + compatible = "qcom,kaanapali-qrd", "qcom,kaanapali"; + chassis-type = "handset"; + + aliases { + serial0 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <76800000>; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32764>; + #clock-cells = <0>; + }; + + bi_tcxo_div2: bi-tcxo-div2-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-mult = <1>; + clock-div = <2>; + }; + + bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + + clocks = <&rpmhcc RPMH_CXO_CLK_A>; + clock-mult = <1>; + clock-div = <2>; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pmh0101-rpmh-regulators"; + qcom,pmic-id = "B_E0"; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <4000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <3552000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name = "vreg_l1b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3048000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + + vreg_l4b_1p8: ldo4 { + regulator-name = "vreg_l4b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + + vreg_l5b_3p1: ldo5 { + regulator-name = "vreg_l5b_3p1"; + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3148000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + + vreg_l7b_1p8: ldo7 { + regulator-name = "vreg_l7b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + + vreg_l8b_1p8: ldo8 { + regulator-name = "vreg_l8b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l10b_1p8: ldo10 { + regulator-name = "vreg_l10b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + + vreg_l11b_1p0: ldo11 { + regulator-name = "vreg_l11b_1p0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1292000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + + vreg_l12b_1p8: ldo12 { + regulator-name = "vreg_l12b_1p8"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + + vreg_l14b_3p2: ldo14 { + regulator-name = "vreg_l14b_3p2"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name = "vreg_l17b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l18b_1p2: ldo18 { + regulator-name = "vreg_l18b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + }; + + regulators-1 { + compatible = "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id = "D_E0"; + + vreg_s10d_1p0: smps10 { + regulator-name = "vreg_s10d_1p0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1d_1p2: ldo1 { + regulator-name = "vreg_l1d_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1256000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + + vreg_l2d_0p9: ldo2 { + regulator-name = "vreg_l2d_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <958000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + + vreg_l3d_0p8: ldo3 { + regulator-name = "vreg_l3d_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + + vreg_l4d_1p2: ldo4 { + regulator-name = "vreg_l4d_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + }; + + regulators-2 { + compatible = "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id = "F_E0"; + + vreg_s6f_0p5: smps6 { + regulator-name = "vreg_s6f_0p5"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <570000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s7f_1p2: smps7 { + regulator-name = "vreg_s7f_1p2"; + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1372000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s8f_1p8: smps8 { + regulator-name = "vreg_s8f_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1f_1p2: ldo1 { + regulator-name = "vreg_l1f_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + + vreg_l2f_1p2: ldo2 { + regulator-name = "vreg_l2f_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + + vreg_l3f_0p8: ldo3 { + regulator-name = "vreg_l3f_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <936000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + + vreg_l4f_0p8: ldo4 { + regulator-name = "vreg_l4f_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + }; + + regulators-3 { + compatible = "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id = "G_E0"; + + vreg_s7g_0p9: smps7 { + regulator-name = "vreg_s7g_0p9"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s9g_1p0: smps9 { + regulator-name = "vreg_s9g_1p0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1g_1p2: ldo1 { + regulator-name = "vreg_l1g_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + + vreg_l2g_1p8: ldo2 { + regulator-name = "vreg_l2g_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + + vreg_l3g_1p2: ldo3 { + regulator-name = "vreg_l3g_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + + vreg_l4g_0p9: ldo4 { + regulator-name = "vreg_l4g_0p9"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + }; + + regulators-4 { + compatible = "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id = "I_E0"; + + vreg_s7i_0p9: smps7 { + regulator-name = "vreg_s7i_0p9"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <972000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2i_1p2: ldo2 { + regulator-name = "vreg_l2i_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + + vreg_l3i_0p8: ldo3 { + regulator-name = "vreg_l3i_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_AUTO>; + }; + }; + + regulators-5 { + compatible = "qcom,pmh0104-rpmh-regulators"; + qcom,pmic-id = "J_E1"; + + vreg_s1j_0p8: smps1 { + regulator-name = "vreg_s1j_0p8"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s2j_0p8: smps2 { + regulator-name = "vreg_s2j_0p8"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s3j_1p2: smps3 { + regulator-name = "vreg_s3j_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s4j_0p7: smps4 { + regulator-name = "vreg_s4j_0p7"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-6 { + compatible = "qcom,pmr735d-rpmh-regulators"; + qcom,pmic-id = "K_E1"; + + vreg_l1k_0p8: ldo1 { + regulator-name = "vreg_l1k_0p8"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2k_0p7: ldo2 { + regulator-name = "vreg_l2k_0p7"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3k_1p2: ldo3 { + regulator-name = "vreg_l3k_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4k_1p0: ldo4 { + regulator-name = "vreg_l4k_1p0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5k_0p7: ldo5 { + regulator-name = "vreg_l5k_0p7"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6k_1p7: ldo6 { + regulator-name = "vreg_l6k_1p7"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7k_0p7: ldo7 { + regulator-name = "vreg_l7k_0p7"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <848000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-7 { + compatible = "qcom,pm8010-rpmh-regulators"; + qcom,pmic-id = "M_E1"; + + vreg_l1m_1p0: ldo1 { + regulator-name = "vreg_l1m_1p0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2m_1p0: ldo2 { + regulator-name = "vreg_l2m_1p0"; + regulator-min-microvolt = <1096000>; + regulator-max-microvolt = <1104000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3m_2p8: ldo3 { + regulator-name = "vreg_l3m_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2900000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4m_2p2: ldo4 { + regulator-name = "vreg_l4m_2p2"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6m_2p8: ldo6 { + regulator-name = "vreg_l6m_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7m_2p8: ldo7 { + regulator-name = "vreg_l7m_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-8 { + compatible = "qcom,pm8010-rpmh-regulators"; + qcom,pmic-id = "N_E1"; + + vreg_l1n_1p1: ldo1 { + regulator-name = "vreg_l1n_1p1"; + regulator-min-microvolt = <1096000>; + regulator-max-microvolt = <1104000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2n_1p2: ldo2 { + regulator-name = "vreg_l2n_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3n_1p8: ldo3 { + regulator-name = "vreg_l3n_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4n_1p8: ldo4 { + regulator-name = "vreg_l4n_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5n_2p8: ldo5 { + regulator-name = "vreg_l5n_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6n_2p8: ldo6 { + regulator-name = "vreg_l6n_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7n_3p3: ldo7 { + regulator-name = "vreg_l7n_3p3"; + regulator-min-microvolt = <3304000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; +}; + +&sdhc_2 { + cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>; + + vmmc-supply = <&vreg_l9b_2p9>; + vqmmc-supply = <&vreg_l8b_1p8>; + + bus-width = <4>; + no-sdio; + no-mmc; + + pinctrl-0 = <&sdc2_default>; + pinctrl-1 = <&sdc2_sleep>; + pinctrl-names = "default", "sleep"; + + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <36 4>, /* NFC eSE SPI */ + <74 1>, /* eSE */ + <119 2>, /* SoCCP */ + <144 4>; /* CXM UART */ +}; + +&uart7 { + status = "okay"; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 217 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l17b_2p5>; + vcc-max-microamp = <1200000>; + vccq-supply = <&vreg_l4d_1p2>; + vccq-max-microamp = <1200000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l4g_0p9>; + vdda-pll-supply = <&vreg_l1d_1p2>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi new file mode 100644 index 000000000000..9ef57ad0ca71 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -0,0 +1,1606 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include <dt-bindings/clock/qcom,kaanapali-gcc.h> +#include <dt-bindings/clock/qcom,rpmh.h> +#include <dt-bindings/clock/qcom,sm8750-tcsr.h> +#include <dt-bindings/firmware/qcom,scm.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interconnect/qcom,icc.h> +#include <dt-bindings/interconnect/qcom,kaanapali-rpmh.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/mailbox/qcom-ipcc.h> +#include <dt-bindings/phy/phy-qcom-qmp.h> +#include <dt-bindings/power/qcom-rpmpd.h> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include <dt-bindings/soc/qcom,rpmh-rsc.h> + +#include "kaanapali-ipcc.h" + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&l2_0>; + power-domains = <&cpu_pd0>; + power-domain-names = "psci"; + clocks = <&pdp_scmi_perf 0>; + + l2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&l2_0>; + power-domains = <&cpu_pd1>; + power-domain-names = "psci"; + clocks = <&pdp_scmi_perf 0>; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x200>; + enable-method = "psci"; + next-level-cache = <&l2_0>; + power-domains = <&cpu_pd2>; + power-domain-names = "psci"; + clocks = <&pdp_scmi_perf 0>; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x300>; + enable-method = "psci"; + next-level-cache = <&l2_0>; + power-domains = <&cpu_pd3>; + power-domain-names = "psci"; + clocks = <&pdp_scmi_perf 0>; + }; + + cpu4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x400>; + enable-method = "psci"; + next-level-cache = <&l2_0>; + power-domains = <&cpu_pd4>; + power-domain-names = "psci"; + clocks = <&pdp_scmi_perf 0>; + }; + + cpu5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x500>; + enable-method = "psci"; + next-level-cache = <&l2_0>; + power-domains = <&cpu_pd5>; + power-domain-names = "psci"; + clocks = <&pdp_scmi_perf 0>; + }; + + cpu6: cpu@10000 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x10000>; + enable-method = "psci"; + next-level-cache = <&l2_1>; + power-domains = <&cpu_pd6>; + power-domain-names = "psci"; + clocks = <&pdp_scmi_perf 1>; + + l2_1: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + }; + + cpu7: cpu@10100 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x10100>; + enable-method = "psci"; + next-level-cache = <&l2_1>; + power-domains = <&cpu_pd7>; + power-domain-names = "psci"; + clocks = <&pdp_scmi_perf 1>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + + core4 { + cpu = <&cpu4>; + }; + + core5 { + cpu = <&cpu5>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu6>; + }; + + core1 { + cpu = <&cpu7>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + cluster0_c4: cpu-sleep-0 { + compatible = "arm,idle-state"; + idle-state-name = "retention"; + arm,psci-suspend-param = <0x00000004>; + entry-latency-us = <93>; + exit-latency-us = <129>; + min-residency-us = <560>; + }; + + cluster1_c4: cpu-sleep-1 { + compatible = "arm,idle-state"; + idle-state-name = "retention"; + arm,psci-suspend-param = <0x00000004>; + entry-latency-us = <172>; + exit-latency-us = <130>; + min-residency-us = <686>; + }; + }; + + domain-idle-states { + cluster_cl5: cluster-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x01000054>; + entry-latency-us = <2150>; + exit-latency-us = <1983>; + min-residency-us = <9144>; + }; + + domain_ss3: domain-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x0200c354>; + entry-latency-us = <2800>; + exit-latency-us = <4400>; + min-residency-us = <10150>; + }; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-kaanapali", "qcom,scm"; + qcom,dload-mode = <&tcsr 0x19000>; + interconnects = <&aggre_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + }; + + scmi: scmi { + compatible = "arm,scmi"; + mboxes = <&pdp0_mbox 0>, <&pdp0_mbox 1>; + mbox-names = "tx", "rx"; + shmem = <&pdp_tx>, <&pdp_rx>; + + #address-cells = <1>; + #size-cells = <0>; + + pdp_scmi_perf: protocol@13 { + reg = <0x13>; + #clock-cells = <1>; + }; + }; + }; + + clk_virt: interconnect-0 { + compatible = "qcom,kaanapali-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mc_virt: interconnect-1 { + compatible = "qcom,kaanapali-mc-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + memory@a0000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0x0 0xa0000000 0x0 0x0>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + cpu_pd0: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&cluster0_c4>; + }; + + cpu_pd1: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&cluster0_c4>; + }; + + cpu_pd2: power-domain-cpu2 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&cluster0_c4>; + }; + + cpu_pd3: power-domain-cpu3 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&cluster0_c4>; + }; + + cpu_pd4: power-domain-cpu4 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&cluster0_c4>; + }; + + cpu_pd5: power-domain-cpu5 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&cluster0_c4>; + }; + + cpu_pd6: power-domain-cpu6 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&cluster1_c4>; + }; + + cpu_pd7: power-domain-cpu7 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&cluster1_c4>; + }; + + cluster_pd: power-domain-cluster { + #power-domain-cells = <0>; + domain-idle-states = <&cluster_cl5>; + power-domains = <&system_pd>; + }; + + system_pd: power-domain-system { + #power-domain-cells = <0>; + domain-idle-states = <&domain_ss3>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + pdp_mem: pdp@81300000 { + reg = <0x0 0x81300000 0x0 0x100000>; + no-map; + }; + + aop_cmd_db_mem: aop-cmd-db@81c60000 { + compatible = "qcom,cmd-db"; + reg = <0x0 0x81c60000 0x0 0x20000>; + no-map; + }; + + smem_mem: smem@81d00000 { + compatible = "qcom,smem"; + reg = <0x0 0x81d00000 0x0 0x200000>; + hwlocks = <&tcsr_mutex 3>; + no-map; + }; + + pdp_ns_shared_mem: pdp-ns-shared@81f00000 { + reg = <0x0 0x81f00000 0x0 0x100000>; + no-map; + }; + + dsm_partition_1_mem: dsm-partition-1@84a00000 { + reg = <0x0 0x84a00000 0x0 0x5500000>; + no-map; + }; + + dsm_partition_2_mem: dsm-partition-2@89f00000 { + reg = <0x0 0x89f00000 0x0 0xa80000>; + no-map; + }; + + mpss_mem: mpss@8aa00000 { + reg = <0x0 0x8aa00000 0x0 0xeb00000>; + no-map; + }; + + q6_mpss_dtb_mem: q6-mpss-dtb@99500000 { + reg = <0x0 0x99500000 0x0 0x80000>; + no-map; + }; + + ipa_fw_mem: ipa-fw@99580000 { + reg = <0x0 0x99580000 0x0 0x10000>; + no-map; + }; + + ipa_gsi_mem: ipa-gsi@99590000 { + reg = <0x0 0x99590000 0x0 0xa000>; + no-map; + }; + + gpu_microcode_mem: gpu-microcode@9959a000 { + reg = <0x0 0x9959a000 0x0 0x2000>; + no-map; + }; + + camera_mem: camera@99600000 { + reg = <0x0 0x99600000 0x0 0x800000>; + no-map; + }; + + camera_2_mem: camera-2@99e00000 { + reg = <0x0 0x99e00000 0x0 0x800000>; + no-map; + }; + + video_mem: video@9a600000 { + reg = <0x0 0x9a600000 0x0 0x800000>; + no-map; + }; + + cvp_mem: cvp@9ae00000 { + reg = <0x0 0x9ae00000 0x0 0x700000>; + no-map; + }; + + cdsp_mem: cdsp@9b500000 { + reg = <0x0 0x9b500000 0x0 0x1900000>; + no-map; + }; + + q6_cdsp_dtb_mem: q6-cdsp-dtb@9ce00000 { + reg = <0x0 0x9ce00000 0x0 0x80000>; + no-map; + }; + + soccp_mem: soccp@a03d0000 { + reg = <0x0 0xa03d0000 0x0 0x500000>; + no-map; + }; + + soccp_dtb_mem: soccp-dtb@a08d0000 { + reg = <0x0 0xa08d0000 0x0 0x40000>; + no-map; + }; + + q6_adsp_dtb_mem: q6-adsp-dtb@a1380000 { + reg = <0x0 0xa1380000 0x0 0x80000>; + no-map; + }; + + adspslpi_mem: adspslpi@a1400000 { + reg = <0x0 0xa1400000 0x0 0x4c00000>; + no-map; + }; + + rmtfs_mem: rmtfs@d7c00000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0 0xd7c00000 0x0 0x400000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; + }; + }; + + soc: soc@0 { + compatible = "simple-bus"; + + #address-cells = <2>; + #size-cells = <2>; + dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; + ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; + + gcc: clock-controller@100000 { + compatible = "qcom,kaanapali-gcc"; + reg = <0x0 0x00100000 0x0 0x1f4200>; + + clocks = <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>, + <&pcie0_phy>, + <&ufs_mem_phy 0>, + <&ufs_mem_phy 1>, + <&ufs_mem_phy 2>, + <0>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + qupv3_1: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x00ac0000 0x0 0x2000>; + + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AXI_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + clock-names = "m-ahb", + "s-ahb"; + + iommus = <&apps_smmu 0xa3 0x0>; + + dma-coherent; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + uart7: serial@a9c000 { + compatible = "qcom,geni-debug-uart"; + reg = <0x0 0x00a9c000 0x0 0x4000>; + + interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart7_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; + }; + + ipcc: mailbox@1106000 { + compatible = "qcom,kaanapali-ipcc", "qcom,ipcc"; + reg = <0x0 0x01106000 0x0 0x1000>; + + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <3>; + + #mbox-cells = <2>; + }; + + cnoc_main: interconnect@1500000 { + compatible = "qcom,kaanapali-cnoc-main"; + reg = <0x0 0x01500000 0x0 0x1a080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + config_noc: interconnect@1600000 { + compatible = "qcom,kaanapali-cnoc-cfg"; + reg = <0x0 0x01600000 0x0 0x6200>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + system_noc: interconnect@1680000 { + compatible = "qcom,kaanapali-system-noc"; + reg = <0x0 0x01680000 0x0 0x1f080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + pcie_noc: interconnect@16c0000 { + compatible = "qcom,kaanapali-pcie-anoc"; + reg = <0x0 0x016c0000 0x0 0x11400>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, + <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; + }; + + aggre_noc: interconnect@16e0000 { + compatible = "qcom,kaanapali-aggre-noc"; + reg = <0x0 0x016e0000 0x0 0x42400>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&rpmhcc RPMH_IPA_CLK>; + }; + + mmss_noc: interconnect@1780000 { + compatible = "qcom,kaanapali-mmss-noc"; + reg = <0x0 0x01780000 0x0 0x5b800>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + pcie0: pcie@1c00000 { + device_type = "pci"; + compatible = "qcom,kaanapali-pcie", "qcom,pcie-sm8550"; + reg = <0x0 0x01c00000 0x0 0x3000>, + <0x0 0x40000000 0x0 0xf1d>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x1000>, + <0x0 0x40100000 0x0 0x100000>, + <0x0 0x01c03000 0x0 0x1000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x23d00000>; + + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, + <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ddrss_sf_tbu", + "noc_aggr", + "cnoc_sf_axi"; + + resets = <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; + reset-names = "pci", + "link_down"; + + interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "pcie-mem", + "cpu-pcie"; + + power-domains = <&gcc GCC_PCIE_0_GDSC>; + + eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; + + operating-points-v2 = <&pcie0_opp_table>; + + iommu-map = <0 &apps_smmu 0x1400 0x1>, + <0x100 &apps_smmu 0x1401 0x1>; + + interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 0x7>; + #interrupt-cells = <1>; + + msi-map = <0x0 &gic_its 0x1400 0x1>, + <0x100 &gic_its 0x1401 0x1>; + msi-map-mask = <0xff00>; + max-link-speed = <3>; + linux,pci-domain = <0>; + num-lanes = <2>; + bus-range = <0x00 0xff>; + + dma-coherent; + + status = "disabled"; + + pcie0_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <250000 1>; + }; + + /* GEN 1 x2 and GEN 2 x1 */ + opp-5000000 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + }; + + /* GEN 2 x2 */ + opp-10000000 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1000000 1>; + }; + + /* GEN 3 x1 */ + opp-8000000 { + opp-hz = /bits/ 64 <8000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <984500 1>; + }; + + /* GEN 3 x2 */ + opp-16000000 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <1969000 1>; + }; + }; + + pcie_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + phys = <&pcie0_phy>; + }; + }; + + pcie0_phy: phy@1c06000 { + compatible = "qcom,kaanapali-qmp-gen3x2-pcie-phy"; + reg = <0x0 0x01c06000 0x0 0x2000>; + + clocks = <&gcc GCC_PCIE_0_PHY_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&tcsr TCSR_PCIE_0_CLKREF_EN>, + <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe"; + + assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + resets = <&gcc GCC_PCIE_0_PHY_BCR>, + <&gcc GCC_PCIE_0_NOCSR_COM_PHY_BCR>; + reset-names = "phy", + "phy_nocsr"; + + power-domains = <&gcc GCC_PCIE_0_PHY_GDSC>; + + #clock-cells = <0>; + clock-output-names = "pcie0_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + + ufs_mem_phy: phy@1d80000 { + compatible = "qcom,kaanapali-qmp-ufs-phy", "qcom,sm8750-qmp-ufs-phy"; + reg = <0x0 0x01d80000 0x0 0x2000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&tcsr TCSR_UFS_CLKREF_EN>; + + clock-names = "ref", + "ref_aux", + "qref"; + + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + + power-domains = <&gcc GCC_UFS_MEM_PHY_GDSC>; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + ufs_mem_hc: ufs@1d84000 { + compatible = "qcom,kaanapali-ufshc", + "qcom,ufshc", + "jedec,ufs-2.0"; + reg = <0x0 0x01d84000 0x0 0x3000>; + + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_LN_BB_CLK3>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + + operating-points-v2 = <&ufs_opp_table>; + + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + interconnects = <&aggre_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "ufs-ddr", + "cpu-ufs"; + + power-domains = <&gcc GCC_UFS_PHY_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + iommus = <&apps_smmu 0x60 0x0>; + dma-coherent; + + lanes-per-direction = <2>; + qcom,ice = <&ice>; + + phys = <&ufs_mem_phy>; + phy-names = "ufsphy"; + + #reset-cells = <1>; + + status = "disabled"; + + ufs_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <75000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <100000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-403000000 { + opp-hz = /bits/ 64 <403000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <403000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + ice: crypto@1d88000 { + compatible = "qcom,kaanapali-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg = <0x0 0x01d88000 0x0 0x18000>; + + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x01f40000 0x0 0x20000>; + #hwlock-cells = <1>; + }; + + tcsr: clock-controller@1fc0000 { + compatible = "qcom,kaanapali-tcsr", "syscon"; + reg = <0x0 0x01fc0000 0x0 0x30000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + + #clock-cells = <1>; + #reset-cells = <1>; + }; + + lpass_lpiaon_noc: interconnect@7400000 { + compatible = "qcom,kaanapali-lpass-lpiaon-noc"; + reg = <0x0 0x07400000 0x0 0x19080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + lpass_lpicx_noc: interconnect@7420000 { + compatible = "qcom,kaanapali-lpass-lpicx-noc"; + reg = <0x0 0x07420000 0x0 0x44080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + lpass_ag_noc: interconnect@7f40000 { + compatible = "qcom,kaanapali-lpass-ag-noc"; + reg = <0x0 0x07f40000 0x0 0xe080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + sdhc_2: mmc@8804000 { + compatible = "qcom,kaanapali-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x0 0x08804000 0x0 0x1000>; + + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "core", "xo"; + + interconnects = <&aggre_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "sdhc-ddr", "cpu-sdhc"; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&sdhc2_opp_table>; + + qcom,dll-config = <0x0007442c>; + qcom,ddr-config = <0x80040868>; + + iommus = <&apps_smmu 0x540 0x0>; + dma-coherent; + + resets = <&gcc GCC_SDCC2_BCR>; + status = "disabled"; + + sdhc2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-peak-kBps = <160000 100000>; + opp-avg-kBps = <50000 0>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + opp-peak-kBps = <200000 120000>; + opp-avg-kBps = <104000 0>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,kaanapali-pdc", "qcom,pdc"; + reg = <0x0 0x0b220000 0x0 0x10000>, + <0x0 0x179600f0 0x0 0xf4>; + + qcom,pdc-ranges = <0 745 38>, + <40 785 11>, + <51 527 4>, + <58 534 2>, + <61 537 20>, + <84 559 14>, + <98 609 32>, + <130 717 12>, + <142 251 5>, + <147 796 16>, + <163 783 2>, + <165 531 2>, + <167 536 1>, + <168 557 2>, + <170 415 1>, + <171 438 1>, + <172 579 1>, + <173 703 1>, + <174 708 1>, + <175 714 1>, + <176 68 1>, + <177 86 1>, + <178 96 1>, + <179 249 1>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + aoss_qmp: power-management@c300000 { + compatible = "qcom,kaanapali-aoss-qmp", "qcom,aoss-qmp"; + reg = <0x0 0x0c300000 0x0 0x400>; + + interrupts-extended = <&ipcc IPCC_MPROC_AOP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_MPROC_AOP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + #clock-cells = <0>; + }; + + tlmm: pinctrl@f100000 { + compatible = "qcom,kaanapali-tlmm"; + reg = <0x0 0x0f100000 0x0 0x300000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 218>; + interrupt-controller; + #interrupt-cells = <2>; + wakeup-parent = <&pdc>; + + qup_uart7_default: qup-uart7-state { + /* TX, RX */ + pins = "gpio62", "gpio63"; + function = "qup1_se7"; + drive-strength = <2>; + bias-disable; + }; + + sdc2_default: sdc2-default-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <10>; + bias-pull-up; + }; + + data-pins { + pins = "sdc2_data"; + drive-strength = <10>; + bias-pull-up; + }; + + card-detect-pins { + pins = "gpio55"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + sdc2_sleep: sdc2-sleep-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "sdc2_data"; + drive-strength = <2>; + bias-pull-up; + }; + + card-detect-pins { + pins = "gpio55"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + sram@14680000 { + compatible = "qcom,kaanapali-imem", "mmio-sram"; + reg = <0x0 0x14680000 0x0 0x1000>; + ranges = <0x0 0x0 0x14680000 0x1000>; + + no-memory-wc; + + #address-cells = <1>; + #size-cells = <1>; + + pil-sram@94c { + compatible = "qcom,pil-reloc-info"; + reg = <0x94c 0xc8>; + }; + }; + + apps_smmu: iommu@15000000 { + compatible = "qcom,kaanapali-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x15000000 0x0 0x100000>; + + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>; + + #iommu-cells = <2>; + #global-interrupts = <1>; + + dma-coherent; + }; + + intc: interrupt-controller@17000000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x17000000 0x0 0x10000>, + <0x0 0x17080000 0x0 0x200000>; + + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + + #interrupt-cells = <3>; + interrupt-controller; + + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x40000>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic_its: msi-controller@17040000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x17040000 0x0 0x20000>; + + msi-controller; + #msi-cells = <1>; + }; + }; + + watchdog@17600000 { + compatible = "qcom,apss-wdt-kaanapali", "qcom,kpss-wdt"; + reg = <0x0 0x17600000 0x0 0x1000>; + clocks = <&sleep_clk>; + interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; + }; + + pdp0_mbox: mailbox@17610000 { + compatible = "qcom,kaanapali-cpucp-mbox", "qcom,x1e80100-cpucp-mbox"; + reg = <0x0 0x17610000 0x0 0x8000>, <0x0 0x19980000 0x0 0x8000>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <1>; + }; + + timer@17810000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x17810000 0x0 0x1000>; + + #address-cells = <2>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x0 0x20000000>; + + frame@17811000 { + reg = <0x0 0x17811000 0x1000>, + <0x0 0x17812000 0x1000>; + frame-number = <0>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + }; + + frame@17813000 { + reg = <0x0 0x17813000 0x1000>; + frame-number = <1>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + frame@17815000 { + reg = <0x0 0x17815000 0x1000>; + frame-number = <2>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + frame@17817000 { + reg = <0x0 0x17817000 0x1000>; + frame-number = <3>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + frame@17819000 { + reg = <0x0 0x17819000 0x1000>; + frame-number = <4>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + frame@1781b000 { + reg = <0x0 0x1781b000 0x1000>; + frame-number = <5>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + frame@1781d000 { + reg = <0x0 0x1781d000 0x1000>; + frame-number = <6>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + }; + + apps_rsc: rsc@18900000 { + compatible = "qcom,rpmh-rsc"; + reg = <0x0 0x18900000 0x0 0x10000>, + <0x0 0x18910000 0x0 0x10000>, + <0x0 0x18920000 0x0 0x10000>; + reg-names = "drv-0", + "drv-1", + "drv-2"; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + + power-domains = <&system_pd>; + label = "apps_rsc"; + + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = <ACTIVE_TCS 3>, + <SLEEP_TCS 2>, + <WAKE_TCS 2>, + <CONTROL_TCS 0>; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible = "qcom,kaanapali-rpmh-clk"; + #clock-cells = <1>; + clocks = <&xo_board>; + clock-names = "xo"; + }; + + rpmhpd: power-controller { + compatible = "qcom,kaanapali-rpmhpd"; + + operating-points-v2 = <&rpmhpd_opp_table>; + + #power-domain-cells = <1>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp-16 { + opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; + }; + + rpmhpd_opp_low_svs_d3: opp-50 { + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D3>; + }; + + rpmhpd_opp_low_svs_d2_1: opp-51 { + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2_1>; + }; + + rpmhpd_opp_low_svs_d2: opp-52 { + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; + }; + + rpmhpd_opp_low_svs_d1_1: opp-54 { + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1_1>; + }; + + rpmhpd_opp_low_svs_d1: opp-56 { + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; + }; + + rpmhpd_opp_low_svs_d0: opp-60 { + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; + }; + + rpmhpd_opp_low_svs: opp-64 { + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + }; + + rpmhpd_opp_low_svs_l0: opp-76 { + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L0>; + }; + + rpmhpd_opp_low_svs_l1: opp-80 { + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; + }; + + rpmhpd_opp_low_svs_l2: opp-96 { + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L2>; + }; + + rpmhpd_opp_svs: opp-128 { + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + }; + + rpmhpd_opp_svs_l0: opp-144 { + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; + }; + + rpmhpd_opp_svs_l1: opp-192 { + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + }; + + rpmhpd_opp_svs_l2: opp-224 { + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; + }; + + rpmhpd_opp_nom: opp-256 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; + }; + + rpmhpd_opp_nom_l1: opp-320 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; + }; + + rpmhpd_opp_nom_l2: opp-336 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; + }; + + rpmhpd_opp_turbo: opp-384 { + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; + }; + + rpmhpd_opp_turbo_l0: opp-400 { + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L0>; + }; + + rpmhpd_opp_turbo_l1: opp-416 { + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; + }; + + rpmhpd_opp_turbo_l2: opp-432 { + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L2>; + }; + + rpmhpd_opp_turbo_l3: opp-448 { + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>; + }; + + rpmhpd_opp_turbo_l4: opp-452 { + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>; + }; + + rpmhpd_opp_turbo_l5: opp-456 { + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L5>; + }; + + rpmhpd_opp_super_turbo_no_cpr: opp-480 { + opp-level = <RPMH_REGULATOR_LEVEL_SUPER_TURBO_NO_CPR>; + }; + }; + }; + }; + + nsp_noc: interconnect@260c0000 { + compatible = "qcom,kaanapali-nsp-noc"; + reg = <0x0 0x260c0000 0x0 0x21280>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + /* Cluster 0 */ + pmu@310b3400 { + compatible = "qcom,kaanapali-cpu-bwmon", "qcom,sdm845-bwmon"; + reg = <0x0 0x310b3400 0x0 0x600>; + + interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; + + operating-points-v2 = <&cpu_bwmon_opp_table>; + + cpu_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-0 { + opp-peak-kBps = <2188000>; + }; + + opp-1 { + opp-peak-kBps = <5412000>; + }; + + opp-2 { + opp-peak-kBps = <6220000>; + }; + + opp-3 { + opp-peak-kBps = <6832000>; + }; + + opp-4 { + opp-peak-kBps = <8368000>; + }; + + opp-5 { + opp-peak-kBps = <10944000>; + }; + + opp-6 { + opp-peak-kBps = <12748000>; + }; + + opp-7 { + opp-peak-kBps = <14744000>; + }; + + opp-8 { + opp-peak-kBps = <16896000>; + }; + + opp-9 { + opp-peak-kBps = <19120000>; + }; + + opp-10 { + opp-peak-kBps = <21332000>; + }; + }; + }; + + /* Cluster 1 */ + pmu@310b7400 { + compatible = "qcom,kaanapali-cpu-bwmon", "qcom,sdm845-bwmon"; + reg = <0x0 0x310b7400 0x0 0x600>; + + interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; + + operating-points-v2 = <&cpu_bwmon_opp_table>; + }; + + gem_noc: interconnect@31100000 { + compatible = "qcom,kaanapali-gem-noc"; + reg = <0x0 0x31100000 0x0 0x153080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + system-cache-controller@31800000 { + compatible = "qcom,kaanapali-llcc"; + reg = <0x0 0x31800000 0x0 0x200000>, + <0x0 0x32800000 0x0 0x200000>, + <0x0 0x31c00000 0x0 0x200000>, + <0x0 0x32c00000 0x0 0x200000>, + <0x0 0x34800000 0x0 0x200000>, + <0x0 0x34c00000 0x0 0x200000>; + reg-names = "llcc0_base", + "llcc1_base", + "llcc2_base", + "llcc3_base", + "llcc_broadcast_base", + "llcc_broadcast_and_base"; + + interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; + }; + + sram: sram@81f08000 { + compatible = "mmio-sram"; + reg = <0x0 0x81f08000 0x0 0x200>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x81f08000 0x200>; + + pdp_rx: scp-sram-section@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x80>; + }; + + pdp_tx: scp-sram-section@100 { + compatible = "arm,scmi-shmem"; + reg = <0x100 0x80>; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi index c2ccbb67f800..6079e67ea829 100644 --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi @@ -190,6 +190,11 @@ qcom,client-id = <1>; qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; }; + + adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@9cb80000 { + reg = <0x0 0x9cb80000 0x0 0x800000>; + no-map; + }; }; cpus { @@ -2424,7 +2429,7 @@ status = "disabled"; - pcie@0 { + pcie1_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -2994,6 +2999,11 @@ compatible = "qcom,sc7280-lpass-lpi-pinctrl"; reg = <0 0x033c0000 0x0 0x20000>, <0 0x03550000 0x0 0x10000>; + + clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio"; + gpio-controller; #gpio-cells = <2>; gpio-ranges = <&lpass_tlmm 0 0 15>; @@ -4431,6 +4441,9 @@ qcom,glink-channels = "fastrpcglink-apps-dsp"; label = "adsp"; qcom,non-secure-domain; + memory-region = <&adsp_rpc_remote_heap_mem>; + qcom,vmids = <QCOM_SCM_VMID_LPASS + QCOM_SCM_VMID_ADSP_HEAP>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/qcom/lemans-el2.dtso b/arch/arm64/boot/dts/qcom/lemans-el2.dtso new file mode 100644 index 000000000000..ed615dce6c78 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/lemans-el2.dtso @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/* + * Lemans specific modifications required to boot in EL2. + */ + +/dts-v1/; +/plugin/; + +&iris { + status = "disabled"; +}; + +&remoteproc_adsp { + iommus = <&apps_smmu 0x3000 0x0>; +}; + +&remoteproc_cdsp0 { + iommus = <&apps_smmu 0x21c0 0x0400>; +}; + +&remoteproc_cdsp1 { + iommus = <&apps_smmu 0x29c0 0x0400>; +}; + +&remoteproc_gpdsp0 { + iommus = <&apps_smmu 0x38a0 0x0>; +}; + +&remoteproc_gpdsp1 { + iommus = <&apps_smmu 0x38c0 0x0>; +}; diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts index b40fa203e4a2..90fce947ca7e 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -38,6 +38,36 @@ stdout-path = "serial0:115200n8"; }; + connector-0 { + compatible = "usb-c-connector"; + label = "USB0-Type-C"; + data-role = "dual"; + power-role = "dual"; + + vbus-supply = <&vbus_supply_regulator_0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb0_con_hs_ep: endpoint { + remote-endpoint = <&usb_0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + usb0_con_ss_ep: endpoint { + remote-endpoint = <&hd3ss3220_in_ep>; + }; + }; + }; + }; + edp0-connector { compatible = "dp-connector"; label = "EDP0"; @@ -102,6 +132,15 @@ }; }; + vbus_supply_regulator_0: regulator-vbus-supply-0 { + compatible = "regulator-fixed"; + regulator-name = "vbus_supply_0"; + gpio = <&expander1 2 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + }; + vmmc_sdc: regulator-vmmc-sdc { compatible = "regulator-fixed"; @@ -454,6 +493,51 @@ status = "okay"; }; +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/sa8775p/a663_zap.mbn"; +}; + +&i2c11 { + status = "okay"; + + usb-typec@67 { + compatible = "ti,hd3ss3220"; + reg = <0x67>; + + interrupts-extended = <&pmm8654au_2_gpios 5 IRQ_TYPE_EDGE_FALLING>; + + id-gpios = <&tlmm 50 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&usb_id>, <&usb0_intr_state>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hd3ss3220_in_ep: endpoint { + remote-endpoint = <&usb0_con_ss_ep>; + }; + }; + + port@1 { + reg = <1>; + + hd3ss3220_out_ep: endpoint { + remote-endpoint = <&usb_0_dwc3_ss>; + }; + }; + }; + }; +}; + &i2c18 { status = "okay"; @@ -607,6 +691,16 @@ status = "okay"; }; +&pmm8654au_2_gpios { + usb0_intr_state: usb0-intr-state { + pins = "gpio5"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0>; + }; +}; + &qup_i2c19_default { drive-strength = <2>; bias-pull-up; @@ -683,6 +777,16 @@ clock-frequency = <32768>; }; +&spi16 { + status = "okay"; + + tpm@0 { + compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi"; + reg = <0>; + spi-max-frequency = <20000000>; + }; +}; + &tlmm { ethernet0_default: ethernet0-default-state { ethernet0_mdc: ethernet0-mdc-pins { @@ -746,11 +850,24 @@ }; }; + qup_i2c11_default: qup-i2c11-state { + pins = "gpio48", "gpio49"; + function = "qup1_se4"; + drive-strength = <2>; + bias-pull-up; + }; + sd_cd: sd-cd-state { pins = "gpio36"; function = "gpio"; bias-pull-up; }; + + usb_id: usb-id-state { + pins = "gpio50"; + function = "gpio"; + bias-pull-up; + }; }; &uart10 { @@ -779,11 +896,17 @@ }; &usb_0 { - dr_mode = "peripheral"; - status = "okay"; }; +&usb_0_dwc3_hs { + remote-endpoint = <&usb0_con_hs_ep>; +}; + +&usb_0_dwc3_ss { + remote-endpoint = <&hd3ss3220_out_ep>; +}; + &usb_0_hsphy { vdda-pll-supply = <&vreg_l7a>; vdda18-supply = <&vreg_l6c>; diff --git a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi index c69aa2f41ce2..8fb7d1fc6d56 100644 --- a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi @@ -436,6 +436,14 @@ }; }; +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/sa8775p/a663_zap.mbn"; +}; + &i2c11 { clock-frequency = <400000>; status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 0b154d57ba24..808827b83553 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -21,6 +21,7 @@ #include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/soc/qcom,gpr.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> +#include <dt-bindings/thermal/thermal.h> / { interrupt-parent = <&intc>; @@ -54,6 +55,7 @@ qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&l2_0>; capacity-dmips-mhz = <1024>; + #cooling-cells = <2>; dynamic-power-coefficient = <100>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY @@ -83,6 +85,7 @@ qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&l2_1>; capacity-dmips-mhz = <1024>; + #cooling-cells = <2>; dynamic-power-coefficient = <100>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY @@ -107,6 +110,7 @@ qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&l2_2>; capacity-dmips-mhz = <1024>; + #cooling-cells = <2>; dynamic-power-coefficient = <100>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY @@ -131,6 +135,7 @@ qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&l2_3>; capacity-dmips-mhz = <1024>; + #cooling-cells = <2>; dynamic-power-coefficient = <100>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY @@ -155,6 +160,7 @@ qcom,freq-domain = <&cpufreq_hw 1>; next-level-cache = <&l2_4>; capacity-dmips-mhz = <1024>; + #cooling-cells = <2>; dynamic-power-coefficient = <100>; operating-points-v2 = <&cpu4_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY @@ -185,6 +191,7 @@ qcom,freq-domain = <&cpufreq_hw 1>; next-level-cache = <&l2_5>; capacity-dmips-mhz = <1024>; + #cooling-cells = <2>; dynamic-power-coefficient = <100>; operating-points-v2 = <&cpu4_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY @@ -209,6 +216,7 @@ qcom,freq-domain = <&cpufreq_hw 1>; next-level-cache = <&l2_6>; capacity-dmips-mhz = <1024>; + #cooling-cells = <2>; dynamic-power-coefficient = <100>; operating-points-v2 = <&cpu4_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY @@ -233,6 +241,7 @@ qcom,freq-domain = <&cpufreq_hw 1>; next-level-cache = <&l2_7>; capacity-dmips-mhz = <1024>; + #cooling-cells = <2>; dynamic-power-coefficient = <100>; operating-points-v2 = <&cpu4_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY @@ -518,90 +527,18 @@ }; }; - aggre1_noc: interconnect-aggre1-noc { - compatible = "qcom,sa8775p-aggre1-noc"; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - aggre2_noc: interconnect-aggre2-noc { - compatible = "qcom,sa8775p-aggre2-noc"; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - clk_virt: interconnect-clk-virt { compatible = "qcom,sa8775p-clk-virt"; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; - config_noc: interconnect-config-noc { - compatible = "qcom,sa8775p-config-noc"; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - dc_noc: interconnect-dc-noc { - compatible = "qcom,sa8775p-dc-noc"; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - gem_noc: interconnect-gem-noc { - compatible = "qcom,sa8775p-gem-noc"; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - gpdsp_anoc: interconnect-gpdsp-anoc { - compatible = "qcom,sa8775p-gpdsp-anoc"; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - lpass_ag_noc: interconnect-lpass-ag-noc { - compatible = "qcom,sa8775p-lpass-ag-noc"; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - mc_virt: interconnect-mc-virt { compatible = "qcom,sa8775p-mc-virt"; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; - mmss_noc: interconnect-mmss-noc { - compatible = "qcom,sa8775p-mmss-noc"; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - nspa_noc: interconnect-nspa-noc { - compatible = "qcom,sa8775p-nspa-noc"; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - nspb_noc: interconnect-nspb-noc { - compatible = "qcom,sa8775p-nspb-noc"; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - pcie_anoc: interconnect-pcie-anoc { - compatible = "qcom,sa8775p-pcie-anoc"; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - system_noc: interconnect-system-noc { - compatible = "qcom,sa8775p-system-noc"; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - /* Will be updated by the bootloader. */ memory@80000000 { device_type = "memory"; @@ -1098,6 +1035,18 @@ #mbox-cells = <2>; }; + qfprom: efuse@784000 { + compatible = "qcom,sa8775p-qfprom", "qcom,qfprom"; + reg = <0x0 0x00784000 0x0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + + gpu_speed_bin: gpu_speed_bin@240c { + reg = <0x240c 0x1>; + bits = <0 8>; + }; + }; + gpi_dma2: dma-controller@800000 { compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma"; reg = <0x0 0x00800000 0x0 0x60000>; @@ -2689,6 +2638,62 @@ reg = <0 0x010d2000 0 0x1000>; }; + config_noc: interconnect@14c0000 { + compatible = "qcom,sa8775p-config-noc"; + reg = <0x0 0x014c0000 0x0 0x13080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect@1680000 { + compatible = "qcom,sa8775p-system-noc"; + reg = <0x0 0x01680000 0x0 0x15080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@16c0000 { + compatible = "qcom,sa8775p-aggre1-noc"; + reg = <0x0 0x016c0000 0x0 0x18080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_QUPV3_AXI_CLK>, + <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>; + }; + + aggre2_noc: interconnect@1700000 { + compatible = "qcom,sa8775p-aggre2-noc"; + reg = <0x0 0x01700000 0x0 0x1b080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>, + <&rpmhcc RPMH_IPA_CLK>; + }; + + pcie_anoc: interconnect@1760000 { + compatible = "qcom,sa8775p-pcie-anoc"; + reg = <0x0 0x01760000 0x0 0xc080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + gpdsp_anoc: interconnect@1780000 { + compatible = "qcom,sa8775p-gpdsp-anoc"; + reg = <0x0 0x01780000 0x0 0xe080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mmss_noc: interconnect@17a0000 { + compatible = "qcom,sa8775p-mmss-noc"; + reg = <0x0 0x017a0000 0x0 0x40000>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; reg = <0x0 0x01d84000 0x0 0x3000>; @@ -2769,6 +2774,25 @@ <&apps_smmu 0x481 0x00>; }; + crypto: crypto@1dfa000 { + compatible = "qcom,sa8775p-qce", "qcom,sm8150-qce", "qcom,qce"; + reg = <0x0 0x01dfa000 0x0 0x6000>; + dmas = <&cryptobam 4>, <&cryptobam 5>; + dma-names = "rx", "tx"; + iommus = <&apps_smmu 0x480 0x0>, + <&apps_smmu 0x481 0x0>; + interconnects = <&aggre2_noc MASTER_CRYPTO_CORE0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "memory"; + }; + + lpass_ag_noc: interconnect@3c40000 { + compatible = "qcom,sa8775p-lpass-ag-noc"; + reg = <0x0 0x03c40000 0x0 0x17200>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + ctcu@4001000 { compatible = "qcom,sa8775p-ctcu"; reg = <0x0 0x04001000 0x0 0x1000>; @@ -2961,6 +2985,14 @@ <&apss_funnel1_out>; }; }; + + port@5 { + reg = <5>; + + funnel1_in5: endpoint { + remote-endpoint = <&dlct0_funnel_out>; + }; + }; }; }; @@ -3118,6 +3150,60 @@ }; }; + tpda@4ad3000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x4ad3000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@10 { + reg = <16>; + dlct0_tpda_in16: endpoint { + remote-endpoint = <&turing0_funnel_out>; + }; + }; + }; + + out-ports { + port { + dlct0_tpda_out: endpoint { + remote-endpoint = + <&dlct0_funnel_in0>; + }; + }; + }; + + }; + + funnel@4ad4000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x4ad4000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + dlct0_funnel_in0: endpoint { + remote-endpoint = <&dlct0_tpda_out>; + }; + }; + }; + + out-ports { + port { + dlct0_funnel_out: endpoint { + remote-endpoint = <&funnel1_in5>; + }; + }; + }; + }; + funnel@4b04000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0x0 0x4b04000 0x0 0x1000>; @@ -3390,6 +3476,35 @@ clock-names = "apb_pclk"; }; + funnel@4b83000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x4b83000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + turing0_funnel_in1: endpoint { + remote-endpoint = <&turing_llm_tpdm_out>; + }; + }; + }; + + out-ports { + port { + turing0_funnel_out: endpoint { + remote-endpoint = <&dlct0_tpda_in16>; + }; + }; + }; + }; + etm@6040000 { compatible = "arm,primecell"; reg = <0x0 0x6040000 0x0 0x1000>; @@ -3981,6 +4096,20 @@ reg = <0x0 0x0891c000 0x0 0x84>; }; + dc_noc: interconnect@90e0000 { + compatible = "qcom,sa8775p-dc-noc"; + reg = <0x0 0x090e0000 0x0 0x5080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + gem_noc: interconnect@9100000 { + compatible = "qcom,sa8775p-gem-noc"; + reg = <0x0 0x09100000 0x0 0xf6080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + usb_0: usb@a600000 { compatible = "qcom,sa8775p-dwc3", "qcom,snps-dwc3"; reg = <0 0x0a600000 0 0xfc100>; @@ -4026,7 +4155,27 @@ snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; + usb-role-switch; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_0_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_0_dwc3_ss: endpoint { + }; + }; + }; }; usb_1: usb@a800000 { @@ -4135,6 +4284,113 @@ reg = <0x0 0x1fc0000 0x0 0x30000>; }; + gpu: gpu@3d00000 { + compatible = "qcom,adreno-663.0", "qcom,adreno"; + reg = <0x0 0x03d00000 0x0 0x40000>, + <0x0 0x03d9e000 0x0 0x1000>, + <0x0 0x03d61000 0x0 0x800>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&adreno_smmu 0 0xc00>, + <&adreno_smmu 1 0xc00>; + operating-points-v2 = <&gpu_opp_table>; + qcom,gmu = <&gmu>; + interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "gfx-mem"; + #cooling-cells = <2>; + + nvmem-cells = <&gpu_speed_bin>; + nvmem-cell-names = "speed_bin"; + + status = "disabled"; + + gpu_zap_shader: zap-shader { + memory-region = <&pil_gpu_mem>; + }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-405000000 { + opp-hz = /bits/ 64 <405000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + opp-peak-kBps = <5285156>; + opp-supported-hw = <0x3>; + }; + + opp-530000000 { + opp-hz = /bits/ 64 <530000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + opp-peak-kBps = <12484375>; + opp-supported-hw = <0x2>; + }; + + opp-676000000 { + opp-hz = /bits/ 64 <676000000>; + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; + opp-peak-kBps = <8171875>; + opp-supported-hw = <0x1>; + }; + + opp-778000000 { + opp-hz = /bits/ 64 <778000000>; + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; + opp-peak-kBps = <10687500>; + opp-supported-hw = <0x1>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; + opp-peak-kBps = <12484375>; + opp-supported-hw = <0x1>; + }; + }; + }; + + gmu: gmu@3d6a000 { + compatible = "qcom,adreno-gmu-663.0", "qcom,adreno-gmu"; + reg = <0x0 0x03d6a000 0x0 0x34000>, + <0x0 0x03de0000 0x0 0x10000>, + <0x0 0x0b290000 0x0 0x10000>; + reg-names = "gmu", "rscc", "gmu_pdc"; + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hfi", "gmu"; + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + clock-names = "gmu", + "cxo", + "axi", + "memnoc", + "ahb", + "hub", + "smmu_vote"; + power-domains = <&gpucc GPU_CC_CX_GDSC>, + <&gpucc GPU_CC_GX_GDSC>; + power-domain-names = "cx", + "gx"; + iommus = <&adreno_smmu 5 0xc00>; + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + }; + }; + }; + gpucc: clock-controller@3d90000 { compatible = "qcom,sa8775p-gpucc"; reg = <0x0 0x03d90000 0x0 0xa000>; @@ -4928,7 +5184,7 @@ port@1 { reg = <1>; - mdss0_dsi0_out: endpoint{ }; + mdss0_dsi0_out: endpoint { }; }; }; @@ -6888,6 +7144,13 @@ status = "disabled"; }; + nspa_noc: interconnect@260c0000 { + compatible = "qcom,sa8775p-nspa-noc"; + reg = <0x0 0x260c0000 0x0 0x16080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + remoteproc_cdsp0: remoteproc@26300000 { compatible = "qcom,sa8775p-cdsp0-pas"; reg = <0x0 0x26300000 0x0 0x10000>; @@ -7020,9 +7283,16 @@ }; }; + nspb_noc: interconnect@2a0c0000 { + compatible = "qcom,sa8775p-nspb-noc"; + reg = <0x0 0x2a0c0000 0x0 0x16080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + remoteproc_cdsp1: remoteproc@2a300000 { compatible = "qcom,sa8775p-cdsp1-pas"; - reg = <0x0 0x2A300000 0x0 0x10000>; + reg = <0x0 0x2a300000 0x0 0x10000>; interrupts-extended = <&intc GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, <&smp2p_cdsp1_in 0 IRQ_TYPE_EDGE_RISING>, @@ -7395,8 +7665,15 @@ thermal-sensors = <&tsens0 5>; + cooling-maps { + map0 { + trip = <&gpuss0_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { + gpuss0_alert0: trip-point0 { temperature = <105000>; hysteresis = <5000>; type = "passive"; @@ -7415,8 +7692,15 @@ thermal-sensors = <&tsens0 6>; + cooling-maps { + map0 { + trip = <&gpuss1_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { + gpuss1_alert0: trip-point0 { temperature = <105000>; hysteresis = <5000>; type = "passive"; @@ -7435,8 +7719,15 @@ thermal-sensors = <&tsens0 7>; + cooling-maps { + map0 { + trip = <&gpuss2_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { + gpuss2_alert0: trip-point0 { temperature = <105000>; hysteresis = <5000>; type = "passive"; @@ -7625,8 +7916,15 @@ thermal-sensors = <&tsens1 5>; + cooling-maps { + map0 { + trip = <&gpuss3_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { + gpuss3_alert0: trip-point0 { temperature = <105000>; hysteresis = <5000>; type = "passive"; @@ -7645,8 +7943,15 @@ thermal-sensors = <&tsens1 6>; + cooling-maps { + map0 { + trip = <&gpuss4_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { + gpuss4_alert0: trip-point0 { temperature = <105000>; hysteresis = <5000>; type = "passive"; @@ -7665,8 +7970,15 @@ thermal-sensors = <&tsens1 7>; + cooling-maps { + map0 { + trip = <&gpuss5_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { + gpuss5_alert0: trip-point0 { temperature = <105000>; hysteresis = <5000>; type = "passive"; @@ -8269,6 +8581,20 @@ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; }; + turing-llm-tpdm { + compatible = "qcom,coresight-static-tpdm"; + + qcom,cmb-element-bits = <32>; + + out-ports { + port { + turing_llm_tpdm_out: endpoint { + remote-endpoint = <&turing0_funnel_in1>; + }; + }; + }; + }; + pcie0: pcie@1c00000 { compatible = "qcom,pcie-sa8775p"; reg = <0x0 0x01c00000 0x0 0x3000>, diff --git a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts new file mode 100644 index 000000000000..52895dd9e4fa --- /dev/null +++ b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts @@ -0,0 +1,790 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com> + */ + +/dts-v1/; + +#define PMIV0104_SID 7 + +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include "milos.dtsi" +#include "pm7550.dtsi" +#include "pm8550vs.dtsi" +#include "pmiv0104.dtsi" /* PMIV0108 */ +#include "pmk8550.dtsi" /* PMK7635 */ +#include "pmr735b.dtsi" + +/ { + model = "The Fairphone (Gen. 6)"; + compatible = "fairphone,fp6", "qcom,milos"; + chassis-type = "handset"; + + aliases { + serial0 = &uart5; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&volume_up_default>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume Up"; + gpios = <&pm7550_gpios 6 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + }; + + switch { + label = "Switch"; + gpios = <&tlmm 107 GPIO_ACTIVE_HIGH>; + linux,input-type = <EV_SW>; + linux,code = <SW_MUTE_DEVICE>; + }; + }; + + pmic-glink { + compatible = "qcom,milos-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + orientation-gpios = <&tlmm 131 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + }; + }; + }; + + vreg_ff_afvdd_2p8: regulator-ff-afvdd-2p8 { + compatible = "regulator-fixed"; + regulator-name = "ff_afvdd_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + startup-delay-us = <100>; + + gpio = <&tlmm 93 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vreg_bob>; + }; + + vreg_uw_afvdd_2p8: regulator-uw-afvdd-2p8 { + compatible = "regulator-fixed"; + regulator-name = "uw_afvdd_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + startup-delay-us = <100>; + + gpio = <&tlmm 23 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vreg_bob>; + }; + + vreg_uw_dvdd: regulator-uw-dvdd { + compatible = "regulator-fixed"; + regulator-name = "uw_dvdd"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + startup-delay-us = <100>; + + gpio = <&tlmm 28 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vreg_s1b>; + }; + + vreg_ois_avdd0_1p8: regulator-ois-avdd0-1p8 { + compatible = "regulator-fixed"; + regulator-name = "ois_avdd0_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <100>; + + gpio = <&tlmm 27 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vreg_bob>; + }; + + vreg_ois_vdd: regulator-ois-vdd { + compatible = "regulator-fixed"; + regulator-name = "ois_vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100>; + + gpio = <&tlmm 24 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vph_pwr>; + }; + + vreg_oled_dvdd_1p2: regulator-oled-dvdd-1p2 { + compatible = "regulator-fixed"; + regulator-name = "oled_dvdd_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + gpio = <&tlmm 54 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vreg_s2b>; + + regulator-boot-on; + }; + + vreg_s1j: regulator-pm3001a-s1j { + compatible = "regulator-fixed"; + regulator-name = "pm3001a_s1j"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + startup-delay-us = <1000>; + + gpio = <&pmr735b_gpios 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vph_pwr>; + + pinctrl-0 = <&s1j_enable_default>; + pinctrl-names = "default"; + }; + + vreg_vtof_ldo_3p3: regulator-vtof-ldo-3p3 { + compatible = "regulator-fixed"; + regulator-name = "vtof_ldo_3p3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100>; + + gpio = <&tlmm 76 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vph_pwr>; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + thermal-zones { + pm8008-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pm8008>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm7550-rpmh-regulators"; + + vdd-l1-supply = <&vreg_s1b>; + vdd-l2-l3-supply = <&vreg_s3b>; + vdd-l4-l5-supply = <&vreg_s2b>; + vdd-l6-supply = <&vreg_s2b>; + vdd-l7-supply = <&vreg_s1b>; + vdd-l8-supply = <&vreg_s1b>; + vdd-l9-l10-supply = <&vreg_s1b>; + vdd-l11-supply = <&vreg_s1b>; + vdd-l12-l14-supply = <&vreg_bob>; + vdd-l13-l16-supply = <&vreg_bob>; + vdd-l15-l17-l18-l19-l20-l21-l22-l23-supply = <&vreg_bob>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + + qcom,pmic-id = "b"; + + vreg_s1b: smps1 { + regulator-name = "vreg_s1b"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2080000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s2b: smps2 { + regulator-name = "vreg_s2b"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1408000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s3b: smps3 { + regulator-name = "vreg_s3b"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <1040000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2b: ldo2 { + regulator-name = "vreg_l2b"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3b: ldo3 { + regulator-name = "vreg_l3b"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4b: ldo4 { + regulator-name = "vreg_l4b"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5b: ldo5 { + regulator-name = "vreg_l5b"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7b: ldo7 { + regulator-name = "vreg_l7b"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8b: ldo8 { + regulator-name = "vreg_l8b"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l9b: ldo9 { + regulator-name = "vreg_l9b"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l10b: ldo10 { + regulator-name = "vreg_l10b"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l11b: ldo11 { + regulator-name = "vreg_l11b"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l12b: ldo12 { + regulator-name = "vreg_l12b"; + /* + * Skip voltage voting for UFS VCC. + */ + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l13b: ldo13 { + regulator-name = "vreg_l13b"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l14b: ldo14 { + regulator-name = "vreg_l14b"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l15b: ldo15 { + regulator-name = "vreg_l15b"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l16b: ldo16 { + regulator-name = "vreg_l16b"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l17b: ldo17 { + regulator-name = "vreg_l17b"; + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l18b: ldo18 { + regulator-name = "vreg_l18b"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l19b: ldo19 { + regulator-name = "vreg_l19b"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l20b: ldo20 { + regulator-name = "vreg_l20b"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l21b: ldo21 { + regulator-name = "vreg_l21b"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l22b: ldo22 { + regulator-name = "vreg_l22b"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l23b: ldo23 { + regulator-name = "vreg_l23b"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_bob: bob { + regulator-name = "vreg_bob"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + + vdd-l1-supply = <&vreg_s3b>; + vdd-l3-supply = <&vreg_s3b>; + + qcom,pmic-id = "c"; + + vreg_l2c: ldo2 { + regulator-name = "vreg_l2c"; + regulator-min-microvolt = <320000>; + regulator-max-microvolt = <650000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-2 { + compatible = "qcom,pmr735b-rpmh-regulators"; + + vdd-l1-l2-supply= <&vreg_s3b>; + vdd-l3-supply= <&vreg_s3b>; + vdd-l4-supply= <&vreg_s1b>; + vdd-l5-supply= <&vreg_s2b>; + vdd-l6-supply= <&vreg_s2b>; + vdd-l7-l8-supply= <&vreg_s2b>; + vdd-l9-supply= <&vreg_s3b>; + vdd-l10-supply= <&vreg_s1b>; + vdd-l11-supply= <&vreg_s3b>; + vdd-l12-supply= <&vreg_s3b>; + + qcom,pmic-id = "f"; + + vreg_l1f: ldo1 { + regulator-name = "vreg_l1f"; + regulator-min-microvolt = <852000>; + regulator-max-microvolt = <950000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2f: ldo2 { + regulator-name = "vreg_l2f"; + regulator-min-microvolt = <751000>; + regulator-max-microvolt = <824000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3f: ldo3 { + regulator-name = "vreg_l3f"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4f: ldo4 { + regulator-name = "vreg_l4f"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1950000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5f: ldo5 { + regulator-name = "vreg_l5f"; + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6f: ldo6 { + regulator-name = "vreg_l6f"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7f: ldo7 { + regulator-name = "vreg_l7f"; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1350000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8f: ldo8 { + regulator-name = "vreg_l8f"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1320000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l9f: ldo9 { + regulator-name = "vreg_l9f"; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <970000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l10f: ldo10 { + regulator-name = "vreg_l10f"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l11f: ldo11 { + regulator-name = "vreg_l11f"; + regulator-min-microvolt = <320000>; + regulator-max-microvolt = <864000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; +}; + +&gcc { + protected-clocks = <GCC_PCIE_1_AUX_CLK>, <GCC_PCIE_1_AUX_CLK_SRC>, + <GCC_PCIE_1_CFG_AHB_CLK>, <GCC_PCIE_1_MSTR_AXI_CLK>, + <GCC_PCIE_1_PHY_RCHNG_CLK>, <GCC_PCIE_1_PHY_RCHNG_CLK_SRC>, + <GCC_PCIE_1_PIPE_CLK>, <GCC_PCIE_1_PIPE_CLK_SRC>, + <GCC_PCIE_1_PIPE_DIV2_CLK>, <GCC_PCIE_1_PIPE_DIV2_CLK_SRC>, + <GCC_PCIE_1_SLV_AXI_CLK>, <GCC_PCIE_1_SLV_Q2A_AXI_CLK>; +}; + +&i2c1 { + /* Samsung NFC @ 0x27 */ + + status = "okay"; +}; + +&i2c3 { + /* AW88261FCR amplifier (top) @ 0x34 */ + /* AW88261FCR amplifier (bottom) @ 0x35 */ + + status = "okay"; +}; + +&i2c7 { + status = "okay"; + + pm8008: pmic@8 { + compatible = "qcom,pm8008"; + reg = <0x8>; + + interrupts-extended = <&tlmm 125 IRQ_TYPE_EDGE_RISING>; + reset-gpios = <&pmr735b_gpios 3 GPIO_ACTIVE_LOW>; + + vdd-l1-l2-supply = <&vreg_s2b>; + vdd-l3-l4-supply = <&vreg_bob>; + vdd-l5-supply = <&vreg_bob>; + vdd-l6-supply = <&vreg_s1b>; + vdd-l7-supply = <&vreg_bob>; + + pinctrl-0 = <&pm8008_int_default>, <&pm8008_reset_n_default>; + pinctrl-names = "default"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pm8008 0 0 2>; + + interrupt-controller; + #interrupt-cells = <2>; + + #thermal-sensor-cells = <0>; + + regulators { + vreg_l1p: ldo1 { + regulator-name = "vreg_l1p"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + }; + + vreg_l2p: ldo2 { + regulator-name = "vreg_l2p"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1144000>; + }; + + vreg_l3p: ldo3 { + regulator-name = "vreg_l3p"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3000000>; + }; + + vreg_l4p: ldo4 { + regulator-name = "vreg_l4p"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2900000>; + }; + + vreg_l5p: ldo5 { + regulator-name = "vreg_l5p"; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2900000>; + }; + + vreg_l6p: ldo6 { + regulator-name = "vreg_l6p"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1896000>; + }; + + vreg_l7p: ldo7 { + regulator-name = "vreg_l7p"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3400000>; + }; + }; + }; + + /* VL53L3 ToF @ 0x29 */ + /* AW86938FCR vibrator @ 0x5a */ +}; + +&pm8550vs_c { + status = "okay"; +}; + +&pmiv0104_eusb2_repeater { + vdd18-supply = <&vreg_l7b>; + vdd3-supply = <&vreg_l17b>; + + qcom,tune-res-fsdif = /bits/ 8 <0x5>; + qcom,tune-usb2-amplitude = /bits/ 8 <0x8>; + qcom,tune-usb2-disc-thres = /bits/ 8 <0x7>; + qcom,tune-usb2-preem = /bits/ 8 <0x6>; +}; + +&pmr735b_gpios { + s1j_enable_default: s1j-enable-default-state { + pins = "gpio1"; + function = PMIC_GPIO_FUNC_NORMAL; + power-source = <0>; + bias-disable; + output-low; + }; + + pm8008_reset_n_default: pm8008-reset-n-default-state { + pins = "gpio3"; + function = PMIC_GPIO_FUNC_NORMAL; + bias-pull-down; + }; +}; + +&pm7550_gpios { + volume_up_default: volume-up-default-state { + pins = "gpio6"; + function = PMIC_GPIO_FUNC_NORMAL; + power-source = <1>; + bias-pull-up; + }; +}; + +&pm7550_flash { + status = "okay"; + + led-0 { + function = LED_FUNCTION_FLASH; + color = <LED_COLOR_ID_WHITE>; + led-sources = <1>, <4>; + led-max-microamp = <350000>; + flash-max-microamp = <1500000>; + flash-max-timeout-us = <400000>; + }; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = <KEY_VOLUMEDOWN>; + + status = "okay"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/milos/fairphone/fp6/adsp.mbn", + "qcom/milos/fairphone/fp6/adsp_dtb.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/milos/fairphone/fp6/cdsp.mbn", + "qcom/milos/fairphone/fp6/cdsp_dtb.mbn"; + + status = "okay"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/milos/fairphone/fp6/modem.mbn"; + + status = "okay"; +}; + +&remoteproc_wpss { + firmware-name = "qcom/milos/fairphone/fp6/wpss.mbn"; + + status = "okay"; +}; + +&sdhc_2 { + cd-gpios = <&tlmm 65 GPIO_ACTIVE_HIGH>; + + vmmc-supply = <&vreg_l13b>; + vqmmc-supply = <&vreg_l23b>; + no-sdio; + no-mmc; + + pinctrl-0 = <&sdc2_default>, <&sdc2_card_det_n>; + pinctrl-1 = <&sdc2_sleep>, <&sdc2_card_det_n>; + pinctrl-names = "default", "sleep"; + + status = "okay"; +}; + +&spi0 { + /* Eswin EPH8621 touchscreen @ 0 */ +}; + +&tlmm { + gpio-reserved-ranges = <8 4>, /* Fingerprint SPI */ + <13 1>, /* NC */ + <63 2>; /* WLAN UART */ + + sdc2_card_det_n: sdc2-card-det-state { + pins = "gpio65"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + pm8008_int_default: pm8008-int-default-state { + pins = "gpio125"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + +&uart5 { + status = "okay"; +}; + +&usb_1 { + dr_mode = "otg"; + + /* USB 2.0 only, HW does not support USB 3.x */ + qcom,select-utmi-as-pipe-clk; + + status = "okay"; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_1_hsphy { + vdd-supply = <&vreg_l2b>; + vdda12-supply = <&vreg_l4b>; + + phys = <&pmiv0104_eusb2_repeater>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi new file mode 100644 index 000000000000..e1a51d43943f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/milos.dtsi @@ -0,0 +1,2633 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com> + */ + +#include <dt-bindings/clock/qcom,milos-camcc.h> +#include <dt-bindings/clock/qcom,milos-dispcc.h> +#include <dt-bindings/clock/qcom,milos-gcc.h> +#include <dt-bindings/clock/qcom,milos-gpucc.h> +#include <dt-bindings/clock/qcom,rpmh.h> +#include <dt-bindings/clock/qcom,sm8650-tcsr.h> +#include <dt-bindings/dma/qcom-gpi.h> +#include <dt-bindings/firmware/qcom,scm.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interconnect/qcom,icc.h> +#include <dt-bindings/interconnect/qcom,milos-rpmh.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/mailbox/qcom-ipcc.h> +#include <dt-bindings/power/qcom,rpmhpd.h> +#include <dt-bindings/power/qcom-rpmpd.h> +#include <dt-bindings/soc/qcom,rpmh-rsc.h> + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <76800000>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32764>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a520"; + reg = <0x0 0x0>; + + clocks = <&cpufreq_hw 0>; + + power-domains = <&cpu_pd0>; + power-domain-names = "psci"; + + enable-method = "psci"; + next-level-cache = <&l2_0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + + qcom,freq-domain = <&cpufreq_hw 0>; + + #cooling-cells = <2>; + + l2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; + + l3_0: l3-cache { + compatible = "cache"; + cache-level = <3>; + cache-unified; + }; + }; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a520"; + reg = <0x0 0x100>; + + clocks = <&cpufreq_hw 0>; + + power-domains = <&cpu_pd1>; + power-domain-names = "psci"; + + enable-method = "psci"; + next-level-cache = <&l2_0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + + qcom,freq-domain = <&cpufreq_hw 0>; + + #cooling-cells = <2>; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a520"; + reg = <0x0 0x200>; + + clocks = <&cpufreq_hw 0>; + + power-domains = <&cpu_pd2>; + power-domain-names = "psci"; + + enable-method = "psci"; + next-level-cache = <&l2_2>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + + qcom,freq-domain = <&cpufreq_hw 0>; + + #cooling-cells = <2>; + + l2_2: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a520"; + reg = <0x0 0x300>; + + clocks = <&cpufreq_hw 0>; + + power-domains = <&cpu_pd3>; + power-domain-names = "psci"; + + enable-method = "psci"; + next-level-cache = <&l2_2>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + + qcom,freq-domain = <&cpufreq_hw 0>; + + #cooling-cells = <2>; + }; + + cpu4: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a720"; + reg = <0x0 0x400>; + + clocks = <&cpufreq_hw 1>; + + power-domains = <&cpu_pd4>; + power-domain-names = "psci"; + + enable-method = "psci"; + next-level-cache = <&l2_4>; + capacity-dmips-mhz = <1670>; + dynamic-power-coefficient = <264>; + + qcom,freq-domain = <&cpufreq_hw 1>; + + #cooling-cells = <2>; + + l2_4: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + cpu5: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a720"; + reg = <0x0 0x500>; + + clocks = <&cpufreq_hw 1>; + + power-domains = <&cpu_pd5>; + power-domain-names = "psci"; + + enable-method = "psci"; + next-level-cache = <&l2_5>; + capacity-dmips-mhz = <1670>; + dynamic-power-coefficient = <264>; + + qcom,freq-domain = <&cpufreq_hw 1>; + + #cooling-cells = <2>; + + l2_5: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + cpu6: cpu@600 { + device_type = "cpu"; + compatible = "arm,cortex-a720"; + reg = <0x0 0x600>; + + clocks = <&cpufreq_hw 1>; + + power-domains = <&cpu_pd6>; + power-domain-names = "psci"; + + enable-method = "psci"; + next-level-cache = <&l2_6>; + capacity-dmips-mhz = <1670>; + dynamic-power-coefficient = <264>; + + qcom,freq-domain = <&cpufreq_hw 1>; + + #cooling-cells = <2>; + + l2_6: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + cpu7: cpu@700 { + device_type = "cpu"; + compatible = "arm,cortex-a720"; + reg = <0x0 0x700>; + + clocks = <&cpufreq_hw 2>; + + power-domains = <&cpu_pd7>; + power-domain-names = "psci"; + + enable-method = "psci"; + next-level-cache = <&l2_7>; + capacity-dmips-mhz = <1670>; + dynamic-power-coefficient = <287>; + + qcom,freq-domain = <&cpufreq_hw 2>; + + #cooling-cells = <2>; + + l2_7: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu4>; + }; + + core1 { + cpu = <&cpu5>; + }; + + core2 { + cpu = <&cpu6>; + }; + }; + + cluster2 { + core0 { + cpu = <&cpu7>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + silver_cpu_sleep_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + idle-state-name = "pc"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <250>; + exit-latency-us = <700>; + min-residency-us = <5200>; + local-timer-stop; + }; + + silver_cpu_sleep_1: cpu-sleep-0-1 { + compatible = "arm,idle-state"; + idle-state-name = "silver-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <550>; + exit-latency-us = <750>; + min-residency-us = <6700>; + local-timer-stop; + }; + + gold_cpu_sleep_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + idle-state-name = "silver-power-collapse"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <400>; + exit-latency-us = <900>; + min-residency-us = <5511>; + local-timer-stop; + }; + + gold_cpu_sleep_1: cpu-sleep-1-1 { + compatible = "arm,idle-state"; + idle-state-name = "gold-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <600>; + exit-latency-us = <1300>; + min-residency-us = <8136>; + local-timer-stop; + }; + + gold_plus_cpu_sleep_0: cpu-sleep-2-0 { + compatible = "arm,idle-state"; + idle-state-name = "gold-plus-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <600>; + exit-latency-us = <1500>; + min-residency-us = <8551>; + local-timer-stop; + }; + }; + + domain-idle-states { + cluster_sleep_0: cluster-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41000044>; + entry-latency-us = <750>; + exit-latency-us = <2350>; + min-residency-us = <9144>; + }; + + cluster_sleep_1: cluster-sleep-1 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41003344>; + entry-latency-us = <2800>; + exit-latency-us = <4400>; + min-residency-us = <10150>; + }; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-milos", "qcom,scm"; + qcom,dload-mode = <&tcsr 0x19000>; + }; + }; + + clk_virt: interconnect-0 { + compatible = "qcom,milos-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mc_virt: interconnect-1 { + compatible = "qcom,milos-mc-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + memory@0 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0 0 0 0>; + }; + + pmu-a520 { + compatible = "arm,cortex-a520-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; + }; + + pmu-a720 { + compatible = "arm,cortex-a720-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + cpu_pd0: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&silver_cpu_sleep_0>, <&silver_cpu_sleep_1>; + }; + + cpu_pd1: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&silver_cpu_sleep_0>, <&silver_cpu_sleep_1>; + }; + + cpu_pd2: power-domain-cpu2 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&silver_cpu_sleep_0>, <&silver_cpu_sleep_1>; + }; + + cpu_pd3: power-domain-cpu3 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&silver_cpu_sleep_0>, <&silver_cpu_sleep_1>; + }; + + cpu_pd4: power-domain-cpu4 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&gold_cpu_sleep_0>, <&gold_cpu_sleep_1>; + }; + + cpu_pd5: power-domain-cpu5 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&gold_cpu_sleep_0>, <&gold_cpu_sleep_1>; + }; + + cpu_pd6: power-domain-cpu6 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&gold_cpu_sleep_0>, <&gold_cpu_sleep_1>; + }; + + cpu_pd7: power-domain-cpu7 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&gold_plus_cpu_sleep_0>; + }; + + cluster_pd: power-domain-cluster { + #power-domain-cells = <0>; + domain-idle-states = <&cluster_sleep_0>, <&cluster_sleep_1>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gunyah_hyp_mem: gunyah-hyp-region@80000000 { + reg = <0x0 0x80000000 0x0 0xe00000>; + no-map; + }; + + xbl_sc_mem: xbl-sc-region@81800000 { + reg = <0x0 0x81800000 0x0 0x40000>; + no-map; + }; + + cpucp_fw_mem: cpucp-fw-region@81840000 { + reg = <0x0 0x81840000 0x0 0x1c0000>; + no-map; + }; + + xbl_dtlog_mem: xbl-dtlog-region@81a00000 { + reg = <0x0 0x81a00000 0x0 0x40000>; + no-map; + }; + + xbl_ramdump_mem: xbl-ramdump-region@81a40000 { + reg = <0x0 0x81a40000 0x0 0x1c0000>; + no-map; + }; + + aop_image_mem: aop-image-region@81c00000 { + reg = <0x0 0x81c00000 0x0 0x60000>; + no-map; + }; + + aop_cmd_db_mem: aop-cmd-db-region@81c60000 { + compatible = "qcom,cmd-db"; + reg = <0x0 0x81c60000 0x0 0x20000>; + no-map; + }; + + aop_config_mem: aop-config-region@81c80000 { + reg = <0x0 0x81c80000 0x0 0x20000>; + no-map; + }; + + tme_crash_dump_mem: tme-crash-dump-region@81ca0000 { + reg = <0x0 0x81ca0000 0x0 0x40000>; + no-map; + }; + + tme_log_mem: tme-log-region@81ce0000 { + reg = <0x0 0x81ce0000 0x0 0x4000>; + no-map; + }; + + uefi_log_mem: uefi-log-region@81ce4000 { + reg = <0x0 0x81ce4000 0x0 0x10000>; + no-map; + }; + + chipinfo_mem: chipinfo-region@81cf4000 { + reg = <0x0 0x81cf4000 0x0 0x1000>; + no-map; + }; + + secdata_apss_mem: secdata-apss-region@81cff000 { + reg = <0x0 0x81cff000 0x0 0x1000>; + no-map; + }; + + smem_mem: smem-region@81d00000 { + compatible = "qcom,smem"; + reg = <0x0 0x81d00000 0x0 0x200000>; + hwlocks = <&tcsr_mutex 3>; + no-map; + }; + + adsp_mhi_mem: adsp-mhi-region@81f00000 { + reg = <0x0 0x81f00000 0x0 0x20000>; + no-map; + }; + + pvm_fw_mem: pvm-fw-region@824a0000 { + reg = <0x0 0x824a0000 0x0 0x100000>; + no-map; + }; + + hyp_mem_database_mem: hyp-mem-database-region@825a0000 { + reg = <0x0 0x825a0000 0x0 0x60000>; + no-map; + }; + + global_sync_mem: global-sync-region@82600000 { + reg = <0x0 0x82600000 0x0 0x100000>; + no-map; + }; + + tz_stat_mem: tz-stat-region@82700000 { + reg = <0x0 0x82700000 0x0 0x100000>; + no-map; + }; + + qdss_apps_mem: qdss-apps-region@82800000 { + reg = <0x0 0x82800000 0x0 0x2000000>; + reusable; + }; + + mpss_mem: mpss-region@8ac00000 { + reg = <0x0 0x8ac00000 0x0 0xe600000>; + no-map; + }; + + q6_mpss_dtb_mem: q6-mpss-dtb-region@99200000 { + reg = <0x0 0x99200000 0x0 0x80000>; + no-map; + }; + + q6_adsp_dtb_mem: q6-adsp-dtb-region@99280000 { + reg = <0x0 0x99280000 0x0 0x80000>; + no-map; + }; + + adspslpi_mem: adspslpi-region@99300000 { + reg = <0x0 0x99300000 0x0 0x2800000>; + no-map; + }; + + wpss_mem: wpss-region@9bb00000 { + reg = <0x0 0x9bb00000 0x0 0x1900000>; + no-map; + }; + + video_mem: video-region@9d400000 { + reg = <0x0 0x9d400000 0x0 0x700000>; + no-map; + }; + + cdsp_mem: cdsp-region@9db00000 { + reg = <0x0 0x9db00000 0x0 0xf00000>; + no-map; + }; + + q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9ea00000 { + reg = <0x0 0x9ea00000 0x0 0x80000>; + no-map; + }; + + ipa_fw_mem: ipa-fw-region@9ea80000 { + reg = <0x0 0x9ea80000 0x0 0x10000>; + no-map; + }; + + ipa_gsi_mem: ipa-gsi-region@9ea90000 { + reg = <0x0 0x9ea90000 0x0 0xa000>; + no-map; + }; + + gpu_microcode_mem: gpu-microcode-region@9ea9a000 { + reg = <0x0 0x9ea9a000 0x0 0x2000>; + no-map; + }; + + camera_mem: camera-region@9eb00000 { + reg = <0x0 0x9eb00000 0x0 0x800000>; + no-map; + }; + + wlan_msa_mem: wlan-msa-region@a6400000 { + reg = <0x0 0xa6400000 0x0 0xc00000>; + no-map; + }; + + cpusys_vm_mem: cpusys-vm-region@e0600000 { + reg = <0x0 0xe0600000 0x0 0x400000>; + no-map; + }; + + rmtfs_mem: rmtfs@e1f00000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0 0xe1f00000 0x0 0x600000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; + }; + + qtee_mem: qtee-region@e8900000 { + reg = <0x0 0xe8900000 0x0 0x500000>; + no-map; + }; + + tags_mem: tags-region@e8e00000 { + reg = <0x0 0xe8e00000 0x0 0x700000>; + no-map; + }; + + trusted_apps_mem: trusted-apps-region@e9500000 { + reg = <0x0 0xe9500000 0x0 0x1200000>; + no-map; + }; + }; + + smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + smp2p_adsp_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_adsp_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-cdsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + smp2p_cdsp_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_cdsp_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts-extended = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + smp2p_modem_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_modem_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_ipa_out: ipa-ap-to-modem { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_ipa_in: ipa-modem-to-ap { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-wpss { + compatible = "qcom,smp2p"; + qcom,smem = <617>, <616>; + interrupts-extended = <&ipcc IPCC_CLIENT_WPSS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_WPSS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <13>; + + smp2p_wpss_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_wpss_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_wlan_out: wlan-ap-to-wpss { + qcom,entry-name = "wlan"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_wlan_in: wlan-wpss-to-ap { + qcom,entry-name = "wlan"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + soc: soc@0 { + compatible = "simple-bus"; + + #address-cells = <2>; + #size-cells = <2>; + dma-ranges = <0 0 0 0 0x10 0>; + ranges = <0 0 0 0 0x10 0>; + + gcc: clock-controller@100000 { + compatible = "qcom,milos-gcc"; + reg = <0x0 0x00100000 0x0 0x1f4200>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <0>, /* pcie_0_pipe_clk */ + <0>, /* pcie_1_pipe_clk */ + <0>, /* ufs_phy_rx_symbol_0_clk */ + <0>, /* ufs_phy_rx_symbol_1_clk */ + <0>, /* ufs_phy_tx_symbol_0_clk */ + <0>; /* usb3_phy_wrapper_gcc_usb30_pipe_clk */ + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + ipcc: mailbox@405000 { + compatible = "qcom,milos-ipcc", "qcom,ipcc"; + reg = <0x0 0x00405000 0x0 0x1000>; + + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-controller; + #interrupt-cells = <3>; + + #mbox-cells = <2>; + }; + + gpi_dma1: dma-controller@800000 { + compatible = "qcom,milos-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0x0 0x00800000 0x0 0x60000>; + + interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; + + dma-channels = <12>; + dma-channel-mask = <0x3f>; + #dma-cells = <3>; + + iommus = <&apps_smmu 0x36 0x0>; + dma-coherent; + }; + + qupv3_id_1: geniqup@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x008c0000 0x0 0x2000>; + + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + clock-names = "m-ahb", + "s-ahb"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core"; + + iommus = <&apps_smmu 0x23 0>; + + dma-coherent; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + i2c7: i2c@880000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00880000 0x0 0x4000>; + + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH 0>; + + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_cfg SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c7_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart11: serial@890000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00890000 0x0 0x4000>; + + interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>; + + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_cfg SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart11_default>, <&qup_uart11_cts_rts>; + pinctrl-names = "default"; + + status = "disabled"; + }; + }; + + gpi_dma0: dma-controller@a00000 { + compatible = "qcom,milos-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0x0 0x00a00000 0x0 0x60000>; + + interrupts = <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH 0>; + + dma-channels = <12>; + dma-channel-mask = <0x3e>; + #dma-cells = <3>; + + iommus = <&apps_smmu 0x576 0x0>; + dma-coherent; + }; + + qupv3_id_0: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x00ac0000 0x0 0x2000>; + + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + clock-names = "m-ahb", + "s-ahb"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core"; + + iommus = <&apps_smmu 0x563 0>; + + dma-coherent; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + spi0: spi@a80000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a80000 0x0 0x4000>; + + interrupts = <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH 0>; + + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_cfg SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c1: i2c@a84000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a84000 0x0 0x4000>; + + interrupts = <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH 0>; + + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_cfg SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c1_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c3: i2c@a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a8c000 0x0 0x4000>; + + interrupts = <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH 0>; + + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_cfg SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c3_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart5: serial@a94000 { + compatible = "qcom,geni-debug-uart"; + reg = <0x0 0x00a94000 0x0 0x4000>; + + interrupts = <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH 0>; + + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_cfg SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart5_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; + }; + + rng: rng@10c3000 { + compatible = "qcom,milos-trng", "qcom,trng"; + reg = <0x0 0x010c3000 0x0 0x1000>; + }; + + mmss_noc: interconnect@1400000 { + compatible = "qcom,milos-mmss-noc"; + reg = <0x0 0x01400000 0x0 0xdb800>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + cnoc_main: interconnect@1500000 { + compatible = "qcom,milos-cnoc-main"; + reg = <0x0 0x01500000 0x0 0x14400>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + cnoc_cfg: interconnect@1600000 { + compatible = "qcom,milos-cnoc-cfg"; + reg = <0x0 0x01600000 0x0 0x6e00>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect@1680000 { + compatible = "qcom,milos-system-noc"; + reg = <0x0 0x01680000 0x0 0x40000>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + pcie_anoc: interconnect@16c0000 { + compatible = "qcom,milos-pcie-anoc"; + reg = <0x0 0x016c0000 0x0 0x12400>; + #interconnect-cells = <2>; + clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, + <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@16e0000 { + compatible = "qcom,milos-aggre1-noc"; + reg = <0x0 0x016e0000 0x0 0x16400>; + #interconnect-cells = <2>; + clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre2_noc: interconnect@1700000 { + compatible = "qcom,milos-aggre2-noc"; + reg = <0x0 0x01700000 0x0 0x1f400>; + #interconnect-cells = <2>; + clocks = <&rpmhcc RPMH_IPA_CLK>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x01f40000 0x0 0x20000>; + + #hwlock-cells = <1>; + }; + + tcsr: clock-controller@1fc0000 { + compatible = "qcom,milos-tcsr", "syscon"; + reg = <0x0 0x01fc0000 0x0 0xa0000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + + #clock-cells = <1>; + #reset-cells = <1>; + }; + + remoteproc_adsp: remoteproc@3000000 { + compatible = "qcom,milos-adsp-pas"; + reg = <0x0 0x03000000 0x0 0x10000>; + + interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd RPMHPD_LCX>, + <&rpmhpd RPMHPD_LMX>; + power-domain-names = "lcx", + "lmx"; + + interconnects = <&lpass_ag_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_adsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "lpass"; + qcom,remote-pid = <2>; + }; + }; + + lpass_ag_noc: interconnect@3c40000 { + compatible = "qcom,milos-lpass-ag-noc"; + reg = <0x0 0x03c40000 0x0 0x17200>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + gpucc: clock-controller@3d90000 { + compatible = "qcom,milos-gpucc"; + reg = <0x0 0x03d90000 0x0 0x9800>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + adreno_smmu: iommu@3da0000 { + compatible = "qcom,milos-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x03da0000 0x0 0x40000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>; + clock-names = "hlos", + "bus", + "iface", + "ahb"; + power-domains = <&gpucc GPU_CC_CX_GDSC>; + dma-coherent; + }; + + remoteproc_mpss: remoteproc@4080000 { + compatible = "qcom,milos-mpss-pas"; + reg = <0x0 0x04080000 0x0 0x10000>; + + interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING 0>, + <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MSS>; + power-domain-names = "cx", + "mss"; + + interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + memory-region = <&mpss_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_modem_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "mpss"; + qcom,remote-pid = <1>; + }; + }; + + sdhc_2: mmc@8804000 { + compatible = "qcom,milos-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x0 0x08804000 0x0 0x1000>; + + interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "hc_irq", + "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", + "core", + "xo"; + + interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_cfg SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "sdhc-ddr", + "cpu-sdhc"; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&sdhc2_opp_table>; + + iommus = <&apps_smmu 0x540 0>; + + bus-width = <4>; + + qcom,dll-config = <0x0007442c>; + qcom,ddr-config = <0x80040868>; + + dma-coherent; + + status = "disabled"; + + sdhc2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + usb_1_hsphy: phy@88e3000 { + compatible = "qcom,milos-snps-eusb2-phy", + "qcom,sm8550-snps-eusb2-phy"; + reg = <0x0 0x088e3000 0x0 0x154>; + #phy-cells = <0>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + status = "disabled"; + }; + + remoteproc_wpss: remoteproc@8a00000 { + compatible = "qcom,milos-wpss-pas"; + reg = <0x0 0x08a00000 0x0 0x10000>; + + interrupts-extended = <&intc GIC_SPI 579 IRQ_TYPE_EDGE_RISING 0>, + <&smp2p_wpss_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_wpss_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_wpss_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_wpss_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_wpss_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MX>; + power-domain-names = "cx", + "mx"; + + memory-region = <&wpss_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_wpss_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_WPSS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_WPSS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "wpss"; + qcom,remote-pid = <13>; + }; + }; + + usb_1: usb@a600000 { + compatible = "qcom,milos-dwc3", "qcom,snps-dwc3"; + reg = <0x0 0x0a600000 0x0 0xfc000>; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "xo"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH 0>, + <&intc GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH 0>, + <&pdc 14 IRQ_TYPE_EDGE_BOTH>, + <&pdc 15 IRQ_TYPE_EDGE_BOTH>, + <&pdc 25 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dwc_usb3", + "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + iommus = <&apps_smmu 0x40 0x0>; + power-domains = <&gcc USB30_PRIM_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_cfg SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "usb-ddr", "apps-usb"; + + phys = <&usb_1_hsphy>; + phy-names = "usb2-phy"; + + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis_enblslpm_quirk; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,is-utmi-l1-suspend; + snps,parkmode-disable-ss-quirk; + tx-fifo-resize; + dma-coherent; + usb-role-switch; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_dwc3_hs: endpoint { + }; + }; + }; + }; + + videocc: clock-controller@aaf0000 { + compatible = "qcom,milos-videocc"; + reg = <0x0 0x0aaf0000 0x0 0x10000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, + <&gcc GCC_VIDEO_AHB_CLK>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + camcc: clock-controller@adb0000 { + compatible = "qcom,milos-camcc"; + reg = <0x0 0x0adb0000 0x0 0x40000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <&gcc GCC_CAMERA_AHB_CLK>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,milos-dispcc"; + reg = <0x0 0x0af00000 0x0 0x20000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, + <0>, /* dsi0_phy_pll_out_byteclk */ + <0>, /* dsi0_phy_pll_out_dsiclk */ + <0>, /* dp0_phy_pll_link_clk */ + <0>; /* dp0_phy_pll_vco_div_clk */ + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,milos-pdc", "qcom,pdc"; + reg = <0x0 0x0b220000 0x0 0x30000>, + <0x0 0x174000f0 0x0 0x64>; + interrupt-parent = <&intc>; + + qcom,pdc-ranges = <0 480 40>, <40 140 11>, <51 527 47>, + <98 609 31>, <129 63 1>, <130 716 12>, + <142 251 5>; + + #interrupt-cells = <2>; + interrupt-controller; + }; + + tsens0: thermal-sensor@c228000 { + compatible = "qcom,milos-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c228000 0x0 0x1000>, + <0x0 0x0c222000 0x0 0x1000>; + + interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <15>; + + #thermal-sensor-cells = <1>; + }; + + tsens1: thermal-sensor@c229000 { + compatible = "qcom,milos-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c229000 0x0 0x1000>, + <0x0 0x0c223000 0x0 0x1000>; + + interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <14>; + + #thermal-sensor-cells = <1>; + }; + + aoss_qmp: power-management@c300000 { + compatible = "qcom,milos-aoss-qmp", "qcom,aoss-qmp"; + reg = <0x0 0x0c300000 0x0 0x400>; + + interrupt-parent = <&ipcc>; + interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + + #clock-cells = <0>; + }; + + sram@c3f0000 { + compatible = "qcom,rpmh-stats"; + reg = <0x0 0x0c3f0000 0x0 0x400>; + }; + + spmi_bus: spmi@c400000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0 0x0c400000 0x0 0x3000>, + <0x0 0x0c500000 0x0 0x400000>, + <0x0 0x0c440000 0x0 0x80000>, + <0x0 0x0c4c0000 0x0 0x10000>, + <0x0 0x0c42d000 0x0 0x4000>; + reg-names = "core", + "chnls", + "obsrvr", + "intr", + "cnfg"; + + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + + qcom,ee = <0>; + qcom,channel = <0>; + qcom,bus-id = <0>; + + interrupt-controller; + #interrupt-cells = <4>; + + #address-cells = <2>; + #size-cells = <0>; + }; + + tlmm: pinctrl@f100000 { + compatible = "qcom,milos-tlmm"; + reg = <0x0 0x0f100000 0x0 0x300000>; + + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 0>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + gpio-ranges = <&tlmm 0 0 168>; + + wakeup-parent = <&pdc>; + + qup_i2c1_data_clk: qup-i2c1-data-clk-state { + /* SDA, SCL */ + pins = "gpio4", "gpio5"; + function = "qup0_se1"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c3_data_clk: qup-i2c3-data-clk-state { + /* SDA, SCL */ + pins = "gpio15", "gpio16"; + function = "qup0_se3"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c7_data_clk: qup-i2c7-data-clk-state { + /* SDA, SCL */ + pins = "gpio32", "gpio33"; + function = "qup1_se0"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi0_cs: qup-spi0-cs-state { + pins = "gpio3"; + function = "qup0_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi0_data_clk: qup-spi0-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio0", "gpio1", "gpio2"; + function = "qup0_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_uart5_default: qup-uart5-default-state { + /* TX, RX */ + pins = "gpio25", "gpio26"; + function = "qup0_se5"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart11_default: qup-uart11-default-state { + /* TX, RX */ + pins = "gpio50", "gpio51"; + function = "qup1_se4"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_uart11_cts_rts: qup-uart11-cts-rts-state { + /* CTS, RTS */ + pins = "gpio48", "gpio49"; + function = "qup1_se4"; + drive-strength = <2>; + bias-pull-down; + }; + + sdc2_default: sdc2-default-state { + clk-pins { + pins = "gpio62"; + function = "sdc2_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-pins { + pins = "gpio61"; + function = "sdc2_cmd"; + drive-strength = <10>; + bias-pull-up; + }; + + data-pins { + pins = "gpio58", "gpio57", "gpio35", "gpio34"; + function = "sdc2_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + sdc2_sleep: sdc2-sleep-state { + clk-pins { + pins = "gpio62"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "gpio61"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "gpio58", "gpio57", "gpio35", "gpio34"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + apps_smmu: iommu@15000000 { + compatible = "qcom,milos-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x15000000 0x0 0x100000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH 0>; + dma-coherent; + }; + + intc: interrupt-controller@17100000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x17100000 0x0 0x10000>, + <0x0 0x17180000 0x0 0x200000>; + + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; + + #interrupt-cells = <4>; + interrupt-controller; + + #redistributor-regions = <1>; + redistributor-stride = <0 0x40000>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; + }; + + ppi_cluster1: interrupt-partition-1 { + affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; + }; + }; + + gic_its: msi-controller@17140000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x17140000 0x0 0x20000>; + + msi-controller; + #msi-cells = <1>; + }; + }; + + timer@17420000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x17420000 0x0 0x1000>; + + ranges = <0 0 0 0x20000000>; + #address-cells = <1>; + #size-cells = <1>; + + frame@17421000 { + reg = <0x17421000 0x1000>, + <0x17422000 0x1000>; + + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; + + frame-number = <0>; + }; + + frame@17423000 { + reg = <0x17423000 0x1000>; + + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>; + + frame-number = <1>; + + status = "disabled"; + }; + + frame@17425000 { + reg = <0x17425000 0x1000>; + + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>; + + frame-number = <2>; + + status = "disabled"; + }; + + frame@17427000 { + reg = <0x17427000 0x1000>; + + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; + + frame-number = <3>; + + status = "disabled"; + }; + + frame@17429000 { + reg = <0x17429000 0x1000>; + + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; + + frame-number = <4>; + + status = "disabled"; + }; + + frame@1742b000 { + reg = <0x1742b000 0x1000>; + + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH 0>; + + frame-number = <5>; + + status = "disabled"; + }; + + frame@1742d000 { + reg = <0x1742d000 0x1000>; + + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; + + frame-number = <6>; + + status = "disabled"; + }; + }; + + apps_rsc: rsc@17a00000 { + compatible = "qcom,rpmh-rsc"; + reg = <0x0 0x17a00000 0x0 0x10000>, + <0x0 0x17a10000 0x0 0x10000>, + <0x0 0x17a20000 0x0 0x10000>; + reg-names = "drv-0", + "drv-1", + "drv-2"; + + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>; + + power-domains = <&cluster_pd>; + + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, + <WAKE_TCS 2>, <CONTROL_TCS 0>; + + label = "apps_rsc"; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible = "qcom,milos-rpmh-clk"; + + clocks = <&xo_board>; + clock-names = "xo"; + + #clock-cells = <1>; + }; + + rpmhpd: power-controller { + compatible = "qcom,milos-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp-16 { + opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; + }; + + rpmhpd_opp_low_svs_d1: opp-56 { + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; + }; + + rpmhpd_opp_low_svs: opp-64 { + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + }; + + rpmhpd_opp_svs: opp-128 { + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + }; + + rpmhpd_opp_svs_l1: opp-192 { + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + }; + + rpmhpd_opp_nom: opp-256 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; + }; + + rpmhpd_opp_nom_l1: opp-320 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; + }; + + rpmhpd_opp_turbo: opp-384 { + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; + }; + + rpmhpd_opp_turbo_l1: opp-416 { + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; + }; + }; + }; + }; + + cpufreq_hw: cpufreq@17d91000 { + compatible = "qcom,milos-cpufreq-epss", "qcom,cpufreq-epss"; + reg = <0x0 0x17d91000 0x0 0x1000>, + <0x0 0x17d92000 0x0 0x1000>, + <0x0 0x17d93000 0x0 0x1000>; + reg-names = "freq-domain0", + "freq-domain1", + "freq-domain2"; + + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "dcvsh-irq-0", + "dcvsh-irq-1", + "dcvsh-irq-2"; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPLL0>; + clock-names = "xo", + "alternate"; + + #freq-domain-cells = <1>; + #clock-cells = <1>; + }; + + gem_noc: interconnect@24100000 { + compatible = "qcom,milos-gem-noc"; + reg = <0x0 0x24100000 0x0 0xff080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + nsp_noc: interconnect@320c0000 { + compatible = "qcom,milos-nsp-noc"; + reg = <0x0 0x320c0000 0x0 0xe080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + remoteproc_cdsp: remoteproc@32300000 { + compatible = "qcom,milos-cdsp-pas"; + reg = <0x0 0x32300000 0x0 0x10000>; + + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING 0>, + <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MX>; + power-domain-names = "cx", + "mx"; + + interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_cdsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "cdsp"; + qcom,remote-pid = <5>; + }; + }; + }; + + thermal-zones { + aoss0-thermal { + thermal-sensors = <&tsens0 0>; + + trips { + aoss0-hot { + temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + aoss0-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpuss0-thermal { + thermal-sensors = <&tsens0 1>; + + trips { + cpuss0-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpuss1-thermal { + thermal-sensors = <&tsens0 2>; + + trips { + cpuss1-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu4-left-thermal { + thermal-sensors = <&tsens0 3>; + + trips { + cpu4-left-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu4-right-thermal { + thermal-sensors = <&tsens0 4>; + + trips { + cpu4-right-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu5-left-thermal { + thermal-sensors = <&tsens0 5>; + + trips { + cpu5-left-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu5-right-thermal { + thermal-sensors = <&tsens0 6>; + + trips { + cpu5-right-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu6-left-thermal { + thermal-sensors = <&tsens0 7>; + + trips { + cpu6-left-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu6-right-thermal { + thermal-sensors = <&tsens0 8>; + + trips { + cpu6-right-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu7-left-thermal { + thermal-sensors = <&tsens0 9>; + + trips { + cpu7-left-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu7-right-thermal { + thermal-sensors = <&tsens0 10>; + + trips { + cpu7-right-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu0-thermal { + thermal-sensors = <&tsens0 11>; + + trips { + cpu0-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu1-thermal { + thermal-sensors = <&tsens0 12>; + + trips { + cpu1-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu2-thermal { + thermal-sensors = <&tsens0 13>; + + trips { + cpu2-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu3-thermal { + thermal-sensors = <&tsens0 14>; + + trips { + cpu3-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + aoss1-thermal { + thermal-sensors = <&tsens1 0>; + + trips { + aoss1-hot { + temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + aoss1-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsphvx0-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens1 1>; + + trips { + nsphvx0-hot { + temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + nsphvx0-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsphmx1-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens1 2>; + + trips { + nsphmx1-hot { + temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + nsphmx1-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsphmx0-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens1 3>; + + trips { + nsphmx0-hot { + temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + nsphmx0-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss0-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens1 4>; + + trips { + gpu0_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <90000>; + hysteresis = <1000>; + type = "hot"; + }; + + gpuss0-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpuss1-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens1 5>; + + trips { + gpu1_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <90000>; + hysteresis = <1000>; + type = "hot"; + }; + + gpuss1-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + video-thermal { + thermal-sensors = <&tsens1 7>; + + trips { + video-hot { + temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + video-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + ddr-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens1 8>; + + trips { + ddr-hot { + temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + ddr-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + camera0-thermal { + thermal-sensors = <&tsens1 9>; + + trips { + camera0-hot { + temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + camera0-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + modem0-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&tsens1 10>; + + trips { + modem0-hot { + temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + modem0-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + modem1-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&tsens1 11>; + + trips { + modem1-hot { + temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + modem1-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + modem2-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&tsens1 12>; + + trips { + modem2-hot { + temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + modem2-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + modem3-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&tsens1 13>; + + trips { + modem3-hot { + temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + modem3-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, + <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW 0>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/monaco-evk.dts b/arch/arm64/boot/dts/qcom/monaco-evk.dts index bb35893da73d..565418b86b2a 100644 --- a/arch/arm64/boot/dts/qcom/monaco-evk.dts +++ b/arch/arm64/boot/dts/qcom/monaco-evk.dts @@ -6,6 +6,7 @@ /dts-v1/; #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pwm/pwm.h> #include <dt-bindings/sound/qcom,q6afe.h> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> @@ -323,6 +324,16 @@ status = "okay"; + fan_controller: fan@18 { + compatible = "ti,amc6821"; + reg = <0x18>; + #pwm-cells = <2>; + + fan { + pwms = <&fan_controller 40000 PWM_POLARITY_INVERTED>; + }; + }; + eeprom0: eeprom@50 { compatible = "atmel,24c256"; reg = <0x50>; @@ -400,6 +411,44 @@ status = "okay"; }; +&pcie0 { + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l6a>; + vdda-pll-supply = <&vreg_l5a>; + + status = "okay"; +}; + +&pcie1 { + pinctrl-0 = <&pcie1_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l6a>; + vdda-pll-supply = <&vreg_l5a>; + + status = "okay"; +}; + +&pcieport0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>; +}; + +&pcieport1 { + reset-gpios = <&tlmm 23 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>; +}; + &qupv3_id_0 { firmware-name = "qcom/qcs8300/qupv3fw.elf"; status = "okay"; @@ -434,7 +483,41 @@ status = "okay"; }; +&spi10 { + status = "okay"; + + tpm@0 { + compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi"; + reg = <0>; + spi-max-frequency = <20000000>; + }; +}; + &tlmm { + + pcie0_default_state: pcie0-default-state { + wake-pins { + pins = "gpio0"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + clkreq-pins { + pins = "gpio1"; + function = "pcie0_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-pins { + pins = "gpio2"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + ethernet0_default: ethernet0-default-state { ethernet0_mdc: ethernet0-mdc-pins { pins = "gpio5"; @@ -458,6 +541,29 @@ bias-pull-up; }; + pcie1_default_state: pcie1-default-state { + wake-pins { + pins = "gpio21"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + clkreq-pins { + pins = "gpio22"; + function = "pcie1_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-pins { + pins = "gpio23"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + qup_i2c15_default: qup-i2c15-state { pins = "gpio91", "gpio92"; function = "qup1_se7"; diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 816fa2af8a9a..5d2df4305d1c 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -55,6 +55,7 @@ power-domain-names = "psci"; capacity-dmips-mhz = <1946>; dynamic-power-coefficient = <472>; + #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY @@ -79,6 +80,7 @@ power-domains = <&cpu_pd1>; power-domain-names = "psci"; capacity-dmips-mhz = <1946>; + #cooling-cells = <2>; dynamic-power-coefficient = <472>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; @@ -104,6 +106,7 @@ power-domains = <&cpu_pd2>; power-domain-names = "psci"; capacity-dmips-mhz = <1946>; + #cooling-cells = <2>; dynamic-power-coefficient = <507>; qcom,freq-domain = <&cpufreq_hw 2>; operating-points-v2 = <&cpu2_opp_table>; @@ -129,6 +132,7 @@ power-domains = <&cpu_pd3>; power-domain-names = "psci"; capacity-dmips-mhz = <1946>; + #cooling-cells = <2>; dynamic-power-coefficient = <507>; qcom,freq-domain = <&cpufreq_hw 2>; operating-points-v2 = <&cpu2_opp_table>; @@ -154,6 +158,7 @@ power-domains = <&cpu_pd4>; power-domain-names = "psci"; capacity-dmips-mhz = <1024>; + #cooling-cells = <2>; dynamic-power-coefficient = <100>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; @@ -179,6 +184,7 @@ power-domains = <&cpu_pd5>; power-domain-names = "psci"; capacity-dmips-mhz = <1024>; + #cooling-cells = <2>; dynamic-power-coefficient = <100>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; @@ -204,6 +210,7 @@ power-domains = <&cpu_pd6>; power-domain-names = "psci"; capacity-dmips-mhz = <1024>; + #cooling-cells = <2>; dynamic-power-coefficient = <100>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; @@ -229,6 +236,7 @@ power-domains = <&cpu_pd7>; power-domain-names = "psci"; capacity-dmips-mhz = <1024>; + #cooling-cells = <2>; dynamic-power-coefficient = <100>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; @@ -904,8 +912,8 @@ #power-domain-cells = <1>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, - <0>, - <0>, + <&pcie0_phy>, + <&pcie1_phy>, <0>, <0>, <0>, @@ -929,7 +937,7 @@ #address-cells = <1>; #size-cells = <1>; - gpu_speed_bin: gpu_speed_bin@240c { + gpu_speed_bin: gpu-speed-bin@240c { reg = <0x240c 0x1>; bits = <0 8>; }; @@ -2256,6 +2264,376 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + pcie0: pci@1c00000 { + device_type = "pci"; + compatible = "qcom,pcie-qcs8300", "qcom,pcie-sa8775p"; + reg = <0x0 0x01c00000 0x0 0x3000>, + <0x0 0x40000000 0x0 0xf20>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x4000>, + <0x0 0x40100000 0x0 0x100000>, + <0x0 0x01c03000 0x0 0x1000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; + bus-range = <0x00 0xff>; + + dma-coherent; + + linux,pci-domain = <0>; + num-lanes = <2>; + + interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; + assigned-clock-rates = <19200000>; + + interconnects = <&pcie_anoc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "pcie-mem", + "cpu-pcie"; + + iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, + <0x100 &pcie_smmu 0x0001 0x1>; + + resets = <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; + reset-names = "pci", + "link_down"; + + power-domains = <&gcc GCC_PCIE_0_GDSC>; + + eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; + eq-presets-16gts = /bits/ 8 <0x55 0x55>; + + operating-points-v2 = <&pcie0_opp_table>; + + status = "disabled"; + + pcie0_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_svs_l1>; + opp-peak-kBps = <250000 1>; + }; + + /* GEN 1 x2 and GEN 2 x1 */ + opp-5000000 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + opp-peak-kBps = <500000 1>; + }; + + /* GEN 2 x2 */ + opp-10000000 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + opp-peak-kBps = <1000000 1>; + }; + + /* GEN 3 x1 */ + opp-8000000 { + opp-hz = /bits/ 64 <8000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + opp-peak-kBps = <984500 1>; + }; + + /* GEN 3 x2 and GEN 4 x1 */ + opp-16000000 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <1969000 1>; + }; + + /* GEN 4 x2 */ + opp-32000000 { + opp-hz = /bits/ 64 <32000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <3938000 1>; + }; + }; + + pcieport0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + phys = <&pcie0_phy>; + }; + }; + + pcie0_phy: phy@1c04000 { + compatible = "qcom,qcs8300-qmp-gen4x2-pcie-phy"; + reg = <0x0 0x01c04000 0x0 0x2000>; + + clocks = <&gcc GCC_PCIE_0_PHY_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_CLKREF_EN>, + <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_PIPEDIV2_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; + + resets = <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + #clock-cells = <0>; + clock-output-names = "pcie_0_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + + pcie1: pci@1c10000 { + device_type = "pci"; + compatible = "qcom,pcie-qcs8300", "qcom,pcie-sa8775p"; + reg = <0x0 0x01c10000 0x0 0x3000>, + <0x0 0x60000000 0x0 0xf20>, + <0x0 0x60000f20 0x0 0xa8>, + <0x0 0x60001000 0x0 0x4000>, + <0x0 0x60100000 0x0 0x100000>, + <0x0 0x01c13000 0x0 0x1000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>; + bus-range = <0x00 0xff>; + + dma-coherent; + + linux,pci-domain = <1>; + num-lanes = <4>; + + interrupts = <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; + assigned-clock-rates = <19200000>; + + interconnects = <&pcie_anoc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + iommu-map = <0x0 &pcie_smmu 0x0080 0x1>, + <0x100 &pcie_smmu 0x0081 0x1>; + + resets = <&gcc GCC_PCIE_1_BCR>, + <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; + reset-names = "pci", + "link_down"; + + power-domains = <&gcc GCC_PCIE_1_GDSC>; + + eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; + eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; + + operating-points-v2 = <&pcie1_opp_table>; + + status = "disabled"; + + pcie1_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_svs_l1>; + opp-peak-kBps = <250000 1>; + }; + + /* GEN 1 x2 and GEN 2 x1 */ + opp-5000000 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + opp-peak-kBps = <500000 1>; + }; + + /* GEN 1 x4 and GEN 2 x2 */ + opp-10000000 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + opp-peak-kBps = <1000000 1>; + }; + + /* GEN 2 x4 */ + opp-20000000 { + opp-hz = /bits/ 64 <20000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <2000000 1>; + }; + + /* GEN 3 x1 */ + opp-8000000 { + opp-hz = /bits/ 64 <8000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + opp-peak-kBps = <984500 1>; + }; + + /* GEN 3 x2 and GEN 4 x1 */ + opp-16000000 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <1969000 1>; + }; + + /* GEN 3 x4 and GEN 4 x2 */ + opp-32000000 { + opp-hz = /bits/ 64 <32000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <3938000 1>; + }; + + /* GEN 4 x4 */ + opp-64000000 { + opp-hz = /bits/ 64 <64000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <7876000 1>; + }; + }; + + pcieport1: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + phys = <&pcie1_phy>; + }; + }; + + pcie1_phy: phy@1c14000 { + compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy"; + reg = <0x0 0x01c14000 0x0 0x4000>; + + clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_CLKREF_EN>, + <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK>, + <&gcc GCC_PCIE_1_PIPEDIV2_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; + + assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + resets = <&gcc GCC_PCIE_1_PHY_BCR>; + reset-names = "phy"; + + #clock-cells = <0>; + clock-output-names = "pcie_1_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + ufs_mem_hc: ufs@1d84000 { compatible = "qcom,qcs8300-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; reg = <0x0 0x01d84000 0x0 0x3000>; @@ -2350,6 +2728,18 @@ clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; }; + crypto: crypto@1dfa000 { + compatible = "qcom,qcs8300-qce", "qcom,sm8150-qce", "qcom,qce"; + reg = <0x0 0x01dfa000 0x0 0x6000>; + dmas = <&cryptobam 4>, <&cryptobam 5>; + dma-names = "rx", "tx"; + iommus = <&apps_smmu 0x480 0x0>, + <&apps_smmu 0x481 0x0>; + interconnects = <&aggre2_noc MASTER_CRYPTO_CORE0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "memory"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x20000>; @@ -2483,6 +2873,35 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + ctcu@4001000 { + compatible = "qcom,qcs8300-ctcu", "qcom,sa8775p-ctcu"; + reg = <0x0 0x04001000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ctcu_in0: endpoint { + remote-endpoint = <&etr0_out>; + }; + }; + + port@1 { + reg = <1>; + + ctcu_in1: endpoint { + remote-endpoint = <&etr1_out>; + }; + }; + }; + }; + stm@4002000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0x0 0x04002000 0x0 0x1000>, @@ -2513,6 +2932,14 @@ #address-cells = <1>; #size-cells = <0>; + port@0 { + reg = <0>; + + swao_rep_out0: endpoint { + remote-endpoint = <&qdss_rep_in>; + }; + }; + port@1 { reg = <1>; @@ -2677,6 +3104,122 @@ }; }; + replicator@4046000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x0 0x04046000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + qdss_rep_in: endpoint { + remote-endpoint = <&swao_rep_out0>; + }; + }; + }; + + out-ports { + port { + qdss_rep_out0: endpoint { + remote-endpoint = <&etr_rep_in>; + }; + }; + }; + }; + + tmc@4048000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x04048000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + iommus = <&apps_smmu 0x04c0 0x00>; + + arm,scatter-gather; + + in-ports { + port { + etr0_in: endpoint { + remote-endpoint = <&etr_rep_out0>; + }; + }; + }; + + out-ports { + port { + etr0_out: endpoint { + remote-endpoint = <&ctcu_in0>; + }; + }; + }; + }; + + replicator@404e000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x0 0x0404e000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + etr_rep_in: endpoint { + remote-endpoint = <&qdss_rep_out0>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + etr_rep_out0: endpoint { + remote-endpoint = <&etr0_in>; + }; + }; + + port@1 { + reg = <1>; + + etr_rep_out1: endpoint { + remote-endpoint = <&etr1_in>; + }; + }; + }; + }; + + tmc@404f000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x0404f000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + iommus = <&apps_smmu 0x04a0 0x40>; + + arm,scatter-gather; + arm,buffer-size = <0x400000>; + + in-ports { + port { + etr1_in: endpoint { + remote-endpoint = <&etr_rep_out1>; + }; + }; + }; + + out-ports { + port { + etr1_out: endpoint { + remote-endpoint = <&ctcu_in1>; + }; + }; + }; + }; + tpdm@4841000 { compatible = "qcom,coresight-tpdm", "arm,primecell"; reg = <0x0 0x04841000 0x0 0x1000>; @@ -4776,6 +5319,178 @@ #power-domain-cells = <1>; }; + camss: isp@ac78000 { + compatible = "qcom,qcs8300-camss"; + + reg = <0x0 0xac78000 0x0 0x1000>, + <0x0 0xac7a000 0x0 0xf00>, + <0x0 0xac7c000 0x0 0xf00>, + <0x0 0xac84000 0x0 0xf00>, + <0x0 0xac88000 0x0 0xf00>, + <0x0 0xac8c000 0x0 0xf00>, + <0x0 0xac90000 0x0 0xf00>, + <0x0 0xac94000 0x0 0xf00>, + <0x0 0xac9c000 0x0 0x2000>, + <0x0 0xac9e000 0x0 0x2000>, + <0x0 0xaca0000 0x0 0x2000>, + <0x0 0xacac000 0x0 0x400>, + <0x0 0xacad000 0x0 0x400>, + <0x0 0xacae000 0x0 0x400>, + <0x0 0xac4d000 0x0 0xf000>, + <0x0 0xac60000 0x0 0xf000>, + <0x0 0xac85000 0x0 0xd00>, + <0x0 0xac89000 0x0 0xd00>, + <0x0 0xac8d000 0x0 0xd00>, + <0x0 0xac91000 0x0 0xd00>, + <0x0 0xac95000 0x0 0xd00>; + reg-names = "csid_wrapper", + "csid0", + "csid1", + "csid_lite0", + "csid_lite1", + "csid_lite2", + "csid_lite3", + "csid_lite4", + "csiphy0", + "csiphy1", + "csiphy2", + "tpg0", + "tpg1", + "tpg2", + "vfe0", + "vfe1", + "vfe_lite0", + "vfe_lite1", + "vfe_lite2", + "vfe_lite3", + "vfe_lite4"; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_CPAS_IFE_0_CLK>, + <&camcc CAM_CC_CPAS_IFE_1_CLK>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_ICP_AHB_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>; + clock-names = "camnoc_axi", + "core_ahb", + "cpas_ahb", + "cpas_fast_ahb_clk", + "cpas_vfe_lite", + "cpas_vfe0", + "cpas_vfe1", + "csid", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy_rx", + "gcc_axi_hf", + "gcc_axi_sf", + "icp_ahb", + "vfe0", + "vfe0_fast_ahb", + "vfe1", + "vfe1_fast_ahb", + "vfe_lite", + "vfe_lite_ahb", + "vfe_lite_cphy_rx", + "vfe_lite_csid"; + + interrupts = <GIC_SPI 565 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 564 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 759 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 758 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 545 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 546 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 547 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 761 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 760 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "csid0", + "csid1", + "csid_lite0", + "csid_lite1", + "csid_lite2", + "csid_lite3", + "csid_lite4", + "csiphy0", + "csiphy1", + "csiphy2", + "tpg0", + "tpg1", + "tpg2", + "vfe0", + "vfe1", + "vfe_lite0", + "vfe_lite1", + "vfe_lite2", + "vfe_lite3", + "vfe_lite4"; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "ahb", + "hf_0"; + + iommus = <&apps_smmu 0x2400 0x20>; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + power-domain-names = "top"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + + port@2 { + reg = <2>; + }; + }; + }; + camcc: clock-controller@ade0000 { compatible = "qcom,qcs8300-camcc"; reg = <0x0 0x0ade0000 0x0 0x20000>; @@ -4789,6 +5504,222 @@ #power-domain-cells = <1>; }; + mdss: display-subsystem@ae00000 { + compatible = "qcom,qcs8300-mdss"; + reg = <0x0 0x0ae00000 0x0 0x1000>; + reg-names = "mdss"; + + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_MDP_CLK>; + + resets = <&dispcc MDSS_DISP_CC_MDSS_CORE_BCR>; + + interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "mdp0-mem", + "mdp1-mem", + "cpu-cfg"; + + power-domains = <&dispcc MDSS_DISP_CC_MDSS_CORE_GDSC>; + + iommus = <&apps_smmu 0x1000 0x402>; + + interrupt-controller; + #interrupt-cells = <1>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdss_mdp: display-controller@ae01000 { + compatible = "qcom,qcs8300-dpu", "qcom,sa8775p-dpu"; + reg = <0x0 0x0ae01000 0x0 0x8f000>, + <0x0 0x0aeb0000 0x0 0x2008>; + reg-names = "mdp", "vbif"; + + interrupts-extended = <&mdss 0>; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_MDP_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpu_intf0_out: endpoint { + remote-endpoint = <&mdss_dp0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-575000000 { + opp-hz = /bits/ 64 <575000000>; + required-opps = <&rpmhpd_opp_turbo>; + }; + + opp-650000000 { + opp-hz = /bits/ 64 <650000000>; + required-opps = <&rpmhpd_opp_turbo_l1>; + }; + }; + }; + + mdss_dp0_phy: phy@aec2a00 { + compatible = "qcom,qcs8300-edp-phy", "qcom,sa8775p-edp-phy"; + + reg = <0x0 0x0aec2a00 0x0 0x19c>, + <0x0 0x0aec2200 0x0 0xec>, + <0x0 0x0aec2600 0x0 0xec>, + <0x0 0x0aec2000 0x0 0x1c8>; + + clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>; + clock-names = "aux", + "cfg_ahb"; + + power-domains = <&rpmhpd RPMHPD_MX>; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + mdss_dp0: displayport-controller@af54000 { + compatible = "qcom,qcs8300-dp", "qcom,sa8775p-dp"; + + reg = <0x0 0x0af54000 0x0 0x200>, + <0x0 0x0af54200 0x0 0x200>, + <0x0 0x0af55000 0x0 0xc00>, + <0x0 0x0af56000 0x0 0x09c>, + <0x0 0x0af57000 0x0 0x09c>, + <0x0 0x0af58000 0x0 0x09c>, + <0x0 0x0af59000 0x0 0x09c>, + <0x0 0x0af5a000 0x0 0x23c>, + <0x0 0x0af5b000 0x0 0x23c>; + + interrupts-extended = <&mdss 12>; + + clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel", + "stream_1_pixel", + "stream_2_pixel", + "stream_3_pixel"; + assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>, + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>, + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>; + assigned-clock-parents = <&mdss_dp0_phy 0>, + <&mdss_dp0_phy 1>, + <&mdss_dp0_phy 1>, + <&mdss_dp0_phy 1>, + <&mdss_dp0_phy 1>; + phys = <&mdss_dp0_phy>; + phy-names = "dp"; + + operating-points-v2 = <&dp_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dp0_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp0_out: endpoint { }; + }; + }; + + dp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + }; + dispcc: clock-controller@af00000 { compatible = "qcom,sa8775p-dispcc0"; reg = <0x0 0x0af00000 0x0 0x20000>; @@ -4796,7 +5727,9 @@ <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, - <0>, <0>, <0>, <0>, + <&mdss_dp0_phy 0>, + <&mdss_dp0_phy 1>, + <0>, <0>, <0>, <0>, <0>, <0>; power-domains = <&rpmhpd RPMHPD_MMCX>; #clock-cells = <1>; @@ -4851,6 +5784,50 @@ <235 723 5>; }; + tsens2: thermal-sensor@c251000 { + compatible = "qcom,qcs8300-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c251000 0x0 0x1000>, + <0x0 0x0c224000 0x0 0x1000>; + interrupts = <GIC_SPI 572 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", "critical"; + #qcom,sensors = <10>; + #thermal-sensor-cells = <1>; + }; + + tsens3: thermal-sensor@c252000 { + compatible = "qcom,qcs8300-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c252000 0x0 0x1000>, + <0x0 0x0c225000 0x0 0x1000>; + interrupts = <GIC_SPI 573 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", "critical"; + #qcom,sensors = <10>; + #thermal-sensor-cells = <1>; + }; + + tsens0: thermal-sensor@c263000 { + compatible = "qcom,qcs8300-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c263000 0x0 0x1000>, + <0x0 0x0c222000 0x0 0x1000>; + interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", "critical"; + #qcom,sensors = <10>; + #thermal-sensor-cells = <1>; + }; + + tsens1: thermal-sensor@c265000 { + compatible = "qcom,qcs8300-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c265000 0x0 0x1000>, + <0x0 0x0c223000 0x0 0x1000>; + interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", "critical"; + #qcom,sensors = <10>; + #thermal-sensor-cells = <1>; + }; + aoss_qmp: power-management@c300000 { compatible = "qcom,qcs8300-aoss-qmp", "qcom,aoss-qmp"; reg = <0x0 0x0c300000 0x0 0x400>; @@ -6220,6 +7197,514 @@ }; }; + thermal_zones: thermal-zones { + aoss-0-thermal { + thermal-sensors = <&tsens0 0>; + + trips { + aoss0-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-0-0-thermal { + thermal-sensors = <&tsens0 1>; + + trips { + cpu-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-1-0-thermal { + thermal-sensors = <&tsens0 2>; + + trips { + cpu-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-2-0-thermal { + thermal-sensors = <&tsens0 3>; + + trips { + cpu-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-3-0-thermal { + thermal-sensors = <&tsens0 4>; + + trips { + cpu-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpuss-0-thermal { + thermal-sensors = <&tsens0 5>; + + trips { + gpuss0_alert0: trip-point0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + gpuss0-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpuss0_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + audio-thermal { + thermal-sensors = <&tsens0 6>; + + trips { + audio-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + camss-0-thermal { + thermal-sensors = <&tsens0 7>; + + trips { + camss-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + pcie-0-thermal { + thermal-sensors = <&tsens0 8>; + + trips { + pcie-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpuss-0-0-thermal { + thermal-sensors = <&tsens0 9>; + + trips { + cpuss0-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + aoss-1-thermal { + thermal-sensors = <&tsens1 0>; + + trips { + aoss1-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-0-1-thermal { + thermal-sensors = <&tsens1 1>; + + trips { + cpu-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-1-1-thermal { + thermal-sensors = <&tsens1 2>; + + trips { + cpu-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-2-1-thermal { + thermal-sensors = <&tsens1 3>; + + trips { + cpu-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-3-1-thermal { + thermal-sensors = <&tsens1 4>; + + trips { + cpu-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpuss-1-thermal { + thermal-sensors = <&tsens1 5>; + + trips { + gpuss1_alert0: trip-point0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + gpuss1-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpuss1_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + video-thermal { + thermal-sensors = <&tsens1 6>; + + trips { + video-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + camss-1-thermal { + thermal-sensors = <&tsens1 7>; + + trips { + camss1-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + pcie-1-thermal { + thermal-sensors = <&tsens1 8>; + + trips { + pcie-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpuss-0-1-thermal { + thermal-sensors = <&tsens1 9>; + + trips { + cpuss0-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + aoss-2-thermal { + thermal-sensors = <&tsens2 0>; + + trips { + aoss2-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-0-0-thermal { + thermal-sensors = <&tsens2 1>; + + trips { + cpu-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-1-0-thermal { + thermal-sensors = <&tsens2 2>; + + trips { + cpu-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-2-0-thermal { + thermal-sensors = <&tsens2 3>; + + trips { + cpu-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-3-0-thermal { + thermal-sensors = <&tsens2 4>; + + trips { + cpu-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + nsp-0-0-0-thermal { + thermal-sensors = <&tsens2 5>; + + trips { + nsp-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + nsp-0-1-0-thermal { + thermal-sensors = <&tsens2 6>; + + trips { + nsp-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + nsp-0-2-0-thermal { + thermal-sensors = <&tsens2 7>; + + trips { + nsp-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + ddrss-0-thermal { + thermal-sensors = <&tsens2 8>; + + trips { + ddrss-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpuss-1-0-thermal { + thermal-sensors = <&tsens2 9>; + + trips { + cpuss1-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + aoss-3-thermal { + thermal-sensors = <&tsens3 0>; + + trips { + aoss3-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-0-1-thermal { + thermal-sensors = <&tsens3 1>; + + trips { + cpu-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-1-1-thermal { + thermal-sensors = <&tsens3 2>; + + trips { + cpu-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-2-1-thermal { + thermal-sensors = <&tsens3 3>; + + trips { + cpu-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-3-1-thermal { + thermal-sensors = <&tsens3 4>; + + trips { + cpu-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + nsp-0-0-1-thermal { + thermal-sensors = <&tsens3 5>; + + trips { + nsp-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + nsp-0-1-1-thermal { + thermal-sensors = <&tsens3 6>; + + trips { + nsp-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + nsp-0-2-1-thermal { + thermal-sensors = <&tsens3 7>; + + trips { + nsp-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + ddrss-1-thermal { + thermal-sensors = <&tsens3 8>; + + trips { + ddrss-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpuss-1-1-thermal { + thermal-sensors = <&tsens3 9>; + + trips { + cpuss1-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index d3a25a837488..e39743e22043 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1945,8 +1945,8 @@ interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; - power-domains = <&rpmpd MSM8916_VDDCX>, - <&rpmpd MSM8916_VDDMX>; + power-domains = <&rpmpd RPMPD_VDDCX>, + <&rpmpd RPMPD_VDDMX>; power-domain-names = "cx", "mx"; clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, @@ -2449,8 +2449,8 @@ <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; - power-domains = <&rpmpd MSM8916_VDDCX>, - <&rpmpd MSM8916_VDDMX>; + power-domains = <&rpmpd RPMPD_VDDCX>, + <&rpmpd RPMPD_VDDMX>; power-domain-names = "cx", "mx"; qcom,smem-states = <&wcnss_smp2p_out 0>; diff --git a/arch/arm64/boot/dts/qcom/msm8917.dtsi b/arch/arm64/boot/dts/qcom/msm8917.dtsi index 8a642fce2e40..a2907f8a6376 100644 --- a/arch/arm64/boot/dts/qcom/msm8917.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8917.dtsi @@ -996,7 +996,7 @@ clock-names = "iface", "bus", "vsync"; - + resets = <&gcc GCC_MDSS_BCR>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; @@ -1070,7 +1070,7 @@ phys = <&mdss_dsi0_phy>; operating-points-v2 = <&mdss_dsi0_opp_table>; - power-domains = <&rpmpd MSM8917_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; #address-cells = <1>; #size-cells = <0>; @@ -1288,7 +1288,7 @@ pinctrl-0 = <&sdc1_default>; pinctrl-1 = <&sdc1_sleep>; pinctrl-names = "default", "sleep"; - power-domains = <&rpmpd MSM8917_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; mmc-hs200-1_8v; mmc-hs400-1_8v; mmc-ddr-1_8v; @@ -1313,7 +1313,7 @@ pinctrl-0 = <&sdc2_default>; pinctrl-1 = <&sdc2_sleep>; pinctrl-names = "default", "sleep"; - power-domains = <&rpmpd MSM8917_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; bus-width = <4>; status = "disabled"; }; @@ -1517,8 +1517,8 @@ <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; - power-domains = <&rpmpd MSM8917_VDDCX>, - <&rpmpd MSM8917_VDDMX>; + power-domains = <&rpmpd RPMPD_VDDCX>, + <&rpmpd RPMPD_VDDMX>; power-domain-names = "cx", "mx"; qcom,smem-states = <&wcnss_smp2p_out 0>; diff --git a/arch/arm64/boot/dts/qcom/msm8937.dtsi b/arch/arm64/boot/dts/qcom/msm8937.dtsi index b93621080989..7de6447de48f 100644 --- a/arch/arm64/boot/dts/qcom/msm8937.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8937.dtsi @@ -1044,6 +1044,7 @@ clock-names = "iface", "bus", "vsync"; + resets = <&gcc GCC_MDSS_BCR>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; @@ -1121,7 +1122,7 @@ phys = <&mdss_dsi0_phy>; operating-points-v2 = <&mdss_dsi0_opp_table>; - power-domains = <&rpmpd MSM8937_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; #address-cells = <1>; #size-cells = <0>; @@ -1209,7 +1210,7 @@ phys = <&mdss_dsi1_phy>; operating-points-v2 = <&mdss_dsi1_opp_table>; - power-domains = <&rpmpd MSM8937_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; #address-cells = <1>; #size-cells = <0>; @@ -1456,7 +1457,7 @@ pinctrl-1 = <&sdc1_sleep>; pinctrl-names = "default", "sleep"; - power-domains = <&rpmpd MSM8937_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; mmc-hs200-1_8v; mmc-hs400-1_8v; mmc-ddr-1_8v; @@ -1486,7 +1487,7 @@ pinctrl-1 = <&sdc2_sleep>; pinctrl-names = "default", "sleep"; - power-domains = <&rpmpd MSM8937_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; bus-width = <4>; status = "disabled"; }; @@ -1709,8 +1710,8 @@ "handover", "stop-ack"; - power-domains = <&rpmpd MSM8937_VDDCX>, - <&rpmpd MSM8937_VDDMX>; + power-domains = <&rpmpd RPMPD_VDDCX>, + <&rpmpd RPMPD_VDDMX>; power-domain-names = "cx", "mx"; diff --git a/arch/arm64/boot/dts/qcom/msm8939-asus-z00t.dts b/arch/arm64/boot/dts/qcom/msm8939-asus-z00t.dts index ebb548e62e02..ea90b00a2c8a 100644 --- a/arch/arm64/boot/dts/qcom/msm8939-asus-z00t.dts +++ b/arch/arm64/boot/dts/qcom/msm8939-asus-z00t.dts @@ -20,6 +20,61 @@ serial0 = &blsp_uart2; }; + battery: battery { + compatible = "simple-battery"; + device-chemistry = "lithium-ion-polymer"; + voltage-min-design-microvolt = <3400000>; + voltage-max-design-microvolt = <4400000>; + energy-full-design-microwatt-hours = <11500000>; + charge-full-design-microamp-hours = <3000000>; + + ocv-capacity-celsius = <(-20) 0 25 40 60>; + ocv-capacity-table-0 = <4378000 100>, <4220000 95>, <4125000 90>, + <4071000 85>, <3977000 80>, <3916000 75>, <3866000 70>, + <3838000 65>, <3822000 60>, <3809000 55>, <3797000 50>, + <3784000 45>, <3771000 40>, <3757000 35>, <3743000 30>, + <3726000 25>, <3707000 20>, <3688000 16>, <3670000 13>, + <3655000 11>, <3648000 10>, <3636000 9>, <3624000 8>, + <3612000 7>, <3592000 6>, <3569000 5>, <3540000 4>, + <3494000 3>, <3418000 2>, <3289000 1>, <3000000 0>; + + ocv-capacity-table-1 = <4378000 100>, <4292000 95>, <4226000 90>, + <4166000 85>, <4109000 80>, <4064000 75>, <3992000 70>, + <3942000 65>, <3898000 60>, <3859000 55>, <3826000 50>, + <3802000 45>, <3788000 40>, <3779000 35>, <3768000 30>, + <3752000 25>, <3732000 20>, <3712000 16>, <3696000 13>, + <3688000 11>, <3684000 10>, <3680000 9>, <3675000 8>, + <3669000 7>, <3658000 6>, <3636000 5>, <3599000 4>, + <3544000 3>, <3466000 2>, <3341000 1>, <3000000 0>; + + ocv-capacity-table-2 = <4372000 100>, <4306000 95>, <4247000 90>, + <4190000 85>, <4134000 80>, <4081000 75>, <4030000 70>, + <3984000 65>, <3930000 60>, <3884000 55>, <3850000 50>, + <3826000 45>, <3804000 40>, <3786000 35>, <3770000 30>, + <3753000 25>, <3734000 20>, <3712000 16>, <3693000 13>, + <3686000 11>, <3684000 10>, <3682000 9>, <3680000 8>, + <3676000 7>, <3668000 6>, <3643000 5>, <3600000 4>, + <3542000 3>, <3462000 2>, <3340000 1>, <3000000 0>; + + ocv-capacity-table-3 = <4365000 100>, <4304000 95>, <4246000 90>, + <4189000 85>, <4133000 80>, <4080000 75>, <4030000 70>, + <3985000 65>, <3933000 60>, <3886000 55>, <3852000 50>, + <3827000 45>, <3806000 40>, <3789000 35>, <3769000 30>, + <3746000 25>, <3726000 20>, <3706000 16>, <3688000 13>, + <3681000 11>, <3678000 10>, <3676000 9>, <3676000 8>, + <3672000 7>, <3660000 6>, <3634000 5>, <3588000 4>, + <3528000 3>, <3448000 2>, <3322000 1>, <3000000 0>; + + ocv-capacity-table-4 = <4358000 100>, <4298000 95>, <4240000 90>, + <4183000 85>, <4128000 80>, <4076000 75>, <4027000 70>, + <3983000 65>, <3935000 60>, <3887000 55>, <3852000 50>, + <3827000 45>, <3806000 40>, <3789000 35>, <3764000 30>, + <3738000 25>, <3715000 20>, <3695000 16>, <3677000 13>, + <3672000 11>, <3669000 10>, <3667000 9>, <3666000 8>, + <3662000 7>, <3652000 6>, <3622000 5>, <3577000 4>, + <3518000 3>, <3440000 2>, <3321000 1>, <3000000 0>; + }; + chosen { stdout-path = "serial0"; }; @@ -27,7 +82,7 @@ gpio-keys { compatible = "gpio-keys"; - pinctrl-0 = <&gpio_keys_default>; + pinctrl-0 = <&gpio_hall_sensor_default>, <&gpio_keys_default>; pinctrl-names = "default"; button-volume-up { @@ -43,6 +98,15 @@ linux,code = <KEY_VOLUMEDOWN>; debounce-interval = <15>; }; + + event-hall-sensor { + label = "Hall Effect Sensor"; + gpios = <&tlmm 108 GPIO_ACTIVE_LOW>; + linux,input-type = <EV_SW>; + linux,code = <SW_LID>; + linux,can-disable; + debounce-interval = <150>; + }; }; reg_sd_vmmc: regulator-sdcard-vmmc { @@ -135,6 +199,12 @@ reg = <0x0 0x86800000 0x0 0x5500000>; }; +&pm8916_bms { + monitored-battery = <&battery>; + + status = "okay"; +}; + &pm8916_codec { qcom,micbias-lvl = <2800>; qcom,mbhc-vthreshold-low = <75 150 237 450 500>; @@ -240,6 +310,13 @@ bias-pull-up; }; + gpio_hall_sensor_default: gpio-hall-sensor-default-state { + pins = "gpio108"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + usb_id_default: usb-id-default-state { pins = "gpio110"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi index adb96cd8d643..659d127b1bc3 100644 --- a/arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi @@ -11,6 +11,10 @@ #include "msm8939.dtsi" #include "pm8916.dtsi" +&camss { + vdda-supply = <&pm8916_l2>; +}; + &mdss_dsi0 { vdda-supply = <&pm8916_l2>; vddio-supply = <&pm8916_l6>; diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qcom/msm8939.dtsi index eb64ec35e7f0..d4d7b0c9206c 100644 --- a/arch/arm64/boot/dts/qcom/msm8939.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8939.dtsi @@ -1436,6 +1436,145 @@ }; }; + camss: isp@1b0ac00 { + compatible = "qcom,msm8939-camss"; + reg = <0x01b0ac00 0x200>, + <0x01b00030 0x4>, + <0x01b0b000 0x200>, + <0x01b00038 0x4>, + <0x01b08000 0x100>, + <0x01b08400 0x100>, + <0x01b0a000 0x500>, + <0x01b00020 0x10>, + <0x01b10000 0x1000>, + <0x01b08800 0x100>, + <0x01b40000 0x200>; + reg-names = "csiphy0", + "csiphy0_clk_mux", + "csiphy1", + "csiphy1_clk_mux", + "csid0", + "csid1", + "ispif", + "csi_clk_mux", + "vfe0", + "csid2", + "vfe0_vbif"; + + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>, + <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>, + <&gcc GCC_CAMSS_CSI0_AHB_CLK>, + <&gcc GCC_CAMSS_CSI0_CLK>, + <&gcc GCC_CAMSS_CSI0PHY_CLK>, + <&gcc GCC_CAMSS_CSI0PIX_CLK>, + <&gcc GCC_CAMSS_CSI0RDI_CLK>, + <&gcc GCC_CAMSS_CSI1_AHB_CLK>, + <&gcc GCC_CAMSS_CSI1_CLK>, + <&gcc GCC_CAMSS_CSI1PHY_CLK>, + <&gcc GCC_CAMSS_CSI1PIX_CLK>, + <&gcc GCC_CAMSS_CSI1RDI_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>, + <&gcc GCC_CAMSS_VFE0_CLK>, + <&gcc GCC_CAMSS_CSI_VFE0_CLK>, + <&gcc GCC_CAMSS_VFE_AHB_CLK>, + <&gcc GCC_CAMSS_VFE_AXI_CLK>, + <&gcc GCC_CAMSS_CSI2_AHB_CLK>, + <&gcc GCC_CAMSS_CSI2_CLK>, + <&gcc GCC_CAMSS_CSI2PHY_CLK>, + <&gcc GCC_CAMSS_CSI2PIX_CLK>, + <&gcc GCC_CAMSS_CSI2RDI_CLK>; + clock-names = "top_ahb", + "ispif_ahb", + "csiphy0_timer", + "csiphy1_timer", + "csi0_ahb", + "csi0", + "csi0_phy", + "csi0_pix", + "csi0_rdi", + "csi1_ahb", + "csi1", + "csi1_phy", + "csi1_pix", + "csi1_rdi", + "ahb", + "vfe0", + "csi_vfe0", + "vfe_ahb", + "vfe_axi", + "csi2_ahb", + "csi2", + "csi2_phy", + "csi2_pix", + "csi2_rdi"; + + interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 153 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "csiphy0", + "csiphy1", + "csid0", + "csid1", + "ispif", + "vfe0", + "csid2"; + + iommus = <&apps_iommu 3>; + + power-domains = <&gcc VFE_GDSC>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + }; + }; + + cci: cci@1b0c000 { + compatible = "qcom,msm8916-cci", "qcom,msm8226-cci"; + reg = <0x01b0c000 0x1000>; + interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_CCI_AHB_CLK>, + <&gcc GCC_CAMSS_CCI_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>; + clock-names = "camss_top_ahb", + "cci_ahb", + "cci", + "camss_ahb"; + assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>, + <&gcc GCC_CAMSS_CCI_CLK>; + assigned-clock-rates = <80000000>, + <19200000>; + pinctrl-0 = <&cci0_default>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + cci_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + gpu: gpu@1c00000 { compatible = "qcom,adreno-405.0", "qcom,adreno"; reg = <0x01c00000 0x10000>; @@ -1500,6 +1639,13 @@ #iommu-cells = <1>; qcom,iommu-secure-id = <17>; + /* vfe */ + iommu-ctx@3000 { + compatible = "qcom,msm-iommu-v1-sec"; + reg = <0x3000 0x1000>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + }; + /* mdp_0: */ iommu-ctx@4000 { compatible = "qcom,msm-iommu-v1-ns"; diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index 76317c578349..753167c3f861 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -545,123 +545,6 @@ interrupt-controller; #interrupt-cells = <2>; - uart_console_active: uart-console-active-state { - pins = "gpio4", "gpio5"; - function = "blsp_uart2"; - drive-strength = <2>; - bias-disable; - }; - - uart_console_sleep: uart-console-sleep-state { - pins = "gpio4", "gpio5"; - function = "blsp_uart2"; - drive-strength = <2>; - bias-pull-down; - }; - - sdc1_clk_on: sdc1-clk-on-state { - pins = "sdc1_clk"; - bias-disable; - drive-strength = <16>; - }; - - sdc1_clk_off: sdc1-clk-off-state { - pins = "sdc1_clk"; - bias-disable; - drive-strength = <2>; - }; - - sdc1_cmd_on: sdc1-cmd-on-state { - pins = "sdc1_cmd"; - bias-disable; - drive-strength = <10>; - }; - - sdc1_cmd_off: sdc1-cmd-off-state { - pins = "sdc1_cmd"; - bias-disable; - drive-strength = <2>; - }; - - sdc1_data_on: sdc1-data-on-state { - pins = "sdc1_data"; - bias-pull-up; - drive-strength = <10>; - }; - - sdc1_data_off: sdc1-data-off-state { - pins = "sdc1_data"; - bias-pull-up; - drive-strength = <2>; - }; - - sdc1_rclk_on: sdc1-rclk-on-state { - pins = "sdc1_rclk"; - bias-pull-down; - }; - - sdc1_rclk_off: sdc1-rclk-off-state { - pins = "sdc1_rclk"; - bias-pull-down; - }; - - sdc2_clk_on: sdc2-clk-on-state { - pins = "sdc2_clk"; - drive-strength = <16>; - bias-disable; - }; - - sdc2_clk_off: sdc2-clk-off-state { - pins = "sdc2_clk"; - bias-disable; - drive-strength = <2>; - }; - - sdc2_cmd_on: sdc2-cmd-on-state { - pins = "sdc2_cmd"; - bias-pull-up; - drive-strength = <10>; - }; - - sdc2_cmd_off: sdc2-cmd-off-state { - pins = "sdc2_cmd"; - bias-pull-up; - drive-strength = <2>; - }; - - sdc2_data_on: sdc2-data-on-state { - pins = "sdc2_data"; - bias-pull-up; - drive-strength = <10>; - }; - - sdc2_data_off: sdc2-data-off-state { - pins = "sdc2_data"; - bias-pull-up; - drive-strength = <2>; - }; - - sdc2_cd_on: cd-on-state { - pins = "gpio133"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - - sdc2_cd_off: cd-off-state { - pins = "gpio133"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - gpio_key_default: gpio-key-default-state { - pins = "gpio85"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - i2c_1_default: i2c-1-default-state { pins = "gpio2", "gpio3"; function = "blsp_i2c1"; @@ -676,99 +559,29 @@ bias-disable; }; - i2c_2_default: i2c-2-default-state { - pins = "gpio6", "gpio7"; - function = "blsp_i2c2"; - drive-strength = <2>; - bias-disable; - }; - - i2c_2_sleep: i2c-2-sleep-state { - pins = "gpio6", "gpio7"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - i2c_3_default: i2c-3-default-state { - pins = "gpio10", "gpio11"; - function = "blsp_i2c3"; - drive-strength = <2>; - bias-disable; - }; - - i2c_3_sleep: i2c-3-sleep-state { - pins = "gpio10", "gpio11"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - i2c_4_default: i2c-4-default-state { - pins = "gpio14", "gpio15"; - function = "blsp_i2c4"; - drive-strength = <2>; - bias-disable; - }; - - i2c_4_sleep: i2c-4-sleep-state { - pins = "gpio14", "gpio15"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - i2c_5_default: i2c-5-default-state { - pins = "gpio18", "gpio19"; - function = "blsp_i2c5"; - drive-strength = <2>; - bias-disable; - }; - - i2c_5_sleep: i2c-5-sleep-state { - pins = "gpio18", "gpio19"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - i2c_6_default: i2c-6-default-state { - pins = "gpio22", "gpio23"; - function = "blsp_i2c6"; - drive-strength = <2>; - bias-disable; - }; - - i2c_6_sleep: i2c-6-sleep-state { - pins = "gpio22", "gpio23"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - i2c_7_default: i2c-7-default-state { - pins = "gpio135", "gpio136"; - function = "blsp_i2c7"; + uart_console_active: uart-console-active-state { + pins = "gpio4", "gpio5"; + function = "blsp_uart2"; drive-strength = <2>; bias-disable; }; - i2c_7_sleep: i2c-7-sleep-state { - pins = "gpio135", "gpio136"; - function = "gpio"; + uart_console_sleep: uart-console-sleep-state { + pins = "gpio4", "gpio5"; + function = "blsp_uart2"; drive-strength = <2>; - bias-disable; + bias-pull-down; }; - i2c_8_default: i2c-8-default-state { - pins = "gpio98", "gpio99"; - function = "blsp_i2c8"; + i2c_2_default: i2c-2-default-state { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; drive-strength = <2>; bias-disable; }; - i2c_8_sleep: i2c-8-sleep-state { - pins = "gpio98", "gpio99"; + i2c_2_sleep: i2c-2-sleep-state { + pins = "gpio6", "gpio7"; function = "gpio"; drive-strength = <2>; bias-disable; @@ -806,6 +619,34 @@ }; }; + i2c_3_default: i2c-3-default-state { + pins = "gpio10", "gpio11"; + function = "blsp_i2c3"; + drive-strength = <2>; + bias-disable; + }; + + i2c_3_sleep: i2c-3-sleep-state { + pins = "gpio10", "gpio11"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + i2c_4_default: i2c-4-default-state { + pins = "gpio14", "gpio15"; + function = "blsp_i2c4"; + drive-strength = <2>; + bias-disable; + }; + + i2c_4_sleep: i2c-4-sleep-state { + pins = "gpio14", "gpio15"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + spi_5_default: spi-5-default-state { cs-pins { pins = "gpio18"; @@ -838,6 +679,34 @@ }; }; + uart_5_default: uart-5-default-state { + pins = "gpio16", "gpio17", "gpio18", "gpio19"; + function = "blsp_uart5"; + drive-strength = <16>; + bias-disable; + }; + + uart_5_sleep: uart-5-sleep-state { + pins = "gpio16", "gpio17", "gpio18", "gpio19"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + i2c_5_default: i2c-5-default-state { + pins = "gpio18", "gpio19"; + function = "blsp_i2c5"; + drive-strength = <2>; + bias-disable; + }; + + i2c_5_sleep: i2c-5-sleep-state { + pins = "gpio18", "gpio19"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + spi_6_default: spi-6-default-state { cs-pins { pins = "gpio22"; @@ -870,6 +739,113 @@ }; }; + i2c_6_default: i2c-6-default-state { + pins = "gpio22", "gpio23"; + function = "blsp_i2c6"; + drive-strength = <2>; + bias-disable; + }; + + i2c_6_sleep: i2c-6-sleep-state { + pins = "gpio22", "gpio23"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + cci0_default: cci0-default-state { + pins = "gpio29", "gpio30"; + function = "cci_i2c"; + drive-strength = <2>; + bias-disable; + }; + + cci1_default: cci1-default-state { + pins = "gpio31", "gpio32"; + function = "cci_i2c"; + drive-strength = <2>; + bias-disable; + }; + + wcnss_pin_a: wcnss-active-state { + wcss-wlan2-pins { + pins = "gpio76"; + function = "wcss_wlan2"; + drive-strength = <6>; + bias-pull-up; + }; + + wcss-wlan1-pins { + pins = "gpio77"; + function = "wcss_wlan1"; + drive-strength = <6>; + bias-pull-up; + }; + + wcss-wlan0-pins { + pins = "gpio78"; + function = "wcss_wlan0"; + drive-strength = <6>; + bias-pull-up; + }; + + wcss-wlan-pins { + pins = "gpio79", "gpio80"; + function = "wcss_wlan"; + drive-strength = <6>; + bias-pull-up; + }; + }; + + gpio_key_default: gpio-key-default-state { + pins = "gpio85"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + i2c_8_default: i2c-8-default-state { + pins = "gpio98", "gpio99"; + function = "blsp_i2c8"; + drive-strength = <2>; + bias-disable; + }; + + i2c_8_sleep: i2c-8-sleep-state { + pins = "gpio98", "gpio99"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + sdc2_cd_on: cd-on-state { + pins = "gpio133"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + sdc2_cd_off: cd-off-state { + pins = "gpio133"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + i2c_7_default: i2c-7-default-state { + pins = "gpio135", "gpio136"; + function = "blsp_i2c7"; + drive-strength = <2>; + bias-disable; + }; + + i2c_7_sleep: i2c-7-sleep-state { + pins = "gpio135", "gpio136"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + spi_7_default: spi-7-default-state { cs-pins { pins = "gpio136"; @@ -902,49 +878,86 @@ }; }; - uart_5_default: uart-5-default-state { - pins = "gpio16", "gpio17", "gpio18", "gpio19"; - function = "blsp_uart5"; + sdc1_clk_on: sdc1-clk-on-state { + pins = "sdc1_clk"; + bias-disable; drive-strength = <16>; + }; + + sdc1_clk_off: sdc1-clk-off-state { + pins = "sdc1_clk"; bias-disable; + drive-strength = <2>; }; - uart_5_sleep: uart-5-sleep-state { - pins = "gpio16", "gpio17", "gpio18", "gpio19"; - function = "gpio"; + sdc1_cmd_on: sdc1-cmd-on-state { + pins = "sdc1_cmd"; + bias-disable; + drive-strength = <10>; + }; + + sdc1_cmd_off: sdc1-cmd-off-state { + pins = "sdc1_cmd"; + bias-disable; drive-strength = <2>; + }; + + sdc1_data_on: sdc1-data-on-state { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sdc1_data_off: sdc1-data-off-state { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + + sdc1_rclk_on: sdc1-rclk-on-state { + pins = "sdc1_rclk"; + bias-pull-down; + }; + + sdc1_rclk_off: sdc1-rclk-off-state { + pins = "sdc1_rclk"; + bias-pull-down; + }; + + sdc2_clk_on: sdc2-clk-on-state { + pins = "sdc2_clk"; + drive-strength = <16>; bias-disable; }; - wcnss_pin_a: wcnss-active-state { + sdc2_clk_off: sdc2-clk-off-state { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; - wcss-wlan2-pins { - pins = "gpio76"; - function = "wcss_wlan2"; - drive-strength = <6>; - bias-pull-up; - }; + sdc2_cmd_on: sdc2-cmd-on-state { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; - wcss-wlan1-pins { - pins = "gpio77"; - function = "wcss_wlan1"; - drive-strength = <6>; - bias-pull-up; - }; + sdc2_cmd_off: sdc2-cmd-off-state { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; - wcss-wlan0-pins { - pins = "gpio78"; - function = "wcss_wlan0"; - drive-strength = <6>; - bias-pull-up; - }; + sdc2_data_on: sdc2-data-on-state { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; - wcss-wlan-pins { - pins = "gpio79", "gpio80"; - function = "wcss_wlan"; - drive-strength = <6>; - bias-pull-up; - }; + sdc2_data_off: sdc2-data-off-state { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; }; }; @@ -1201,6 +1214,49 @@ }; }; + cci: cci@1b0c000 { + compatible = "qcom,msm8953-cci"; + reg = <0x1b0c000 0x4000>; + + interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; + + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_CCI_AHB_CLK>, + <&gcc GCC_CAMSS_CCI_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>; + clock-names = "camss_top_ahb", + "cci_ahb", + "cci", + "camss_ahb"; + + assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>, + <&gcc GCC_CAMSS_CCI_CLK>; + assigned-clock-rates = <80000000>, + <19200000>; + + pinctrl-0 = <&cci0_default &cci1_default>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + gpu: gpu@1c00000 { compatible = "qcom,adreno-506.0", "qcom,adreno"; reg = <0x01c00000 0x40000>; diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi index f9962512f243..80a0a09e055d 100644 --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -1558,8 +1558,8 @@ "handover", "stop-ack"; - power-domains = <&rpmpd MSM8976_VDDCX>, - <&rpmpd MSM8976_VDDMX>; + power-domains = <&rpmpd RPMPD_VDDCX>, + <&rpmpd RPMPD_VDDMX>; power-domain-names = "cx", "mx"; qcom,smem-states = <&wcnss_smp2p_out 0>; diff --git a/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi b/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi index b8f2a01bcb96..1e718accf8f5 100644 --- a/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi @@ -24,7 +24,7 @@ chassis-type = "handset"; qcom,msm-id = <251 0>, <252 0>; - qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>; + qcom,pmic-id = <0x10009 0x1000a 0x0 0x0>; /* Bullhead firmware doesn't support PSCI */ /delete-node/ psci; diff --git a/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts b/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts index 1aca11daf83c..7775532f154e 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts +++ b/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts @@ -16,7 +16,7 @@ chassis-type = "handset"; /* required for bootloader to select correct board */ qcom,msm-id = <207 0x20000>; - qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>; + qcom,pmic-id = <0x10009 0x1000a 0x0 0x0>; qcom,board-id = <8026 0>; aliases { diff --git a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi index 4c983b10dd92..7ace3540ef0a 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi @@ -378,7 +378,7 @@ status = "okay"; sideinteraction: touch@2c { - compatible = "ad,ad7147_captouch"; + compatible = "adi,ad7147_captouch"; reg = <0x2c>; pinctrl-names = "default", "sleep"; diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 5c75fba16ce2..d41b5c470c48 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -1497,8 +1497,8 @@ qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; - power-domains = <&rpmpd MSM8998_VDDCX>, - <&rpmpd MSM8998_VDDMX>; + power-domains = <&rpmpd RPMPD_VDDCX>, + <&rpmpd RPMPD_VDDMX>; power-domain-names = "cx", "mx"; status = "disabled"; @@ -1544,7 +1544,7 @@ interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; iommus = <&adreno_smmu 0>; operating-points-v2 = <&gpu_opp_table>; - power-domains = <&rpmpd MSM8998_VDDMX>; + power-domains = <&rpmpd RPMPD_VDDMX>; status = "disabled"; gpu_opp_table: opp-table { @@ -1680,7 +1680,7 @@ qcom,smem-states = <&slpi_smp2p_out 0>; qcom,smem-state-names = "stop"; - power-domains = <&rpmpd MSM8998_SSCCX>; + power-domains = <&rpmpd RPMPD_SSCCX>; power-domain-names = "ssc_cx"; status = "disabled"; @@ -2871,7 +2871,7 @@ assigned-clock-rates = <19200000>; operating-points-v2 = <&mdp_opp_table>; - power-domains = <&rpmpd MSM8998_VDDMX>; + power-domains = <&rpmpd RPMPD_VDDMX>; mdp_opp_table: opp-table { compatible = "operating-points-v2"; @@ -2953,7 +2953,7 @@ <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; operating-points-v2 = <&dsi_opp_table>; - power-domains = <&rpmpd MSM8998_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; phys = <&mdss_dsi0_phy>; phy-names = "dsi"; @@ -3029,7 +3029,7 @@ <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; operating-points-v2 = <&dsi_opp_table>; - power-domains = <&rpmpd MSM8998_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; phys = <&mdss_dsi1_phy>; phy-names = "dsi"; @@ -3277,7 +3277,7 @@ qcom,smem-states = <&adsp_smp2p_out 0>; qcom,smem-state-names = "stop"; - power-domains = <&rpmpd MSM8998_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; power-domain-names = "cx"; status = "disabled"; diff --git a/arch/arm64/boot/dts/qcom/pm7550.dtsi b/arch/arm64/boot/dts/qcom/pm7550.dtsi new file mode 100644 index 000000000000..b886c2397fe7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm7550.dtsi @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com> + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/spmi/spmi.h> + +/ { + thermal-zones { + pm7550_thermal: pm7550-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&pm7550_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + /* + * Current Linux driver currently only supports up to + * 125°C, should be updated to 145°C once available. + */ + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus { + pm7550: pmic@1 { + compatible = "qcom,pm7550", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm7550_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm7550_gpios: gpio@8800 { + compatible = "qcom,pm7550-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pm7550_gpios 0 0 12>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pm7550_flash: led-controller@ee00 { + compatible = "qcom,pm7550-flash-led", "qcom,spmi-flash-led"; + reg = <0xee00>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pm8550vs.dtsi b/arch/arm64/boot/dts/qcom/pm8550vs.dtsi index 6426b431616b..7b5898c263ad 100644 --- a/arch/arm64/boot/dts/qcom/pm8550vs.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8550vs.dtsi @@ -98,6 +98,8 @@ #address-cells = <1>; #size-cells = <0>; + status = "disabled"; + pm8550vs_c_temp_alarm: temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; reg = <0xa00>; @@ -122,6 +124,8 @@ #address-cells = <1>; #size-cells = <0>; + status = "disabled"; + pm8550vs_d_temp_alarm: temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; reg = <0xa00>; @@ -146,6 +150,8 @@ #address-cells = <1>; #size-cells = <0>; + status = "disabled"; + pm8550vs_e_temp_alarm: temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; reg = <0xa00>; @@ -170,6 +176,8 @@ #address-cells = <1>; #size-cells = <0>; + status = "disabled"; + pm8550vs_g_temp_alarm: temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; reg = <0xa00>; diff --git a/arch/arm64/boot/dts/qcom/pmiv0104.dtsi b/arch/arm64/boot/dts/qcom/pmiv0104.dtsi new file mode 100644 index 000000000000..85ee8911d93e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmiv0104.dtsi @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com> + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/spmi/spmi.h> + +/ { + thermal-zones { + pmiv0104-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&pmiv0104_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + /* + * Current Linux driver currently only supports up to + * 125°C, should be updated to 145°C once available. + */ + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus { + pmic@PMIV0104_SID { + compatible = "qcom,pmiv0104", "qcom,spmi-pmic"; + reg = <PMIV0104_SID SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmiv0104_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <PMIV0104_SID 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmiv0104_gpios: gpio@8800 { + compatible = "qcom,pmiv0104-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmiv0104_gpios 0 0 10>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pmiv0104_eusb2_repeater: phy@fd00 { + compatible = "qcom,pmiv0104-eusb2-repeater"; + reg = <0xfd00>; + #phy-cells = <0>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts index be67eb173046..5a24c19c415e 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -39,6 +39,20 @@ }; }; + dp0-connector { + compatible = "dp-connector"; + label = "DP0"; + type = "mini"; + + hpd-gpios = <&io_expander 8 GPIO_ACTIVE_HIGH>; + + port { + dp0_connector_in: endpoint { + remote-endpoint = <&mdss_dp0_out>; + }; + }; + }; + dp-dsi0-connector { compatible = "dp-connector"; label = "DSI0"; @@ -423,6 +437,15 @@ status = "okay"; }; +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000>; + remote-endpoint = <&dp0_connector_in>; +}; + &mdss_dsi0 { vdda-supply = <&vreg_l11a>; status = "okay"; @@ -624,6 +647,13 @@ status = "okay"; }; +&usb_qmpphy_2 { + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l12a>; + + status = "okay"; +}; + &usb_1 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index f29a352b0288..e3d2f01881ae 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -262,6 +262,30 @@ }; }; + vdd_ntn_0p9: regulator-vdd-ntn-0p9 { + compatible = "regulator-fixed"; + regulator-name = "VDD_NTN_0P9"; + gpio = <&pm8350c_gpios 2 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <899400>; + regulator-max-microvolt = <899400>; + enable-active-high; + pinctrl-0 = <&ntn_0p9_en>; + pinctrl-names = "default"; + regulator-enable-ramp-delay = <4300>; + }; + + vdd_ntn_1p8: regulator-vdd-ntn-1p8 { + compatible = "regulator-fixed"; + regulator-name = "VDD_NTN_1P8"; + gpio = <&pm8350c_gpios 3 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + pinctrl-0 = <&ntn_1p8_en>; + pinctrl-names = "default"; + regulator-enable-ramp-delay = <10000>; + }; + wcn6750-pmu { compatible = "qcom,wcn6750-pmu"; pinctrl-0 = <&bt_en>; @@ -803,6 +827,78 @@ status = "okay"; }; +&pcie1_port0 { + pcie@0,0 { + compatible = "pci1179,0623"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x2 0xff>; + + vddc-supply = <&vdd_ntn_0p9>; + vdd18-supply = <&vdd_ntn_1p8>; + vdd09-supply = <&vdd_ntn_0p9>; + vddio1-supply = <&vdd_ntn_1p8>; + vddio2-supply = <&vdd_ntn_1p8>; + vddio18-supply = <&vdd_ntn_1p8>; + + i2c-parent = <&i2c0 0x77>; + + resx-gpios = <&pm8350c_gpios 1 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&tc9563_resx_n>; + pinctrl-names = "default"; + + pcie@1,0 { + reg = <0x20800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x3 0xff>; + }; + + pcie@2,0 { + reg = <0x21000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x4 0xff>; + }; + + pcie@3,0 { + reg = <0x21800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + bus-range = <0x5 0xff>; + + pci@0,0 { + reg = <0x50000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + }; + + pci@0,1 { + reg = <0x50100 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + }; + }; + }; +}; + &pm7325_gpios { kypd_vol_up_n: kypd-vol-up-n-state { pins = "gpio6"; @@ -1081,6 +1177,38 @@ }; }; +&pm8350c_gpios { + ntn_0p9_en: ntn-0p9-en-state { + pins = "gpio2"; + function = "normal"; + + bias-disable; + input-disable; + output-enable; + power-source = <0>; + }; + + ntn_1p8_en: ntn-1p8-en-state { + pins = "gpio3"; + function = "normal"; + + bias-disable; + input-disable; + output-enable; + power-source = <0>; + }; + + tc9563_resx_n: tc9563-resx-state { + pins = "gpio1"; + function = "normal"; + + bias-disable; + input-disable; + output-enable; + power-source = <0>; + }; +}; + &tlmm { gpio-reserved-ranges = <32 2>, /* ADSP */ <48 4>; /* NFC */ diff --git a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts new file mode 100644 index 000000000000..0b64a0b91202 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts @@ -0,0 +1,1410 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025, Thundercomm All rights reserved. + */ + +/dts-v1/; + +/* PM7250B is configured to use SID8/9 */ +#define PM7250B_SID 8 +#define PM7250B_SID1 9 + +#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h> +#include <dt-bindings/iio/qcom,spmi-adc7-pm7325.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include "kodiak.dtsi" +#include "pm7250b.dtsi" +#include "pm7325.dtsi" +#include "pm8350c.dtsi" /* PM7350C */ +#include "pmk8350.dtsi" /* PMK7325 */ + +/delete-node/ &adsp_mem; +/delete-node/ &cdsp_mem; +/delete-node/ &ipa_fw_mem; +/delete-node/ &mpss_mem; +/delete-node/ &remoteproc_mpss; +/delete-node/ &remoteproc_wpss; +/delete-node/ &rmtfs_mem; +/delete-node/ &video_mem; +/delete-node/ &wifi; +/delete-node/ &wlan_ce_mem; +/delete-node/ &wlan_fw_mem; +/delete-node/ &wpss_mem; +/delete-node/ &xbl_mem; + +/ { + model = "Thundercomm RUBIK Pi 3"; + compatible = "thundercomm,rubikpi3", "qcom,qcm6490"; + chassis-type = "embedded"; + + aliases { + serial0 = &uart5; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&kypd_vol_up_n>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume Up"; + gpios = <&pm7325_gpios 6 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + linux,can-disable; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <<9611_out>; + }; + }; + }; + + pmic-glink { + compatible = "qcom,qcm6490-pmic-glink", "qcom,pmic-glink"; + + #address-cells = <1>; + #size-cells = <0>; + orientation-gpios = <&tlmm 140 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&usb_dp_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_sbu_in: endpoint { + remote-endpoint = <&usb1_sbu_mux>; + }; + }; + }; + }; + }; + + fan0: pwm-fan { + compatible = "pwm-fan"; + + /* cooling level (0, 1, 2, 3) : (0% duty, 25% duty, 50% duty, 100% duty) */ + cooling-levels = <0 64 128 255>; + #cooling-cells = <2>; + pwms = <&pm8350c_pwm 3 1000000>; + + pinctrl-0 = <&fan_pwm_out_default>; + pinctrl-names = "default"; + }; + + vreg_eth_1v8: regulator-eth-1v8 { + compatible = "regulator-fixed"; + + regulator-name = "vreg_eth_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <50000>; + + gpio = <&tlmm 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb_eth_power>; + pinctrl-names = "default"; + + vin-supply = <&vreg_usbhub_pwr_1v8>; + }; + + vreg_lt9611_3v3: regulator-lt9611-3v3 { + compatible = "regulator-fixed"; + + regulator-name = "vreg_lt9611_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 83 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <<9611_vcc_pin>; + pinctrl-names = "default"; + }; + + vreg_m2_1v8: regulator-m2-1v8 { + compatible = "regulator-fixed"; + + regulator-name = "vreg_m2_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <50000>; + + gpio = <&tlmm 56 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&m2_vcc_pin>; + pinctrl-names = "default"; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_usbhub_pwr_1v8: regulator-usbhub-pwr-1v8 { + compatible = "regulator-fixed"; + + regulator-name = "vreg_usbhub_pwr_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <50000>; + + gpio = <&tlmm 86 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usbhub_power>; + pinctrl-names = "default"; + + regulator-always-on; + }; + + vreg_usbhub_rest_1v8: regulator-usbhub-rest-1v8 { + compatible = "regulator-fixed"; + + regulator-name = "vreg_usbhub_rest_1v8"; + regulator-min-microvolt = <1800000>; + regulator-enable-ramp-delay = <50000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 136 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usbhub_rest>; + pinctrl-names = "default"; + + vin-supply = <&vreg_eth_1v8>; + + regulator-always-on; + regulator-boot-on; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + vreg_wifi_1v8: regulator-wifi-1v8 { + compatible = "regulator-fixed"; + + regulator-name = "vreg_wifi_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <50000>; + + gpio = <&tlmm 125 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wifi_reset_active>, + <&wifi_host_wake>, + <&wifi_power_on>; + pinctrl-names = "default"; + + regulator-always-on; + }; + + reserved-memory { + xbl_mem: xbl@80700000 { + reg = <0x0 0x80700000 0x0 0x100000>; + no-map; + }; + + cdsp_secure_heap_mem: cdsp-secure-heap@81800000 { + reg = <0x0 0x81800000 0x0 0x1e00000>; + no-map; + }; + + camera_mem: camera@84300000 { + reg = <0x0 0x84300000 0x0 0x500000>; + no-map; + }; + + adsp_mem: adsp@86100000 { + reg = <0x0 0x86100000 0x0 0x2800000>; + no-map; + }; + + cdsp_mem: cdsp@88900000 { + reg = <0x0 0x88900000 0x0 0x1e00000>; + no-map; + }; + + video_mem: video@8a700000 { + reg = <0x0 0x8a700000 0x0 0x700000>; + no-map; + }; + + cvp_mem: cvp@8ae00000 { + reg = <0x0 0x8ae00000 0x0 0x500000>; + no-map; + }; + + gpu_microcode_mem: gpu-microcode@8b31a000 { + reg = <0x0 0x8b31a000 0x0 0x2000>; + no-map; + }; + + tz_stat_mem: tz-stat@c0000000 { + reg = <0x0 0xc0000000 0x0 0x100000>; + no-map; + }; + + tags_mem: tags@c0100000 { + reg = <0x0 0xc0100000 0x0 0x1200000>; + no-map; + }; + + qtee_mem: qtee@c1300000 { + reg = <0x0 0xc1300000 0x0 0x500000>; + no-map; + }; + + trusted_apps_mem: trusted-apps@c1800000 { + reg = <0x0 0xc1800000 0x0 0x1c00000>; + no-map; + }; + + debug_vm_mem: debug-vm@d0600000 { + reg = <0x0 0xd0600000 0x0 0x100000>; + no-map; + }; + }; + + thermal-zones { + quiet-thermal { + thermal-sensors = <&pmk8350_adc_tm 1>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sdm-skin-thermal { + thermal-sensors = <&pmk8350_adc_tm 3>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + xo-thermal { + thermal-sensors = <&pmk8350_adc_tm 0>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + }; + + usb1-sbu-mux { + compatible = "pericom,pi3usb102", "gpio-sbu-mux"; + + enable-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; + select-gpios = <&tlmm 52 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&usb1_sbu_default>; + pinctrl-names = "default"; + + mode-switch; + orientation-switch; + + port { + usb1_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_sbu_in>; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm7325-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-l1-l4-l12-l15-supply = <&vreg_s7b_0p972>; + vdd-l2-l7-supply = <&vreg_bob_3p296>; + vdd-l3-supply = <&vreg_s2b_0p876>; + vdd-l5-supply = <&vreg_s2b_0p876>; + vdd-l6-l9-l10-supply = <&vreg_s8b_1p272>; + vdd-l8-supply = <&vreg_s7b_0p972>; + vdd-l11-l17-l18-l19-supply = <&vreg_s1b_1p872>; + vdd-l13-supply = <&vreg_s7b_0p972>; + vdd-l14-l16-supply = <&vreg_s8b_1p272>; + + vreg_s1b_1p872: smps1 { + regulator-name = "vreg_s1b_1p872"; + regulator-min-microvolt = <1840000>; + regulator-max-microvolt = <2040000>; + }; + + vreg_s2b_0p876: smps2 { + regulator-name = "vreg_s2b_0p876"; + regulator-min-microvolt = <570070>; + regulator-max-microvolt = <1050000>; + }; + + vreg_s7b_0p972: smps7 { + regulator-name = "vreg_s7b_0p972"; + regulator-min-microvolt = <535000>; + regulator-max-microvolt = <1120000>; + }; + + vreg_s8b_1p272: smps8 { + regulator-name = "vreg_s8b_1p272"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1500000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_RET>; + }; + + vreg_l1b_0p912: ldo1 { + regulator-name = "vreg_l1b_0p912"; + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <925000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2b_3p072: ldo2 { + regulator-name = "vreg_l2b_3p072"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3b_0p504: ldo3 { + regulator-name = "vreg_l3b_0p504"; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <910000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4b_0p752: ldo4 { + regulator-name = "vreg_l4b_0p752"; + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <820000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + reg_l5b_0p752: ldo5 { + regulator-name = "reg_l5b_0p752"; + regulator-min-microvolt = <552000>; + regulator-max-microvolt = <832000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6b_1p2: ldo6 { + regulator-name = "vreg_l6b_1p2"; + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7b_2p952: ldo7 { + regulator-name = "vreg_l7b_2p952"; + regulator-min-microvolt = <2952000>; + regulator-max-microvolt = <2952000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8b_0p904: ldo8 { + regulator-name = "vreg_l8b_0p904"; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <970000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l9b_1p2: ldo9 { + regulator-name = "vreg_l9b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l11b_1p504: ldo11 { + regulator-name = "vreg_l11b_1p504"; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l12b_0p751: ldo12 { + regulator-name = "vreg_l12b_0p751"; + regulator-min-microvolt = <751000>; + regulator-max-microvolt = <824000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l13b_0p53: ldo13 { + regulator-name = "vreg_l13b_0p53"; + regulator-min-microvolt = <530000>; + regulator-max-microvolt = <824000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l14b_1p08: ldo14 { + regulator-name = "vreg_l14b_1p08"; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l15b_0p765: ldo15 { + regulator-name = "vreg_l15b_0p765"; + regulator-min-microvolt = <765000>; + regulator-max-microvolt = <1020000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l16b_1p1: ldo16 { + regulator-name = "vreg_l16b_1p1"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l17b_1p7: ldo17 { + regulator-name = "vreg_l17b_1p7"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l18b_1p8: ldo18 { + regulator-name = "vreg_l18b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l19b_1p8: ldo19 { + regulator-name = "vreg_l19b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-1 { + compatible = "qcom,pm8350c-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-l1-l12-supply = <&vreg_s1b_1p872>; + vdd-l2-l8-supply = <&vreg_s1b_1p872>; + vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob_3p296>; + vdd-l6-l9-l11-supply = <&vreg_bob_3p296>; + vdd-l10-supply = <&vreg_s7b_0p972>; + vdd-bob-supply = <&vph_pwr>; + + vreg_s1c_2p19: smps1 { + regulator-name = "vreg_s1c_2p19"; + regulator-min-microvolt = <2190000>; + regulator-max-microvolt = <2210000>; + }; + + vreg_s2c_0p752: smps2 { + regulator-name = "vreg_s2c_0p752"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <800000>; + }; + + vreg_s5c_0p752: smps5 { + regulator-name = "vreg_s5c_0p752"; + regulator-min-microvolt = <465000>; + regulator-max-microvolt = <1050000>; + }; + + vreg_s7c_0p752: smps7 { + regulator-name = "vreg_s7c_0p752"; + regulator-min-microvolt = <465000>; + regulator-max-microvolt = <800000>; + }; + + vreg_s9c_1p084: smps9 { + regulator-name = "vreg_s9c_1p084"; + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1170000>; + }; + + vreg_l1c_1p8: ldo1 { + regulator-name = "vreg_l1c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1980000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2c_1p62: ldo2 { + regulator-name = "vreg_l2c_1p62"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3c_2p8: ldo3 { + regulator-name = "vreg_l3c_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3540000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4c_1p62: ldo4 { + regulator-name = "vreg_l4c_1p62"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5c_1p62: ldo5 { + regulator-name = "vreg_l5c_1p62"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6c_2p96: ldo6 { + regulator-name = "vreg_l6c_2p96"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7c_3p0: ldo7 { + regulator-name = "vreg_l7c_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8c_1p62: ldo8 { + regulator-name = "vreg_l8c_1p62"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l9c_2p96: ldo9 { + regulator-name = "vreg_l9c_2p96"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l10c_0p88: ldo10 { + regulator-name = "vreg_l10c_0p88"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1050000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l11c_2p8: ldo11 { + regulator-name = "vreg_l11c_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l12c_1p65: ldo12 { + regulator-name = "vreg_l12c_1p65"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l13c_2p7: ldo13 { + regulator-name = "vreg_l13c_2p7"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_bob_3p296: bob { + regulator-name = "vreg_bob_3p296"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + }; + }; +}; + +&gcc { + protected-clocks = <GCC_CFG_NOC_LPASS_CLK>, + <GCC_MSS_CFG_AHB_CLK>, + <GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC>, + <GCC_MSS_OFFLINE_AXI_CLK>, + <GCC_MSS_Q6SS_BOOT_CLK_SRC>, + <GCC_MSS_Q6_MEMNOC_AXI_CLK>, + <GCC_MSS_SNOC_AXI_CLK>, + <GCC_QSPI_CNOC_PERIPH_AHB_CLK>, + <GCC_QSPI_CORE_CLK>, + <GCC_QSPI_CORE_CLK_SRC>, + <GCC_SEC_CTRL_CLK_SRC>, + <GCC_WPSS_AHB_BDG_MST_CLK>, + <GCC_WPSS_AHB_CLK>, + <GCC_WPSS_RSCP_CLK>; +}; + +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/qcs6490/a660_zap.mbn"; +}; + +/* Pin 3, 5 in 40-pin connector */ +&i2c1 { + status = "okay"; +}; + +&i2c9 { + clock-frequency = <400000>; + + status = "okay"; + + lt9611_codec: hdmi-bridge@39 { + compatible = "lontium,lt9611"; + reg = <0x39>; + + interrupts-extended = <&tlmm 20 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>; + + vdd-supply = <&vreg_lt9611_3v3>; + vcc-supply = <&vreg_lt9611_3v3>; + + pinctrl-0 = <<9611_irq_pin>, + <<9611_rst_pin>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lt9611_a: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@2 { + reg = <2>; + + lt9611_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; +}; + +&lpass_audiocc { + compatible = "qcom,qcm6490-lpassaudiocc"; + /delete-property/ power-domains; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp { + status = "okay"; +}; + +&mdss_dp_out { + data-lanes = <0 1>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&usb_dp_qmpphy_dp_in>; +}; + +&mdss_dsi { + vdda-supply = <&vreg_l6b_1p2>; + + status = "okay"; +}; + +&mdss_dsi0_out { + remote-endpoint = <<9611_a>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi_phy { + vdds-supply = <&vreg_l10c_0p88>; + + status = "okay"; +}; + +&pcie0 { + perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&pcie0_clkreq_n>, + <&pcie0_reset_n>, + <&pcie0_wake_n>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l10c_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + + status = "okay"; +}; + +&pcie1 { + perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie1_clkreq_n>, + <&pcie1_reset_n>, + <&pcie1_wake_n>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l10c_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + + status = "okay"; +}; + +&pm7325_gpios { + kypd_vol_up_n: kypd-vol-up-n-state { + pins = "gpio6"; + function = PMIC_GPIO_FUNC_NORMAL; + power-source = <1>; + bias-pull-up; + input-enable; + }; +}; + +&pm7325_temp_alarm { + io-channels = <&pmk8350_vadc PM7325_ADC7_DIE_TEMP>; + io-channel-names = "thermal"; +}; + +&pmk8350_adc_tm { + status = "okay"; + + xo-therm@0 { + reg = <0>; + io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + quiet-therm@1 { + reg = <1>; + io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + sdm-skin-therm@3 { + reg = <3>; + io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + +&pm8350c_pwm { + status = "okay"; + + multi-led { + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_INDICATOR; + + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = <LED_COLOR_ID_RED>; + }; + + led@2 { + reg = <2>; + color = <LED_COLOR_ID_GREEN>; + }; + + led@3 { + reg = <3>; + color = <LED_COLOR_ID_BLUE>; + }; + }; +}; + +&pmk8350_rtc { + allow-set-time; + + status = "okay"; +}; + +&pmk8350_vadc { + channel@3 { + reg = <PMK8350_ADC7_DIE_TEMP>; + label = "pmk8350_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@44 { + reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>; + label = "xo_therm"; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,ratiometric; + }; + + channel@103 { + reg = <PM7325_ADC7_DIE_TEMP>; + label = "pm7325_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@144 { + reg = <PM7325_ADC7_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "pm7325_quiet_therm"; + }; + + channel@146 { + reg = <PM7325_ADC7_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "pm7325_sdm_skin_therm"; + }; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = <KEY_VOLUMEDOWN>; + + status = "okay"; +}; + +&qupv3_id_0 { + firmware-name = "qcom/qcm6490/qupv3fw.elf"; + + status = "okay"; +}; + +&qupv3_id_1 { + firmware-name = "qcom/qcm6490/qupv3fw.elf"; + + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/qcs6490/Thundercomm/RubikPi3/adsp.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/qcs6490/cdsp.mbn"; + + status = "okay"; +}; + +/* WIFI part of the AP6256 connected with SDIO */ +&sdhc_2 { + vmmc-supply = <&vreg_l9c_2p96>; + vqmmc-supply = <&vreg_l6c_2p96>; + + non-removable; + keep-power-in-suspend; + /delete-property/ cd-gpios; + + status = "okay"; +}; + +/* Pin 19, 21, 23, 24 in 40-pin connector */ +&spi12 { + status = "okay"; +}; + +&thermal_zones { + cpu0-thermal { + trips { + cpu_tepid: cpu-tepid { + temperature = <65000>; + hysteresis = <5000>; + type = "active"; + }; + + cpu_warm: cpu-warm { + temperature = <80000>; + hysteresis = <5000>; + type = "active"; + }; + }; + + cooling-maps { + map-cpu-tepid { + cooling-device = <&fan0 1 1>; + trip = <&cpu_tepid>; + }; + + map-cpu-warm { + cooling-device = <&fan0 2 2>; + trip = <&cpu_warm>; + }; + + map-cpu-hot { + cooling-device = <&fan0 3 3>; + trip = <&cpu0_alert0>; + }; + }; + }; +}; + +/* Pin 8, 10 in 40-pin connector */ +&uart2 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +/* BT part of the AP6256 connected with UART */ +&uart7 { + /delete-property/ interrupts; + interrupts-extended = <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 31 IRQ_TYPE_EDGE_FALLING>; + pinctrl-1 = <&qup_uart7_sleep_cts>, + <&qup_uart7_sleep_rts>, + <&qup_uart7_sleep_tx>, + <&qup_uart7_sleep_rx>; + pinctrl-names = "default", + "sleep"; + + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4345c5"; + clocks = <&sleep_clk>; + clock-names = "lpo"; + device-wakeup-gpios = <&tlmm 39 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&tlmm 137 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&tlmm 17 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&bt_device_wake>, + <&bt_host_wake>, + <&bt_reset>; + pinctrl-names = "default"; + vbat-supply = <&vreg_wifi_1v8>; + vddio-supply = <&vreg_wifi_1v8>; + max-speed = <3000000>; + }; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_1_hsphy { + vdda-pll-supply = <&vreg_l10c_0p88>; + vdda33-supply = <&vreg_l2b_3p072>; + vdda18-supply = <&vreg_l1c_1p8>; + + status = "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply = <&vreg_l6b_1p2>; + vdda-pll-supply = <&vreg_l1b_0p912>; + + status = "okay"; +}; + +&usb_2 { + dr_mode = "host"; + + status = "okay"; +}; + +&usb_2_hsphy { + vdda-pll-supply = <&vreg_l10c_0p88>; + vdda18-supply = <&vreg_l1c_1p8>; + vdda33-supply = <&vreg_l2b_3p072>; + + status = "okay"; +}; + +&usb_dp_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in>; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; + vcc-supply = <&vreg_l7b_2p952>; + vcc-max-microamp = <800000>; + vccq-supply = <&vreg_l9b_1p2>; + vccq-max-microamp = <900000>; + vccq2-supply = <&vreg_l9b_1p2>; + vccq2-max-microamp = <900000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l10c_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + + status = "okay"; +}; + +&venus { + status = "okay"; +}; + +/* PINCTRL - additions to nodes defined in kodiak.dtsi */ +&pcie0_clkreq_n { + bias-pull-up; + drive-strength = <8>; +}; + +&pcie1_clkreq_n { + bias-pull-up; + drive-strength = <8>; +}; + +&pm8350c_gpios { + fan_pwm_out_default: fan-pwm-out-default-state { + pins = "gpio8"; + function = "func1"; + power-source = <1>; + drive-push-pull; + output-high; + qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; + }; +}; + +&qup_uart7_cts { + /* + * Configure a bias-bus-hold on CTS to lower power + * usage when Bluetooth is turned off. Bus hold will + * maintain a low power state regardless of whether + * the Bluetooth module drives the pin in either + * direction or leaves the pin fully unpowered. + */ + bias-bus-hold; +}; + +&qup_uart7_rts { + /* We'll drive RTS, so no pull */ + bias-disable; + drive-strength = <2>; +}; + +&qup_uart7_rx { + /* + * Configure a pull-up on RX. This is needed to avoid + * garbage data when the TX pin of the Bluetooth module is + * in tri-state (module powered off or not driving the + * signal yet). + */ + bias-pull-up; +}; + +&qup_uart7_tx { + /* We'll drive TX, so no pull */ + bias-disable; + drive-strength = <2>; +}; + +&sdc2_clk { + bias-disable; + drive-strength = <16>; +}; + +&sdc2_cmd { + bias-pull-up; + drive-strength = <10>; +}; + +&sdc2_data { + bias-pull-up; + drive-strength = <10>; +}; + +&tlmm { + pcie1_reset_n: pcie1-reset-n-state { + pins = "gpio2"; + function = "gpio"; + drive-strength = <8>; + output-low; + bias-disable; + }; + + pcie1_wake_n: pcie1-wake-n-state { + pins = "gpio3"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + usb_eth_power: usb-eth-power-state { + pins = "gpio7"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + wifi_reset_active: wifi-reset-active-state { + pins = "gpio16"; + function = "gpio"; + drive-strength = <8>; + output-high; + bias-disable; + }; + + bt_reset: bt-reset-state { + pins = "gpio17"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + lt9611_irq_pin: lt9611-irq-state { + pins = "gpio20"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + lt9611_rst_pin: lt9611-rst-state { + pins = "gpio21"; + function = "gpio"; + drive-strength = <8>; + output-high; + input-disable; + }; + + qup_uart7_sleep_cts: qup-uart7-sleep-cts-state { + pins = "gpio28"; + function = "gpio"; + /* + * Configure a bias-bus-hold on CTS to lower power + * usage when Bluetooth is turned off. Bus hold will + * maintain a low power state regardless of whether + * the Bluetooth module drives the pin in either + * direction or leaves the pin fully unpowered. + */ + bias-bus-hold; + }; + + qup_uart7_sleep_rts: qup-uart7-sleep-rts-state { + pins = "gpio29"; + function = "gpio"; + /* + * Configure pull-down on RTS. As RTS is active low + * signal, pull it low to indicate the BT SoC that it + * can wakeup the system anytime from suspend state by + * pulling RX low (by sending wakeup bytes). + */ + bias-pull-down; + }; + + qup_uart7_sleep_tx: qup-uart7-sleep-tx-state { + pins = "gpio30"; + function = "gpio"; + /* + * Configure pull-up on TX when it isn't actively driven + * to prevent BT SoC from receiving garbage during sleep. + */ + bias-pull-up; + }; + + qup_uart7_sleep_rx: qup-uart7-sleep-rx-state { + pins = "gpio31"; + function = "gpio"; + /* + * Configure a pull-up on RX. This is needed to avoid + * garbage data when the TX pin of the Bluetooth module + * is floating which may cause spurious wakeups. + */ + bias-pull-up; + }; + + wifi_host_wake: wifi-host-wake-state { + pins = "gpio38"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + bt_device_wake: bt-device-wake-state { + pins = "gpio39"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + usb1_sbu_default: usb1-sbu-state { + sel-pins { + pins = "gpio52"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + oe-n-pins { + pins = "gpio53"; + function = "gpio"; + drive-strength = <8>; + output-high; + bias-disable; + }; + }; + + m2_vcc_pin: m2-vcc-state { + pins = "gpio56"; + function = "gpio"; + drive-strength = <8>; + output-high; + input-disable; + }; + + lt9611_vcc_pin: lt9611-vcc-pin-state { + pins = "gpio83"; + function = "gpio"; + drive-strength = <8>; + output-high; + input-disable; + }; + + usbhub_power: usbhub-power-state { + pins = "gpio86"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + pcie0_reset_n: pcie0-reset-n-state { + pins = "gpio87"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + pcie0_wake_n: pcie0-wake-n-state { + pins = "gpio89"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + wifi_power_on: wifi-power-on-state { + pins = "gpio125"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + usbhub_rest: usbhub-reset-state { + pins = "gpio136"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + bt_host_wake: bt-host-wake-state { + pins = "gpio137"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts index 9bcb869dd270..c04e0ad53eec 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts @@ -24,6 +24,18 @@ stdout-path = "serial0:115200n8"; }; + dp0-connector { + compatible = "dp-connector"; + label = "DP0"; + type = "full-size"; + + port { + dp0_connector_in: endpoint { + remote-endpoint = <&mdss_dp0_out>; + }; + }; + }; + regulator-usb2-vbus { compatible = "regulator-fixed"; regulator-name = "USB2_VBUS"; @@ -317,6 +329,68 @@ status = "okay"; }; +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + pinctrl-0 = <&dp_hot_plug_det>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&mdss_dp0_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + remote-endpoint = <&dp0_connector_in>; +}; + +&mdss_dp0_phy { + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l4a>; + + status = "okay"; +}; + +&pcie0 { + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcieport0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l6a>; + vdda-pll-supply = <&vreg_l5a>; + + status = "okay"; +}; + +&pcie1 { + pinctrl-0 = <&pcie1_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcieport1 { + reset-gpios = <&tlmm 23 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l6a>; + vdda-pll-supply = <&vreg_l5a>; + + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; }; @@ -362,6 +436,29 @@ }; &tlmm { + pcie0_default_state: pcie0-default-state { + wake-pins { + pins = "gpio0"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + clkreq-pins { + pins = "gpio1"; + function = "pcie0_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-pins { + pins = "gpio2"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; + ethernet0_default: ethernet0-default-state { ethernet0_mdc: ethernet0-mdc-pins { pins = "gpio5"; @@ -377,6 +474,35 @@ bias-pull-up; }; }; + + pcie1_default_state: pcie1-default-state { + wake-pins { + pins = "gpio21"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + clkreq-pins { + pins = "gpio22"; + function = "pcie1_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-pins { + pins = "gpio23"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + dp_hot_plug_det: dp-hot-plug-det-state { + pins = "gpio94"; + function = "edp0_hot"; + bias-disable; + }; }; &uart7 { diff --git a/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi index e6ac529e6b72..e6ebb643203b 100644 --- a/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi @@ -366,6 +366,22 @@ vdd3-supply = <&vreg_l5b_3p1>; }; +&pm8550vs_c { + status = "okay"; +}; + +&pm8550vs_d { + status = "okay"; +}; + +&pm8550vs_e { + status = "okay"; +}; + +&pm8550vs_g { + status = "okay"; +}; + &sleep_clk { clock-frequency = <32764>; }; diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi index 846e5e5899aa..cdfe40da5d33 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -1592,7 +1592,7 @@ gem_noc: interconnect@19100000 { compatible = "qcom,qdu1000-gem-noc"; - reg = <0x0 0x19100000 0x0 0xB8080>; + reg = <0x0 0x19100000 0x0 0xb8080>; qcom,bcm-voters = <&apps_bcm_voter>; #interconnect-cells = <2>; }; diff --git a/arch/arm64/boot/dts/qcom/qrb2210-arduino-imola.dts b/arch/arm64/boot/dts/qcom/qrb2210-arduino-imola.dts new file mode 100644 index 000000000000..197ab6eb1666 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qrb2210-arduino-imola.dts @@ -0,0 +1,459 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2025, Arduino SRL + */ + +/dts-v1/; + +#include <dt-bindings/leds/common.h> +#include "agatti.dtsi" +#include "pm4125.dtsi" + +/delete-node/ &cont_splash_memory; + +/ { + model = "Arduino UnoQ"; + compatible = "arduino,imola", "qcom,qrb2210", "qcom,qcm2290"; + chassis-type = "embedded"; + + aliases { + serial0 = &uart4; + serial1 = &uart2; + serial2 = &uart3; + sdhc1 = &sdhc_1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + pinctrl-0 = <&key_volp_n>, <&key_vold_n>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + + key-volume-down { + label = "Volume Down"; + linux,code = <KEY_VOLUMEDOWN>; + gpios = <&tlmm 36 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + + led-bt { + label = "unoq:bt-blue2"; + function = LED_FUNCTION_BLUETOOTH; + color = <LED_COLOR_ID_BLUE>; + gpios = <&tlmm 47 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "bluetooth-power"; + default-state = "off"; + }; + + led-panic { + label = "unoq:panic-red2"; + function = LED_FUNCTION_INDICATOR; + color = <LED_COLOR_ID_RED>; + gpios = <&tlmm 39 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + default-state = "off"; + panic-indicator; + }; + + led-wlan { + label = "unoq:wlan-green2"; + function = LED_FUNCTION_WLAN; + color = <LED_COLOR_ID_GREEN>; + gpios = <&tlmm 40 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tx"; + default-state = "off"; + }; + + ledb: led-user-blue { + label = "unoq:user-blue1"; + gpios = <&tlmm 60 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_BLUE>; + }; + + ledg: led-user-green { + label = "unoq:user-green1"; + gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_GREEN>; + }; + + ledr: led-user-red { + label = "unoq:user-red1"; + gpios = <&tlmm 41 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_RED>; + }; + }; + + multi-led { + compatible = "leds-group-multicolor"; + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_INDICATOR; + leds = <&ledr>, <&ledg>, <&ledb>; + }; + + /* PM4125 charger out, supplied by VBAT */ + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&gpi_dma0 { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/qcm2290/a702_zap.mbn"; +}; + +&i2c0 { + clock-frequency = <100000>; + + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + + status = "okay"; +}; + +&pm4125_vbus { + regulator-min-microamp = <500000>; + regulator-max-microamp = <500000>; + + status = "okay"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/qcm2290/adsp.mbn"; + + status = "okay"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/qcm2290/modem.mbn"; + + status = "okay"; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-pm2250-regulators"; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12-supply = <&pm4125_s3>; + vdd_l4_l17_l18_l19_l20_l21_l22-supply = <&vph_pwr>; + vdd_l13_l14_l15_l16-supply = <&pm4125_s4>; + + pm4125_s3: s3 { + /* 0.4V-1.6625V -> 1.3V (Power tree requirements) */ + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + regulator-boot-on; + }; + + pm4125_s4: s4 { + /* 1.2V-2.35V -> 2.05V (Power tree requirements) */ + regulator-min-microvolt = <2072000>; + regulator-max-microvolt = <2072000>; + regulator-boot-on; + }; + + pm4125_l2: l2 { + /* LPDDR4X VDD2 */ + regulator-min-microvolt = <1136000>; + regulator-max-microvolt = <1136000>; + regulator-always-on; + regulator-boot-on; + }; + + pm4125_l3: l3 { + /* LPDDR4X VDDQ */ + regulator-min-microvolt = <616000>; + regulator-max-microvolt = <616000>; + regulator-always-on; + regulator-boot-on; + }; + + pm4125_l4: l4 { + /* max = 3.05V -> max = 2.7 to disable 3V signaling (SDHCI2) */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2700000>; + regulator-allow-set-load; + }; + + pm4125_l5: l5 { + /* CSI/DSI */ + regulator-min-microvolt = <1232000>; + regulator-max-microvolt = <1232000>; + regulator-allow-set-load; + regulator-boot-on; + }; + + pm4125_l6: l6 { + /* DRAM PLL */ + regulator-min-microvolt = <928000>; + regulator-max-microvolt = <928000>; + regulator-always-on; + regulator-boot-on; + }; + + pm4125_l7: l7 { + /* Wi-Fi CX */ + regulator-min-microvolt = <664000>; + regulator-max-microvolt = <664000>; + }; + + pm4125_l10: l10 { + /* Wi-Fi RFA */ + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + }; + + pm4125_l11: l11 { + /* ANX7625 DVDD1P0V/AVDD1P0V */ + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + }; + + pm4125_l12: l12 { + /* USB PHYs */ + regulator-min-microvolt = <928000>; + regulator-max-microvolt = <928000>; + regulator-allow-set-load; + regulator-boot-on; + }; + + pm4125_l13: l13 { + /* USB/QFPROM/PLLs */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allow-set-load; + regulator-boot-on; + }; + + pm4125_l14: l14 { + /* SDHCI1 EMMC VCCQ */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allow-set-load; + /* Broken hardware, never turn it off! */ + regulator-always-on; + }; + + pm4125_l15: l15 { + /* VDDIO */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allow-set-load; + regulator-always-on; + regulator-boot-on; + }; + + pm4125_l20: l20 { + /* SDHCI1 EMMC */ + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3600000>; + regulator-allow-set-load; + }; + + pm4125_l21: l21 { + /* USB HS */ + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <3300000>; + regulator-allow-set-load; + regulator-boot-on; + }; + + pm4125_l22: l22 { + /* Wi-Fi VDD */ + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3312000>; + }; + }; +}; + +&sdhc_1 { + vmmc-supply = <&pm4125_l20>; + vqmmc-supply = <&pm4125_l14>; + pinctrl-0 = <&sdc1_state_on>; + pinctrl-1 = <&sdc1_state_off>; + pinctrl-names = "default", "sleep"; + mmc-hs400-1_8v; + mmc-hs200-1_8v; + non-removable; + supports-cqe; + no-sdio; + no-sd; + + status = "okay"; +}; + +&spi5 { + status = "okay"; + + spidev@0 { + reg = <0>; + compatible = "arduino,unoq-mcu"; + pinctrl-0 = <&spidev_cs>; + pinctrl-names = "default"; + }; +}; + +&tlmm { + spidev_cs: spidev-cs-state { + pins = "gpio17"; + function = "gpio"; + drive-strength = <16>; + }; + + jmisc_gpio18: jmisc-gpio18-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + jmisc_gpio28: jmisc-gpio28-state { + pins = "gpio28"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + key_vold_n: key-vold-n-state { + pins = "gpio36"; + function = "gpio"; + bias-pull-up; + output-disable; + }; + + key_volp_n: key-volp-n-state { + pins = "gpio96"; + function = "gpio"; + bias-pull-up; + output-disable; + }; + + jmisc_gpio98: jmisc-gpio98-state { + pins = "gpio98"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + jmisc_gpio99: jmisc-gpio99-state { + pins = "gpio99"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + jmisc_gpio100: jmisc-gpio100-state { + pins = "gpio100"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + jmisc_gpio101: jmisc-gpio101-state { + pins = "gpio101"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; +}; + +&uart2 { + status = "okay"; +}; + +/* UART connected to Bluetooth */ +&uart3 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn3988-bt"; + + vddio-supply = <&pm4125_l15>; + vddxo-supply = <&pm4125_l13>; + vddrf-supply = <&pm4125_l10>; + vddch0-supply = <&pm4125_l22>; + enable-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; + max-speed = <3000000>; + }; +}; + +/* UART exposed in JCTL */ +&uart4 { + compatible = "qcom,geni-debug-uart"; + + status = "okay"; +}; + +&usb { + status = "okay"; +}; + +&usb_hsphy { + vdd-supply = <&pm4125_l12>; + vdda-pll-supply = <&pm4125_l13>; + vdda-phy-dpdm-supply = <&pm4125_l21>; + + status = "okay"; +}; + +&usb_qmpphy { + vdda-phy-supply = <&pm4125_l12>; + vdda-pll-supply = <&pm4125_l13>; + + status = "okay"; +}; + +&wifi { + vdd-0.8-cx-mx-supply = <&pm4125_l7>; + vdd-1.8-xo-supply = <&pm4125_l13>; + vdd-1.3-rfa-supply = <&pm4125_l10>; + vdd-3.3-ch0-supply = <&pm4125_l22>; + qcom,ath10k-calibration-variant = "ArduinoImola"; + firmware-name = "qcm2290"; + + status = "okay"; +}; + +&xo_board { + clock-frequency = <38400000>; +}; diff --git a/arch/arm64/boot/dts/qcom/qrb2210-rb1-vision-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qrb2210-rb1-vision-mezzanine.dtso new file mode 100644 index 000000000000..c314cd6dd484 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qrb2210-rb1-vision-mezzanine.dtso @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/clock/qcom,gcc-qcm2290.h> +#include <dt-bindings/gpio/gpio.h> + +&pm8008 { + status = "okay"; +}; + +&camss { + status = "okay"; + + vdd-csiphy-1p2-supply = <&pm4125_l5>; + vdd-csiphy-1p8-supply = <&pm4125_l13>; + + ports { + port@0 { + csiphy0_ep: endpoint { + data-lanes = <0 1>; + remote-endpoint = <&ov9282_ep>; + }; + }; + }; +}; + +&cci { + status = "okay"; +}; + +&cci_i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + /* Vision Mezzanine DIP3-1 must be ON (Selects camera CAM0A&B) */ + camera@60 { + compatible = "ovti,ov9282"; + reg = <0x60>; + + /* Reset is active-low, but driver applies inverted reset logic */ + reset-gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&mclk3_default>; + pinctrl-names = "default"; + + clocks = <&gcc GCC_CAMSS_MCLK3_CLK>; + assigned-clocks = <&gcc GCC_CAMSS_MCLK3_CLK>; + assigned-clock-rates = <24000000>; + + avdd-supply = <&vreg_l3p>; + dvdd-supply = <&vreg_l1p>; + dovdd-supply = <&vreg_l7p>; + + port { + ov9282_ep: endpoint { + link-frequencies = /bits/ 64 <400000000>; + data-lanes = <1 2>; + remote-endpoint = <&csiphy0_ep>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts index 1b9ca957a94b..9814ac4896c5 100644 --- a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts +++ b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts @@ -267,6 +267,81 @@ firmware-name = "qcom/qcm2290/a702_zap.mbn"; }; +&i2c1 { + clock-frequency = <400000>; + + status = "okay"; + + pm8008: pmic@8 { + compatible = "qcom,pm8008"; + reg = <0x8>; + + interrupts-extended = <&tlmm 25 IRQ_TYPE_EDGE_RISING>; + reset-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>; + + vdd-l1-l2-supply = <&pm4125_s3>; + vdd-l3-l4-supply = <&vph_pwr>; + vdd-l5-supply = <&vph_pwr>; + vdd-l6-supply = <&vph_pwr>; + vdd-l7-supply = <&vph_pwr>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pm8008 0 0 2>; + + interrupt-controller; + #interrupt-cells = <2>; + + #thermal-sensor-cells = <0>; + + status = "disabled"; + + regulators { + vreg_l1p: ldo1 { + regulator-name = "vreg_l1p"; + regulator-min-microvolt = <528000>; + regulator-max-microvolt = <1200000>; + }; + + vreg_l2p: ldo2 { + regulator-name = "vreg_l2p"; + regulator-min-microvolt = <528000>; + regulator-max-microvolt = <1200000>; + }; + + vreg_l3p: ldo3 { + regulator-name = "vreg_l3p"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3400000>; + }; + + vreg_l4p: ldo4 { + regulator-name = "vreg_l4p"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3404000>; + }; + + vreg_l5p: ldo5 { + regulator-name = "vreg_l5p"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3400000>; + }; + + vreg_l6p: ldo6 { + regulator-name = "vreg_l6p"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3400000>; + }; + + vreg_l7p: ldo7 { + regulator-name = "vreg_l7p"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3400000>; + }; + }; + }; +}; + &i2c2_gpio { clock-frequency = <400000>; status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts index 0cd36c54632f..5f8613150bdd 100644 --- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts @@ -694,7 +694,7 @@ &uart3 { interrupts-extended = <&intc GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, - <&tlmm 11 IRQ_TYPE_LEVEL_HIGH>; + <&tlmm 11 IRQ_TYPE_EDGE_FALLING>; pinctrl-0 = <&uart3_default>; pinctrl-1 = <&uart3_sleep>; pinctrl-names = "default", "sleep"; diff --git a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi index 84c6d662b54f..617a39d32488 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi @@ -67,6 +67,11 @@ status = "okay"; }; +&lpass_tlmm { + /delete-property/ clocks; + /delete-property/ clock-names; +}; + &lpasscc { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index b9e0d9c7c065..706eb1309d3f 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -3041,8 +3041,8 @@ qcom,dout-ports = <5>; qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; - qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>; - qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>; + qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>; + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff>; qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff>; qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 8b1a45a4e56e..f4b8e8f468f2 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -262,7 +262,7 @@ pwr_cluster_sleep_0: cluster-sleep-0-0 { compatible = "arm,idle-state"; idle-state-name = "pwr-cluster-dynamic-retention"; - arm,psci-suspend-param = <0x400000F2>; + arm,psci-suspend-param = <0x400000f2>; entry-latency-us = <284>; exit-latency-us = <384>; min-residency-us = <9987>; @@ -272,7 +272,7 @@ pwr_cluster_sleep_1: cluster-sleep-0-1 { compatible = "arm,idle-state"; idle-state-name = "pwr-cluster-retention"; - arm,psci-suspend-param = <0x400000F3>; + arm,psci-suspend-param = <0x400000f3>; entry-latency-us = <338>; exit-latency-us = <423>; min-residency-us = <9987>; @@ -282,7 +282,7 @@ pwr_cluster_sleep_2: cluster-sleep-0-2 { compatible = "arm,idle-state"; idle-state-name = "pwr-cluster-retention"; - arm,psci-suspend-param = <0x400000F4>; + arm,psci-suspend-param = <0x400000f4>; entry-latency-us = <515>; exit-latency-us = <1821>; min-residency-us = <9987>; @@ -292,7 +292,7 @@ perf_cluster_sleep_0: cluster-sleep-1-0 { compatible = "arm,idle-state"; idle-state-name = "perf-cluster-dynamic-retention"; - arm,psci-suspend-param = <0x400000F2>; + arm,psci-suspend-param = <0x400000f2>; entry-latency-us = <272>; exit-latency-us = <329>; min-residency-us = <9987>; @@ -302,7 +302,7 @@ perf_cluster_sleep_1: cluster-sleep-1-1 { compatible = "arm,idle-state"; idle-state-name = "perf-cluster-retention"; - arm,psci-suspend-param = <0x400000F3>; + arm,psci-suspend-param = <0x400000f3>; entry-latency-us = <332>; exit-latency-us = <368>; min-residency-us = <9987>; @@ -312,7 +312,7 @@ perf_cluster_sleep_2: cluster-sleep-1-2 { compatible = "arm,idle-state"; idle-state-name = "perf-cluster-retention"; - arm,psci-suspend-param = <0x400000F4>; + arm,psci-suspend-param = <0x400000f4>; entry-latency-us = <545>; exit-latency-us = <1609>; min-residency-us = <9987>; @@ -563,7 +563,7 @@ }; }; - soc@0 { + soc: soc@0 { #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0 0xffffffff>; @@ -598,8 +598,8 @@ }; gpu_speed_bin: gpu-speed-bin@41a0 { - reg = <0x41a2 0x1>; - bits = <5 7>; + reg = <0x41a2 0x2>; + bits = <5 8>; }; }; @@ -1058,8 +1058,8 @@ qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; - power-domains = <&rpmpd SDM660_VDDCX>, - <&rpmpd SDM660_VDDMX>; + power-domains = <&rpmpd RPMPD_VDDCX>, + <&rpmpd RPMPD_VDDMX>; power-domain-names = "cx", "mx"; memory-region = <&mba_region>, <&mpss_region>, <&mdata_mem>; @@ -1096,7 +1096,7 @@ "rbcpr", "core"; - power-domains = <&rpmpd SDM660_VDDMX>; + power-domains = <&rpmpd RPMPD_VDDMX>; iommus = <&kgsl_smmu 0>; nvmem-cells = <&gpu_speed_bin>; @@ -1217,6 +1217,11 @@ reg = <0x05100000 0x40000>; #iommu-cells = <1>; + clocks = <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>; + clock-names = "bus"; + + power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>; + #global-interrupts = <2>; interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, @@ -1396,7 +1401,7 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdc2_state_on>; pinctrl-1 = <&sdc2_state_off>; - power-domains = <&rpmpd SDM660_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; status = "disabled"; @@ -1450,7 +1455,7 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdc1_state_on>; pinctrl-1 = <&sdc1_state_off>; - power-domains = <&rpmpd SDM660_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; bus-width = <8>; non-removable; @@ -1563,6 +1568,7 @@ reg-names = "mdss_phys", "vbif_phys"; power-domains = <&mmcc MDSS_GDSC>; + resets = <&mmcc MDSS_BCR>; clocks = <&mmcc MDSS_AHB_CLK>, <&mmcc MDSS_AXI_CLK>, @@ -1612,7 +1618,7 @@ "rotator-mem"; iommus = <&mmss_smmu 0>; operating-points-v2 = <&mdp_opp_table>; - power-domains = <&rpmpd SDM660_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; ports { #address-cells = <1>; @@ -1664,7 +1670,7 @@ reg-names = "dsi_ctrl"; operating-points-v2 = <&dsi_opp_table>; - power-domains = <&rpmpd SDM660_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; interrupt-parent = <&mdss>; interrupts = <4>; @@ -2263,6 +2269,79 @@ status = "disabled"; }; + lpi_tlmm: pinctrl@15070000 { + compatible = "qcom,sdm660-lpass-lpi-pinctrl"; + reg = <0x15070000 0x20000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpi_tlmm 0 0 32>; + + cdc_pdm_default: cdc-pdm-default-state { + clk-pins { + pins = "gpio18"; + function = "pdm_clk"; + drive-strength = <8>; + output-high; + }; + + sync-pins { + pins = "gpio19"; + function = "pdm_sync"; + drive-strength = <4>; + output-high; + }; + + tx-pins { + pins = "gpio20"; + function = "pdm_tx"; + drive-strength = <8>; + }; + + rx-pins { + pins = "gpio21", "gpio23", "gpio25"; + function = "pdm_rx"; + drive-strength = <4>; + output-high; + }; + }; + + cdc_comp_default: cdc-comp-default-state { + pins = "gpio22", "gpio24"; + function = "comp_rx"; + drive-strength = <8>; + }; + + cdc_dmic_default: cdc-dmic-default-state { + dmic1-clk-pins { + pins = "gpio26"; + function = "dmic1_clk"; + drive-strength = <8>; + output-high; + }; + + dmic1-data-pins { + pins = "gpio27"; + function = "dmic1_data"; + drive-strength = <8>; + output-high; + }; + + dmic2-clk-pins { + pins = "gpio28"; + function = "dmic2_clk"; + drive-strength = <8>; + input-enable; + }; + + dmic2-data-pins { + pins = "gpio29"; + function = "dmic2_data"; + drive-strength = <8>; + input-enable; + }; + }; + }; + adsp_pil: remoteproc@15700000 { compatible = "qcom,sdm660-adsp-pas"; reg = <0x15700000 0x4040>; @@ -2280,7 +2359,7 @@ clock-names = "xo"; memory-region = <&adsp_region>; - power-domains = <&rpmpd SDM660_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; power-domain-names = "cx"; qcom,smem-states = <&adsp_smp2p_out 0>; @@ -2337,6 +2416,39 @@ }; }; }; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "adsp"; + qcom,non-secure-domain; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&lpass_smmu 3>; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&lpass_smmu 7>; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&lpass_smmu 8>; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&lpass_smmu 9>; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts index 55a45b528bd3..0edb2992b902 100644 --- a/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts +++ b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts @@ -36,6 +36,42 @@ }; }; + vreg_cam_af_2p85: regulator-cam-af-2p85 { + compatible = "regulator-fixed"; + regulator-name = "cam_af_2p85"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + + gpio = <&tlmm 128 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vph_pwr>; + }; + + vreg_cam_io_1p8: regulator-cam-io-1p8 { + compatible = "regulator-fixed"; + regulator-name = "cam_io_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 130 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vph_pwr>; + }; + + vreg_cam2_dig_1p2: regulator-cam2-dig-1p2 { + compatible = "regulator-fixed"; + regulator-name = "cam2_dig_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + gpio = <&tlmm 46 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vph_pwr>; + }; + /* Dummy regulator until PMI632 has LCDB VSP/VSN support */ lcdb_dummy: regulator-lcdb-dummy { compatible = "regulator-fixed"; @@ -52,6 +88,27 @@ }; }; +&cci { + status = "okay"; +}; + +&cci_i2c0 { + /* Sony IMX363 (rear) @ 0x10 */ + + eeprom@50 { + compatible = "belling,bl24s64", "atmel,24c64"; + reg = <0x50>; + vcc-supply = <&vreg_cam_io_1p8>; + read-only; + }; + + /* ON Semi LC898217 VCM @ 0x72 */ +}; + +&cci_i2c1 { + /* Samsung S5K4H7YX (front) @ 0x10 */ +}; + &gpu { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sdm636.dtsi b/arch/arm64/boot/dts/qcom/sdm636.dtsi index ae15d81fa3f9..38e6e3bfc3ce 100644 --- a/arch/arm64/boot/dts/qcom/sdm636.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm636.dtsi @@ -7,15 +7,20 @@ #include "sdm660.dtsi" -/* - * According to the downstream DTS, - * 636 is basically a 660 except for - * different CPU frequencies, Adreno - * 509 instead of 512 and lack of - * turing IP. These differences will - * be addressed when the aforementioned - * peripherals will be enabled upstream. - */ +/delete-node/ &remoteproc_cdsp; +/delete-node/ &cdsp_smmu; +/delete-node/ &cdsp_region; + +/ { + /delete-node/ smp2p-cdsp; + + reserved-memory { + buffer_mem: tzbuffer@94a00000 { + reg = <0x0 0x94a00000 0x00 0x100000>; + no-map; + }; + }; +}; &adreno_gpu { compatible = "qcom,adreno-509.0", "qcom,adreno"; diff --git a/arch/arm64/boot/dts/qcom/sdm660.dtsi b/arch/arm64/boot/dts/qcom/sdm660.dtsi index ef4a563c0feb..3fd6dd82a992 100644 --- a/arch/arm64/boot/dts/qcom/sdm660.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm660.dtsi @@ -9,6 +9,37 @@ #include "sdm630.dtsi" +/delete-node/ &buffer_mem; + +/ { + smp2p-cdsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + interrupts = <GIC_SPI 514 IRQ_TYPE_EDGE_RISING>; + mboxes = <&apcs_glb 30>; + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + cdsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + cdsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + reserved-memory { + cdsp_region: cdsp@94a00000 { + reg = <0x0 0x94a00000 0x00 0x600000>; + no-map; + }; + }; +}; + &adreno_gpu { compatible = "qcom,adreno-512.0", "qcom,adreno"; operating-points-v2 = <&gpu_sdm660_opp_table>; @@ -163,7 +194,7 @@ /* DSI1 shares the OPP table with DSI0 */ operating-points-v2 = <&dsi_opp_table>; - power-domains = <&rpmpd SDM660_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; interrupt-parent = <&mdss>; interrupts = <5>; @@ -247,6 +278,136 @@ <0>; }; +&soc { + cdsp_smmu: iommu@5180000 { + compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; + reg = <0x5180000 0x40000>; + #iommu-cells = <1>; + + #global-interrupts = <2>; + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 537 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 538 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 540 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_HLOS1_VOTE_TURING_ADSP_SMMU_CLK>; + clock-names = "bus"; + + power-domains = <&gcc HLOS1_VOTE_TURING_ADSP_GDSC>; + + }; + + remoteproc_cdsp: remoteproc@1a300000 { + compatible = "qcom,sdm660-cdsp-pas"; + reg = <0x1a300000 0x00100>; + interrupts-extended = <&intc GIC_SPI 518 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + + memory-region = <&cdsp_region>; + power-domains = <&rpmpd SDM660_VDDCX>; + power-domain-names = "cx"; + + qcom,smem-states = <&cdsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + glink-edge { + interrupts = <GIC_SPI 513 IRQ_TYPE_EDGE_RISING>; + + label = "cdsp"; + mboxes = <&apcs_glb 29>; + qcom,remote-pid = <5>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "cdsp"; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&cdsp_smmu 3>; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&cdsp_smmu 4>; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&cdsp_smmu 5>; + }; + + compute-cb@8 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; + iommus = <&cdsp_smmu 6>; + }; + + compute-cb@9 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <9>; + iommus = <&cdsp_smmu 7>; + }; + + compute-cb@10 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <10>; + iommus = <&cdsp_smmu 8>; + }; + + compute-cb@11 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <11>; + iommus = <&cdsp_smmu 9>; + }; + + compute-cb@12 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <12>; + iommus = <&cdsp_smmu 10>; + }; + + compute-cb@13 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <13>; + iommus = <&cdsp_smmu 11>; + }; + }; + }; + }; +}; + &tlmm { compatible = "qcom,sdm660-pinctrl"; }; diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index b8a8dcbdfbe3..746e9deba526 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -634,7 +634,7 @@ #address-cells = <1>; #size-cells = <1>; - gpu_speed_bin: gpu_speed_bin@1a2 { + gpu_speed_bin: gpu-speed-bin@1a2 { reg = <0x1a2 0x2>; bits = <5 8>; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index ce23f87e0316..5118b776a9bb 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -379,6 +379,12 @@ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; + vreg_l23a_3p3: ldo23 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + vreg_l24a_3p075: ldo24 { regulator-min-microvolt = <3088000>; regulator-max-microvolt = <3088000>; @@ -850,7 +856,6 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi0_default>; - cs-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>; can@0 { compatible = "microchip,mcp2517fd"; @@ -1156,6 +1161,7 @@ vdd-1.8-xo-supply = <&vreg_l7a_1p8>; vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; + vdd-3.3-ch1-supply = <&vreg_l23a_3p3>; qcom,snoc-host-cap-8bit-quirk; qcom,calibration-variant = "Thundercomm_DB845C"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts b/arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts new file mode 100644 index 000000000000..fa89be500fb8 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "sdm845-google-common.dtsi" + +/ { + model = "Google Pixel 3"; + compatible = "google,blueline", "qcom,sdm845"; +}; + +&battery { + charge-full-design-microamp-hours = <2970000>; + voltage-min-design-microvolt = <3600000>; + voltage-max-design-microvolt = <4400000>; +}; + +&framebuffer0 { + width = <1080>; + height = <2160>; + stride = <(1080 * 4)>; +}; + +&i2c2 { + clock-frequency = <1000000>; + + status = "okay"; + + /* ST,FTS @ 49 */ +}; + +&mdss_dsi0 { + vdda-supply = <&vdda_mipi_dsi0_1p2>; + + status = "okay"; + + panel@0 { + compatible = "lg,sw43408-lh546wf1-ed01", "lg,sw43408"; + reg = <0>; + + vddi-supply = <&vreg_l14a_1p8>; + vpnl-supply = <&vreg_l28a_3p0>; + + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&panel_default>; + pinctrl-names = "default"; + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + data-lanes = <0 1 2 3>; + remote-endpoint = <&panel_in>; + qcom,te-source = "mdp_vsync_e"; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vdda_mipi_dsi0_pll>; + + status = "okay"; +}; + +&tlmm { + panel_default: panel-default-state { + reset-pins { + pins = "gpio6"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + te-pins { + pins = "gpio12"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; + }; +}; + +&wifi { + qcom,calibration-variant = "Google_blueline"; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi new file mode 100644 index 000000000000..fd9788d5c3f5 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi @@ -0,0 +1,536 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include <dt-bindings/arm/qcom,ids.h> +#include <dt-bindings/dma/qcom-gpi.h> +#include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> + +#include "sdm845.dtsi" +#include "pm8998.dtsi" +#include "pmi8998.dtsi" + +/delete-node/ &mpss_region; +/delete-node/ &venus_mem; +/delete-node/ &cdsp_mem; +/delete-node/ &mba_region; +/delete-node/ &slpi_mem; +/delete-node/ &spss_mem; +/delete-node/ &rmtfs_mem; + +/ { + chassis-type = "handset"; + qcom,board-id = <0x00021505 0>; + qcom,msm-id = <QCOM_ID_SDM845 0x20001>; + + aliases { + serial0 = &uart9; + serial1 = &uart6; + }; + + battery: battery { + compatible = "simple-battery"; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + stdout-path = "serial0:115200n8"; + + /* Use display framebuffer as setup by bootloader */ + framebuffer0: framebuffer-0 { + compatible = "simple-framebuffer"; + memory-region = <&cont_splash_mem>; + + format = "a8r8g8b8"; + }; + }; + + reserved-memory { + cont_splash_mem: splash@9d400000 { + reg = <0 0x9d400000 0 0x02400000>; + no-map; + }; + + mpss_region: memory@8e000000 { + reg = <0 0x8e000000 0 0x9800000>; + no-map; + }; + + venus_mem: venus@97800000 { + reg = <0 0x97800000 0 0x500000>; + no-map; + }; + + cdsp_mem: cdsp-mem@97D00000 { + reg = <0 0x97D00000 0 0x800000>; + no-map; + }; + + mba_region: mba@98500000 { + reg = <0 0x98500000 0 0x200000>; + no-map; + }; + + slpi_mem: slpi@98700000 { + reg = <0 0x98700000 0 0x1400000>; + no-map; + }; + + spss_mem: spss@99B00000 { + reg = <0 0x99B00000 0 0x100000>; + no-map; + }; + + rmtfs_mem: rmtfs-region@f2700000 { + compatible = "qcom,rmtfs-mem"; + reg = <0 0xf2700000 0 0x202000>; + qcom,use-guard-pages; + no-map; + + qcom,client-id = <1>; + qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + label = "Volume keys"; + autorepeat; + + pinctrl-0 = <&volume_up_gpio>; + pinctrl-names = "default"; + + key-vol-up { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + }; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + vreg_s4a_1p8: regulator-vreg-s4a-1p8 { + compatible = "regulator-fixed"; + regulator-name = "vreg_s4a_1p8"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + vin-supply = <&vph_pwr>; + }; +}; + +&adsp_pas { + firmware-name = "qcom/sdm845/Google/blueline/adsp.mbn"; + + status = "okay"; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8998-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-s11-supply = <&vph_pwr>; + vdd-s12-supply = <&vph_pwr>; + vdd-s13-supply = <&vph_pwr>; + vdd-l1-l27-supply = <&vreg_s7a_1p025>; + vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>; + vdd-l3-l11-supply = <&vreg_s7a_1p025>; + vdd-l4-l5-supply = <&vreg_s7a_1p025>; + vdd-l6-supply = <&vph_pwr>; + vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>; + vdd-l9-supply = <&vreg_bob>; + vdd-l10-l23-l25-supply = <&vreg_bob>; + vdd-l13-l19-l21-supply = <&vreg_bob>; + vdd-l16-l28-supply = <&vreg_bob>; + vdd-l18-l22-supply = <&vreg_bob>; + vdd-l20-l24-supply = <&vreg_bob>; + vdd-l26-supply = <&vreg_s3a_1p35>; + vin-lvs-1-2-supply = <&vreg_s4a_1p8>; + + vreg_s3a_1p35: smps3 { + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + }; + + vreg_s5a_2p04: smps5 { + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <2040000>; + }; + + vreg_s7a_1p025: smps7 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1028000>; + }; + + vdda_mipi_dsi0_pll: + vreg_l1a_0p875: ldo1 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-boot-on; + }; + + vreg_l5a_0p8: ldo5 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7a_1p8: ldo7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l13a_2p95: ldo13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l14a_1p8: ldo14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-boot-on; + /* + * We can't properly bring the panel back if it gets turned off + * so keep it's regulators always on for now. + */ + regulator-always-on; + }; + + vreg_l17a_1p3: ldo17 { + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l19a_3p3: ldo19 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + /* + * The touchscreen needs this to be 3.3v, which is apparently + * quite close to the hardware limit for this LDO (3.312v) + * It must be kept in high power mode to prevent TS brownouts + */ + regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l20a_2p95: ldo20 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2968000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l21a_2p95: ldo21 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2968000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l24a_3p075: ldo24 { + regulator-min-microvolt = <3088000>; + regulator-max-microvolt = <3088000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l25a_3p3: ldo25 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vdda_mipi_dsi0_1p2: + vreg_l26a_1p2: ldo26 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-boot-on; + }; + + vreg_l28a_3p0: ldo28 { + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + regulator-boot-on; + /* + * We can't properly bring the panel back if it gets turned off + * so keep it's regulators always on for now. + */ + regulator-always-on; + }; + }; + + regulators-1 { + compatible = "qcom,pmi8998-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-bob-supply = <&vph_pwr>; + + vreg_bob: bob { + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3600000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-bypass; + }; + }; + + regulators-2 { + compatible = "qcom,pm8005-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + + vreg_s3c_0p6: smps3 { + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <600000>; + }; + }; +}; + +&cci { + status = "okay"; +}; + +&cci_i2c1 { + /* actuator @0c */ + + /* front camera, imx355 @1a */ + + /* eeprom @50, at24 driver says 8K */ +}; + +&cdsp_pas { + firmware-name = "qcom/sdm845/Google/blueline/cdsp.mbn"; + + status = "okay"; +}; + +&gcc { + protected-clocks = <GCC_QSPI_CORE_CLK>, + <GCC_QSPI_CORE_CLK_SRC>, + <GCC_QSPI_CNOC_PERIPH_AHB_CLK>; +}; + +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/sdm845/Google/blueline/a630_zap.mbn"; +}; + +&i2c12 { + /* Bottom spkr (right) CS35L36 @ 40 */ + + /* Top spkr (left) CS35L36 @ 41 */ +}; + +&ipa { + firmware-name = "qcom/sdm845/Google/blueline/ipa_fws.mbn"; + memory-region = <&ipa_fw_mem>; + + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&mss_pil { + firmware-name = "qcom/sdm845/Google/blueline/mba.mbn", + "qcom/sdm845/Google/blueline/modem.mbn"; + + status = "okay"; +}; + +&pm8998_gpios { + volume_up_gpio: vol-up-active-state { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-pull-up; + qcom,drive-strength = <0>; + }; +}; + +&pm8998_resin { + linux,code = <KEY_VOLUMEDOWN>; + + status = "okay"; +}; + +&pmi8998_charger { + monitored-battery = <&battery>; + + status = "okay"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&qup_uart9_rx { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_uart9_tx { + drive-strength = <2>; + bias-disable; +}; + +&tlmm { + gpio-reserved-ranges = < 0 4>, /* SPI (Intel MNH Pixel Visual Core) */ + <81 4>; /* SPI (most likely Fingerprint Cards FPC1075) */ + + touchscreen_reset: ts-reset-state { + pins = "gpio99"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + touchscreen_pins: ts-pins-gpio-state { + pins = "gpio125"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + touchscreen_i2c_pins: qup-i2c2-gpio-state { + pins = "gpio27", "gpio28"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + +&uart6 { + pinctrl-0 = <&qup_uart6_4pin>; + + status = "okay"; + + bluetooth { + compatible = "qcom,wcn3990-bt"; + + vddio-supply = <&vreg_s4a_1p8>; + vddxo-supply = <&vreg_l7a_1p8>; + vddrf-supply = <&vreg_l17a_1p3>; + vddch0-supply = <&vreg_l25a_3p3>; + max-speed = <3200000>; + }; +}; + +&uart9 { + status = "okay"; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l20a_2p95>; + vcc-max-microamp = <800000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l26a_1p2>; + + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_1_hsphy { + vdd-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l12a_1p8>; + vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; + + qcom,imp-res-offset-value = <8>; + qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>; + qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>; + qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>; + + status = "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply = <&vreg_l26a_1p2>; + vdda-pll-supply = <&vreg_l1a_0p875>; + + status = "okay"; +}; + +&venus { + firmware-name = "qcom/sdm845/Google/blueline/venus.mbn"; + + status = "okay"; +}; + +&wifi { + vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; + vdd-1.8-xo-supply = <&vreg_l7a_1p8>; + vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; + vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; + + qcom,snoc-host-cap-8bit-quirk; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts b/arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts new file mode 100644 index 000000000000..2a81ca1d00b1 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "sdm845-google-common.dtsi" + +/ { + model = "Google Pixel 3 XL"; + compatible = "google,crosshatch", "qcom,sdm845"; +}; + +&battery { + charge-full-design-microamp-hours = <3480000>; + voltage-min-design-microvolt = <3600000>; + voltage-max-design-microvolt = <4400000>; +}; + +&dispcc { + /* Disable for now so simple-framebuffer continues working */ + status = "disabled"; +}; + +&framebuffer0 { + width = <1440>; + height = <2960>; + stride = <(1440 * 4)>; +}; + +&mdss { + /* Disable for now so simple-framebuffer continues working */ + status = "disabled"; +}; + +&wifi { + qcom,calibration-variant = "Google_crosshatch"; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index db6dd04c51bb..5b121ea5520f 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -31,7 +31,20 @@ }; chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + stdout-path = "serial0:115200n8"; + + framebuffer: framebuffer@9d400000 { + compatible = "simple-framebuffer"; + memory-region = <&cont_splash_mem>; + + format = "a8r8g8b8"; + stride = <(1080 * 4)>; + width = <1080>; + }; }; gpio-hall-sensor { @@ -75,6 +88,11 @@ }; reserved-memory { + cont_splash_mem: splash@9d400000 { + reg = <0 0x9d400000 0 0x02400000>; + no-map; + }; + /* * The rmtfs memory region in downstream is 'dynamically allocated' * but given the same address every time. Hard code it as this address is @@ -148,7 +166,6 @@ gpio = <&tlmm 88 0>; enable-active-high; - regulator-boot-on; }; panel_vci_3v3: panel-vci-3v3-regulator { @@ -181,8 +198,9 @@ }; &adsp_pas { + firmware-name = "qcom/sdm845/OnePlus/enchilada/adsp.mbn"; + status = "okay"; - firmware-name = "qcom/sdm845/oneplus6/adsp.mbn"; }; &apps_rsc { @@ -273,7 +291,7 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - regulator-always-on; + regulator-boot-on; }; vreg_l17a_1p3: ldo17 { @@ -353,8 +371,9 @@ }; &cdsp_pas { + firmware-name = "qcom/sdm845/OnePlus/enchilada/cdsp.mbn"; + status = "okay"; - firmware-name = "qcom/sdm845/oneplus6/cdsp.mbn"; }; &gcc { @@ -370,7 +389,7 @@ }; &gpu_zap_shader { - firmware-name = "qcom/sdm845/oneplus6/a630_zap.mbn"; + firmware-name = "qcom/sdm845/OnePlus/enchilada/a630_zap.mbn"; }; &i2c10 { @@ -422,7 +441,8 @@ &ipa { qcom,gsi-loader = "self"; memory-region = <&ipa_fw_mem>; - firmware-name = "qcom/sdm845/oneplus6/ipa_fws.mbn"; + firmware-name = "qcom/sdm845/OnePlus/enchilada/ipa_fws.mbn"; + status = "okay"; }; @@ -474,8 +494,10 @@ /* Modem/wifi */ &mss_pil { + firmware-name = "qcom/sdm845/OnePlus/enchilada/mba.mbn", + "qcom/sdm845/OnePlus/enchilada/modem.mbn"; + status = "okay"; - firmware-name = "qcom/sdm845/oneplus6/mba.mbn", "qcom/sdm845/oneplus6/modem.mbn"; }; &pm8998_gpios { @@ -593,7 +615,8 @@ }; &slpi_pas { - firmware-name = "qcom/sdm845/oneplus6/slpi.mbn"; + firmware-name = "qcom/sdm845/OnePlus/enchilada/slpi.mbn"; + status = "okay"; }; @@ -744,7 +767,7 @@ * This path is relative to the qca/ * subdir under lib/firmware. */ - firmware-name = "oneplus6/crnv21.bin"; + firmware-name = "OnePlus/enchilada/crnv21.bin"; vddio-supply = <&vreg_s4a_1p8>; vddxo-supply = <&vreg_l7a_1p8>; @@ -906,8 +929,9 @@ }; &venus { + firmware-name = "qcom/sdm845/OnePlus/enchilada/venus.mbn"; + status = "okay"; - firmware-name = "qcom/sdm845/oneplus6/venus.mbn"; }; &wcd9340 { @@ -929,5 +953,6 @@ vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; vdd-3.3-ch1-supply = <&vreg_l23a_3p3>; + qcom,calibration-variant = "oneplus_sdm845"; qcom,snoc-host-cap-8bit-quirk; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts b/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts index 8aead6dc25e0..3b30d79706fe 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts @@ -30,17 +30,23 @@ }; }; +&bq27441_fg { + monitored-battery = <&battery>; +}; + &display_panel { compatible = "samsung,sofef00-ams628nw01", "samsung,sofef00"; status = "okay"; }; -&bq27441_fg { - monitored-battery = <&battery>; +&framebuffer { + height = <2280>; }; &i2c4 { + clock-frequency = <100000>; + status = "okay"; max98927_codec: max98927@3a { diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts b/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts index d6cd873aef0d..0542333a8357 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts @@ -35,6 +35,10 @@ compatible = "samsung,s6e3fc2x01-ams641rw", "samsung,s6e3fc2x01"; }; +&framebuffer { + height = <2340>; +}; + &i2c4 { /* nxp,tfa9894 @ 0x34 */ }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts index 5d41a92cfebf..77f5872de6f1 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts @@ -254,7 +254,7 @@ }; &gpu_zap_shader { - firmware-name = "qcom/sdm845/starqltechn/a630_zap.mbn"; + firmware-name = "qcom/sdm845/Samsung/starqltechn/a630_zap.mbn"; }; &mdss { @@ -699,7 +699,8 @@ }; &adsp_pas { - firmware-name = "qcom/sdm845/starqltechn/adsp.mbn"; + firmware-name = "qcom/sdm845/Samsung/starqltechn/adsp.mbn"; + status = "okay"; }; @@ -904,20 +905,22 @@ }; &mss_pil { - firmware-name = "qcom/sdm845/starqltechn/mba.mbn", - "qcom/sdm845/starqltechn/modem.mbn"; + firmware-name = "qcom/sdm845/Samsung/starqltechn/mba.mbn", + "qcom/sdm845/Samsung/starqltechn/modem.mbn"; + status = "okay"; }; &ipa { qcom,gsi-loader = "self"; memory-region = <&ipa_fw_mem>; - firmware-name = "qcom/sdm845/starqltechn/ipa_fws.mbn"; + firmware-name = "qcom/sdm845/Samsung/starqltechn/ipa_fws.mbn"; + status = "okay"; }; &slpi_pas { - firmware-name = "qcom/sdm845/starqltechn/slpi.mbn"; + firmware-name = "qcom/sdm845/Samsung/starqltechn/slpi.mbn"; cx-supply = <&slpi_regulator>; status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts index ddc2b3ca3bc5..51b041f91d3e 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts @@ -108,8 +108,9 @@ }; &adsp_pas { + firmware-name = "qcom/sdm845/SHIFT/axolotl/adsp.mbn"; + status = "okay"; - firmware-name = "qcom/sdm845/axolotl/adsp.mbn"; }; &apps_rsc { @@ -409,8 +410,9 @@ }; &cdsp_pas { + firmware-name = "qcom/sdm845/SHIFT/axolotl/cdsp.mbn"; + status = "okay"; - firmware-name = "qcom/sdm845/axolotl/cdsp.mbn"; }; &gcc { @@ -426,7 +428,7 @@ }; &gpu_zap_shader { - firmware-name = "qcom/sdm845/axolotl/a630_zap.mbn"; + firmware-name = "qcom/sdm845/SHIFT/axolotl/a630_zap.mbn"; }; &i2c5 { @@ -458,7 +460,8 @@ &ipa { qcom,gsi-loader = "self"; memory-region = <&ipa_fw_mem>; - firmware-name = "qcom/sdm845/axolotl/ipa_fws.mbn"; + firmware-name = "qcom/sdm845/SHIFT/axolotl/ipa_fws.mbn"; + status = "okay"; }; @@ -502,8 +505,9 @@ }; &mss_pil { + firmware-name = "qcom/sdm845/SHIFT/axolotl/mba.mbn", "qcom/sdm845/SHIFT/axolotl/modem.mbn"; + status = "okay"; - firmware-name = "qcom/sdm845/axolotl/mba.mbn", "qcom/sdm845/axolotl/modem.mbn"; }; &pm8998_gpios { @@ -597,7 +601,8 @@ }; &slpi_pas { - firmware-name = "qcom/sdm845/axolotl/slpi.mbn"; + firmware-name = "qcom/sdm845/SHIFT/axolotl/slpi.mbn"; + status = "okay"; }; @@ -673,7 +678,7 @@ * This path is relative to the qca/ * subdir under lib/firmware. */ - firmware-name = "axolotl/crnv21.bin"; + firmware-name = "SHIFT/axolotl/crnv21.bin"; vddio-supply = <&vreg_s4a_1p8>; vddxo-supply = <&vreg_l7a_1p8>; @@ -727,8 +732,9 @@ }; &venus { + firmware-name = "qcom/sdm845/SHIFT/axolotl/venus.mbn"; + status = "okay"; - firmware-name = "qcom/sdm845/axolotl/venus.mbn"; }; &wifi { @@ -740,5 +746,6 @@ vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; vdd-3.3-ch1-supply = <&vreg_l23a_3p3>; + qcom,calibration-variant = "shift_axolotl"; qcom,snoc-host-cap-8bit-quirk; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi index 785006a15e97..01b570d0880d 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi @@ -136,7 +136,7 @@ &adsp_pas { status = "okay"; - firmware-name = "qcom/sdm845/beryllium/adsp.mbn"; + firmware-name = "qcom/sdm845/Xiaomi/beryllium/adsp.mbn"; }; &apps_rsc { @@ -227,9 +227,15 @@ }; }; +&cci_i2c0 { + status = "okay"; + + /* IMX363 @ 10 */ +}; + &cdsp_pas { status = "okay"; - firmware-name = "qcom/sdm845/beryllium/cdsp.mbn"; + firmware-name = "qcom/sdm845/Xiaomi/beryllium/cdsp.mbn"; }; &gcc { @@ -249,7 +255,7 @@ }; &gpu_zap_shader { - firmware-name = "qcom/sdm845/beryllium/a630_zap.mbn"; + firmware-name = "qcom/sdm845/Xiaomi/beryllium/a630_zap.mbn"; }; &ibb { @@ -261,6 +267,22 @@ qcom,discharge-resistor-kohms = <300>; }; +&ipa { + qcom,gsi-loader = "self"; + memory-region = <&ipa_fw_mem>; + firmware-name = "qcom/sdm845/beryllium/ipa_fws.mbn"; + + status = "okay"; +}; + +&i2c5 { + clock-frequency = <400000>; + + status = "okay"; + + /* TAS2559 @ 4C */ +}; + &lab { regulator-min-microvolt = <4600000>; regulator-max-microvolt = <6000000>; @@ -308,14 +330,8 @@ &mss_pil { status = "okay"; - firmware-name = "qcom/sdm845/beryllium/mba.mbn", "qcom/sdm845/beryllium/modem.mbn"; -}; - -&ipa { - qcom,gsi-loader = "self"; - memory-region = <&ipa_fw_mem>; - firmware-name = "qcom/sdm845/beryllium/ipa_fws.mbn"; - status = "okay"; + firmware-name = "qcom/sdm845/Xiaomi/beryllium/mba.mbn", + "qcom/sdm845/Xiaomi/beryllium/modem.mbn"; }; &pm8998_gpios { @@ -425,6 +441,12 @@ cd-gpios = <&tlmm 126 GPIO_ACTIVE_HIGH>; }; +&slpi_pas { + firmware-name = "qcom/sdm845/Xiaomi/beryllium/slpi.mbn"; + + status = "okay"; +}; + &sound { compatible = "qcom,db845c-sndcard", "qcom,sdm845-sndcard"; pinctrl-0 = <&quat_mi2s_active @@ -612,7 +634,7 @@ &venus { status = "okay"; - firmware-name = "qcom/sdm845/beryllium/venus.mbn"; + firmware-name = "qcom/sdm845/Xiaomi/beryllium/venus.mbn"; }; &wcd9340 { @@ -636,4 +658,7 @@ vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; vdd-3.3-ch1-supply = <&vreg_l23a_3p3>; + + qcom,calibration-variant = "xiaomi_beryllium"; }; + diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts index 30e88ff010a3..a44d6e776c82 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts @@ -370,7 +370,8 @@ }; &cdsp_pas { - firmware-name = "qcom/sdm845/polaris/cdsp.mbn"; + firmware-name = "qcom/sdm845/Xiaomi/polaris/cdsp.mbn"; + status = "okay"; }; @@ -395,7 +396,7 @@ }; &gpu_zap_shader { - firmware-name = "qcom/sdm845/polaris/a630_zap.mbn"; + firmware-name = "qcom/sdm845/Xiaomi/polaris/a630_zap.mbn"; }; &ibb { @@ -410,7 +411,8 @@ &ipa { qcom,gsi-loader = "self"; memory-region = <&ipa_fw_mem>; - firmware-name = "qcom/sdm845/polaris/ipa_fws.mbn"; + firmware-name = "qcom/sdm845/Xiaomi/polaris/ipa_fws.mbn"; + status = "okay"; }; @@ -502,7 +504,9 @@ }; &mss_pil { - firmware-name = "qcom/sdm845/polaris/mba.mbn", "qcom/sdm845/polaris/modem.mbn"; + firmware-name = "qcom/sdm845/Xiaomi/polaris/mba.mbn", + "qcom/sdm845/Xiaomi/polaris/modem.mbn"; + status = "okay"; }; @@ -623,7 +627,7 @@ compatible = "qcom,wcn3990-bt"; /* This path is relative to the qca/ subdir under lib/firmware. */ - firmware-name = "polaris/crnv21.bin"; + firmware-name = "Xiaomi/polaris/crnv21.bin"; vddio-supply = <&vreg_s4a_1p8>; vddxo-supply = <&vreg_l7a_1p8>; @@ -683,7 +687,8 @@ }; &venus { - firmware-name = "qcom/sdm845/polaris/venus.mbn"; + firmware-name = "qcom/sdm845/Xiaomi/polaris/venus.mbn"; + status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sdm850-huawei-matebook-e-2019.dts b/arch/arm64/boot/dts/qcom/sdm850-huawei-matebook-e-2019.dts index 0ef9ea38a424..f04865381870 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-huawei-matebook-e-2019.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-huawei-matebook-e-2019.dts @@ -30,9 +30,7 @@ /delete-node/ &ipa_fw_mem; /delete-node/ &ipa_gsi_mem; /delete-node/ &gpu_mem; -/delete-node/ &adsp_mem; /delete-node/ &wlan_msa_mem; -/delete-node/ &slpi_mem; / { model = "Huawei MateBook E 2019"; @@ -145,22 +143,13 @@ no-map; }; - adsp_mem: adsp@8c500000 { - reg = <0 0x8c500000 0 0x1a00000>; - no-map; - }; - ipa_fw_mem: ipa-fw@8df00000 { - reg = <0 0x8df00000 0 0x100000>; + reg = <0 0x8df00000 0 0x5a000>; no-map; }; - slpi_mem: slpi@96700000 { - reg = <0 0x96700000 0 0x1200000>; - }; - - gpu_mem: gpu@97900000 { - reg = <0 0x97900000 0 0x5000>; + gpu_mem: gpu@8df5a000 { + reg = <0 0x8df5a000 0 0x5000>; no-map; }; diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 5e2032c26ea3..e9336adbc391 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -870,7 +870,7 @@ <&apps_smmu 0x94 0x11>, <&apps_smmu 0x96 0x11>, <&apps_smmu 0x98 0x1>, - <&apps_smmu 0x9F 0>; + <&apps_smmu 0x9f 0>; }; crypto: crypto@1b3a000 { @@ -885,7 +885,7 @@ <&apps_smmu 0x94 0x11>, <&apps_smmu 0x96 0x11>, <&apps_smmu 0x98 0x1>, - <&apps_smmu 0x9F 0>; + <&apps_smmu 0x9f 0>; }; usb_qmpphy: phy@1615000 { @@ -1715,8 +1715,12 @@ gpu: gpu@5900000 { compatible = "qcom,adreno-610.0", "qcom,adreno"; - reg = <0x0 0x05900000 0x0 0x40000>; - reg-names = "kgsl_3d0_reg_memory"; + reg = <0x0 0x05900000 0x0 0x40000>, + <0x0 0x0599e000 0x0 0x1000>, + <0x0 0x05961000 0x0 0x800>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; /* There's no (real) GMU, so we have to handle quite a bunch of clocks! */ clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>, diff --git a/arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo.dts b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo.dts index 68a237215bd1..6b68e391cf3e 100644 --- a/arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo.dts +++ b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo.dts @@ -19,7 +19,7 @@ chassis-type = "handset"; /* required for bootloader to select correct board */ - qcom,msm-id = <QCOM_ID_SM6125>; + qcom,msm-id = <QCOM_ID_SM6125 0x10000>; qcom,board-id = <22 0>; chosen { diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index 8f2d65543373..80c42dff5399 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -724,7 +724,7 @@ clock-names = "iface", "core", "xo"; iommus = <&apps_smmu 0x160 0x0>; - power-domains = <&rpmpd SM6125_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; qcom,dll-config = <0x000f642c>; qcom,ddr-config = <0x80040873>; @@ -755,7 +755,7 @@ pinctrl-1 = <&sdc2_off_state>; pinctrl-names = "default", "sleep"; - power-domains = <&rpmpd SM6125_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; qcom,dll-config = <0x0007642c>; qcom,ddr-config = <0x80040873>; @@ -1275,7 +1275,7 @@ assigned-clock-rates = <19200000>; operating-points-v2 = <&mdp_opp_table>; - power-domains = <&rpmpd SM6125_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; ports { #address-cells = <1>; @@ -1345,7 +1345,7 @@ <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; operating-points-v2 = <&dsi_opp_table>; - power-domains = <&rpmpd SM6125_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; phys = <&mdss_dsi0_phy>; phy-names = "dsi"; @@ -1406,7 +1406,7 @@ "ref"; required-opps = <&rpmpd_opp_nom>; - power-domains = <&rpmpd SM6125_VDDMX>; + power-domains = <&rpmpd RPMPD_VDDMX>; status = "disabled"; }; @@ -1434,7 +1434,7 @@ "gcc_disp_gpll0_div_clk_src"; required-opps = <&rpmpd_opp_ret>; - power-domains = <&rpmpd SM6125_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; #clock-cells = <1>; #power-domain-cells = <1>; diff --git a/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts b/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts index 8848043f95f2..6e2bbf4f060a 100644 --- a/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts +++ b/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts @@ -14,7 +14,7 @@ compatible = "sony,pdx213", "qcom,sm6350"; chassis-type = "handset"; qcom,msm-id = <434 0x10000>, <459 0x10000>; - qcom,board-id = <0x1000B 0>; + qcom,board-id = <0x1000b 0>; chosen { #address-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index f34dc6e278b8..9f9b9f9af0da 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1117,6 +1117,7 @@ reg = <0x0 0x016e0000 0x0 0x15080>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; }; aggre2_noc: interconnect@1700000 { @@ -1124,6 +1125,8 @@ reg = <0x0 0x01700000 0x0 0x1f880>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&rpmhcc RPMH_IPA_CLK>; compute_noc: interconnect-compute-noc { compatible = "qcom,sm6350-compute-noc"; diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts index 4afbab570ca1..a3c2b26736f4 100644 --- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts @@ -246,6 +246,46 @@ }; }; }; + + vreg_32m_cam_dvdd_1p05: regulator-32m-cam-dvdd-1p05 { + compatible = "regulator-fixed"; + regulator-name = "32M_CAM_DVDD_1P05"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + gpio = <&pm6150l_gpios 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vreg_s8e>; + }; + + vreg_48m_ois_avdd0_1p8: regulator-48m-ois-avdd0-1p8 { + compatible = "regulator-fixed"; + regulator-name = "48M_OIS_AVDD0_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&pm6150l_gpios 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vreg_bob>; + }; + + vreg_48m_uw_avdd0_1p8: regulator-48m-uw-avdd0-1p8 { + compatible = "regulator-fixed"; + regulator-name = "48M_UW_AVDD0_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&pm6150l_gpios 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vreg_bob>; + }; + + vreg_ois_2p8: regulator-ois-2p8 { + compatible = "regulator-fixed"; + regulator-name = "OIS_2P8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&tlmm 72 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vreg_bob>; + }; }; &adsp { @@ -512,11 +552,28 @@ }; &cci0_i2c0 { - /* IMX582 @ 0x1a */ + /* Main cam (Sony IMX582) @ 0x1a */ + /* VCM driver (Onsemi LC898219XI) @ 0x28 */ + /* OIS driver (CML CM401) @ 0x30 */ + + eeprom@50 { + compatible = "giantec,gt24p128e", "atmel,24c128"; + reg = <0x50>; + vcc-supply = <&vreg_l6p>; + read-only; + }; }; &cci0_i2c1 { - /* IMX582 @ 0x1a */ + /* VCM driver (Dongwoon DW9800W) @ 0xc */ + /* Ultra-wide cam (Sony IMX582) @ 0x1a */ + + eeprom@50 { + compatible = "giantec,gt24p64a", "atmel,24c64"; + reg = <0x50>; + vcc-supply = <&vreg_l6p>; + read-only; + }; }; &cci1 { @@ -524,7 +581,14 @@ }; &cci1_i2c0 { - /* IMX576 @ 0x10 */ + /* Front cam (Sony IMX576) @ 0x10 */ + + eeprom@50 { + compatible = "giantec,gt24p64a", "atmel,24c64"; + reg = <0x50>; + vcc-supply = <&vreg_l6p>; + read-only; + }; }; &cdsp { @@ -629,6 +693,8 @@ regulator-name = "vreg_l6p"; regulator-min-microvolt = <1500000>; regulator-max-microvolt = <1800000>; + /* Pull-up for CCI I2C busses */ + regulator-always-on; }; vreg_l7p: ldo7 { diff --git a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts index 0339a572f34d..1eea9c5c6684 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts @@ -387,6 +387,10 @@ status = "okay"; }; +&gpu_zap_shader { + firmware-name = "qcom/sm8150/a640_zap.mbn"; +}; + &i2c4 { clock-frequency = <100000>; diff --git a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts index 12e8e1ada6d8..0f2d511624a8 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts @@ -358,6 +358,10 @@ status = "okay"; }; +&gpu_zap_shader { + firmware-name = "qcom/sm8150/a640_zap.mbn"; +}; + &pon { mode-bootloader = <0x2>; mode-recovery = <0x1>; diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index e3ec99972a28..97ca5275d740 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1693,6 +1693,15 @@ status = "disabled"; }; + uart13: serial@c8c000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00c8c000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + i2c14: i2c@c90000 { compatible = "qcom,geni-i2c"; reg = <0 0x00c90000 0 0x4000>; @@ -2381,7 +2390,7 @@ reg = <0x0 0x03100000 0x0 0x300000>, <0x0 0x03500000 0x0 0x300000>, <0x0 0x03900000 0x0 0x300000>, - <0x0 0x03D00000 0x0 0x300000>; + <0x0 0x03d00000 0x0 0x300000>; reg-names = "west", "east", "north", "south"; interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; gpio-ranges = <&tlmm 0 0 176>; diff --git a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts index f5c193c6c5f9..3ea9d2b1a7d5 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts @@ -373,6 +373,10 @@ status = "okay"; }; +&gpu_zap_shader { + firmware-name = "qcom/sm8250/a650_zap.mbn"; +}; + &pon { mode-bootloader = <0x2>; mode-recovery = <0x1>; diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk-rear-camera-card.dtso b/arch/arm64/boot/dts/qcom/sm8550-hdk-rear-camera-card.dtso index 66bec0fef766..21bfba6a1182 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-hdk-rear-camera-card.dtso +++ b/arch/arm64/boot/dts/qcom/sm8550-hdk-rear-camera-card.dtso @@ -52,14 +52,13 @@ pinctrl-0 = <&cam3_default>; pinctrl-names = "default"; afvdd-supply = <&vreg_l7n_2p96>; - avdd-supply = <&vreg_l4m_2p8>; - dovdd-supply = <&vreg_l5n_1p8>; - dvdd-supply = <&vreg_l2m_1p056>; + vdda-supply = <&vreg_l4m_2p8>; + vddd-supply = <&vreg_l2m_1p056>; + vddio-supply = <&vreg_l5n_1p8>; port { cam_tele: endpoint { link-frequencies = /bits/ 64 <602500000>; - data-lanes = <0 1 2 3>; remote-endpoint = <&csiphy3_ep>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts index 599850c48494..ee13e6136a82 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts @@ -1107,6 +1107,22 @@ vdd3-supply = <&vreg_l5b_3p1>; }; +&pm8550vs_c { + status = "okay"; +}; + +&pm8550vs_d { + status = "okay"; +}; + +&pm8550vs_e { + status = "okay"; +}; + +&pm8550vs_g { + status = "okay"; +}; + &pon_pwrkey { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index f430038bd402..94ed1c221856 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -789,6 +789,22 @@ vdd3-supply = <&vreg_l5b_3p1>; }; +&pm8550vs_c { + status = "okay"; +}; + +&pm8550vs_d { + status = "okay"; +}; + +&pm8550vs_e { + status = "okay"; +}; + +&pm8550vs_g { + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index 05c98fe2c25b..c35d4737a412 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -748,14 +748,13 @@ pinctrl-0 = <&cam3_default>; pinctrl-names = "default"; afvdd-supply = <&vreg_l7n_2p96>; - avdd-supply = <&vreg_l4m_2p8>; - dovdd-supply = <&vreg_l5n_1p8>; - dvdd-supply = <&vreg_l2m_1p056>; + vdda-supply = <&vreg_l4m_2p8>; + vddd-supply = <&vreg_l2m_1p056>; + vddio-supply = <&vreg_l5n_1p8>; port { cam_tele: endpoint { link-frequencies = /bits/ 64 <602500000>; - data-lanes = <0 1 2 3>; remote-endpoint = <&csiphy3_ep>; }; }; @@ -1003,6 +1002,22 @@ vdd3-supply = <&vreg_l5b_3p1>; }; +&pm8550vs_c { + status = "okay"; +}; + +&pm8550vs_d { + status = "okay"; +}; + +&pm8550vs_e { + status = "okay"; +}; + +&pm8550vs_g { + status = "okay"; +}; + &pon_pwrkey { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts index b4ef40ae2cd9..81c02ee27fe9 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts @@ -533,6 +533,22 @@ }; }; +&pm8550vs_c { + status = "okay"; +}; + +&pm8550vs_d { + status = "okay"; +}; + +&pm8550vs_e { + status = "okay"; +}; + +&pm8550vs_g { + status = "okay"; +}; + &pon_pwrkey { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts index d90dc7b37c4a..0e6ed6fce614 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts @@ -661,6 +661,22 @@ }; }; +&pm8550vs_c { + status = "okay"; +}; + +&pm8550vs_d { + status = "okay"; +}; + +&pm8550vs_e { + status = "okay"; +}; + +&pm8550vs_g { + status = "okay"; +}; + &pm8550vs_g_gpios { cam_pwr_a_cs: cam-pwr-a-cs-state { pins = "gpio4"; diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk-rear-camera-card.dtso b/arch/arm64/boot/dts/qcom/sm8650-hdk-rear-camera-card.dtso new file mode 100644 index 000000000000..8a7c6d7634d3 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8650-hdk-rear-camera-card.dtso @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * SM8650-HDK Rear Camera Card overlay + * + * Copyright (c) 2025, Linaro Limited + */ + +#include <dt-bindings/clock/qcom,sm8650-camcc.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> + +/dts-v1/; +/plugin/; + +&camss { + vdd-csiphy35-0p9-supply = <&vreg_l2i_0p88>; + vdd-csiphy35-1p2-supply = <&vreg_l3i_1p2>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@3 { + reg = <3>; + + csiphy3_ep: endpoint { + data-lanes = <0 1 2 3>; + remote-endpoint = <&cam_tele>; + }; + }; + }; +}; + +&cci1 { + status = "okay"; +}; + +&cci1_i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + sensor@56 { + compatible = "samsung,s5kjn1"; + reg = <0x56>; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + assigned-clocks = <&camcc CAM_CC_MCLK3_CLK>; + assigned-clock-rates = <24000000>; + reset-gpios = <&tlmm 109 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&cam3_default>; + pinctrl-names = "default"; + afvdd-supply = <&vreg_l7m_2p96>; + vdda-supply = <&vreg_l4m_2p8>; + vddd-supply = <&vreg_l2m_1p056>; + vddio-supply = <&vreg_l3n_1p8>; + + port { + cam_tele: endpoint { + link-frequencies = /bits/ 64 <700000000>; + remote-endpoint = <&csiphy3_ep>; + }; + }; + }; +}; + +&pm8550_flash { + status = "okay"; + + led-0 { + function = LED_FUNCTION_FLASH; + color = <LED_COLOR_ID_YELLOW>; + led-sources = <1>, <4>; + led-max-microamp = <500000>; + flash-max-microamp = <2000000>; + flash-max-timeout-us = <1280000>; + function-enumerator = <0>; + }; + + led-1 { + function = LED_FUNCTION_FLASH; + color = <LED_COLOR_ID_WHITE>; + led-sources = <2>, <3>; + led-max-microamp = <500000>; + flash-max-microamp = <2000000>; + flash-max-timeout-us = <1280000>; + function-enumerator = <1>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts index 5bf1af3308ce..eabc828c05b4 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts @@ -1046,6 +1046,22 @@ vdd3-supply = <&vreg_l5b_3p1>; }; +&pm8550vs_c { + status = "okay"; +}; + +&pm8550vs_d { + status = "okay"; +}; + +&pm8550vs_e { + status = "okay"; +}; + +&pm8550vs_g { + status = "okay"; +}; + &pon_pwrkey { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts index c67bbace2743..bb688a5d21c2 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts @@ -692,6 +692,22 @@ vdd3-supply = <&vreg_l5b_3p1>; }; +&pm8550vs_c { + status = "okay"; +}; + +&pm8550vs_d { + status = "okay"; +}; + +&pm8550vs_e { + status = "okay"; +}; + +&pm8550vs_g { + status = "okay"; +}; + &qupv3_id_1 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts index b2feac61a89f..087828c60692 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -741,6 +741,49 @@ }; }; +&camss { + vdd-csiphy35-0p9-supply = <&vreg_l2i_0p88>; + vdd-csiphy35-1p2-supply = <&vreg_l3i_1p2>; + status = "okay"; + + ports { + port@3 { + csiphy3_ep: endpoint { + data-lanes = <0 1 2 3>; + remote-endpoint = <&cam_tele>; + }; + }; + }; +}; + +&cci1 { + status = "okay"; +}; + +&cci1_i2c0 { + sensor@56 { + compatible = "samsung,s5kjn1"; + reg = <0x56>; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + assigned-clocks = <&camcc CAM_CC_MCLK3_CLK>; + assigned-clock-rates = <24000000>; + reset-gpios = <&tlmm 109 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&cam3_default>; + pinctrl-names = "default"; + afvdd-supply = <&vreg_l7m_2p96>; + vdda-supply = <&vreg_l4m_2p8>; + vddd-supply = <&vreg_l2m_1p056>; + vddio-supply = <&vreg_l3n_1p8>; + + port { + cam_tele: endpoint { + link-frequencies = /bits/ 64 <700000000>; + remote-endpoint = <&csiphy3_ep>; + }; + }; + }; +}; + &gpi_dma1 { status = "okay"; }; @@ -1002,6 +1045,22 @@ vdd3-supply = <&vreg_l5b_3p1>; }; +&pm8550vs_c { + status = "okay"; +}; + +&pm8550vs_d { + status = "okay"; +}; + +&pm8550vs_e { + status = "okay"; +}; + +&pm8550vs_g { + status = "okay"; +}; + &qup_i2c3_data_clk { /* Use internal I2C pull-up */ bias-pull-up = <2200>; diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index f8e1950a74ac..357e43b90740 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -5377,6 +5377,193 @@ }; }; + camss: isp@acb6000 { + compatible = "qcom,sm8650-camss"; + + reg = <0 0x0acb6000 0 0x1000>, + <0 0x0acb8000 0 0x1000>, + <0 0x0acba000 0 0x1000>, + <0 0x0acbc000 0 0x1000>, + <0 0x0accb000 0 0x1000>, + <0 0x0acd0000 0 0x1000>, + <0 0x0ace4000 0 0x2000>, + <0 0x0ace6000 0 0x2000>, + <0 0x0ace8000 0 0x2000>, + <0 0x0acea000 0 0x2000>, + <0 0x0acec000 0 0x2000>, + <0 0x0acee000 0 0x2000>, + <0 0x0ac62000 0 0xf000>, + <0 0x0ac71000 0 0xf000>, + <0 0x0ac80000 0 0xf000>, + <0 0x0accc000 0 0x2000>, + <0 0x0acd1000 0 0x2000>; + reg-names = "csid_wrapper", + "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csiphy5", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1"; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, + <&camcc CAM_CC_CPAS_IFE_0_CLK>, + <&camcc CAM_CC_CPAS_IFE_1_CLK>, + <&camcc CAM_CC_CPAS_IFE_2_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY3_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI5PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY5_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_2_CLK>, + <&camcc CAM_CC_IFE_2_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>; + clock-names = "camnoc_axi", + "cpas_ahb", + "cpas_fast_ahb", + "cpas_vfe0", + "cpas_vfe1", + "cpas_vfe2", + "cpas_vfe_lite", + "csid", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy3", + "csiphy3_timer", + "csiphy4", + "csiphy4_timer", + "csiphy5", + "csiphy5_timer", + "csiphy_rx", + "gcc_axi_hf", + "qdss_debug_xo", + "vfe0", + "vfe0_fast_ahb", + "vfe1", + "vfe1_fast_ahb", + "vfe2", + "vfe2_fast_ahb", + "vfe_lite", + "vfe_lite_ahb", + "vfe_lite_cphy_rx", + "vfe_lite_csid"; + + interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 603 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 431 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 605 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 376 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 477 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 448 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 122 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 89 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 602 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 604 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 688 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 606 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 377 IRQ_TYPE_EDGE_RISING 0>; + interrupt-names = "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csiphy5", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1"; + + interconnects = <&gem_noc MASTER_APPSS_PROC 0 + &config_noc SLAVE_CAMERA_CFG 0>, + <&mmss_noc MASTER_CAMNOC_HF 0 + &mc_virt SLAVE_EBI1 0>; + interconnect-names = "ahb", + "hf_mnoc"; + + iommus = <&apps_smmu 0x800 0x20>, + <&apps_smmu 0x18a0 0x40>, + <&apps_smmu 0x1860 0x00>; + + power-domains = <&camcc CAM_CC_IFE_0_GDSC>, + <&camcc CAM_CC_IFE_1_GDSC>, + <&camcc CAM_CC_IFE_2_GDSC>, + <&camcc CAM_CC_TITAN_TOP_GDSC>; + power-domain-names = "ife0", "ife1", "ife2", "top"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + + port@2 { + reg = <2>; + }; + + port@3 { + reg = <3>; + }; + + port@4 { + reg = <4>; + }; + + port@5 { + reg = <5>; + }; + }; + }; + camcc: clock-controller@ade0000 { compatible = "qcom,sm8650-camcc"; reg = <0 0x0ade0000 0 0x20000>; @@ -5919,6 +6106,118 @@ wakeup-parent = <&pdc>; + cam0_default: cam0-default-state { + pins = "gpio100"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + cam0_sleep: cam0-sleep-state { + pins = "gpio100"; + function = "cam_mclk"; + drive-strength = <2>; + bias-pull-down; + }; + + cam1_default: cam1-default-state { + pins = "gpio101"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + cam1_sleep: cam1-sleep-state { + pins = "gpio101"; + function = "cam_mclk"; + drive-strength = <2>; + bias-pull-down; + }; + + cam2_default: cam2-default-state { + pins = "gpio102"; + function = "cam_aon_mclk2"; + drive-strength = <2>; + bias-disable; + }; + + cam2_sleep: cam2-sleep-state { + pins = "gpio102"; + function = "cam_aon_mclk2"; + drive-strength = <2>; + bias-pull-down; + }; + + cam3_default: cam3-default-state { + pins = "gpio103"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + cam3_sleep: cam3-sleep-state { + pins = "gpio103"; + function = "cam_mclk"; + drive-strength = <2>; + bias-pull-down; + }; + + cam4_default: cam4-default-state { + pins = "gpio104"; + function = "cam_aon_mclk4"; + drive-strength = <2>; + bias-disable; + }; + + cam4_sleep: cam4-sleep-state { + pins = "gpio104"; + function = "cam_aon_mclk4"; + drive-strength = <2>; + bias-pull-down; + }; + + cam5_default: cam5-default-state { + pins = "gpio105"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + cam5_sleep: cam5-sleep-state { + pins = "gpio105"; + function = "cam_mclk"; + drive-strength = <2>; + bias-pull-down; + }; + + cam6_default: cam6-default-state { + pins = "gpio108"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + cam6_sleep: cam6-sleep-state { + pins = "gpio108"; + function = "cam_mclk"; + drive-strength = <2>; + bias-pull-down; + }; + + cam7_default: cam7-default-state { + pins = "gpio106"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + cam7_sleep: cam7-sleep-state { + pins = "gpio106"; + function = "cam_mclk"; + drive-strength = <2>; + bias-pull-down; + }; + cci0_0_default: cci0-0-default-state { sda-pins { pins = "gpio113"; diff --git a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts index c8cb521b4c26..cb718331496e 100644 --- a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts @@ -925,6 +925,10 @@ }; }; +&iris { + status = "okay"; +}; + &lpass_vamacro { pinctrl-0 = <&dmic01_default>, <&dmic23_default>; pinctrl-names = "default"; @@ -1039,10 +1043,14 @@ }; &pmih0108_eusb2_repeater { - status = "okay"; + qcom,tune-usb2-preem = /bits/ 8 <0x3>; + qcom,tune-usb2-amplitude = /bits/ 8 <0xa>; + qcom,squelch-detector-bp = <(-2000)>; vdd18-supply = <&vreg_l15b_1p8>; vdd3-supply = <&vreg_l5b_3p1>; + + status = "okay"; }; &qupv3_1 { @@ -1075,6 +1083,22 @@ status = "fail"; }; +&sdhc_2 { + cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>; + + vmmc-supply = <&vreg_l9b_2p9>; + vqmmc-supply = <&vreg_l8b_1p8>; + + no-sdio; + no-mmc; + + pinctrl-0 = <&sdc2_default &sdc2_card_det_n>; + pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>; + pinctrl-names = "default", "sleep"; + + status = "okay"; +}; + &swr0 { status = "okay"; @@ -1194,6 +1218,13 @@ }; }; + sdc2_card_det_n: sd-card-det-n-state { + pins = "gpio55"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + wcd_default: wcd-reset-n-active-state { pins = "gpio101"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/sm8750-qrd.dts b/arch/arm64/boot/dts/qcom/sm8750-qrd.dts index b0cb61c5a603..801c46d55602 100644 --- a/arch/arm64/boot/dts/qcom/sm8750-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8750-qrd.dts @@ -858,6 +858,10 @@ }; }; +&iris { + status = "okay"; +}; + &pm8550_flash { status = "okay"; @@ -961,6 +965,22 @@ status = "okay"; }; +&sdhc_2 { + cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>; + + vmmc-supply = <&vreg_l9b_2p9>; + vqmmc-supply = <&vreg_l8b_1p8>; + + no-sdio; + no-mmc; + + pinctrl-0 = <&sdc2_default &sdc2_card_det_n>; + pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>; + pinctrl-names = "default", "sleep"; + + status = "okay"; +}; + &swr0 { status = "okay"; @@ -1053,6 +1073,13 @@ /* reserved for secure world */ gpio-reserved-ranges = <36 4>, <74 1>; + sdc2_card_det_n: sd-card-det-n-state { + pins = "gpio55"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + spkr_0_sd_n_active: spkr-0-sd-n-active-state { pins = "gpio76"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 3f0b57f428bb..f56b1f889b85 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -6,7 +6,9 @@ #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/clock/qcom,sm8750-gcc.h> #include <dt-bindings/clock/qcom,sm8750-tcsr.h> +#include <dt-bindings/clock/qcom,sm8750-videocc.h> #include <dt-bindings/dma/qcom-gpi.h> +#include <dt-bindings/firmware/qcom,scm.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interconnect/qcom,icc.h> #include <dt-bindings/interconnect/qcom,sm8750-rpmh.h> @@ -35,8 +37,8 @@ reg = <0x0 0x0>; enable-method = "psci"; next-level-cache = <&l2_0>; - power-domains = <&cpu_pd0>; - power-domain-names = "psci"; + power-domains = <&cpu_pd0>, <&scmi_dvfs 0>; + power-domain-names = "psci", "perf"; l2_0: l2-cache { compatible = "cache"; @@ -51,8 +53,8 @@ reg = <0x0 0x100>; enable-method = "psci"; next-level-cache = <&l2_0>; - power-domains = <&cpu_pd1>; - power-domain-names = "psci"; + power-domains = <&cpu_pd1>, <&scmi_dvfs 0>; + power-domain-names = "psci", "perf"; }; cpu2: cpu@200 { @@ -61,8 +63,8 @@ reg = <0x0 0x200>; enable-method = "psci"; next-level-cache = <&l2_0>; - power-domains = <&cpu_pd2>; - power-domain-names = "psci"; + power-domains = <&cpu_pd2>, <&scmi_dvfs 0>; + power-domain-names = "psci", "perf"; }; cpu3: cpu@300 { @@ -71,8 +73,8 @@ reg = <0x0 0x300>; enable-method = "psci"; next-level-cache = <&l2_0>; - power-domains = <&cpu_pd3>; - power-domain-names = "psci"; + power-domains = <&cpu_pd3>, <&scmi_dvfs 0>; + power-domain-names = "psci", "perf"; }; cpu4: cpu@400 { @@ -81,8 +83,8 @@ reg = <0x0 0x400>; enable-method = "psci"; next-level-cache = <&l2_0>; - power-domains = <&cpu_pd4>; - power-domain-names = "psci"; + power-domains = <&cpu_pd4>, <&scmi_dvfs 0>; + power-domain-names = "psci", "perf"; }; cpu5: cpu@500 { @@ -91,8 +93,8 @@ reg = <0x0 0x500>; enable-method = "psci"; next-level-cache = <&l2_0>; - power-domains = <&cpu_pd5>; - power-domain-names = "psci"; + power-domains = <&cpu_pd5>, <&scmi_dvfs 0>; + power-domain-names = "psci", "perf"; }; cpu6: cpu@10000 { @@ -101,8 +103,8 @@ reg = <0x0 0x10000>; enable-method = "psci"; next-level-cache = <&l2_1>; - power-domains = <&cpu_pd6>; - power-domain-names = "psci"; + power-domains = <&cpu_pd6>, <&scmi_dvfs 1>; + power-domain-names = "psci", "perf"; l2_1: l2-cache { compatible = "cache"; @@ -117,8 +119,8 @@ reg = <0x0 0x10100>; enable-method = "psci"; next-level-cache = <&l2_1>; - power-domains = <&cpu_pd7>; - power-domain-names = "psci"; + power-domains = <&cpu_pd7>, <&scmi_dvfs 1>; + power-domain-names = "psci", "perf"; }; cpu-map { @@ -206,6 +208,21 @@ interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; }; + + scmi { + compatible = "arm,scmi"; + mboxes = <&cpucp_mbox 0>, <&cpucp_mbox 2>; + mbox-names = "tx", "rx"; + shmem = <&cpu_scp_lpri0>, <&cpu_scp_lpri1>; + + #address-cells = <1>; + #size-cells = <0>; + + scmi_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + }; }; clk_virt: interconnect-0 { @@ -524,6 +541,14 @@ reg = <0x0 0xff800000 0x0 0x800000>; no-map; }; + + adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + alignment = <0x0 0x400000>; + size = <0x0 0xc00000>; + reusable; + }; }; smp2p-adsp { @@ -2073,6 +2098,8 @@ <&apps_smmu 0x481 0>; qcom,ee = <0>; + qcom,num-ees = <4>; + num-channels = <20>; qcom,controlled-remotely; }; @@ -2196,6 +2223,66 @@ qcom,remote-pid = <2>; label = "lpass"; + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "adsp"; + memory-region = <&adsp_rpc_remote_heap_mem>; + qcom,vmids = <QCOM_SCM_VMID_LPASS + QCOM_SCM_VMID_ADSP_HEAP>; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x1003 0x80>, + <&apps_smmu 0x1043 0x20>; + dma-coherent; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x1004 0x80>, + <&apps_smmu 0x1044 0x20>; + dma-coherent; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x1005 0x80>, + <&apps_smmu 0x1045 0x20>; + dma-coherent; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x1006 0x80>, + <&apps_smmu 0x1046 0x20>; + dma-coherent; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x1007 0x40>, + <&apps_smmu 0x1067 0x0>, + <&apps_smmu 0x1087 0x0>; + dma-coherent; + }; + + compute-cb@8 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; + iommus = <&apps_smmu 0x1008 0x80>, + <&apps_smmu 0x1048 0x20>; + dma-coherent; + }; + }; + gpr { compatible = "qcom,gpr"; qcom,glink-channels = "adsp_apps"; @@ -2582,6 +2669,60 @@ }; }; + sdhc_2: mmc@8804000 { + compatible = "qcom,sm8750-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x0 0x08804000 0x0 0x1000>; + + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", + "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", + "core", + "xo"; + + interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "sdhc-ddr", + "cpu-sdhc"; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&sdhc2_opp_table>; + + qcom,dll-config = <0x0007442c>; + qcom,ddr-config = <0x80040868>; + + iommus = <&apps_smmu 0x540 0x0>; + dma-coherent; + + bus-width = <4>; + max-sd-hs-hz = <37500000>; + + resets = <&gcc GCC_SDCC2_BCR>; + + status = "disabled"; + + sdhc2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + usb_hsphy: phy@88e3000 { compatible = "qcom,sm8750-m31-eusb2-phy"; reg = <0x0 0x88e3000 0x0 0x29c>; @@ -2740,6 +2881,126 @@ }; }; + iris: video-codec@aa00000 { + compatible = "qcom,sm8750-iris"; + reg = <0x0 0x0aa00000 0x0 0xf0000>; + + clocks = <&gcc GCC_VIDEO_AXI0_CLK>, + <&videocc VIDEO_CC_MVS0C_CLK>, + <&videocc VIDEO_CC_MVS0_CLK>, + <&gcc GCC_VIDEO_AXI1_CLK>, + <&videocc VIDEO_CC_MVS0C_FREERUN_CLK>, + <&videocc VIDEO_CC_MVS0_FREERUN_CLK>; + clock-names = "iface", + "core", + "vcodec0_core", + "iface1", + "core_freerun", + "vcodec0_core_freerun"; + + dma-coherent; + iommus = <&apps_smmu 0x1940 0>, + <&apps_smmu 0x1947 0>; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_VIDEO_MVP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "cpu-cfg", + "video-mem"; + + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + + memory-region = <&video_mem>; + + operating-points-v2 = <&iris_opp_table>; + + power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, + <&videocc VIDEO_CC_MVS0_GDSC>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_MMCX>; + power-domain-names = "venus", + "vcodec0", + "mxc", + "mmcx"; + + resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, + <&gcc GCC_VIDEO_AXI1_CLK_ARES>, + <&videocc VIDEO_CC_MVS0C_FREERUN_CLK_ARES>, + <&videocc VIDEO_CC_MVS0_FREERUN_CLK_ARES>; + reset-names = "bus0", + "bus1", + "core", + "vcodec0_core"; + + /* + * IRIS firmware is signed by vendors, only + * enable in boards where the proper signed firmware + * is available. + */ + status = "disabled"; + + iris_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>, + <&rpmhpd_opp_low_svs_d1>; + }; + + opp-338000000 { + opp-hz = /bits/ 64 <338000000>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + }; + + opp-420000000 { + opp-hz = /bits/ 64 <420000000>; + required-opps = <&rpmhpd_opp_svs>, + <&rpmhpd_opp_svs>; + }; + + opp-444000000 { + opp-hz = /bits/ 64 <444000000>; + required-opps = <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_svs_l1>; + }; + + opp-533333334 { + opp-hz = /bits/ 64 <533333334>; + required-opps = <&rpmhpd_opp_nom>, + <&rpmhpd_opp_nom>; + }; + + opp-570000000 { + opp-hz = /bits/ 64 <570000000>; + required-opps = <&rpmhpd_opp_nom_l1>, + <&rpmhpd_opp_nom_l1>; + }; + + opp-630000000 { + opp-hz = /bits/ 64 <630000000>; + required-opps = <&rpmhpd_opp_turbo>, + <&rpmhpd_opp_turbo>; + }; + }; + }; + + videocc: clock-controller@aaf0000 { + compatible = "qcom,sm8750-videocc"; + reg = <0x0 0x0aaf0000 0x0 0x10000>; + clocks = <&bi_tcxo_div2>, + <&gcc GCC_VIDEO_AHB_CLK>; + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm8750-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>; @@ -3313,6 +3574,947 @@ #reset-cells = <1>; }; + stm@10002000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0x0 0x10002000 0x0 0x1000>, + <0x0 0x37280000 0x0 0x180000>; + reg-names = "stm-base", + "stm-stimulus-base"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + stm_out: endpoint { + remote-endpoint = <&funnel_in0_in7>; + }; + }; + }; + }; + + tpda@10004000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x10004000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + tpda_qdss_in1: endpoint { + remote-endpoint = <&tpdm_spdm_out>; + }; + }; + + }; + + out-ports { + port { + tpda_qdss_out: endpoint { + remote-endpoint = <&funnel_in0_in6>; + }; + }; + }; + }; + + tpdm@1000f000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1000f000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + tpdm_spdm_out: endpoint { + remote-endpoint = <&tpda_qdss_in1>; + }; + }; + }; + }; + + funnel@10041000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x10041000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + funnel_in0_in0: endpoint { + remote-endpoint = <&tn_ag_out>; + }; + }; + + port@6 { + reg = <6>; + + funnel_in0_in6: endpoint { + remote-endpoint = <&tpda_qdss_out>; + }; + }; + + port@7 { + reg = <7>; + + funnel_in0_in7: endpoint { + remote-endpoint = <&stm_out>; + }; + }; + }; + + out-ports { + port { + funnel_in0_out: endpoint { + remote-endpoint = <&funnel_aoss_in7>; + }; + }; + }; + }; + + tpdm@10800000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10800000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_modem0_out: endpoint { + remote-endpoint = <&tpda_modem_in0>; + }; + }; + }; + }; + + tpda@10803000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x10803000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tpda_modem_in0: endpoint { + remote-endpoint = <&tpdm_modem0_out>; + }; + }; + + port@1 { + reg = <1>; + + tpda_modem_in1: endpoint { + remote-endpoint = <&tpdm_modem1_out>; + }; + }; + }; + + out-ports { + port { + tpda_modem_out: endpoint { + remote-endpoint = <&funnel_modem_dl_in0>; + }; + }; + }; + }; + + funnel@10804000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x10804000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + funnel_modem_dl_in0: endpoint { + remote-endpoint = <&tpda_modem_out>; + }; + }; + }; + + out-ports { + port { + funnel_modem_dl_out: endpoint { + remote-endpoint = <&tn_ag_in13>; + }; + }; + }; + }; + + cti@1080b000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x1080b000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + tpdm@1082c000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1082c000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_gcc_out: endpoint { + remote-endpoint = <&tn_ag_in17>; + }; + }; + }; + }; + + tpdm@10841000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10841000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + tpdm_prng_out: endpoint { + remote-endpoint = <&tn_ag_in18>; + }; + }; + }; + }; + + tpdm@1084e000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1084e000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <32>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + tpdm_mm_bcv_out: endpoint { + remote-endpoint = <&tpda_mm_in0>; + }; + }; + }; + }; + + tpdm@1084f000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1084f000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <32>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + tpdm_mm_lmh_out: endpoint { + remote-endpoint = <&tpda_mm_in1>; + }; + }; + }; + }; + + tpdm@10850000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10850000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + tpdm_mm_dpm_out: endpoint { + remote-endpoint = <&tpda_mm_in2>; + }; + }; + }; + }; + + tpda@10851000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x10851000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tpda_mm_in0: endpoint { + remote-endpoint = <&tpdm_mm_bcv_out>; + }; + }; + + port@1 { + reg = <1>; + + tpda_mm_in1: endpoint { + remote-endpoint = <&tpdm_mm_lmh_out>; + }; + }; + + port@2 { + reg = <2>; + + tpda_mm_in2: endpoint { + remote-endpoint = <&tpdm_mm_dpm_out>; + }; + }; + }; + + out-ports { + port { + tpda_mm_out: endpoint { + remote-endpoint = <&tn_ag_in4>; + }; + }; + }; + }; + + tpdm@10980000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10980000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_cdsp_out: endpoint { + remote-endpoint = <&tpda_cdsp_in0>; + }; + }; + }; + }; + + tpda@10986000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x10986000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tpda_cdsp_in0: endpoint { + remote-endpoint = <&tpdm_cdsp_out>; + }; + }; + + port@1 { + reg = <1>; + + tpda_cdsp_in1: endpoint { + remote-endpoint = <&tpdm_cdsp_llm_out>; + }; + }; + + port@2 { + reg = <2>; + + tpda_cdsp_in2: endpoint { + remote-endpoint = <&tpdm_cdsp_llm2_out>; + }; + }; + }; + + out-ports { + port { + tpda_cdsp_out: endpoint { + remote-endpoint = <&funnel_cdsp_in0>; + }; + }; + }; + }; + + funnel@10987000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x10987000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + funnel_cdsp_in0: endpoint { + remote-endpoint = <&tpda_cdsp_out>; + }; + }; + }; + + out-ports { + port { + funnel_cdsp_out: endpoint { + remote-endpoint = <&tn_ag_in16>; + }; + }; + }; + }; + + cti@1098b000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x1098b000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + tpdm@109a3000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x109a3000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-msrs-num = <32>; + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_pmu_out: endpoint { + remote-endpoint = <&tn_ag_in29>; + }; + }; + }; + }; + + tpdm@109a4000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x109a4000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + tpdm_ipcc_cmb_out: endpoint { + remote-endpoint = <&tn_ag_in28>; + }; + }; + }; + }; + + tpdm@109a5000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x109a5000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_dl_mm_out: endpoint { + remote-endpoint = <&tn_ag_in25>; + }; + }; + }; + }; + + tpdm@109a6000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x109a6000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_north_dsb_out: endpoint { + remote-endpoint = <&tn_ag_in26>; + }; + }; + }; + }; + + tpdm@109a7000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x109a7000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_south_dsb_out: endpoint { + remote-endpoint = <&tn_ag_in27>; + }; + }; + }; + }; + + tpdm@109a8000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x109a8000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + tpdm_rdpm_cmb0_out: endpoint { + remote-endpoint = <&tn_ag_in30>; + }; + }; + }; + }; + + tpdm@109a9000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x109a9000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + tpdm_rdpm_cmb1_out: endpoint { + remote-endpoint = <&tn_ag_in31>; + }; + }; + }; + }; + + tpdm@109aa000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x109aa000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + tpdm_rdpm_cmb2_out: endpoint { + remote-endpoint = <&tn_ag_in32>; + }; + }; + }; + }; + + tn@109ab000 { + compatible = "qcom,coresight-tnoc", "arm,primecell"; + reg = <0x0 0x109ab000 0x0 0x4200>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@4 { + reg = <4>; + + tn_ag_in4: endpoint { + remote-endpoint = <&tpda_mm_out>; + }; + }; + + port@d { + reg = <0xd>; + + tn_ag_in13: endpoint { + remote-endpoint = <&funnel_modem_dl_out>; + }; + }; + + port@10 { + reg = <0x10>; + + tn_ag_in16: endpoint { + remote-endpoint = <&funnel_cdsp_out>; + }; + }; + + port@11 { + reg = <0x11>; + + tn_ag_in17: endpoint { + remote-endpoint = <&tpdm_gcc_out>; + }; + }; + + port@12 { + reg = <0x12>; + + tn_ag_in18: endpoint { + remote-endpoint = <&tpdm_prng_out>; + }; + }; + + port@13 { + reg = <0x13>; + + tn_ag_in19: endpoint { + remote-endpoint = <&tpdm_qm_out>; + }; + }; + + port@19 { + reg = <0x19>; + + tn_ag_in25: endpoint { + remote-endpoint = <&tpdm_dl_mm_out>; + }; + }; + + port@1a { + reg = <0x1a>; + + tn_ag_in26: endpoint { + remote-endpoint = <&tpdm_north_dsb_out>; + }; + }; + + port@1b { + reg = <0x1b>; + + tn_ag_in27: endpoint { + remote-endpoint = <&tpdm_south_dsb_out>; + }; + }; + + port@1c { + reg = <0x1c>; + + tn_ag_in28: endpoint { + remote-endpoint = <&tpdm_ipcc_cmb_out>; + }; + }; + + port@1d { + reg = <0x1d>; + + tn_ag_in29: endpoint { + remote-endpoint = <&tpdm_pmu_out>; + }; + }; + + port@1e { + reg = <0x1e>; + + tn_ag_in30: endpoint { + remote-endpoint = <&tpdm_rdpm_cmb0_out>; + }; + }; + + port@1f { + reg = <0x1f>; + + tn_ag_in31: endpoint { + remote-endpoint = <&tpdm_rdpm_cmb1_out>; + }; + }; + + port@20 { + reg = <0x20>; + + tn_ag_in32: endpoint { + remote-endpoint = <&tpdm_rdpm_cmb2_out>; + }; + }; + }; + + out-ports { + port { + tn_ag_out: endpoint { + remote-endpoint = <&funnel_in0_in0>; + }; + }; + }; + }; + + tpdm@109d0000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x109d0000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_qm_out: endpoint { + remote-endpoint = <&tn_ag_in19>; + }; + }; + }; + }; + + funnel@10b04000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x10b04000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@6 { + reg = <6>; + + funnel_aoss_in6: endpoint { + remote-endpoint = <&tpda_aoss_out>; + }; + }; + + port@7 { + reg = <7>; + + funnel_aoss_in7: endpoint { + remote-endpoint = <&funnel_in0_out>; + }; + }; + + }; + + out-ports { + port { + funnel_aoss_out: endpoint { + remote-endpoint = <&tmc_etf_in>; + }; + }; + }; + }; + + tmc@10b05000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x10b05000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + tmc_etf_in: endpoint { + remote-endpoint = <&funnel_aoss_out>; + }; + }; + }; + }; + + tpda@10b08000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x10b08000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tpda_aoss_in0: endpoint { + remote-endpoint = <&tpdm_swao_prio0_out>; + }; + }; + + port@1 { + reg = <1>; + + tpda_aoss_in1: endpoint { + remote-endpoint = <&tpdm_swao_prio1_out>; + }; + }; + + port@2 { + reg = <2>; + + tpda_aoss_in2: endpoint { + remote-endpoint = <&tpdm_swao_prio2_out>; + }; + }; + + port@3 { + reg = <3>; + + tpda_aoss_in3: endpoint { + remote-endpoint = <&tpdm_swao_prio3_out>; + }; + }; + + port@4 { + reg = <4>; + + tpda_aoss_in4: endpoint { + remote-endpoint =<&tpdm_swao_out>; + }; + }; + }; + + out-ports { + port { + tpda_aoss_out: endpoint { + remote-endpoint = <&funnel_aoss_in6>; + }; + }; + }; + }; + + tpdm@10b09000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10b09000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + tpdm_swao_prio0_out: endpoint { + remote-endpoint = <&tpda_aoss_in0>; + }; + }; + }; + }; + + tpdm@10b0a000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10b0a000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + tpdm_swao_prio1_out: endpoint { + remote-endpoint = <&tpda_aoss_in1>; + }; + }; + }; + }; + + tpdm@10b0b000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10b0b000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + tpdm_swao_prio2_out: endpoint { + remote-endpoint = <&tpda_aoss_in2>; + }; + }; + }; + }; + + tpdm@10b0c000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10b0c000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + tpdm_swao_prio3_out: endpoint { + remote-endpoint = <&tpda_aoss_in3>; + }; + }; + }; + }; + + tpdm@10b0d000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10b0d000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_swao_out: endpoint { + remote-endpoint = <&tpda_aoss_in4>; + }; + }; + }; + }; + apps_smmu: iommu@15000000 { compatible = "qcom,sm8750-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0x0 0x15000000 0x0 0x100000>; @@ -3471,7 +4673,7 @@ <0x0 0x40000f20 0x0 0xa8>, <0x0 0x40001000 0x0 0x1000>, <0x0 0x40100000 0x0 0x100000>, - <0x0 0x01C03000 0x0 0x1000>; + <0x0 0x01c03000 0x0 0x1000>; reg-names = "parf", "dbi", "elbi", @@ -3743,6 +4945,13 @@ }; }; + cpucp_mbox: mailbox@16430000 { + compatible = "qcom,sm8750-cpucp-mbox", "qcom,x1e80100-cpucp-mbox"; + reg = <0x0 0x16430000 0x0 0x8000>, <0x0 0x17830000 0x0 0x8000>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <1>; + }; + apps_rsc: rsc@16500000 { compatible = "qcom,rpmh-rsc"; reg = <0x0 0x16500000 0x0 0x10000>, @@ -3954,6 +5163,25 @@ }; }; + sram: sram@17b4e000 { + compatible = "mmio-sram"; + reg = <0x0 0x17b4e000 0x0 0x400>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x17b4e000 0x400>; + + cpu_scp_lpri0: scp-sram-section@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x200>; + }; + + cpu_scp_lpri1: scp-sram-section@200 { + compatible = "arm,scmi-shmem"; + reg = <0x200 0x200>; + }; + }; + /* cluster0 */ pmu@240b3400 { compatible = "qcom,sm8750-cpu-bwmon", "qcom,sdm845-bwmon"; @@ -4239,4 +5467,43 @@ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; }; + + tpdm-cdsp-llm { + compatible = "qcom,coresight-static-tpdm"; + qcom,cmb-element-bits = <32>; + + out-ports { + port { + tpdm_cdsp_llm_out: endpoint { + remote-endpoint = <&tpda_cdsp_in1>; + }; + }; + }; + }; + + tpdm-cdsp-llm2 { + compatible = "qcom,coresight-static-tpdm"; + qcom,cmb-element-bits = <32>; + + out-ports { + port { + tpdm_cdsp_llm2_out: endpoint { + remote-endpoint = <&tpda_cdsp_in2>; + }; + }; + }; + }; + + tpdm-modem1 { + compatible = "qcom,coresight-static-tpdm"; + qcom,dsb-element-bits = <32>; + + out-ports { + port { + tpdm_modem1_out: endpoint { + remote-endpoint = <&tpda_modem_in1>; + }; + }; + }; + }; }; diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index 95d26e313622..75716b4a58d6 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -15,6 +15,7 @@ #include <dt-bindings/interconnect/qcom,osm-l3.h> #include <dt-bindings/interconnect/qcom,qcs615-rpmh.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/phy/phy-qcom-qmp.h> #include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/power/qcom,rpmhpd.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> @@ -479,12 +480,6 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; - ipa_virt: interconnect-1 { - compatible = "qcom,qcs615-ipa-virt"; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - mc_virt: interconnect-2 { compatible = "qcom,qcs615-mc-virt"; #interconnect-cells = <2>; @@ -494,7 +489,7 @@ smp2p-adsp { compatible = "qcom,smp2p"; qcom,smem = <443>, <429>; - interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; + interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING 0>; /* On this platform, bit 26 (normally SLPI) is repurposed for ADSP */ mboxes = <&apss_shared 26>; @@ -516,7 +511,7 @@ smp2p-cdsp { compatible = "qcom,smp2p"; qcom,smem = <94>, <432>; - interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; + interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING 0>; mboxes = <&apss_shared 6>; qcom,local-pid = <0>; @@ -537,7 +532,6 @@ qup_opp_table: opp-table-qup { compatible = "operating-points-v2"; - opp-shared; opp-75000000 { opp-hz = /bits/ 64 <75000000>; @@ -555,6 +549,16 @@ }; }; + pmu-a55 { + compatible = "arm,cortex-a55-pmu"; + interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; + }; + + pmu-a76 { + compatible = "arm,cortex-a76-pmu"; + interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -694,8 +698,8 @@ "cqhci", "ice"; - interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-names = "hc_irq", "pwr_irq"; @@ -756,14 +760,14 @@ compatible = "qcom,qcs615-gpi-dma", "qcom,sdm845-gpi-dma"; reg = <0x0 0x800000 0x0 0x60000>; #dma-cells = <3>; - interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>; dma-channels = <8>; dma-channel-mask = <0xf>; iommus = <&apps_smmu 0xd6 0x0>; @@ -790,7 +794,7 @@ clock-names = "se"; pinctrl-0 = <&qup_uart0_tx>, <&qup_uart0_rx>; pinctrl-names = "default"; - interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH 0>; interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -807,7 +811,7 @@ reg = <0x0 0x884000 0x0 0x4000>; #address-cells = <1>; #size-cells = <0>; - interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; clock-names = "se"; pinctrl-0 = <&qup_i2c1_data_clk>; @@ -835,7 +839,7 @@ reg = <0x0 0x888000 0x0 0x4000>; #address-cells = <1>; #size-cells = <0>; - interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; clock-names = "se"; pinctrl-0 = <&qup_i2c2_data_clk>; @@ -861,7 +865,7 @@ spi2: spi@888000 { compatible = "qcom,geni-spi"; reg = <0x0 0x00888000 0x0 0x4000>; - interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; clock-names = "se"; pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; @@ -886,7 +890,7 @@ uart2: serial@888000 { compatible = "qcom,geni-uart"; reg = <0x0 0x00888000 0x0 0x4000>; - interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; clock-names = "se"; pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, @@ -908,7 +912,7 @@ reg = <0x0 0x88c000 0x0 0x4000>; #address-cells = <1>; #size-cells = <0>; - interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; clock-names = "se"; pinctrl-0 = <&qup_i2c3_data_clk>; @@ -936,14 +940,14 @@ compatible = "qcom,qcs615-gpi-dma", "qcom,sdm845-gpi-dma"; reg = <0x0 0xa00000 0x0 0x60000>; #dma-cells = <3>; - interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>; dma-channels = <8>; dma-channel-mask = <0xf>; iommus = <&apps_smmu 0x376 0x0>; @@ -970,7 +974,7 @@ clock-names = "se"; pinctrl-0 = <&qup_i2c4_data_clk>; pinctrl-names = "default"; - interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>; #address-cells = <1>; #size-cells = <0>; interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS @@ -998,7 +1002,7 @@ clock-names = "se"; pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; pinctrl-names = "default"; - interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>; #address-cells = <1>; #size-cells = <0>; interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS @@ -1024,7 +1028,7 @@ pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; pinctrl-names = "default"; - interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>; interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -1043,7 +1047,7 @@ clock-names = "se"; pinctrl-0 = <&qup_i2c5_data_clk>; pinctrl-names = "default"; - interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>; #address-cells = <1>; #size-cells = <0>; interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS @@ -1071,7 +1075,7 @@ clock-names = "se"; pinctrl-0 = <&qup_i2c6_data_clk>; pinctrl-names = "default"; - interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; #address-cells = <1>; #size-cells = <0>; interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS @@ -1099,7 +1103,7 @@ clock-names = "se"; pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; pinctrl-names = "default"; - interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; #address-cells = <1>; #size-cells = <0>; interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS @@ -1125,7 +1129,7 @@ pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; pinctrl-names = "default"; - interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -1144,7 +1148,7 @@ clock-names = "se"; pinctrl-0 = <&qup_i2c7_data_clk>; pinctrl-names = "default"; - interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; #address-cells = <1>; #size-cells = <0>; interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS @@ -1172,7 +1176,7 @@ clock-names = "se"; pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; pinctrl-names = "default"; - interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; #address-cells = <1>; #size-cells = <0>; interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS @@ -1198,7 +1202,7 @@ pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; pinctrl-names = "default"; - interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -1265,15 +1269,15 @@ linux,pci-domain = <0>; num-lanes = <1>; - interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-names = "msi0", "msi1", "msi2", @@ -1286,10 +1290,10 @@ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, <&gcc GCC_PCIE_0_AUX_CLK>, @@ -1393,7 +1397,7 @@ reg-names = "std", "ice"; - interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, @@ -1502,7 +1506,7 @@ cryptobam: dma-controller@1dc4000 { compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; reg = <0x0 0x01dc4000 0x0 0x24000>; - interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <1>; qcom,ee = <0>; qcom,controlled-remotely; @@ -1541,7 +1545,7 @@ reg-names = "east", "west", "south"; - interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 0>; gpio-ranges = <&tlmm 0 0 124>; gpio-controller; #gpio-cells = <2>; @@ -3468,7 +3472,7 @@ compatible = "qcom,qcs615-cdsp-pas", "qcom,sm8150-cdsp-pas"; reg = <0x0 0x08300000 0x0 0x4040>; - interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING 0>, <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, @@ -3495,7 +3499,7 @@ status = "disabled"; glink-edge { - interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; + interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING 0>; mboxes = <&apss_shared 4>; label = "cdsp"; qcom,remote-pid = <5>; @@ -3555,7 +3559,7 @@ pmu@90b6300 { compatible = "qcom,qcs615-cpu-bwmon", "qcom,sdm845-bwmon"; reg = <0x0 0x090b6300 0x0 0x600>; - interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH 0>; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; @@ -3577,7 +3581,7 @@ pmu@90cd000 { compatible = "qcom,qcs615-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; reg = <0x0 0x090cd000 0x0 0x1000>; - interrupts = <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH 0>; interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; @@ -3629,8 +3633,8 @@ reg = <0x0 0x08804000 0x0 0x1000>; reg-names = "hc"; - interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-names = "hc_irq", "pwr_irq"; @@ -3703,7 +3707,7 @@ venus: video-codec@aa00000 { compatible = "qcom,qcs615-venus", "qcom,sc7180-venus"; reg = <0x0 0x0aa00000 0x0 0x100000>; - interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, <&videocc VIDEO_CC_VENUS_AHB_CLK>, @@ -3814,7 +3818,7 @@ <&gcc GCC_DISP_HF_AXI_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK>; - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-controller; #interrupt-cells = <1>; @@ -3855,6 +3859,7 @@ reg = <0>; dpu_intf0_out: endpoint { + remote-endpoint = <&mdss_dp0_in>; }; }; @@ -3887,6 +3892,89 @@ }; }; + mdss_dp0: displayport-controller@ae90000 { + compatible = "qcom,sm6150-dp", "qcom,sm8150-dp", "qcom,sm8350-dp"; + + reg = <0x0 0x0ae90000 0x0 0x200>, + <0x0 0x0ae90200 0x0 0x200>, + <0x0 0x0ae90400 0x0 0x600>, + <0x0 0x0ae90a00 0x0 0x600>, + <0x0 0x0ae91000 0x0 0x600>; + + interrupt-parent = <&mdss>; + interrupts = <12>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel", + "stream_1_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>; + assigned-clock-parents = <&usb_qmpphy_2 QMP_USB43DP_DP_LINK_CLK>, + <&usb_qmpphy_2 QMP_USB43DP_DP_VCO_DIV_CLK>, + <&usb_qmpphy_2 QMP_USB43DP_DP_VCO_DIV_CLK>; + + phys = <&usb_qmpphy_2 QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + operating-points-v2 = <&dp_opp_table>; + power-domains = <&rpmhpd RPMHPD_CX>; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dp0_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp0_out: endpoint { + data-lanes = <3 2 0 1>; + }; + }; + }; + + dp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + mdss_dsi0: dsi@ae94000 { compatible = "qcom,sm6150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0x0 0x0ae94000 0x0 0x400>; @@ -3982,8 +4070,8 @@ <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, <0>, - <0>, - <0>; + <&usb_qmpphy_2 QMP_USB43DP_DP_LINK_CLK>, + <&usb_qmpphy_2 QMP_USB43DP_DP_VCO_DIV_CLK>; #clock-cells = <1>; #reset-cells = <1>; @@ -4003,7 +4091,7 @@ aoss_qmp: power-management@c300000 { compatible = "qcom,qcs615-aoss-qmp", "qcom,aoss-qmp"; reg = <0x0 0x0c300000 0x0 0x400>; - interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; + interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING 0>; mboxes = <&apss_shared 0>; #clock-cells = <0>; @@ -4035,71 +4123,71 @@ #global-interrupts = <1>; dma-coherent; - interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>; }; spmi_bus: spmi@c440000 { @@ -4128,12 +4216,22 @@ compatible = "arm,gic-v3"; reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; #address-cells = <0>; - #interrupt-cells = <3>; + #interrupt-cells = <4>; interrupt-controller; #redistributor-regions = <1>; redistributor-stride = <0x0 0x20000>; + + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>; + }; + + ppi_cluster1: interrupt-partition-1 { + affinity = <&cpu6 &cpu7>; + }; + }; }; apss_shared: mailbox@17c00000 { @@ -4146,7 +4244,7 @@ watchdog: watchdog@17c10000 { compatible = "qcom,apss-wdt-qcs615", "qcom,kpss-wdt"; reg = <0x0 0x17c10000 0x0 0x1000>; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&sleep_clk>; }; @@ -4161,49 +4259,49 @@ reg = <0x17c21000 0x1000>, <0x17c22000 0x1000>; frame-number = <0>; - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; }; frame@17c23000 { reg = <0x17c23000 0x1000>; frame-number = <1>; - interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>; status = "disabled"; }; frame@17c25000 { reg = <0x17c25000 0x1000>; frame-number = <2>; - interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>; status = "disabled"; }; frame@17c27000 { reg = <0x17c27000 0x1000>; frame-number = <3>; - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; status = "disabled"; }; frame@17c29000 { reg = <0x17c29000 0x1000>; frame-number = <4>; - interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; status = "disabled"; }; frame@17c2b000 { reg = <0x17c2b000 0x1000>; frame-number = <5>; - interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH 0>; status = "disabled"; }; frame@17c2d000 { reg = <0x17c2d000 0x1000>; frame-number = <6>; - interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; status = "disabled"; }; }; @@ -4217,9 +4315,9 @@ "drv-1", "drv-2"; - interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>; qcom,drv-id = <2>; qcom,tcs-offset = <0xd00>; @@ -4362,6 +4460,32 @@ status = "disabled"; }; + usb_qmpphy_2: phy@88e8000 { + compatible = "qcom,qcs615-qmp-usb3-dp-phy"; + reg = <0x0 0x088e8000 0x0 0x2000>; + + clocks = <&gcc GCC_USB2_SEC_PHY_AUX_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_CLK>, + <&gcc GCC_AHB2PHY_WEST_CLK>, + <&gcc GCC_USB2_SEC_PHY_PIPE_CLK>; + clock-names = "aux", + "ref", + "cfg_ahb", + "pipe"; + + resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR >, + <&gcc GCC_USB3_DP_PHY_SEC_BCR>; + reset-names = "phy_phy", + "dp_phy"; + + #clock-cells = <1>; + #phy-cells = <1>; + + qcom,tcsr-reg = <&tcsr 0xbff0 0xb24c>; + + status = "disabled"; + }; + usb_1: usb@a6f8800 { compatible = "qcom,qcs615-dwc3", "qcom,dwc3"; reg = <0x0 0x0a6f8800 0x0 0x400>; @@ -4383,8 +4507,8 @@ <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, - <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>, <&pdc 9 IRQ_TYPE_EDGE_BOTH>, <&pdc 8 IRQ_TYPE_EDGE_BOTH>, <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; @@ -4410,7 +4534,7 @@ reg = <0x0 0x0a600000 0x0 0xcd00>; iommus = <&apps_smmu 0x140 0x0>; - interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>; phys = <&usb_1_hsphy>, <&usb_qmpphy>; phy-names = "usb2-phy", "usb3-phy"; @@ -4447,8 +4571,8 @@ <&gcc GCC_USB20_SEC_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH>, - <&intc GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH 0>, + <&intc GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH 0>, <&pdc 11 IRQ_TYPE_EDGE_BOTH>, <&pdc 10 IRQ_TYPE_EDGE_BOTH>; interrupt-names = "pwr_event", @@ -4474,7 +4598,7 @@ reg = <0x0 0x0a800000 0x0 0xcd00>; iommus = <&apps_smmu 0xe0 0x0>; - interrupts = <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH 0>; phys = <&usb_hsphy_2>; phy-names = "usb2-phy"; @@ -4493,8 +4617,8 @@ compatible = "qcom,qcs615-tsens", "qcom,tsens-v2"; reg = <0x0 0x0c263000 0x0 0x1000>, <0x0 0x0c222000 0x0 0x1000>; - interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-names = "uplow", "critical"; #qcom,sensors = <16>; #thermal-sensor-cells = <1>; @@ -4504,7 +4628,7 @@ compatible = "qcom,qcs615-adsp-pas", "qcom,sm8150-adsp-pas"; reg = <0x0 0x62400000 0x0 0x4040>; - interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, + interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING 0>, <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, @@ -4531,7 +4655,7 @@ status = "disabled"; glink_edge: glink-edge { - interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; + interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING 0>; mboxes = <&apss_shared 24>; label = "lpass"; qcom,remote-pid = <2>; @@ -4590,10 +4714,10 @@ arch_timer: timer { compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>, + <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>, + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>, + <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>; }; thermal-zones { diff --git a/arch/arm64/boot/dts/qcom/x1-el2.dtso b/arch/arm64/boot/dts/qcom/x1-el2.dtso index 2d1c9151cf1b..175679be01eb 100644 --- a/arch/arm64/boot/dts/qcom/x1-el2.dtso +++ b/arch/arm64/boot/dts/qcom/x1-el2.dtso @@ -7,6 +7,10 @@ /dts-v1/; /plugin/; +&apss_watchdog { + status = "okay"; +}; + /* We can't and don't need to use zap shader in EL2 as linux can zap the gpu on it's own. */ &gpu_zap_shader { status = "disabled"; diff --git a/arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi b/arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi new file mode 100644 index 000000000000..d77be02848b5 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi @@ -0,0 +1,1322 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2025 Dale Whinham <daleyo@gmail.com> + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/gpio-keys.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> + +#include "hamoa-pmics.dtsi" + +/ { + aliases { + serial0 = &uart2; + serial1 = &uart14; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&hall_int_n_default>; + pinctrl-names = "default"; + + switch-lid { + gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + linux,input-type = <EV_SW>; + linux,code = <SW_LID>; + wakeup-source; + wakeup-event-action = <EV_ACT_DEASSERTED>; + }; + }; + + pmic-glink { + compatible = "qcom,x1e80100-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>, + <&tlmm 123 GPIO_ACTIVE_HIGH>; + + /* Left-side bottom port */ + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss0_hs_in: endpoint { + remote-endpoint = <&usb_1_ss0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss0_ss_in: endpoint { + remote-endpoint = <&retimer_ss0_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss0_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss0_con_sbu_out>; + }; + }; + }; + }; + + /* Left-side top port */ + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss1_hs_in: endpoint { + remote-endpoint = <&usb_1_ss1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss1_ss_in: endpoint { + remote-endpoint = <&retimer_ss1_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss1_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss1_con_sbu_out>; + }; + }; + }; + }; + }; + + reserved-memory { + linux,cma { + compatible = "shared-dma-pool"; + size = <0x0 0x8000000>; + reusable; + linux,cma-default; + }; + }; + + vreg_edp_3p3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_1p15: regulator-rtmr0-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_1P15"; + + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&rtmr0_1p15_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_1p8: regulator-rtmr0-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_1P8"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&rtmr0_1p8_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_3p3: regulator-rtmr0-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_3P3"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&rtmr0_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_1p15: regulator-rtmr1-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_1P15"; + + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&tlmm 188 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&rtmr1_1p15_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_1p8: regulator-rtmr1-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_1P8"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 175 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&rtmr1_1p8_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_3p3: regulator-rtmr1-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_3P3"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 186 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&rtmr1_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_nvme: regulator-nvme { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&nvme_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 214 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wcn_sw_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_wcn_0p95: regulator-wcn-0p95 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_0P95"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_1p9: regulator-wcn-1p9 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_1P9"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + sound { + compatible = "qcom,x1e80100-sndcard"; + model = "X1E80100-Microsoft-Surface-Pro-11"; + audio-routing = "SpkrLeft IN", "WSA WSA_SPK1 OUT", + "SpkrRight IN", "WSA WSA_SPK2 OUT", + "VA DMIC0", "vdd-micb", + "VA DMIC1", "vdd-micb"; + + wsa-dai-link { + link-name = "WSA Playback"; + + codec { + sound-dai = <&left_spkr>, <&right_spkr>, + <&swr0 0>, <&lpass_wsamacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + vdd-supply = <&vreg_wcn_0p95>; + vddio-supply = <&vreg_l15b_1p8>; + vddaon-supply = <&vreg_wcn_0p95>; + vdddig-supply = <&vreg_wcn_0p95>; + vddrfa1p2-supply = <&vreg_wcn_1p9>; + vddrfa1p8-supply = <&vreg_wcn_1p9>; + + wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; + bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&wcn_wlan_bt_en>; + pinctrl-names = "default"; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-bob1-supply = <&vph_pwr>; + vdd-bob2-supply = <&vph_pwr>; + vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>; + vdd-l2-l13-l14-supply = <&vreg_bob1>; + vdd-l5-l16-supply = <&vreg_bob1>; + vdd-l6-l7-supply = <&vreg_bob2>; + vdd-l8-l9-supply = <&vreg_bob1>; + vdd-l12-supply = <&vreg_s5j_1p2>; + vdd-l15-supply = <&vreg_s4c_1p8>; + vdd-l17-supply = <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name = "vreg_l1b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4b_1p8: ldo4 { + regulator-name = "vreg_l4b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8b_3p0: ldo8 { + regulator-name = "vreg_l8b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l10b_1p8: ldo10 { + regulator-name = "vreg_l10b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l12b_1p2: ldo12 { + regulator-name = "vreg_l12b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l14b_3p0: ldo14 { + regulator-name = "vreg_l14b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name = "vreg_l17b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s4-supply = <&vph_pwr>; + + vreg_s4c_1p8: smps4 { + regulator-name = "vreg_s4c_1p8"; + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1c_1p2: ldo1 { + regulator-name = "vreg_l1c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2c_0p8: ldo2 { + regulator-name = "vreg_l2c_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3c_0p8: ldo3 { + regulator-name = "vreg_l3c_0p8"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-2 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "d"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s4c_1p8>; + vdd-s1-supply = <&vph_pwr>; + + vreg_l1d_0p8: ldo1 { + regulator-name = "vreg_l1d_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2d_0p9: ldo2 { + regulator-name = "vreg_l2d_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3d_1p8: ldo3 { + regulator-name = "vreg_l3d_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-3 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s5j_1p2>; + + vreg_l2e_0p8: ldo2 { + regulator-name = "vreg_l2e_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-4 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s5j_1p2>; + vdd-s1-supply = <&vph_pwr>; + + vreg_s1f_0p7: smps1 { + regulator-name = "vreg_s1f_0p7"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-6 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "i"; + + vdd-l1-supply = <&vreg_s4c_1p8>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + + vreg_s1i_0p9: smps1 { + regulator-name = "vreg_s1i_0p9"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s2i_1p0: smps2 { + regulator-name = "vreg_s2i_1p0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1i_1p8: ldo1 { + regulator-name = "vreg_l1i_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2i_1p2: ldo2 { + regulator-name = "vreg_l2i_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3i_0p8: ldo3 { + regulator-name = "vreg_l3i_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-7 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "j"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s5-supply = <&vph_pwr>; + + vreg_s5j_1p2: smps5 { + regulator-name = "vreg_s5j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1j_0p8: ldo1 { + regulator-name = "vreg_l1j_0p8"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2j_1p2: ldo2 { + regulator-name = "vreg_l2j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1256000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3j_0p8: ldo3 { + regulator-name = "vreg_l3j_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; +}; + +&gpu { + status = "okay"; + + zap-shader { + memory-region = <&gpu_microcode_mem>; + firmware-name = "qcom/x1e80100/microsoft/qcdxkmsuc8380.mbn"; + }; +}; + +&i2c0 { + clock-frequency = <100000>; + + status = "okay"; + + /* Something @39, @3e, @44 */ +}; + +&i2c3 { + clock-frequency = <400000>; + + status = "okay"; + + /* Left-side bottom port */ + typec-mux@8 { + compatible = "parade,ps8830"; + reg = <0x8>; + + reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_LOW>; + + clocks = <&rpmhcc RPMH_RF_CLK3>; + + vdd-supply = <&vreg_rtmr0_1p15>; + vdd33-supply = <&vreg_rtmr0_3p3>; + vdd33-cap-supply = <&vreg_rtmr0_3p3>; + vddar-supply = <&vreg_rtmr0_1p15>; + vddat-supply = <&vreg_rtmr0_1p15>; + vddio-supply = <&vreg_rtmr0_1p8>; + + pinctrl-0 = <&rtmr0_default>; + pinctrl-names = "default"; + + retimer-switch; + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss0_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss0_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss0_ss_in: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss0_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss0_con_sbu_in>; + }; + }; + }; + }; +}; + +&i2c4 { + clock-frequency = <400000>; + + status = "okay"; + + /* Something @12, @14, @16, @18, @1a */ +}; + +&i2c7 { + clock-frequency = <400000>; + + status = "okay"; + + /* Left-side top port */ + typec-mux@8 { + compatible = "parade,ps8830"; + reg = <0x8>; + + reset-gpios = <&tlmm 176 GPIO_ACTIVE_LOW>; + + clocks = <&rpmhcc RPMH_RF_CLK4>; + + vdd-supply = <&vreg_rtmr1_1p15>; + vdd33-supply = <&vreg_rtmr1_3p3>; + vdd33-cap-supply = <&vreg_rtmr1_3p3>; + vddar-supply = <&vreg_rtmr1_1p15>; + vddat-supply = <&vreg_rtmr1_1p15>; + vddio-supply = <&vreg_rtmr1_1p8>; + + retimer-switch; + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss1_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss1_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss1_ss_in: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss1_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss1_con_sbu_in>; + }; + }; + }; + }; +}; + +&lpass_tlmm { + spkr_01_sd_n_active: spkr-01-sd-n-active-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; +}; + +&lpass_vamacro { + pinctrl-0 = <&dmic01_default>, <&dmic23_default>; + pinctrl-names = "default"; + + vdd-micb-supply = <&vreg_l1b_1p8>; + qcom,dmic-sample-rate = <4800000>; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp1 { + status = "okay"; +}; + +&mdss_dp1_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp3 { + compatible = "qcom,x1e80100-dp"; + /delete-property/ #sound-dai-cells; + + status = "okay"; + + aux-bus { + panel: panel { + compatible = "edp-panel"; + enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>; + power-supply = <&vreg_edp_3p3>; + + pinctrl-0 = <&edp_bl_en>; + pinctrl-names = "default"; + + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + }; + + ports { + port@1 { + reg = <1>; + + mdss_dp3_out: endpoint { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&edp_panel_in>; + }; + }; + }; +}; + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pcie4 { + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l3i_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie4_port0 { + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; +}; + +&pcie6a { + perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; + + vddpe-3v3-supply = <&vreg_nvme>; + + pinctrl-0 = <&pcie6a_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie6a_phy { + vdda-phy-supply = <&vreg_l1d_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pm8550_gpios { + rtmr0_default: rtmr0-reset-n-active-state { + pins = "gpio10"; + function = "normal"; + power-source = <1>; /* 1.8V */ + }; + + rtmr0_3p3_reg_en: rtmr0-3p3-reg-en-state { + pins = "gpio11"; + function = "normal"; + power-source = <1>; /* 1.8V */ + }; +}; + +&pm8550ve_9_gpios { + rtmr0_1p8_reg_en: rtmr0-1p8-reg-en-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; /* 1.8V */ + }; +}; + +&pmc8380_3_gpios { + edp_bl_en: edp-bl-en-state { + pins = "gpio4"; + function = "normal"; + power-source = <1>; /* 1.8V */ + input-disable; + output-enable; + }; +}; + +&pmc8380_5_gpios { + rtmr0_1p15_reg_en: rtmr0-1p15-reg-en-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; /* 1.8V */ + }; +}; + +&qupv3_0 { + status = "okay"; +}; + +&qupv3_1 { + status = "okay"; +}; + +&qupv3_2 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/x1e80100/microsoft/Denali/qcadsp8380.mbn", + "qcom/x1e80100/microsoft/Denali/adsp_dtb.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1e80100/microsoft/Denali/qccdsp8380.mbn", + "qcom/x1e80100/microsoft/Denali/cdsp_dtb.mbn"; + + status = "okay"; +}; + +&smb2360_0 { + status = "okay"; +}; + +&smb2360_0_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l2b_3p0>; +}; + +&smb2360_1 { + status = "okay"; +}; + +&smb2360_1_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l14b_3p0>; +}; + +&smb2360_2 { + status = "okay"; +}; + +&smb2360_2_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l8b_3p0>; +}; + +&swr0 { + status = "okay"; + + pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>; + pinctrl-names = "default"; + + /* WSA8845, Left Speaker */ + left_spkr: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Right Speaker */ + right_spkr: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + +&tlmm { + gpio-reserved-ranges = <44 4>, /* SPI (TPM) */ + <238 1>; /* UFS Reset */ + + hall_int_n_default: hall-int-n-state { + pins = "gpio2"; + function = "gpio"; + bias-disable; + }; + + nvme_reg_en: nvme-reg-en-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + edp_reg_en: edp-reg-en-state { + pins = "gpio70"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + ssam_state: ssam-state-state { + pins = "gpio91"; + function = "gpio"; + bias-disable; + }; + + wcn_wlan_bt_en: wcn-wlan-bt-en-state { + pins = "gpio116", "gpio117"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins = "gpio147"; + function = "pcie4_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio146"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio148"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie6a_default: pcie6a-default-state { + perst-n-pins { + pins = "gpio152"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + clkreq-n-pins { + pins = "gpio153"; + function = "pcie6a_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + wake-n-pins { + pins = "gpio154"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + rtmr1_1p8_reg_en: rtmr1-1p8-reg-en-state { + pins = "gpio175"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + rtmr1_3p3_reg_en: rtmr1-3p3-reg-en-state { + pins = "gpio186"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + rtmr1_1p15_reg_en: rtmr1-1p15-reg-en-state { + pins = "gpio188"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wcn_sw_en: wcn-sw-en-state { + pins = "gpio214"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + cam_indicator_en: cam-indicator-en-state { + pins = "gpio225"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + +&uart2 { + status = "okay"; + + embedded-controller { + compatible = "microsoft,surface-sam"; + + interrupts-extended = <&tlmm 91 IRQ_TYPE_EDGE_RISING>; + + current-speed = <4000000>; + + pinctrl-0 = <&ssam_state>; + pinctrl-names = "default"; + }; +}; + +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + max-speed = <3200000>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + }; +}; + +&usb_1_ss0_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_0_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss0_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l1j_0p8>; + + status = "okay"; +}; + +&usb_1_ss0 { + status = "okay"; +}; + +&usb_1_ss0_dwc3 { + dr_mode = "host"; +}; + +&usb_1_ss0_dwc3_hs { + remote-endpoint = <&pmic_glink_ss0_hs_in>; +}; + +&usb_1_ss0_qmpphy_out { + remote-endpoint = <&retimer_ss0_ss_in>; +}; + +&usb_1_ss1_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_1_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss1_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + status = "okay"; +}; + +&usb_1_ss1 { + status = "okay"; +}; + +&usb_1_ss1_dwc3 { + dr_mode = "host"; +}; + +&usb_1_ss1_dwc3_hs { + remote-endpoint = <&pmic_glink_ss1_hs_in>; +}; + +&usb_1_ss1_qmpphy_out { + remote-endpoint = <&retimer_ss1_ss_in>; +}; diff --git a/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts b/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts index a9643cd746d5..d5a60671a383 100644 --- a/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts +++ b/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts @@ -1003,9 +1003,6 @@ }; &pcie4 { - perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie4_default>; pinctrl-names = "default"; @@ -1019,10 +1016,12 @@ status = "okay"; }; -&pcie5 { - perst-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; +&pcie4_port0 { + reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; +}; +&pcie5 { vddpe-3v3-supply = <&vreg_wwan>; pinctrl-0 = <&pcie5_default>; @@ -1038,10 +1037,12 @@ status = "okay"; }; -&pcie6a { - perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; +&pcie5_port0 { + reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; +}; +&pcie6a { vddpe-3v3-supply = <&vreg_nvme>; pinctrl-names = "default"; @@ -1057,6 +1058,11 @@ status = "okay"; }; +&pcie6a_port0 { + reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; +}; + &pm8550_gpios { rtmr0_default: rtmr0-reset-n-active-state { pins = "gpio10"; diff --git a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi index 80ece9db875a..4d7fd51f370b 100644 --- a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi @@ -62,6 +62,45 @@ }; }; + hdmi-bridge { + compatible = "realtek,rtd2171"; + + pinctrl-0 = <&hdmi_hpd_default>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_bridge_dp_in: endpoint { + remote-endpoint = <&usb_1_ss2_qmpphy_out_dp>; + }; + }; + + port@1 { + reg = <1>; + + hdmi_bridge_tmds_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&hdmi_bridge_tmds_out>; + }; + }; + }; + pmic-glink { compatible = "qcom,x1e80100-pmic-glink", "qcom,sm8550-pmic-glink", @@ -351,6 +390,54 @@ "VA DMIC1", "VA MIC BIAS1", "TX SWR_INPUT1", "ADC2_OUTPUT"; + displayport-0-dai-link { + link-name = "DisplayPort0 Playback"; + + codec { + sound-dai = <&mdss_dp0>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + displayport-1-dai-link { + link-name = "DisplayPort1 Playback"; + + codec { + sound-dai = <&mdss_dp1>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_1>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + displayport-2-dai-link { + link-name = "DisplayPort2 Playback"; + + codec { + sound-dai = <&mdss_dp2>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_2>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + wcd-playback-dai-link { link-name = "WCD Playback"; @@ -1028,6 +1115,14 @@ link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; +&mdss_dp2 { + status = "okay"; +}; + +&mdss_dp2_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + &mdss_dp3 { /delete-property/ #sound-dai-cells; @@ -1065,9 +1160,6 @@ }; &pcie4 { - perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie4_default>; pinctrl-names = "default"; @@ -1081,10 +1173,12 @@ status = "okay"; }; -&pcie5 { - perst-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; +&pcie4_port0 { + reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; +}; +&pcie5 { vddpe-3v3-supply = <&vreg_wwan>; pinctrl-0 = <&pcie5_default>; @@ -1100,10 +1194,12 @@ status = "okay"; }; -&pcie6a { - perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; +&pcie5_port0 { + reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; +}; +&pcie6a { vddpe-3v3-supply = <&vreg_nvme>; pinctrl-0 = <&pcie6a_default>; @@ -1119,6 +1215,11 @@ status = "okay"; }; +&pcie6a_port0 { + reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; +}; + &pm8550_gpios { rtmr0_default: rtmr0-reset-n-active-state { pins = "gpio10"; @@ -1317,6 +1418,12 @@ output-low; }; + hdmi_hpd_default: hdmi-hpd-default-state { + pins = "gpio126"; + function = "usb2_dp"; + bias-disable; + }; + tpad_default: tpad-default-state { pins = "gpio3"; function = "gpio"; @@ -1548,6 +1655,34 @@ remote-endpoint = <&retimer_ss1_ss_in>; }; +&usb_1_ss2_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + /delete-property/ mode-switch; + /delete-property/ orientation-switch; + + status = "okay"; + + ports { + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + /delete-node/ endpoint; + + usb_1_ss2_qmpphy_out_dp: endpoint@0 { + reg = <0>; + + data-lanes = <3 2 1 0>; + remote-endpoint = <&hdmi_bridge_dp_in>; + }; + + /* No USB3 lanes connected */ + }; + }; +}; + &usb_2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts b/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts index d4df21de0d95..17269eb0638a 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts @@ -37,6 +37,45 @@ }; }; + hdmi-bridge { + compatible = "parade,ps185hdm"; + + pinctrl-0 = <&hdmi_hpd_default>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_bridge_dp_in: endpoint { + remote-endpoint = <&usb_1_ss2_qmpphy_out_dp>; + }; + }; + + port@1 { + reg = <1>; + + hdmi_bridge_tmds_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&hdmi_bridge_tmds_out>; + }; + }; + }; + pmic-glink { compatible = "qcom,x1e80100-pmic-glink", "qcom,sm8550-pmic-glink", @@ -69,7 +108,15 @@ reg = <1>; pmic_glink_ss0_ss_in: endpoint { - remote-endpoint = <&usb_1_ss0_qmpphy_out>; + remote-endpoint = <&retimer_ss0_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss0_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss0_con_sbu_out>; }; }; }; @@ -98,7 +145,15 @@ reg = <1>; pmic_glink_ss1_ss_in: endpoint { - remote-endpoint = <&usb_1_ss1_qmpphy_out>; + remote-endpoint = <&retimer_ss1_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss1_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss1_con_sbu_out>; }; }; }; @@ -147,6 +202,102 @@ regulator-boot-on; }; + vreg_rtmr0_1p15: regulator-rtmr0-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_1P15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_pwr_1p15_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_1p8: regulator-rtmr0-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_1p8_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_3p3: regulator-rtmr0-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_1p15: regulator-rtmr1-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_1P15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&tlmm 188 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb1_pwr_1p15_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_1p8: regulator-rtmr1-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 175 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb1_pwr_1p8_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_3p3: regulator-rtmr1-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 186 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb1_pwr_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + vph_pwr: regulator-vph-pwr { compatible = "regulator-fixed"; @@ -506,15 +657,62 @@ &i2c1 { clock-frequency = <400000>; status = "okay"; - - /* PS8830 USB4 Retimer? @ 0x8 */ }; &i2c3 { clock-frequency = <400000>; status = "okay"; - /* PS8830 USB4 Retimer? @ 0x8 */ + typec-mux@8 { + compatible = "parade,ps8830"; + reg = <0x08>; + + clocks = <&rpmhcc RPMH_RF_CLK3>; + + vdd-supply = <&vreg_rtmr0_1p15>; + vdd33-supply = <&vreg_rtmr0_3p3>; + vdd33-cap-supply = <&vreg_rtmr0_3p3>; + vddar-supply = <&vreg_rtmr0_1p15>; + vddat-supply = <&vreg_rtmr0_1p15>; + vddio-supply = <&vreg_rtmr0_1p8>; + + reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&rtmr0_default>; + pinctrl-names = "default"; + + orientation-switch; + retimer-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss0_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss0_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss0_ss_in: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss0_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss0_con_sbu_in>; + }; + }; + }; + }; }; &i2c5 { @@ -583,13 +781,91 @@ clock-frequency = <400000>; status = "okay"; - /* PS8830 USB4 Retimer? @ 0x8 */ + typec-mux@8 { + compatible = "parade,ps8830"; + reg = <0x8>; + + clocks = <&rpmhcc RPMH_RF_CLK4>; + + vdd-supply = <&vreg_rtmr1_1p15>; + vdd33-supply = <&vreg_rtmr1_3p3>; + vdd33-cap-supply = <&vreg_rtmr1_3p3>; + vddar-supply = <&vreg_rtmr1_1p15>; + vddat-supply = <&vreg_rtmr1_1p15>; + vddio-supply = <&vreg_rtmr1_1p8>; + + reset-gpios = <&tlmm 176 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&rtmr1_default>; + pinctrl-names = "default"; + + retimer-switch; + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss1_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss1_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss1_ss_in: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss1_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss1_con_sbu_in>; + }; + }; + }; + }; +}; + +&iris { + firmware-name = "qcom/x1e80100/ASUSTeK/vivobook-s15/qcvss8380.mbn"; + status = "okay"; }; &mdss { status = "okay"; }; +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp1 { + status = "okay"; +}; + +&mdss_dp1_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp2 { + status = "okay"; +}; + +&mdss_dp2_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + &mdss_dp3 { /delete-property/ #sound-dai-cells; @@ -631,9 +907,6 @@ }; &pcie4 { - perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie4_default>; pinctrl-names = "default"; @@ -648,6 +921,9 @@ }; &pcie4_port0 { + reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + wifi@0 { compatible = "pci17cb,1107"; reg = <0x10000 0x0 0x0 0x0 0x0>; @@ -665,9 +941,6 @@ }; &pcie6a { - perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_nvme>; pinctrl-0 = <&pcie6a_default>; @@ -683,6 +956,42 @@ status = "okay"; }; +&pcie6a_port0 { + reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; +}; + +&pm8550_gpios { + rtmr0_default: rtmr0-reset-n-active-state { + pins = "gpio10"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; + + usb0_3p3_reg_en: usb0-3p3-reg-en-state { + pins = "gpio11"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + +&pm8550ve_9_gpios { + usb0_1p8_reg_en: usb0-1p8-reg-en-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + &pmc8380_3_gpios { edp_bl_en: edp-bl-en-state { pins = "gpio4"; @@ -695,6 +1004,17 @@ }; }; +&pmc8380_5_gpios { + usb0_pwr_1p15_reg_en: usb0-pwr-1p15-reg-en-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + &qupv3_0 { status = "okay"; }; @@ -781,6 +1101,12 @@ bias-disable; }; + hdmi_hpd_default: hdmi-hpd-default-state { + pins = "gpio126"; + function = "usb2_dp"; + bias-disable; + }; + kybd_default: kybd-default-state { pins = "gpio67"; function = "gpio"; @@ -840,12 +1166,40 @@ }; }; + rtmr1_default: rtmr1-reset-n-active-state { + pins = "gpio176"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + tpad_default: tpad-default-state { pins = "gpio3"; function = "gpio"; bias-disable; }; + usb1_pwr_1p15_reg_en: usb1-pwr-1p15-reg-en-state { + pins = "gpio188"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + usb1_pwr_1p8_reg_en: usb1-pwr-1p8-reg-en-state { + pins = "gpio175"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + usb1_pwr_3p3_reg_en: usb1-pwr-3p3-reg-en-state { + pins = "gpio186"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + wcn_bt_en: wcn-bt-en-state { pins = "gpio116"; function = "gpio"; @@ -914,7 +1268,7 @@ }; &usb_1_ss0_qmpphy_out { - remote-endpoint = <&pmic_glink_ss0_ss_in>; + remote-endpoint = <&retimer_ss0_ss_in>; }; &usb_1_ss1_hsphy { @@ -946,7 +1300,35 @@ }; &usb_1_ss1_qmpphy_out { - remote-endpoint = <&pmic_glink_ss1_ss_in>; + remote-endpoint = <&retimer_ss1_ss_in>; +}; + +&usb_1_ss2_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + /delete-property/ mode-switch; + /delete-property/ orientation-switch; + + status = "okay"; + + ports { + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + /delete-node/ endpoint; + + usb_1_ss2_qmpphy_out_dp: endpoint@0 { + reg = <0>; + + data-lanes = <3 2 1 0>; + remote-endpoint = <&hdmi_bridge_dp_in>; + }; + + /* No USB3 lanes connected */ + }; + }; }; &usb_2 { diff --git a/arch/arm64/boot/dts/qcom/x1e80100-asus-zenbook-a14.dts b/arch/arm64/boot/dts/qcom/x1e80100-asus-zenbook-a14.dts index 0408ade7150f..b42318c75ed2 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-asus-zenbook-a14.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-asus-zenbook-a14.dts @@ -82,6 +82,9 @@ }; &pcie4_port0 { + reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + wifi@0 { compatible = "pci17cb,1107"; reg = <0x10000 0x0 0x0 0x0 0x0>; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts b/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts index 2f533e56c8c8..4c95b1af2c64 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts @@ -941,9 +941,6 @@ }; &pcie4 { - perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie4_default>; pinctrl-names = "default"; @@ -958,6 +955,9 @@ }; &pcie4_port0 { + reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + wifi@0 { compatible = "pci17cb,1107"; reg = <0x10000 0x0 0x0 0x0 0x0>; @@ -975,9 +975,6 @@ }; &pcie6a { - perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_nvme>; pinctrl-0 = <&pcie6a_default>; @@ -993,6 +990,11 @@ status = "okay"; }; +&pcie6a_port0 { + reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; +}; + &pm8550_gpios { rtmr0_default: rtmr0-reset-n-active-state { pins = "gpio10"; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts index 4c31d14a07bc..d6472e5a3f9f 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts @@ -1160,9 +1160,6 @@ }; &pcie6a { - perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_nvme>; pinctrl-0 = <&pcie6a_default>; @@ -1178,6 +1175,11 @@ status = "okay"; }; +&pcie6a_port0 { + reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; +}; + &pm8550_gpios { rtmr0_default: rtmr0-reset-n-active-state { pins = "gpio10"; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts b/arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts new file mode 100644 index 000000000000..20a33e6f27ee --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts @@ -0,0 +1,1515 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2025 TUXEDO Computers GmbH + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> + +#include "hamoa.dtsi" +#include "hamoa-pmics.dtsi" + +/* + * This device tree also works for the TUXEDO Elite 14 Gen1 notebook + * prototype. + */ + +/ { + model = "Medion SPRCHRGD 14 S1"; + compatible = "medion,sprchrgd14s1", "qcom,x1e78100", "qcom,x1e80100"; + + aliases { + serial0 = &uart21; + serial1 = &uart14; + }; + + wcd938x: audio-codec { + compatible = "qcom,wcd9385-codec"; + + pinctrl-0 = <&wcd_default>; + pinctrl-names = "default"; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>; + + vdd-buck-supply = <&vreg_l15b_1p8>; + vdd-rxtx-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l15b_1p8>; + vdd-mic-bias-supply = <&vreg_bob1>; + + #sound-dai-cells = <1>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&hall_int_n_default>; + pinctrl-names = "default"; + + switch-lid { + gpios = <&tlmm 92 GPIO_ACTIVE_LOW>; + linux,input-type = <EV_SW>; + linux,code = <SW_LID>; + wakeup-source; + }; + }; + + hdmi-bridge { + compatible = "asl-tek,cs5263"; + + pinctrl-0 = <&hdmi_hpd_default>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_bridge_dp_in: endpoint { + remote-endpoint = <&usb_1_ss2_qmpphy_out_dp>; + }; + }; + + port@1 { + reg = <1>; + + hdmi_bridge_tmds_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&hdmi_bridge_tmds_out>; + }; + }; + }; + + pmic-glink { + compatible = "qcom,x1e80100-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss0_hs_in: endpoint { + remote-endpoint = <&usb_1_ss0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss0_ss_in: endpoint { + remote-endpoint = <&retimer_ss0_ss_out>; + }; + }; + port@2 { + reg = <2>; + + pmic_glink_ss0_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss0_con_sbu_out>; + }; + }; + }; + }; + }; + + vreg_edp_3p3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 54 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_nvme: regulator-nvme { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&nvme_reg_en>; + pinctrl-names = "default"; + regulator-boot-on; + }; + + vreg_rtmr0_1p15: regulator-rtmr0-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_1P15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_pwr_1p15_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_1p8: regulator-rtmr0-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_1p8_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_3p3: regulator-rtmr0-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + /* + * TODO: These two regulators are actually part of the removable M.2 + * card and not the mainboard. Need to describe this differently. + * Functionally it works correctly, because all we need to do is to + * turn on the actual 3.3V supply above. + */ + vreg_wcn_0p95: regulator-wcn-0p95 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_0P95"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_1p9: regulator-wcn-1p9 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_1P9"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 214 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wcn_sw_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + reserved-memory { + linux,cma { + compatible = "shared-dma-pool"; + size = <0x0 0x8000000>; + reusable; + linux,cma-default; + }; + }; + + sound { + compatible = "qcom,x1e80100-sndcard"; + model = "X1E80100-MEDION-SPRCHRGD-14-S1"; + audio-routing = "WooferLeft IN", "WSA WSA_SPK1 OUT", + "TweeterLeft IN", "WSA WSA_SPK2 OUT", + "WooferRight IN", "WSA2 WSA_SPK2 OUT", + "TweeterRight IN", "WSA2 WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "VA DMIC0", "MIC BIAS1", + "VA DMIC1", "MIC BIAS1", + "TX SWR_INPUT1", "ADC2_OUTPUT"; + + displayport-0-dai-link { + link-name = "DisplayPort0 Playback"; + + codec { + sound-dai = <&mdss_dp0>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + displayport-2-dai-link { + link-name = "DisplayPort2 Playback"; + + codec { + sound-dai = <&mdss_dp2>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_2>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + + codec { + sound-dai = <&wcd938x 1>, <&swr2 1>, <&lpass_txmacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + codec { + sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + codec { + sound-dai = <&left_woofer>, <&left_tweeter>, + <&swr0 0>, <&lpass_wsamacro 0>, + <&right_woofer>, <&right_tweeter>, + <&swr3 0>, <&lpass_wsa2macro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + vdd-supply = <&vreg_wcn_0p95>; + vddio-supply = <&vreg_l15b_1p8>; + vddaon-supply = <&vreg_wcn_0p95>; + vdddig-supply = <&vreg_wcn_0p95>; + vddrfa1p2-supply = <&vreg_wcn_1p9>; + vddrfa1p8-supply = <&vreg_wcn_1p9>; + + wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; + bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&wcn_wlan_bt_en>; + pinctrl-names = "default"; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id = "b"; + vdd-bob1-supply = <&vph_pwr>; + vdd-bob2-supply = <&vph_pwr>; + vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>; + vdd-l2-l13-l14-supply = <&vreg_bob1>; + vdd-l5-l16-supply = <&vreg_bob1>; + vdd-l6-l7-supply = <&vreg_bob2>; + vdd-l8-l9-supply = <&vreg_bob1>; + vdd-l12-supply = <&vreg_s5j_1p2>; + vdd-l15-supply = <&vreg_s4c_1p8>; + vdd-l17-supply = <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name = "vreg_l1b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4b_1p8: ldo4 { + regulator-name = "vreg_l4b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7b_2p8: ldo7 { + regulator-name = "vreg_l7b_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8b_3p0: ldo8 { + regulator-name = "vreg_l8b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l10b_1p8: ldo10 { + regulator-name = "vreg_l10b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l12b_1p2: ldo12 { + regulator-name = "vreg_l12b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l14b_3p0: ldo14 { + regulator-name = "vreg_l14b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l16b_2p8: ldo16 { + regulator-name = "vreg_l16b_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name = "vreg_l17b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s4-supply = <&vph_pwr>; + + vreg_l1c_1p2: ldo1 { + regulator-name = "vreg_l1c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2c_0p8: ldo2 { + regulator-name = "vreg_l2c_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3c_0p9: ldo3 { + regulator-name = "vreg_l3c_0p9"; + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s4c_1p8: smps4 { + regulator-name = "vreg_s4c_1p8"; + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-2 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "d"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s4c_1p8>; + vdd-s1-supply = <&vph_pwr>; + + vreg_l1d_0p8: ldo1 { + regulator-name = "vreg_l1d_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2d_0p9: ldo2 { + regulator-name = "vreg_l2d_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3d_1p8: ldo3 { + regulator-name = "vreg_l3d_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-3 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s5j_1p2>; + + vreg_l2e_0p8: ldo2 { + regulator-name = "vreg_l2e_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-4 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s5j_1p2>; + vdd-s1-supply = <&vph_pwr>; + + vreg_s1f_0p7: smps1 { + regulator-name = "vreg_s1f_0p7"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-6 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "i"; + + vdd-l1-supply = <&vreg_s4c_1p8>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + + vreg_l1i_1p8: ldo1 { + regulator-name = "vreg_l1i_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2i_1p2: ldo2 { + regulator-name = "vreg_l2i_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3i_0p8: ldo3 { + regulator-name = "vreg_l3i_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s1i_0p9: smps1 { + regulator-name = "vreg_s1i_0p9"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s2i_1p0: smps2 { + regulator-name = "vreg_s2i_1p0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-7 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "j"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s5-supply = <&vph_pwr>; + + vreg_l1j_0p9: ldo1 { + regulator-name = "vreg_l1j_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2j_1p2: ldo2 { + regulator-name = "vreg_l2j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1256000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3j_0p8: ldo3 { + regulator-name = "vreg_l3j_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s5j_1p2: smps5 { + regulator-name = "vreg_s5j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; +}; + +&gpu { + status = "okay"; + + zap-shader { + firmware-name = "qcom/x1e80100/Medion/sprchrgd-14-s1/qcdxkmsuc8380.mbn"; + }; +}; + +&i2c0 { + clock-frequency = <400000>; + + status = "okay"; + + touchpad@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + + hid-descr-addr = <0x20>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&tpad_default>; + pinctrl-names = "default"; + + wakeup-source; + }; + + keyboard@3a { + compatible = "hid-over-i2c"; + reg = <0x3a>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&kybd_default>; + pinctrl-names = "default"; + + wakeup-source; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + + status = "okay"; + + typec-mux@8 { + compatible = "parade,ps8830"; + reg = <0x8>; + + clocks = <&rpmhcc RPMH_RF_CLK3>; + + vdd33-supply = <&vreg_rtmr0_3p3>; + vdd33-cap-supply = <&vreg_rtmr0_3p3>; + + vddio-supply = <&vreg_rtmr0_1p8>; + + vdd-supply = <&vreg_rtmr0_1p15>; + vddar-supply = <&vreg_rtmr0_1p15>; + vddat-supply = <&vreg_rtmr0_1p15>; + + reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&rtmr0_default>; + pinctrl-names = "default"; + + retimer-switch; + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss0_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss0_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss0_ss_in: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss0_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss0_con_sbu_in>; + }; + }; + }; + }; +}; + +&i2c5 { + clock-frequency = <400000>; + + status = "okay"; + + eusb5_repeater: redriver@43 { + compatible = "nxp,ptn3222"; + reg = <0x43>; + #phy-cells = <0>; + + vdd1v8-supply = <&vreg_l4b_1p8>; + vdd3v3-supply = <&vreg_l13b_3p0>; + + reset-gpios = <&tlmm 184 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb5_reset_n>; + pinctrl-names = "default"; + }; + + eusb3_repeater: redriver@47 { + compatible = "nxp,ptn3222"; + reg = <0x47>; + #phy-cells = <0>; + + vdd1v8-supply = <&vreg_l4b_1p8>; + vdd3v3-supply = <&vreg_l13b_3p0>; + + reset-gpios = <&tlmm 124 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb3_reset_n>; + pinctrl-names = "default"; + }; + + eusb6_repeater: redriver@4f { + compatible = "nxp,ptn3222"; + reg = <0x4f>; + #phy-cells = <0>; + + vdd1v8-supply = <&vreg_l4b_1p8>; + vdd3v3-supply = <&vreg_l13b_3p0>; + + reset-gpios = <&tlmm 111 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb6_reset_n>; + pinctrl-names = "default"; + }; +}; + +&iris { + firmware-name = "qcom/x1e80100/Medion/sprchrgd-14-s1/qcvss8380.mbn"; + + status = "okay"; +}; + +&lpass_tlmm { + spkr_01_sd_n_active: spkr-01-sd-n-active-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + spkr_23_sd_n_active: spkr-23-sd-n-active-state { + pins = "gpio13"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; +}; + +&lpass_vamacro { + pinctrl-0 = <&dmic01_default>; + pinctrl-names = "default"; + + vdd-micb-supply = <&vreg_l1b_1p8>; + qcom,dmic-sample-rate = <4800000>; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + sound-name-prefix = "DisplayPort0"; + + status = "okay"; +}; + +&mdss_dp0_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp2 { + sound-name-prefix = "DisplayPort2"; + + status = "okay"; +}; + +&mdss_dp2_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp3 { + /delete-property/ #sound-dai-cells; + + pinctrl-0 = <&edp0_hpd_default>; + pinctrl-names = "default"; + + status = "okay"; + + aux-bus { + panel { + compatible = "edp-panel"; + power-supply = <&vreg_edp_3p3>; + + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + }; + + ports { + port@1 { + reg = <1>; + + mdss_dp3_out: endpoint { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&edp_panel_in>; + }; + }; + }; +}; + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pcie4 { + perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie4_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie4_port0 { + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; +}; + +&pcie6a { + perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; + + vddpe-3v3-supply = <&vreg_nvme>; + + pinctrl-0 = <&pcie6a_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie6a_phy { + vdda-phy-supply = <&vreg_l1d_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pm8550_gpios { + rtmr0_default: rtmr0-reset-n-active-state { + pins = "gpio10"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; + + usb0_3p3_reg_en: usb0-3p3-reg-en-state { + pins = "gpio11"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + +&pm8550ve_9_gpios { + usb0_1p8_reg_en: usb0-1p8-reg-en-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + +&pmc8380_5_gpios { + usb0_pwr_1p15_reg_en: usb0-pwr-1p15-reg-en-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + +&qupv3_0 { + status = "okay"; +}; + +&qupv3_1 { + status = "okay"; +}; + +&qupv3_2 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/x1e80100/Medion/sprchrgd-14-s1/qcadsp8380.mbn", + "qcom/x1e80100/Medion/sprchrgd-14-s1/adsp_dtbs.elf"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1e80100/Medion/sprchrgd-14-s1/qccdsp8380.mbn", + "qcom/x1e80100/Medion/sprchrgd-14-s1/cdsp_dtbs.elf"; + + status = "okay"; +}; + +&smb2360_0 { + status = "okay"; +}; + +&smb2360_0_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l2b_3p0>; +}; + +&swr0 { + status = "okay"; + + pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>; + pinctrl-names = "default"; + + /* WSA8845, Left Woofer */ + left_woofer: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "WooferLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Left Tweeter */ + left_tweeter: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "TweeterLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + +&swr1 { + status = "okay"; + + /* WCD9385 RX */ + wcd_rx: codec@0,4 { + compatible = "sdw20217010d00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5>; + }; +}; + +&swr2 { + status = "okay"; + + /* WCD9385 TX */ + wcd_tx: codec@0,3 { + compatible = "sdw20217010d00"; + reg = <0 3>; + qcom,tx-port-mapping = <2 2 3 4>; + }; +}; + +&swr3 { + status = "okay"; + + pinctrl-0 = <&wsa2_swr_active>, <&spkr_23_sd_n_active>; + pinctrl-names = "default"; + + /* WSA8845, Right Woofer */ + right_woofer: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "WooferRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Right Tweeter */ + right_tweeter: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "TweeterRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + +&tlmm { + gpio-reserved-ranges = <28 4>, /* Unused */ + <44 4>, /* SPI (TPM) */ + <238 1>; /* UFS Reset */ + + edp_reg_en: edp-reg-en-state { + pins = "gpio54"; + function = "gpio"; + drive-strength = <16>; + bias-pull-up; + }; + + eusb3_reset_n: eusb3-reset-n-state { + pins = "gpio124"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + eusb6_reset_n: eusb6-reset-n-state { + pins = "gpio111"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + eusb5_reset_n: eusb5-reset-n-state { + pins = "gpio184"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + hall_int_n_default: hall-int-n-state { + pins = "gpio92"; + function = "gpio"; + bias-disable; + }; + + hdmi_hpd_default: hdmi-hpd-default-state { + pins = "gpio126"; + function = "usb2_dp"; + bias-disable; + }; + + kybd_default: kybd-default-state { + pins = "gpio67"; + function = "gpio"; + bias-disable; + }; + + nvme_reg_en: nvme-reg-en-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins = "gpio147"; + function = "pcie4_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio146"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio148"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie6a_default: pcie6a-default-state { + clkreq-n-pins { + pins = "gpio153"; + function = "pcie6a_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio152"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio154"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + tpad_default: tpad-default-state { + pins = "gpio3"; + function = "gpio"; + bias-disable; + }; + + wcd_default: wcd-reset-n-active-state { + pins = "gpio191"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + wcn_sw_en: wcn-sw-en-state { + pins = "gpio214"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wcn_wlan_bt_en: wcn-wlan-bt-en-state { + pins = "gpio116", "gpio117"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + max-speed = <3200000>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + }; +}; + +&usb_1_ss0_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_0_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss0_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l1j_0p9>; + + status = "okay"; +}; + +&usb_1_ss0 { + status = "okay"; +}; + +&usb_1_ss0_dwc3 { + dr_mode = "host"; +}; + +&usb_1_ss0_dwc3_hs { + remote-endpoint = <&pmic_glink_ss0_hs_in>; +}; + +&usb_1_ss0_qmpphy_out { + remote-endpoint = <&retimer_ss0_ss_in>; +}; + +&usb_1_ss2_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + /delete-property/ mode-switch; + /delete-property/ orientation-switch; + + status = "okay"; + + ports { + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + /delete-node/ endpoint; + + usb_1_ss2_qmpphy_out_dp: endpoint@0 { + reg = <0>; + + data-lanes = <3 2 1 0>; + remote-endpoint = <&hdmi_bridge_dp_in>; + }; + + /* No USB3 lanes connected */ + }; + }; +}; + +/* Camera */ +&usb_2 { + status = "okay"; +}; + +&usb_2_dwc3 { + dr_mode = "host"; +}; + +&usb_2_hsphy { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb5_repeater>; + + status = "okay"; +}; + +&usb_mp { + status = "okay"; +}; + +/* Right side USB-A (eUSB 3) */ +&usb_mp_hsphy0 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb3_repeater>; + + status = "okay"; +}; + +/* Left side USB-A (eUSB 6) */ +&usb_mp_hsphy1 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb6_repeater>; + + status = "okay"; +}; + +/* Right side USB-A (USB-SS 3) */ +&usb_mp_qmpphy0 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p9>; + + status = "okay"; +}; + +/* Left side USB-A (USB-SS 4) */ +&usb_mp_qmpphy1 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p9>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-denali-oled.dts b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-denali-oled.dts new file mode 100644 index 000000000000..07ce43ccf394 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-denali-oled.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025 Dale Whinham <daleyo@gmail.com> + */ + +/dts-v1/; + +#include "hamoa.dtsi" +#include "x1-microsoft-denali.dtsi" + +/ { + model = "Microsoft Surface Pro 11th Edition (OLED)"; + compatible = "microsoft,denali-oled", "microsoft,denali", + "qcom,x1e80100"; +}; + +&panel { + compatible = "samsung,atna30dw01", "samsung,atna33xc20"; +}; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi index 7e1e808ea983..37539a09b76e 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi @@ -1094,9 +1094,6 @@ }; &pcie3 { - perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 145 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&pcie3_default>; pinctrl-names = "default"; @@ -1112,6 +1109,11 @@ status = "okay"; }; +&pcie3_port0 { + reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; +}; + &pcie4 { status = "okay"; }; @@ -1124,6 +1126,9 @@ }; &pcie4_port0 { + reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + wifi@0 { compatible = "pci17cb,1107"; reg = <0x10000 0x0 0x0 0x0 0x0>; @@ -1141,9 +1146,6 @@ }; &pcie6a { - perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_nvme>; pinctrl-0 = <&pcie6a_default>; @@ -1159,6 +1161,11 @@ status = "okay"; }; +&pcie6a_port0 { + reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; +}; + &pm8550_gpios { rtmr0_default: rtmr0-reset-n-active-state { pins = "gpio10"; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts index b742aabd9c04..1d402ef86512 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts @@ -979,8 +979,6 @@ &pcie3 { pinctrl-names = "default"; pinctrl-0 = <&pcie3_default>; - perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; status = "okay"; }; @@ -992,16 +990,16 @@ status = "okay"; }; -&pcie3_port { +&pcie3_port0 { vpcie12v-supply = <&vreg_pcie_12v>; vpcie3v3-supply = <&vreg_pcie_3v3>; vpcie3v3aux-supply = <&vreg_pcie_3v3_aux>; + + reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; }; &pcie4 { - perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie4_default>; pinctrl-names = "default"; @@ -1016,6 +1014,9 @@ }; &pcie4_port0 { + reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + wifi@0 { compatible = "pci17cb,1107"; reg = <0x10000 0x0 0x0 0x0 0x0>; @@ -1033,9 +1034,6 @@ }; &pcie6a { - perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_nvme>; pinctrl-names = "default"; @@ -1051,6 +1049,11 @@ status = "okay"; }; +&pcie6a_port0 { + reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; +}; + &qupv3_0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts b/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts index 3186e79e862d..1e5eb8c5dc98 100644 --- a/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts +++ b/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts @@ -78,6 +78,47 @@ vdd-supply = <&vreg_cam_5p0>; }; + hdmi-bridge { + compatible = "realtek,rtd2171"; + + enable-gpios = <&tlmm 120 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&hdmi_hpd_default>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_bridge_dp_in: endpoint { + remote-endpoint = <&usb_1_ss2_qmpphy_out_dp>; + }; + }; + + port@1 { + reg = <1>; + + hdmi_bridge_tmds_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&hdmi_bridge_tmds_out>; + }; + }; + }; + gpio-keys { compatible = "gpio-keys"; @@ -1038,6 +1079,14 @@ link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; +&mdss_dp2 { + status = "okay"; +}; + +&mdss_dp2_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + &mdss_dp3 { /delete-property/ #sound-dai-cells; @@ -1327,6 +1376,19 @@ bias-disable; }; + hdmi_bridge_en: hdmi-bridge-en-state { + pins = "gpio120"; + function = "gpio"; + drive-strength = <16>; + bias-pull-down; + }; + + hdmi_hpd_default: hdmi-hpd-default-state { + pins = "gpio126"; + function = "usb2_dp"; + bias-disable; + }; + kybd_default: kybd-default-state { pins = "gpio67"; function = "gpio"; @@ -1560,6 +1622,8 @@ maximum-speed = "high-speed"; phys = <&usb_1_ss2_hsphy>; phy-names = "usb2-phy"; + + /delete-property/ port@1; }; &usb_1_ss2_hsphy { @@ -1571,6 +1635,32 @@ status = "okay"; }; +&usb_1_ss2_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + /delete-property/ mode-switch; + /delete-property/ orientation-switch; + + status = "okay"; + + ports { + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + /delete-node/ endpoint; + + usb_1_ss2_qmpphy_out_dp: endpoint@0 { + reg = <0>; + + data-lanes = <0 1 2 3>; + remote-endpoint = <&hdmi_bridge_dp_in>; + }; + }; + }; +}; + &usb_2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1p64100-microsoft-denali.dts b/arch/arm64/boot/dts/qcom/x1p64100-microsoft-denali.dts new file mode 100644 index 000000000000..d96202e2afc6 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1p64100-microsoft-denali.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025 Dale Whinham <daleyo@gmail.com> + */ + +/dts-v1/; + +#include "hamoa.dtsi" +#include "x1-microsoft-denali.dtsi" + +/ { + model = "Microsoft Surface Pro 11th Edition (LCD)"; + compatible = "microsoft,denali-lcd", "microsoft,denali", + "qcom,x1p64100", "qcom,x1e80100"; +}; diff --git a/arch/arm64/boot/dts/realtek/Makefile b/arch/arm64/boot/dts/realtek/Makefile index ef8d8fcbaa05..60a37d5a948c 100644 --- a/arch/arm64/boot/dts/realtek/Makefile +++ b/arch/arm64/boot/dts/realtek/Makefile @@ -1,15 +1,14 @@ # SPDX-License-Identifier: GPL-2.0-only dtb-$(CONFIG_ARCH_REALTEK) += rtd1293-ds418j.dtb - dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-mele-v9.dtb dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-probox2-ava.dtb dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-xnano-x5.dtb dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-zidoo-x9s.dtb - dtb-$(CONFIG_ARCH_REALTEK) += rtd1296-ds418.dtb - dtb-$(CONFIG_ARCH_REALTEK) += rtd1395-bpi-m4.dtb dtb-$(CONFIG_ARCH_REALTEK) += rtd1395-lionskin.dtb - +dtb-$(CONFIG_ARCH_REALTEK) += rtd1501s-phantom-8gb.dtb dtb-$(CONFIG_ARCH_REALTEK) += rtd1619-mjolnir.dtb +dtb-$(CONFIG_ARCH_REALTEK) += rtd1861b-krypton-8gb.dtb +dtb-$(CONFIG_ARCH_REALTEK) += rtd1920s-smallville-4gb.dtb diff --git a/arch/arm64/boot/dts/realtek/kent.dtsi b/arch/arm64/boot/dts/realtek/kent.dtsi new file mode 100644 index 000000000000..ae006ce24420 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/kent.dtsi @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Realtek Kent SoC family + * + * Copyright (c) 2024 Realtek Semiconductor Corp. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart0; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a78"; + reg = <0x0>; + enable-method = "psci"; + next-level-cache = <&l2_0>; + dynamic-power-coefficient = <454>; + #cooling-cells = <2>; + + l2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-line-size = <64>; + cache-sets = <256>; + cache-size = <0x40000>; + cache-unified; + next-level-cache = <&l3>; + }; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a78"; + reg = <0x100>; + enable-method = "psci"; + next-level-cache = <&l2_1>; + dynamic-power-coefficient = <454>; + #cooling-cells = <2>; + + l2_1: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-line-size = <64>; + cache-sets = <256>; + cache-size = <0x40000>; + cache-unified; + next-level-cache = <&l3>; + }; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a78"; + reg = <0x200>; + enable-method = "psci"; + next-level-cache = <&l2_2>; + dynamic-power-coefficient = <454>; + #cooling-cells = <2>; + + l2_2: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-line-size = <64>; + cache-sets = <256>; + cache-size = <0x40000>; + cache-unified; + next-level-cache = <&l3>; + }; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a78"; + reg = <0x300>; + enable-method = "psci"; + next-level-cache = <&l2_3>; + dynamic-power-coefficient = <454>; + #cooling-cells = <2>; + + l2_3: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-line-size = <64>; + cache-sets = <256>; + cache-size = <0x40000>; + cache-unified; + next-level-cache = <&l3>; + }; + }; + + l3: l3-cache { + compatible = "cache"; + cache-level = <3>; + cache-line-size = <64>; + cache-sets = <512>; + cache-size = <0x200000>; + cache-unified; + }; + }; + + psci: psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + soc@0 { + compatible = "simple-bus"; + ranges = <0x0 0x0 0x0 0x40000>, /* boot code */ + <0x98000000 0x0 0x98000000 0xef0000>, /* rbus */ + <0xa0000000 0x0 0xa0000000 0x10000000>, /* PCIE */ + <0xff000000 0x0 0xff000000 0x200000>; /* GIC */ + #address-cells = <1>; + #size-cells = <1>; + + rbus: bus@98000000 { + compatible = "simple-bus"; + ranges = <0x0 0x98000000 0xef0000>, + <0xa0000000 0xa0000000 0x10000000>; /* PCIE */ + #address-cells = <1>; + #size-cells = <1>; + + uart0: serial@7800 { + compatible = "snps,dw-apb-uart"; + reg = <0x7800 0x100>; + clock-frequency = <432000000>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + }; + + gic: interrupt-controller@ff100000 { + compatible = "arm,gic-v3"; + reg = <0xff100000 0x10000>, + <0xff140000 0x80000>; + interrupt-controller; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #interrupt-cells = <3>; + #size-cells = <1>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/realtek/rtd1501.dtsi b/arch/arm64/boot/dts/realtek/rtd1501.dtsi new file mode 100644 index 000000000000..65f7ede3df73 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1501.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Realtek RTD1501 SoC + * + * Copyright (c) 2024 Realtek Semiconductor Corp. + */ + +#include "kent.dtsi" + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/realtek/rtd1501s-phantom-8gb.dts b/arch/arm64/boot/dts/realtek/rtd1501s-phantom-8gb.dts new file mode 100644 index 000000000000..09e544acfd34 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1501s-phantom-8gb.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Realtek RTD1501S Phantom EVB + * + * Copyright (c) 2024 Realtek Semiconductor Corp. + */ + +/dts-v1/; + +#include "rtd1501s-phantom.dtsi" + +/ { + compatible = "realtek,phantom", "realtek,rtd1501s"; + model = "Realtek Phantom EVB Chromium (8GB)"; + + memory@40000 { + device_type = "memory"; + reg = <0x0 0x50000 0x0 0x7ffb0000>, + <0x0 0x8a100000 0x0 0xdef0000>, + <0x0 0x98700000 0x0 0x7900000>, + <0x0 0xa0600000 0x0 0x5ea00000>, + <0x1 0x0 0x0 0xa0000000>, + <0x1 0xa0600000 0x0 0x5fa00000>; + }; +}; diff --git a/arch/arm64/boot/dts/realtek/rtd1501s-phantom.dtsi b/arch/arm64/boot/dts/realtek/rtd1501s-phantom.dtsi new file mode 100644 index 000000000000..bcfb96799671 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1501s-phantom.dtsi @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Realtek RTD1501S Phantom EVB + * + * Copyright (c) 2024 Realtek Semiconductor Corp. + */ + +/dts-v1/; + +#include <dt-bindings/thermal/thermal.h> +#include "rtd1501.dtsi" + +/ { + chosen { + stdout-path = "serial0:460800n8"; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + alignment = <0x0 0x400000>; + alloc-ranges = <0x0 0x0 0x0 0x20000000>; + size = <0x0 0x2000000>; + reusable; + linux,cma-default; + }; + }; + + cpu_opps: opp-table-cpu { + compatible = "operating-points-v2"; + opp-shared; + + opp800: opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <830000 830000 1100000>; + }; + + opp900: opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <850000 850000 1100000>; + }; + + opp1000: opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <870000 870000 1100000>; + }; + + opp1100: opp-1100000000 { + opp-hz = /bits/ 64 <1100000000>; + opp-microvolt = <890000 890000 1100000>; + }; + + opp1200: opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <910000 910000 1100000>; + }; + + opp1300: opp-1300000000 { + opp-hz = /bits/ 64 <1300000000>; + opp-microvolt = <930000 930000 1100000>; + }; + + opp1400: opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-microvolt = <950000 950000 1100000>; + }; + + opp1500: opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <970000 970000 1100000>; + }; + + opp1600: opp-1600000000 { + opp-hz = /bits/ 64 <1600000000>; + opp-microvolt = <990000 990000 1100000>; + opp-suspend; + }; + + opp1700: opp-1700000000 { + opp-hz = /bits/ 64 <1700000000>; + opp-microvolt = <1010000 1010000 1100000>; + }; + + opp1800: opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1030000 1030000 1100000>; + }; + + opp1900: opp-1900000000 { + opp-hz = /bits/ 64 <1900000000>; + opp-microvolt = <1050000 1050000 1100000>; + }; + }; +}; + +&cpu0 { + operating-points-v2 = <&cpu_opps>; + #cooling-cells = <2>; +}; + +&cpu1 { + operating-points-v2 = <&cpu_opps>; + #cooling-cells = <2>; +}; + +&cpu2 { + operating-points-v2 = <&cpu_opps>; + #cooling-cells = <2>; +}; + +&cpu3 { + operating-points-v2 = <&cpu_opps>; + #cooling-cells = <2>; +}; diff --git a/arch/arm64/boot/dts/realtek/rtd1861.dtsi b/arch/arm64/boot/dts/realtek/rtd1861.dtsi new file mode 100644 index 000000000000..44c3de8f1f48 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1861.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Realtek RTD1861 SoC + * + * Copyright (c) 2024 Realtek Semiconductor Corp. + */ + +#include "kent.dtsi" + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/realtek/rtd1861b-krypton-8gb.dts b/arch/arm64/boot/dts/realtek/rtd1861b-krypton-8gb.dts new file mode 100644 index 000000000000..9c23d901c49c --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1861b-krypton-8gb.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Realtek RTD1861B Krypton EVB + * + * Copyright (c) 2024 Realtek Semiconductor Corp. + */ + +/dts-v1/; + +#include "rtd1861b-krypton.dtsi" + +/ { + compatible = "realtek,krypton", "realtek,rtd1861b"; + model = "Realtek Krypton EVB (8GB)"; + + memory@40000 { + device_type = "memory"; + reg = <0x0 0x50000 0x0 0x7ffb0000>, + <0x0 0x8a100000 0x0 0xdef0000>, + <0x0 0x98700000 0x0 0x7900000>, + <0x0 0xa0600000 0x0 0x5ea00000>, + <0x1 0x0 0x0 0xa0000000>, + <0x1 0xa0600000 0x0 0x5fa00000>; + }; +}; diff --git a/arch/arm64/boot/dts/realtek/rtd1861b-krypton.dtsi b/arch/arm64/boot/dts/realtek/rtd1861b-krypton.dtsi new file mode 100644 index 000000000000..b500f4d2c502 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1861b-krypton.dtsi @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Realtek RTD1861B Krypton EVB + * + * Copyright (c) 2024 Realtek Semiconductor Corp. + */ + +/dts-v1/; + +#include "rtd1861.dtsi" + +/ { + chosen { + stdout-path = "serial0:460800n8"; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + alignment = <0x0 0x400000>; + alloc-ranges = <0x0 0x0 0x0 0x20000000>; + size = <0x0 0x2000000>; + reusable; + linux,cma-default; + }; + }; + + cpu_opps: opp-table-cpu { + compatible = "operating-points-v2"; + opp-shared; + + opp1200: opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <900000>; + }; + + opp1600: opp-1600000000 { + opp-hz = /bits/ 64 <1600000000>; + opp-microvolt = <1000000>; + opp-suspend; + }; + + opp1800: opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1050000>; + }; + }; +}; + +&cpu0 { + operating-points-v2 = <&cpu_opps>; + #cooling-cells = <2>; +}; + +&cpu1 { + operating-points-v2 = <&cpu_opps>; + #cooling-cells = <2>; +}; + +&cpu2 { + operating-points-v2 = <&cpu_opps>; + #cooling-cells = <2>; +}; + +&cpu3 { + operating-points-v2 = <&cpu_opps>; + #cooling-cells = <2>; +}; diff --git a/arch/arm64/boot/dts/realtek/rtd1920.dtsi b/arch/arm64/boot/dts/realtek/rtd1920.dtsi new file mode 100644 index 000000000000..becf546216e9 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1920.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Realtek RTD1920 SoC + * + * Copyright (c) 2024 Realtek Semiconductor Corp. + */ + +#include "kent.dtsi" + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/realtek/rtd1920s-smallville-4gb.dts b/arch/arm64/boot/dts/realtek/rtd1920s-smallville-4gb.dts new file mode 100644 index 000000000000..9fd6976e0d9b --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1920s-smallville-4gb.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Realtek RTD1920S Smallville EVB + * + * Copyright (c) 2024 Realtek Semiconductor Corp. + */ + +/dts-v1/; + +#include "rtd1920s-smallville.dtsi" + +/ { + compatible = "realtek,smallville", "realtek,rtd1920s"; + model = "Realtek Smallville EVB (4GB)"; + + memory@40000 { + device_type = "memory"; + reg = <0x0 0x50000 0x0 0x7ffb0000>, + <0x0 0x8a100000 0x0 0xdef0000>, + <0x0 0x98700000 0x0 0x7900000>, + <0x0 0xa1000000 0x0 0x5e000000>; + }; +}; diff --git a/arch/arm64/boot/dts/realtek/rtd1920s-smallville.dtsi b/arch/arm64/boot/dts/realtek/rtd1920s-smallville.dtsi new file mode 100644 index 000000000000..3db8fcea6447 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1920s-smallville.dtsi @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Realtek RTD1920S Smallville EVB + * + * Copyright (c) 2024 Realtek Semiconductor Corp. + */ + +/dts-v1/; + +#include <dt-bindings/thermal/thermal.h> +#include "rtd1920.dtsi" + +/ { + chosen { + stdout-path = "serial0:460800n8"; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + protected_mem: protected-mem@50000 { + reg = <0x0 0x50000 0x0 0xbf0000>; + no-map; + }; + + metadata: metadata@c40000 { + reg = <0x0 0xc40000 0x0 0x3c4000>; + no-map; + }; + + linux,cma { + compatible = "shared-dma-pool"; + alignment = <0x0 0x400000>; + alloc-ranges = <0x0 0x0 0x0 0x20000000>; + size = <0x0 0x2000000>; + reusable; + linux,cma-default; + }; + }; + + cpu_opps: opp-table-cpu { + compatible = "operating-points-v2"; + opp-shared; + + opp800: opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <830000 830000 1100000>; + }; + + opp900: opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <850000 850000 1100000>; + }; + + opp1000: opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <870000 870000 1100000>; + }; + + opp1100: opp-1100000000 { + opp-hz = /bits/ 64 <1100000000>; + opp-microvolt = <890000 890000 1100000>; + }; + + opp1200: opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <910000 910000 1100000>; + }; + + opp1300: opp-1300000000 { + opp-hz = /bits/ 64 <1300000000>; + opp-microvolt = <930000 930000 1100000>; + }; + + opp1400: opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-microvolt = <950000 950000 1100000>; + }; + + opp1500: opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <970000 970000 1100000>; + }; + + opp1600: opp-1600000000 { + opp-hz = /bits/ 64 <1600000000>; + opp-microvolt = <990000 990000 1100000>; + opp-suspend; + }; + + opp1700: opp-1700000000 { + opp-hz = /bits/ 64 <1700000000>; + opp-microvolt = <1010000 1010000 1100000>; + }; + + opp1800: opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1030000 1030000 1100000>; + }; + + opp1900: opp-1900000000 { + opp-hz = /bits/ 64 <1900000000>; + opp-microvolt = <1050000 1050000 1100000>; + }; + }; +}; + +&cpu0 { + operating-points-v2 = <&cpu_opps>; + #cooling-cells = <2>; +}; + +&cpu1 { + operating-points-v2 = <&cpu_opps>; + #cooling-cells = <2>; +}; + +&cpu2 { + operating-points-v2 = <&cpu_opps>; + #cooling-cells = <2>; +}; + +&cpu3 { + operating-points-v2 = <&cpu_opps>; + #cooling-cells = <2>; +}; diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi index d40a7224f9c3..af6d15f90c65 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi @@ -158,7 +158,7 @@ reg = <0x51>; }; - versaclock5: versaclock_som@6a { + versaclock5: versaclock-som@6a { compatible = "idt,5p49v6965"; reg = <0x6a>; #clock-cells = <1>; diff --git a/arch/arm64/boot/dts/renesas/condor-common.dtsi b/arch/arm64/boot/dts/renesas/condor-common.dtsi index 9fe9c722187d..6b22cc0b05b1 100644 --- a/arch/arm64/boot/dts/renesas/condor-common.dtsi +++ b/arch/arm64/boot/dts/renesas/condor-common.dtsi @@ -501,7 +501,7 @@ reg = <0x00040000 0x080000>; read-only; }; - cert_header_sa3@c0000 { + cert-header-sa3@c0000 { reg = <0x000c0000 0x080000>; read-only; }; @@ -509,7 +509,7 @@ reg = <0x00140000 0x040000>; read-only; }; - cert_header_sa6@180000 { + cert-header-sa6@180000 { reg = <0x00180000 0x040000>; read-only; }; @@ -554,3 +554,8 @@ &scif_clk { clock-frequency = <14745600>; }; + +/* Firmware should reserve it but sadly doesn't */ +&swdt { + status = "reserved"; +}; diff --git a/arch/arm64/boot/dts/renesas/draak.dtsi b/arch/arm64/boot/dts/renesas/draak.dtsi index 733a55f77cfb..c83c97d99113 100644 --- a/arch/arm64/boot/dts/renesas/draak.dtsi +++ b/arch/arm64/boot/dts/renesas/draak.dtsi @@ -660,7 +660,7 @@ reg = <0x00040000 0x140000>; read-only; }; - cert_header_sa6@180000 { + cert-header-sa6@180000 { reg = <0x00180000 0x040000>; read-only; }; diff --git a/arch/arm64/boot/dts/renesas/ebisu.dtsi b/arch/arm64/boot/dts/renesas/ebisu.dtsi index adc4449b809a..692a2b12aa03 100644 --- a/arch/arm64/boot/dts/renesas/ebisu.dtsi +++ b/arch/arm64/boot/dts/renesas/ebisu.dtsi @@ -765,7 +765,7 @@ reg = <0x00040000 0x140000>; read-only; }; - cert_header_sa6@180000 { + cert-header-sa6@180000 { reg = <0x00180000 0x040000>; read-only; }; diff --git a/arch/arm64/boot/dts/renesas/gmsl-cameras.dtsi b/arch/arm64/boot/dts/renesas/gmsl-cameras.dtsi deleted file mode 100644 index e0930d1ba3aa..000000000000 --- a/arch/arm64/boot/dts/renesas/gmsl-cameras.dtsi +++ /dev/null @@ -1,332 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2017 Ideas on Board <kieran.bingham@ideasonboard.com> - * Copyright (C) 2021 Jacopo Mondi <jacopo+renesas@jmondi.org> - * - * Device Tree Source (overlay) that describes GMSL camera connected to - * Fakra connectors for the Eagle V3M and Condor V3H (and compatible) boards. - * - * The following cameras are currently supported: RDACM20 and RDACM21. - * - * The board .dts file that include this has to select which cameras are in use - * by specifying the camera model with: - * - * #define GMSL_CAMERA_RDACM20 - * or - * #define GMSL_CAMERA_RDACM21 - * - * And which cameras are connected to the board by defining: - * for GMSL channel 0: - * #define GMSL_CAMERA_0 - * #define GMSL_CAMERA_1 - * #define GMSL_CAMERA_2 - * #define GMSL_CAMERA_3 - * - * for GMSL channel 1: - * #define GMSL_CAMERA_4 - * #define GMSL_CAMERA_5 - * #define GMSL_CAMERA_6 - * #define GMSL_CAMERA_7 - */ - -#include <dt-bindings/gpio/gpio.h> - -/* Validate the board file settings. */ -#if !defined(GMSL_CAMERA_RDACM20) && !defined(GMSL_CAMERA_RDACM21) -#error "Camera model should be defined by the board file" -#endif - -#if defined(GMSL_CAMERA_RDACM20) && defined(GMSL_CAMERA_RDACM21) -#error "A single camera model should be selected" -#endif - -#if !defined(GMSL_CAMERA_0) && !defined(GMSL_CAMERA_1) && \ - !defined(GMSL_CAMERA_2) && !defined(GMSL_CAMERA_3) && \ - !defined(GMSL_CAMERA_4) && !defined(GMSL_CAMERA_5) && \ - !defined(GMSL_CAMERA_6) && !defined(GMSL_CAMERA_7) -#error "At least one camera should be selected" -#endif - -/* Deduce from the enabled cameras which GMSL channels are active. */ -#if defined(GMSL_CAMERA_0) || defined(GMSL_CAMERA_1) || \ - defined(GMSL_CAMERA_2) || defined(GMSL_CAMERA_3) -#define GMSL_0 -#endif - -#if defined(GMSL_CAMERA_4) || defined(GMSL_CAMERA_5) || \ - defined(GMSL_CAMERA_6) || defined(GMSL_CAMERA_7) -#define GMSL_1 -#endif - -/* Deduce the camera model compatible string. */ -#if defined(GMSL_CAMERA_RDACM20) -#define GMSL_CAMERA_MODEL "imi,rdacm20" -#elif defined(GMSL_CAMERA_RDACM21) -#define GMSL_CAMERA_MODEL "imi,rdacm21" -#endif - -#ifdef GMSL_0 -&vin0 { - status = "okay"; -}; - -&vin1 { - status = "okay"; -}; - -&vin2 { - status = "okay"; -}; - -&vin3 { - status = "okay"; -}; - -&gmsl0 { - status = "okay"; - -#if defined(GMSL_CAMERA_RDACM21) - maxim,reverse-channel-microvolt = <100000>; -#endif - - ports { -#ifdef GMSL_CAMERA_0 - port@0 { - max9286_in0: endpoint { - remote-endpoint = <&fakra_con0>; - }; - }; -#endif - -#ifdef GMSL_CAMERA_1 - port@1 { - max9286_in1: endpoint { - remote-endpoint = <&fakra_con1>; - }; - - }; -#endif - -#ifdef GMSL_CAMERA_2 - port@2 { - max9286_in2: endpoint { - remote-endpoint = <&fakra_con2>; - }; - - }; -#endif - -#ifdef GMSL_CAMERA_3 - port@3 { - max9286_in3: endpoint { - remote-endpoint = <&fakra_con3>; - }; - - }; -#endif - }; - - i2c-mux { -#ifdef GMSL_CAMERA_0 - i2c@0 { - status = "okay"; - - camera@51 { - compatible = GMSL_CAMERA_MODEL; - reg = <0x51>, <0x61>; - - port { - fakra_con0: endpoint { - remote-endpoint = <&max9286_in0>; - }; - }; - }; - }; -#endif - -#ifdef GMSL_CAMERA_1 - i2c@1 { - status = "okay"; - - camera@52 { - compatible = GMSL_CAMERA_MODEL; - reg = <0x52>, <0x62>; - - port { - fakra_con1: endpoint { - remote-endpoint = <&max9286_in1>; - }; - }; - }; - }; -#endif - -#ifdef GMSL_CAMERA_2 - i2c@2 { - status = "okay"; - - camera@53 { - compatible = GMSL_CAMERA_MODEL; - reg = <0x53>, <0x63>; - - port { - fakra_con2: endpoint { - remote-endpoint = <&max9286_in2>; - }; - }; - }; - }; -#endif - -#ifdef GMSL_CAMERA_3 - i2c@3 { - status = "okay"; - - camera@54 { - compatible = GMSL_CAMERA_MODEL; - reg = <0x54>, <0x64>; - - port { - fakra_con3: endpoint { - remote-endpoint = <&max9286_in3>; - }; - }; - }; - }; -#endif - }; -}; -#endif /* ifdef GMSL_0 */ - -#ifdef GMSL_1 -&vin4 { - status = "okay"; -}; - -&vin5 { - status = "okay"; -}; - -&vin6 { - status = "okay"; -}; - -&vin7 { - status = "okay"; -}; - -&gmsl1 { - status = "okay"; - -#if defined(GMSL_CAMERA_RDACM21) - maxim,reverse-channel-microvolt = <100000>; -#endif - - ports { -#ifdef GMSL_CAMERA_4 - port@0 { - max9286_in4: endpoint { - remote-endpoint = <&fakra_con4>; - }; - }; -#endif - -#ifdef GMSL_CAMERA_5 - port@1 { - max9286_in5: endpoint { - remote-endpoint = <&fakra_con5>; - }; - - }; -#endif - -#ifdef GMSL_CAMERA_6 - port@2 { - max9286_in6: endpoint { - remote-endpoint = <&fakra_con6>; - }; - - }; -#endif - -#ifdef GMSL_CAMERA_7 - port@3 { - max9286_in7: endpoint { - remote-endpoint = <&fakra_con7>; - }; - - }; -#endif - }; - - i2c-mux { -#ifdef GMSL_CAMERA_4 - i2c@0 { - status = "okay"; - - camera@55 { - compatible = GMSL_CAMERA_MODEL; - reg = <0x55>, <0x65>; - - port { - fakra_con4: endpoint { - remote-endpoint = <&max9286_in4>; - }; - }; - }; - }; -#endif - -#ifdef GMSL_CAMERA_5 - i2c@1 { - status = "okay"; - - camera@56 { - compatible = GMSL_CAMERA_MODEL; - reg = <0x56>, <0x66>; - - port { - fakra_con5: endpoint { - remote-endpoint = <&max9286_in5>; - }; - }; - }; - }; -#endif - -#ifdef GMSL_CAMERA_6 - i2c@2 { - status = "okay"; - - camera@57 { - compatible = GMSL_CAMERA_MODEL; - reg = <0x57>, <0x67>; - - port { - fakra_con6: endpoint { - remote-endpoint = <&max9286_in6>; - }; - }; - }; - }; -#endif - -#ifdef GMSL_CAMERA_7 - i2c@3 { - status = "okay"; - - camera@58 { - compatible = GMSL_CAMERA_MODEL; - reg = <0x58>, <0x68>; - - port { - fakra_con7: endpoint { - remote-endpoint = <&max9286_in7>; - }; - }; - }; - }; -#endif - }; -}; -#endif /* ifdef GMSL_1 */ diff --git a/arch/arm64/boot/dts/renesas/hihope-rev4.dtsi b/arch/arm64/boot/dts/renesas/hihope-rev4.dtsi index deb69c272775..8bfc66b8ef86 100644 --- a/arch/arm64/boot/dts/renesas/hihope-rev4.dtsi +++ b/arch/arm64/boot/dts/renesas/hihope-rev4.dtsi @@ -50,7 +50,7 @@ pinctrl-names = "default"; status = "okay"; - cs2000: clk_multiplier@4f { + cs2000: clk-multiplier@4f { #clock-cells = <0>; compatible = "cirrus,cs2000-cp"; reg = <0x4f>; diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index f0729a482cef..36675f5bcdea 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -1901,7 +1901,7 @@ dma-names = "rx", "tx"; }; ssiu04: ssiu-4 { - dmas = <&audma0 0x3F>, <&audma1 0x40>; + dmas = <&audma0 0x3f>, <&audma1 0x40>; dma-names = "rx", "tx"; }; ssiu05: ssiu-5 { @@ -1909,7 +1909,7 @@ dma-names = "rx", "tx"; }; ssiu06: ssiu-6 { - dmas = <&audma0 0x4F>, <&audma1 0x50>; + dmas = <&audma0 0x4f>, <&audma1 0x50>; dma-names = "rx", "tx"; }; ssiu07: ssiu-7 { @@ -1921,7 +1921,7 @@ dma-names = "rx", "tx"; }; ssiu11: ssiu-9 { - dmas = <&audma0 0x4B>, <&audma1 0x4C>; + dmas = <&audma0 0x4b>, <&audma1 0x4c>; dma-names = "rx", "tx"; }; ssiu12: ssiu-10 { @@ -1929,23 +1929,23 @@ dma-names = "rx", "tx"; }; ssiu13: ssiu-11 { - dmas = <&audma0 0x59>, <&audma1 0x5A>; + dmas = <&audma0 0x59>, <&audma1 0x5a>; dma-names = "rx", "tx"; }; ssiu14: ssiu-12 { - dmas = <&audma0 0x5F>, <&audma1 0x60>; + dmas = <&audma0 0x5f>, <&audma1 0x60>; dma-names = "rx", "tx"; }; ssiu15: ssiu-13 { - dmas = <&audma0 0xC3>, <&audma1 0xC4>; + dmas = <&audma0 0xc3>, <&audma1 0xc4>; dma-names = "rx", "tx"; }; ssiu16: ssiu-14 { - dmas = <&audma0 0xC7>, <&audma1 0xC8>; + dmas = <&audma0 0xc7>, <&audma1 0xc8>; dma-names = "rx", "tx"; }; ssiu17: ssiu-15 { - dmas = <&audma0 0xCB>, <&audma1 0xCC>; + dmas = <&audma0 0xcb>, <&audma1 0xcc>; dma-names = "rx", "tx"; }; ssiu20: ssiu-16 { @@ -1957,27 +1957,27 @@ dma-names = "rx", "tx"; }; ssiu22: ssiu-18 { - dmas = <&audma0 0x6B>, <&audma1 0x6C>; + dmas = <&audma0 0x6b>, <&audma1 0x6c>; dma-names = "rx", "tx"; }; ssiu23: ssiu-19 { - dmas = <&audma0 0x6D>, <&audma1 0x6E>; + dmas = <&audma0 0x6d>, <&audma1 0x6e>; dma-names = "rx", "tx"; }; ssiu24: ssiu-20 { - dmas = <&audma0 0xCF>, <&audma1 0xCE>; + dmas = <&audma0 0xcf>, <&audma1 0xce>; dma-names = "rx", "tx"; }; ssiu25: ssiu-21 { - dmas = <&audma0 0xEB>, <&audma1 0xEC>; + dmas = <&audma0 0xeb>, <&audma1 0xec>; dma-names = "rx", "tx"; }; ssiu26: ssiu-22 { - dmas = <&audma0 0xED>, <&audma1 0xEE>; + dmas = <&audma0 0xed>, <&audma1 0xee>; dma-names = "rx", "tx"; }; ssiu27: ssiu-23 { - dmas = <&audma0 0xEF>, <&audma1 0xF0>; + dmas = <&audma0 0xef>, <&audma1 0xf0>; dma-names = "rx", "tx"; }; ssiu30: ssiu-24 { @@ -2001,15 +2001,15 @@ dma-names = "rx", "tx"; }; ssiu35: ssiu-29 { - dmas = <&audma0 0x29>, <&audma1 0x2A>; + dmas = <&audma0 0x29>, <&audma1 0x2a>; dma-names = "rx", "tx"; }; ssiu36: ssiu-30 { - dmas = <&audma0 0x2B>, <&audma1 0x2C>; + dmas = <&audma0 0x2b>, <&audma1 0x2c>; dma-names = "rx", "tx"; }; ssiu37: ssiu-31 { - dmas = <&audma0 0x2D>, <&audma1 0x2E>; + dmas = <&audma0 0x2d>, <&audma1 0x2e>; dma-names = "rx", "tx"; }; ssiu40: ssiu-32 { @@ -2021,19 +2021,19 @@ dma-names = "rx", "tx"; }; ssiu42: ssiu-34 { - dmas = <&audma0 0x19>, <&audma1 0x1A>; + dmas = <&audma0 0x19>, <&audma1 0x1a>; dma-names = "rx", "tx"; }; ssiu43: ssiu-35 { - dmas = <&audma0 0x1B>, <&audma1 0x1C>; + dmas = <&audma0 0x1b>, <&audma1 0x1c>; dma-names = "rx", "tx"; }; ssiu44: ssiu-36 { - dmas = <&audma0 0x1D>, <&audma1 0x1E>; + dmas = <&audma0 0x1d>, <&audma1 0x1e>; dma-names = "rx", "tx"; }; ssiu45: ssiu-37 { - dmas = <&audma0 0x1F>, <&audma1 0x20>; + dmas = <&audma0 0x1f>, <&audma1 0x20>; dma-names = "rx", "tx"; }; ssiu46: ssiu-38 { @@ -2065,7 +2065,7 @@ dma-names = "rx", "tx"; }; ssiu91: ssiu-45 { - dmas = <&audma0 0x7F>, <&audma1 0x80>; + dmas = <&audma0 0x7f>, <&audma1 0x80>; dma-names = "rx", "tx"; }; ssiu92: ssiu-46 { @@ -2077,19 +2077,19 @@ dma-names = "rx", "tx"; }; ssiu94: ssiu-48 { - dmas = <&audma0 0xA3>, <&audma1 0xA4>; + dmas = <&audma0 0xa3>, <&audma1 0xa4>; dma-names = "rx", "tx"; }; ssiu95: ssiu-49 { - dmas = <&audma0 0xA5>, <&audma1 0xA6>; + dmas = <&audma0 0xa5>, <&audma1 0xa6>; dma-names = "rx", "tx"; }; ssiu96: ssiu-50 { - dmas = <&audma0 0xA7>, <&audma1 0xA8>; + dmas = <&audma0 0xa7>, <&audma1 0xa8>; dma-names = "rx", "tx"; }; ssiu97: ssiu-51 { - dmas = <&audma0 0xA9>, <&audma1 0xAA>; + dmas = <&audma0 0xa9>, <&audma1 0xaa>; dma-names = "rx", "tx"; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index c9857ea944ed..ceef0104f75e 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -1785,7 +1785,7 @@ dma-names = "rx", "tx"; }; ssiu04: ssiu-4 { - dmas = <&audma0 0x3F>, <&audma1 0x40>; + dmas = <&audma0 0x3f>, <&audma1 0x40>; dma-names = "rx", "tx"; }; ssiu05: ssiu-5 { @@ -1793,7 +1793,7 @@ dma-names = "rx", "tx"; }; ssiu06: ssiu-6 { - dmas = <&audma0 0x4F>, <&audma1 0x50>; + dmas = <&audma0 0x4f>, <&audma1 0x50>; dma-names = "rx", "tx"; }; ssiu07: ssiu-7 { @@ -1805,7 +1805,7 @@ dma-names = "rx", "tx"; }; ssiu11: ssiu-9 { - dmas = <&audma0 0x4B>, <&audma1 0x4C>; + dmas = <&audma0 0x4b>, <&audma1 0x4c>; dma-names = "rx", "tx"; }; ssiu12: ssiu-10 { @@ -1813,23 +1813,23 @@ dma-names = "rx", "tx"; }; ssiu13: ssiu-11 { - dmas = <&audma0 0x59>, <&audma1 0x5A>; + dmas = <&audma0 0x59>, <&audma1 0x5a>; dma-names = "rx", "tx"; }; ssiu14: ssiu-12 { - dmas = <&audma0 0x5F>, <&audma1 0x60>; + dmas = <&audma0 0x5f>, <&audma1 0x60>; dma-names = "rx", "tx"; }; ssiu15: ssiu-13 { - dmas = <&audma0 0xC3>, <&audma1 0xC4>; + dmas = <&audma0 0xc3>, <&audma1 0xc4>; dma-names = "rx", "tx"; }; ssiu16: ssiu-14 { - dmas = <&audma0 0xC7>, <&audma1 0xC8>; + dmas = <&audma0 0xc7>, <&audma1 0xc8>; dma-names = "rx", "tx"; }; ssiu17: ssiu-15 { - dmas = <&audma0 0xCB>, <&audma1 0xCC>; + dmas = <&audma0 0xcb>, <&audma1 0xcc>; dma-names = "rx", "tx"; }; ssiu20: ssiu-16 { @@ -1841,27 +1841,27 @@ dma-names = "rx", "tx"; }; ssiu22: ssiu-18 { - dmas = <&audma0 0x6B>, <&audma1 0x6C>; + dmas = <&audma0 0x6b>, <&audma1 0x6c>; dma-names = "rx", "tx"; }; ssiu23: ssiu-19 { - dmas = <&audma0 0x6D>, <&audma1 0x6E>; + dmas = <&audma0 0x6d>, <&audma1 0x6e>; dma-names = "rx", "tx"; }; ssiu24: ssiu-20 { - dmas = <&audma0 0xCF>, <&audma1 0xCE>; + dmas = <&audma0 0xcf>, <&audma1 0xce>; dma-names = "rx", "tx"; }; ssiu25: ssiu-21 { - dmas = <&audma0 0xEB>, <&audma1 0xEC>; + dmas = <&audma0 0xeb>, <&audma1 0xec>; dma-names = "rx", "tx"; }; ssiu26: ssiu-22 { - dmas = <&audma0 0xED>, <&audma1 0xEE>; + dmas = <&audma0 0xed>, <&audma1 0xee>; dma-names = "rx", "tx"; }; ssiu27: ssiu-23 { - dmas = <&audma0 0xEF>, <&audma1 0xF0>; + dmas = <&audma0 0xef>, <&audma1 0xf0>; dma-names = "rx", "tx"; }; ssiu30: ssiu-24 { @@ -1885,15 +1885,15 @@ dma-names = "rx", "tx"; }; ssiu35: ssiu-29 { - dmas = <&audma0 0x29>, <&audma1 0x2A>; + dmas = <&audma0 0x29>, <&audma1 0x2a>; dma-names = "rx", "tx"; }; ssiu36: ssiu-30 { - dmas = <&audma0 0x2B>, <&audma1 0x2C>; + dmas = <&audma0 0x2b>, <&audma1 0x2c>; dma-names = "rx", "tx"; }; ssiu37: ssiu-31 { - dmas = <&audma0 0x2D>, <&audma1 0x2E>; + dmas = <&audma0 0x2d>, <&audma1 0x2e>; dma-names = "rx", "tx"; }; ssiu40: ssiu-32 { @@ -1905,19 +1905,19 @@ dma-names = "rx", "tx"; }; ssiu42: ssiu-34 { - dmas = <&audma0 0x19>, <&audma1 0x1A>; + dmas = <&audma0 0x19>, <&audma1 0x1a>; dma-names = "rx", "tx"; }; ssiu43: ssiu-35 { - dmas = <&audma0 0x1B>, <&audma1 0x1C>; + dmas = <&audma0 0x1b>, <&audma1 0x1c>; dma-names = "rx", "tx"; }; ssiu44: ssiu-36 { - dmas = <&audma0 0x1D>, <&audma1 0x1E>; + dmas = <&audma0 0x1d>, <&audma1 0x1e>; dma-names = "rx", "tx"; }; ssiu45: ssiu-37 { - dmas = <&audma0 0x1F>, <&audma1 0x20>; + dmas = <&audma0 0x1f>, <&audma1 0x20>; dma-names = "rx", "tx"; }; ssiu46: ssiu-38 { @@ -1949,7 +1949,7 @@ dma-names = "rx", "tx"; }; ssiu91: ssiu-45 { - dmas = <&audma0 0x7F>, <&audma1 0x80>; + dmas = <&audma0 0x7f>, <&audma1 0x80>; dma-names = "rx", "tx"; }; ssiu92: ssiu-46 { @@ -1961,19 +1961,19 @@ dma-names = "rx", "tx"; }; ssiu94: ssiu-48 { - dmas = <&audma0 0xA3>, <&audma1 0xA4>; + dmas = <&audma0 0xa3>, <&audma1 0xa4>; dma-names = "rx", "tx"; }; ssiu95: ssiu-49 { - dmas = <&audma0 0xA5>, <&audma1 0xA6>; + dmas = <&audma0 0xa5>, <&audma1 0xa6>; dma-names = "rx", "tx"; }; ssiu96: ssiu-50 { - dmas = <&audma0 0xA7>, <&audma1 0xA8>; + dmas = <&audma0 0xa7>, <&audma1 0xa8>; dma-names = "rx", "tx"; }; ssiu97: ssiu-51 { - dmas = <&audma0 0xA9>, <&audma1 0xAA>; + dmas = <&audma0 0xa9>, <&audma1 0xaa>; dma-names = "rx", "tx"; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 52920a6bf592..9df5f1a42400 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -1944,7 +1944,7 @@ dma-names = "rx", "tx"; }; ssiu04: ssiu-4 { - dmas = <&audma0 0x3F>, <&audma1 0x40>; + dmas = <&audma0 0x3f>, <&audma1 0x40>; dma-names = "rx", "tx"; }; ssiu05: ssiu-5 { @@ -1952,7 +1952,7 @@ dma-names = "rx", "tx"; }; ssiu06: ssiu-6 { - dmas = <&audma0 0x4F>, <&audma1 0x50>; + dmas = <&audma0 0x4f>, <&audma1 0x50>; dma-names = "rx", "tx"; }; ssiu07: ssiu-7 { @@ -1964,7 +1964,7 @@ dma-names = "rx", "tx"; }; ssiu11: ssiu-9 { - dmas = <&audma0 0x4B>, <&audma1 0x4C>; + dmas = <&audma0 0x4b>, <&audma1 0x4c>; dma-names = "rx", "tx"; }; ssiu12: ssiu-10 { @@ -1972,23 +1972,23 @@ dma-names = "rx", "tx"; }; ssiu13: ssiu-11 { - dmas = <&audma0 0x59>, <&audma1 0x5A>; + dmas = <&audma0 0x59>, <&audma1 0x5a>; dma-names = "rx", "tx"; }; ssiu14: ssiu-12 { - dmas = <&audma0 0x5F>, <&audma1 0x60>; + dmas = <&audma0 0x5f>, <&audma1 0x60>; dma-names = "rx", "tx"; }; ssiu15: ssiu-13 { - dmas = <&audma0 0xC3>, <&audma1 0xC4>; + dmas = <&audma0 0xc3>, <&audma1 0xc4>; dma-names = "rx", "tx"; }; ssiu16: ssiu-14 { - dmas = <&audma0 0xC7>, <&audma1 0xC8>; + dmas = <&audma0 0xc7>, <&audma1 0xc8>; dma-names = "rx", "tx"; }; ssiu17: ssiu-15 { - dmas = <&audma0 0xCB>, <&audma1 0xCC>; + dmas = <&audma0 0xcb>, <&audma1 0xcc>; dma-names = "rx", "tx"; }; ssiu20: ssiu-16 { @@ -2000,27 +2000,27 @@ dma-names = "rx", "tx"; }; ssiu22: ssiu-18 { - dmas = <&audma0 0x6B>, <&audma1 0x6C>; + dmas = <&audma0 0x6b>, <&audma1 0x6c>; dma-names = "rx", "tx"; }; ssiu23: ssiu-19 { - dmas = <&audma0 0x6D>, <&audma1 0x6E>; + dmas = <&audma0 0x6d>, <&audma1 0x6e>; dma-names = "rx", "tx"; }; ssiu24: ssiu-20 { - dmas = <&audma0 0xCF>, <&audma1 0xCE>; + dmas = <&audma0 0xcf>, <&audma1 0xce>; dma-names = "rx", "tx"; }; ssiu25: ssiu-21 { - dmas = <&audma0 0xEB>, <&audma1 0xEC>; + dmas = <&audma0 0xeb>, <&audma1 0xec>; dma-names = "rx", "tx"; }; ssiu26: ssiu-22 { - dmas = <&audma0 0xED>, <&audma1 0xEE>; + dmas = <&audma0 0xed>, <&audma1 0xee>; dma-names = "rx", "tx"; }; ssiu27: ssiu-23 { - dmas = <&audma0 0xEF>, <&audma1 0xF0>; + dmas = <&audma0 0xef>, <&audma1 0xf0>; dma-names = "rx", "tx"; }; ssiu30: ssiu-24 { @@ -2044,15 +2044,15 @@ dma-names = "rx", "tx"; }; ssiu35: ssiu-29 { - dmas = <&audma0 0x29>, <&audma1 0x2A>; + dmas = <&audma0 0x29>, <&audma1 0x2a>; dma-names = "rx", "tx"; }; ssiu36: ssiu-30 { - dmas = <&audma0 0x2B>, <&audma1 0x2C>; + dmas = <&audma0 0x2b>, <&audma1 0x2c>; dma-names = "rx", "tx"; }; ssiu37: ssiu-31 { - dmas = <&audma0 0x2D>, <&audma1 0x2E>; + dmas = <&audma0 0x2d>, <&audma1 0x2e>; dma-names = "rx", "tx"; }; ssiu40: ssiu-32 { @@ -2064,19 +2064,19 @@ dma-names = "rx", "tx"; }; ssiu42: ssiu-34 { - dmas = <&audma0 0x19>, <&audma1 0x1A>; + dmas = <&audma0 0x19>, <&audma1 0x1a>; dma-names = "rx", "tx"; }; ssiu43: ssiu-35 { - dmas = <&audma0 0x1B>, <&audma1 0x1C>; + dmas = <&audma0 0x1b>, <&audma1 0x1c>; dma-names = "rx", "tx"; }; ssiu44: ssiu-36 { - dmas = <&audma0 0x1D>, <&audma1 0x1E>; + dmas = <&audma0 0x1d>, <&audma1 0x1e>; dma-names = "rx", "tx"; }; ssiu45: ssiu-37 { - dmas = <&audma0 0x1F>, <&audma1 0x20>; + dmas = <&audma0 0x1f>, <&audma1 0x20>; dma-names = "rx", "tx"; }; ssiu46: ssiu-38 { @@ -2108,7 +2108,7 @@ dma-names = "rx", "tx"; }; ssiu91: ssiu-45 { - dmas = <&audma0 0x7F>, <&audma1 0x80>; + dmas = <&audma0 0x7f>, <&audma1 0x80>; dma-names = "rx", "tx"; }; ssiu92: ssiu-46 { @@ -2120,19 +2120,19 @@ dma-names = "rx", "tx"; }; ssiu94: ssiu-48 { - dmas = <&audma0 0xA3>, <&audma1 0xA4>; + dmas = <&audma0 0xa3>, <&audma1 0xa4>; dma-names = "rx", "tx"; }; ssiu95: ssiu-49 { - dmas = <&audma0 0xA5>, <&audma1 0xA6>; + dmas = <&audma0 0xa5>, <&audma1 0xa6>; dma-names = "rx", "tx"; }; ssiu96: ssiu-50 { - dmas = <&audma0 0xA7>, <&audma1 0xA8>; + dmas = <&audma0 0xa7>, <&audma1 0xa8>; dma-names = "rx", "tx"; }; ssiu97: ssiu-51 { - dmas = <&audma0 0xA9>, <&audma1 0xAA>; + dmas = <&audma0 0xa9>, <&audma1 0xaa>; dma-names = "rx", "tx"; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi index 9ad700bde4ba..607f62a448d8 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi @@ -2176,7 +2176,7 @@ dma-names = "rx", "tx"; }; ssiu04: ssiu-4 { - dmas = <&audma0 0x3F>, <&audma1 0x40>; + dmas = <&audma0 0x3f>, <&audma1 0x40>; dma-names = "rx", "tx"; }; ssiu05: ssiu-5 { @@ -2184,7 +2184,7 @@ dma-names = "rx", "tx"; }; ssiu06: ssiu-6 { - dmas = <&audma0 0x4F>, <&audma1 0x50>; + dmas = <&audma0 0x4f>, <&audma1 0x50>; dma-names = "rx", "tx"; }; ssiu07: ssiu-7 { @@ -2196,7 +2196,7 @@ dma-names = "rx", "tx"; }; ssiu11: ssiu-9 { - dmas = <&audma0 0x4B>, <&audma1 0x4C>; + dmas = <&audma0 0x4b>, <&audma1 0x4c>; dma-names = "rx", "tx"; }; ssiu12: ssiu-10 { @@ -2204,23 +2204,23 @@ dma-names = "rx", "tx"; }; ssiu13: ssiu-11 { - dmas = <&audma0 0x59>, <&audma1 0x5A>; + dmas = <&audma0 0x59>, <&audma1 0x5a>; dma-names = "rx", "tx"; }; ssiu14: ssiu-12 { - dmas = <&audma0 0x5F>, <&audma1 0x60>; + dmas = <&audma0 0x5f>, <&audma1 0x60>; dma-names = "rx", "tx"; }; ssiu15: ssiu-13 { - dmas = <&audma0 0xC3>, <&audma1 0xC4>; + dmas = <&audma0 0xc3>, <&audma1 0xc4>; dma-names = "rx", "tx"; }; ssiu16: ssiu-14 { - dmas = <&audma0 0xC7>, <&audma1 0xC8>; + dmas = <&audma0 0xc7>, <&audma1 0xc8>; dma-names = "rx", "tx"; }; ssiu17: ssiu-15 { - dmas = <&audma0 0xCB>, <&audma1 0xCC>; + dmas = <&audma0 0xcb>, <&audma1 0xcc>; dma-names = "rx", "tx"; }; ssiu20: ssiu-16 { @@ -2232,27 +2232,27 @@ dma-names = "rx", "tx"; }; ssiu22: ssiu-18 { - dmas = <&audma0 0x6B>, <&audma1 0x6C>; + dmas = <&audma0 0x6b>, <&audma1 0x6c>; dma-names = "rx", "tx"; }; ssiu23: ssiu-19 { - dmas = <&audma0 0x6D>, <&audma1 0x6E>; + dmas = <&audma0 0x6d>, <&audma1 0x6e>; dma-names = "rx", "tx"; }; ssiu24: ssiu-20 { - dmas = <&audma0 0xCF>, <&audma1 0xCE>; + dmas = <&audma0 0xcf>, <&audma1 0xce>; dma-names = "rx", "tx"; }; ssiu25: ssiu-21 { - dmas = <&audma0 0xEB>, <&audma1 0xEC>; + dmas = <&audma0 0xeb>, <&audma1 0xec>; dma-names = "rx", "tx"; }; ssiu26: ssiu-22 { - dmas = <&audma0 0xED>, <&audma1 0xEE>; + dmas = <&audma0 0xed>, <&audma1 0xee>; dma-names = "rx", "tx"; }; ssiu27: ssiu-23 { - dmas = <&audma0 0xEF>, <&audma1 0xF0>; + dmas = <&audma0 0xef>, <&audma1 0xf0>; dma-names = "rx", "tx"; }; ssiu30: ssiu-24 { @@ -2276,15 +2276,15 @@ dma-names = "rx", "tx"; }; ssiu35: ssiu-29 { - dmas = <&audma0 0x29>, <&audma1 0x2A>; + dmas = <&audma0 0x29>, <&audma1 0x2a>; dma-names = "rx", "tx"; }; ssiu36: ssiu-30 { - dmas = <&audma0 0x2B>, <&audma1 0x2C>; + dmas = <&audma0 0x2b>, <&audma1 0x2c>; dma-names = "rx", "tx"; }; ssiu37: ssiu-31 { - dmas = <&audma0 0x2D>, <&audma1 0x2E>; + dmas = <&audma0 0x2d>, <&audma1 0x2e>; dma-names = "rx", "tx"; }; ssiu40: ssiu-32 { @@ -2296,19 +2296,19 @@ dma-names = "rx", "tx"; }; ssiu42: ssiu-34 { - dmas = <&audma0 0x19>, <&audma1 0x1A>; + dmas = <&audma0 0x19>, <&audma1 0x1a>; dma-names = "rx", "tx"; }; ssiu43: ssiu-35 { - dmas = <&audma0 0x1B>, <&audma1 0x1C>; + dmas = <&audma0 0x1b>, <&audma1 0x1c>; dma-names = "rx", "tx"; }; ssiu44: ssiu-36 { - dmas = <&audma0 0x1D>, <&audma1 0x1E>; + dmas = <&audma0 0x1d>, <&audma1 0x1e>; dma-names = "rx", "tx"; }; ssiu45: ssiu-37 { - dmas = <&audma0 0x1F>, <&audma1 0x20>; + dmas = <&audma0 0x1f>, <&audma1 0x20>; dma-names = "rx", "tx"; }; ssiu46: ssiu-38 { @@ -2340,7 +2340,7 @@ dma-names = "rx", "tx"; }; ssiu91: ssiu-45 { - dmas = <&audma0 0x7F>, <&audma1 0x80>; + dmas = <&audma0 0x7f>, <&audma1 0x80>; dma-names = "rx", "tx"; }; ssiu92: ssiu-46 { @@ -2352,19 +2352,19 @@ dma-names = "rx", "tx"; }; ssiu94: ssiu-48 { - dmas = <&audma0 0xA3>, <&audma1 0xA4>; + dmas = <&audma0 0xa3>, <&audma1 0xa4>; dma-names = "rx", "tx"; }; ssiu95: ssiu-49 { - dmas = <&audma0 0xA5>, <&audma1 0xA6>; + dmas = <&audma0 0xa5>, <&audma1 0xa6>; dma-names = "rx", "tx"; }; ssiu96: ssiu-50 { - dmas = <&audma0 0xA7>, <&audma1 0xA8>; + dmas = <&audma0 0xa7>, <&audma1 0xa8>; dma-names = "rx", "tx"; }; ssiu97: ssiu-51 { - dmas = <&audma0 0xA9>, <&audma1 0xAA>; + dmas = <&audma0 0xa9>, <&audma1 0xaa>; dma-names = "rx", "tx"; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index e03b1f7cbfd6..e64c7b1aebc4 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -2101,7 +2101,7 @@ dma-names = "rx", "tx"; }; ssiu04: ssiu-4 { - dmas = <&audma0 0x3F>, <&audma1 0x40>; + dmas = <&audma0 0x3f>, <&audma1 0x40>; dma-names = "rx", "tx"; }; ssiu05: ssiu-5 { @@ -2109,7 +2109,7 @@ dma-names = "rx", "tx"; }; ssiu06: ssiu-6 { - dmas = <&audma0 0x4F>, <&audma1 0x50>; + dmas = <&audma0 0x4f>, <&audma1 0x50>; dma-names = "rx", "tx"; }; ssiu07: ssiu-7 { @@ -2121,7 +2121,7 @@ dma-names = "rx", "tx"; }; ssiu11: ssiu-9 { - dmas = <&audma0 0x4B>, <&audma1 0x4C>; + dmas = <&audma0 0x4b>, <&audma1 0x4c>; dma-names = "rx", "tx"; }; ssiu12: ssiu-10 { @@ -2129,23 +2129,23 @@ dma-names = "rx", "tx"; }; ssiu13: ssiu-11 { - dmas = <&audma0 0x59>, <&audma1 0x5A>; + dmas = <&audma0 0x59>, <&audma1 0x5a>; dma-names = "rx", "tx"; }; ssiu14: ssiu-12 { - dmas = <&audma0 0x5F>, <&audma1 0x60>; + dmas = <&audma0 0x5f>, <&audma1 0x60>; dma-names = "rx", "tx"; }; ssiu15: ssiu-13 { - dmas = <&audma0 0xC3>, <&audma1 0xC4>; + dmas = <&audma0 0xc3>, <&audma1 0xc4>; dma-names = "rx", "tx"; }; ssiu16: ssiu-14 { - dmas = <&audma0 0xC7>, <&audma1 0xC8>; + dmas = <&audma0 0xc7>, <&audma1 0xc8>; dma-names = "rx", "tx"; }; ssiu17: ssiu-15 { - dmas = <&audma0 0xCB>, <&audma1 0xCC>; + dmas = <&audma0 0xcb>, <&audma1 0xcc>; dma-names = "rx", "tx"; }; ssiu20: ssiu-16 { @@ -2157,27 +2157,27 @@ dma-names = "rx", "tx"; }; ssiu22: ssiu-18 { - dmas = <&audma0 0x6B>, <&audma1 0x6C>; + dmas = <&audma0 0x6b>, <&audma1 0x6c>; dma-names = "rx", "tx"; }; ssiu23: ssiu-19 { - dmas = <&audma0 0x6D>, <&audma1 0x6E>; + dmas = <&audma0 0x6d>, <&audma1 0x6e>; dma-names = "rx", "tx"; }; ssiu24: ssiu-20 { - dmas = <&audma0 0xCF>, <&audma1 0xCE>; + dmas = <&audma0 0xcf>, <&audma1 0xce>; dma-names = "rx", "tx"; }; ssiu25: ssiu-21 { - dmas = <&audma0 0xEB>, <&audma1 0xEC>; + dmas = <&audma0 0xeb>, <&audma1 0xec>; dma-names = "rx", "tx"; }; ssiu26: ssiu-22 { - dmas = <&audma0 0xED>, <&audma1 0xEE>; + dmas = <&audma0 0xed>, <&audma1 0xee>; dma-names = "rx", "tx"; }; ssiu27: ssiu-23 { - dmas = <&audma0 0xEF>, <&audma1 0xF0>; + dmas = <&audma0 0xef>, <&audma1 0xf0>; dma-names = "rx", "tx"; }; ssiu30: ssiu-24 { @@ -2201,15 +2201,15 @@ dma-names = "rx", "tx"; }; ssiu35: ssiu-29 { - dmas = <&audma0 0x29>, <&audma1 0x2A>; + dmas = <&audma0 0x29>, <&audma1 0x2a>; dma-names = "rx", "tx"; }; ssiu36: ssiu-30 { - dmas = <&audma0 0x2B>, <&audma1 0x2C>; + dmas = <&audma0 0x2b>, <&audma1 0x2c>; dma-names = "rx", "tx"; }; ssiu37: ssiu-31 { - dmas = <&audma0 0x2D>, <&audma1 0x2E>; + dmas = <&audma0 0x2d>, <&audma1 0x2e>; dma-names = "rx", "tx"; }; ssiu40: ssiu-32 { @@ -2221,19 +2221,19 @@ dma-names = "rx", "tx"; }; ssiu42: ssiu-34 { - dmas = <&audma0 0x19>, <&audma1 0x1A>; + dmas = <&audma0 0x19>, <&audma1 0x1a>; dma-names = "rx", "tx"; }; ssiu43: ssiu-35 { - dmas = <&audma0 0x1B>, <&audma1 0x1C>; + dmas = <&audma0 0x1b>, <&audma1 0x1c>; dma-names = "rx", "tx"; }; ssiu44: ssiu-36 { - dmas = <&audma0 0x1D>, <&audma1 0x1E>; + dmas = <&audma0 0x1d>, <&audma1 0x1e>; dma-names = "rx", "tx"; }; ssiu45: ssiu-37 { - dmas = <&audma0 0x1F>, <&audma1 0x20>; + dmas = <&audma0 0x1f>, <&audma1 0x20>; dma-names = "rx", "tx"; }; ssiu46: ssiu-38 { @@ -2265,7 +2265,7 @@ dma-names = "rx", "tx"; }; ssiu91: ssiu-45 { - dmas = <&audma0 0x7F>, <&audma1 0x80>; + dmas = <&audma0 0x7f>, <&audma1 0x80>; dma-names = "rx", "tx"; }; ssiu92: ssiu-46 { @@ -2277,19 +2277,19 @@ dma-names = "rx", "tx"; }; ssiu94: ssiu-48 { - dmas = <&audma0 0xA3>, <&audma1 0xA4>; + dmas = <&audma0 0xa3>, <&audma1 0xa4>; dma-names = "rx", "tx"; }; ssiu95: ssiu-49 { - dmas = <&audma0 0xA5>, <&audma1 0xA6>; + dmas = <&audma0 0xa5>, <&audma1 0xa6>; dma-names = "rx", "tx"; }; ssiu96: ssiu-50 { - dmas = <&audma0 0xA7>, <&audma1 0xA8>; + dmas = <&audma0 0xa7>, <&audma1 0xa8>; dma-names = "rx", "tx"; }; ssiu97: ssiu-51 { - dmas = <&audma0 0xA9>, <&audma1 0xAA>; + dmas = <&audma0 0xa9>, <&audma1 0xaa>; dma-names = "rx", "tx"; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index 31b11bdab69b..89f6c052c5e0 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -1981,7 +1981,7 @@ dma-names = "rx", "tx"; }; ssiu04: ssiu-4 { - dmas = <&audma0 0x3F>, <&audma1 0x40>; + dmas = <&audma0 0x3f>, <&audma1 0x40>; dma-names = "rx", "tx"; }; ssiu05: ssiu-5 { @@ -1989,7 +1989,7 @@ dma-names = "rx", "tx"; }; ssiu06: ssiu-6 { - dmas = <&audma0 0x4F>, <&audma1 0x50>; + dmas = <&audma0 0x4f>, <&audma1 0x50>; dma-names = "rx", "tx"; }; ssiu07: ssiu-7 { @@ -2001,7 +2001,7 @@ dma-names = "rx", "tx"; }; ssiu11: ssiu-9 { - dmas = <&audma0 0x4B>, <&audma1 0x4C>; + dmas = <&audma0 0x4b>, <&audma1 0x4c>; dma-names = "rx", "tx"; }; ssiu12: ssiu-10 { @@ -2009,23 +2009,23 @@ dma-names = "rx", "tx"; }; ssiu13: ssiu-11 { - dmas = <&audma0 0x59>, <&audma1 0x5A>; + dmas = <&audma0 0x59>, <&audma1 0x5a>; dma-names = "rx", "tx"; }; ssiu14: ssiu-12 { - dmas = <&audma0 0x5F>, <&audma1 0x60>; + dmas = <&audma0 0x5f>, <&audma1 0x60>; dma-names = "rx", "tx"; }; ssiu15: ssiu-13 { - dmas = <&audma0 0xC3>, <&audma1 0xC4>; + dmas = <&audma0 0xc3>, <&audma1 0xc4>; dma-names = "rx", "tx"; }; ssiu16: ssiu-14 { - dmas = <&audma0 0xC7>, <&audma1 0xC8>; + dmas = <&audma0 0xc7>, <&audma1 0xc8>; dma-names = "rx", "tx"; }; ssiu17: ssiu-15 { - dmas = <&audma0 0xCB>, <&audma1 0xCC>; + dmas = <&audma0 0xcb>, <&audma1 0xcc>; dma-names = "rx", "tx"; }; ssiu20: ssiu-16 { @@ -2037,27 +2037,27 @@ dma-names = "rx", "tx"; }; ssiu22: ssiu-18 { - dmas = <&audma0 0x6B>, <&audma1 0x6C>; + dmas = <&audma0 0x6b>, <&audma1 0x6c>; dma-names = "rx", "tx"; }; ssiu23: ssiu-19 { - dmas = <&audma0 0x6D>, <&audma1 0x6E>; + dmas = <&audma0 0x6d>, <&audma1 0x6e>; dma-names = "rx", "tx"; }; ssiu24: ssiu-20 { - dmas = <&audma0 0xCF>, <&audma1 0xCE>; + dmas = <&audma0 0xcf>, <&audma1 0xce>; dma-names = "rx", "tx"; }; ssiu25: ssiu-21 { - dmas = <&audma0 0xEB>, <&audma1 0xEC>; + dmas = <&audma0 0xeb>, <&audma1 0xec>; dma-names = "rx", "tx"; }; ssiu26: ssiu-22 { - dmas = <&audma0 0xED>, <&audma1 0xEE>; + dmas = <&audma0 0xed>, <&audma1 0xee>; dma-names = "rx", "tx"; }; ssiu27: ssiu-23 { - dmas = <&audma0 0xEF>, <&audma1 0xF0>; + dmas = <&audma0 0xef>, <&audma1 0xf0>; dma-names = "rx", "tx"; }; ssiu30: ssiu-24 { @@ -2081,15 +2081,15 @@ dma-names = "rx", "tx"; }; ssiu35: ssiu-29 { - dmas = <&audma0 0x29>, <&audma1 0x2A>; + dmas = <&audma0 0x29>, <&audma1 0x2a>; dma-names = "rx", "tx"; }; ssiu36: ssiu-30 { - dmas = <&audma0 0x2B>, <&audma1 0x2C>; + dmas = <&audma0 0x2b>, <&audma1 0x2c>; dma-names = "rx", "tx"; }; ssiu37: ssiu-31 { - dmas = <&audma0 0x2D>, <&audma1 0x2E>; + dmas = <&audma0 0x2d>, <&audma1 0x2e>; dma-names = "rx", "tx"; }; ssiu40: ssiu-32 { @@ -2101,19 +2101,19 @@ dma-names = "rx", "tx"; }; ssiu42: ssiu-34 { - dmas = <&audma0 0x19>, <&audma1 0x1A>; + dmas = <&audma0 0x19>, <&audma1 0x1a>; dma-names = "rx", "tx"; }; ssiu43: ssiu-35 { - dmas = <&audma0 0x1B>, <&audma1 0x1C>; + dmas = <&audma0 0x1b>, <&audma1 0x1c>; dma-names = "rx", "tx"; }; ssiu44: ssiu-36 { - dmas = <&audma0 0x1D>, <&audma1 0x1E>; + dmas = <&audma0 0x1d>, <&audma1 0x1e>; dma-names = "rx", "tx"; }; ssiu45: ssiu-37 { - dmas = <&audma0 0x1F>, <&audma1 0x20>; + dmas = <&audma0 0x1f>, <&audma1 0x20>; dma-names = "rx", "tx"; }; ssiu46: ssiu-38 { @@ -2145,7 +2145,7 @@ dma-names = "rx", "tx"; }; ssiu91: ssiu-45 { - dmas = <&audma0 0x7F>, <&audma1 0x80>; + dmas = <&audma0 0x7f>, <&audma1 0x80>; dma-names = "rx", "tx"; }; ssiu92: ssiu-46 { @@ -2157,19 +2157,19 @@ dma-names = "rx", "tx"; }; ssiu94: ssiu-48 { - dmas = <&audma0 0xA3>, <&audma1 0xA4>; + dmas = <&audma0 0xa3>, <&audma1 0xa4>; dma-names = "rx", "tx"; }; ssiu95: ssiu-49 { - dmas = <&audma0 0xA5>, <&audma1 0xA6>; + dmas = <&audma0 0xa5>, <&audma1 0xa6>; dma-names = "rx", "tx"; }; ssiu96: ssiu-50 { - dmas = <&audma0 0xA7>, <&audma1 0xA8>; + dmas = <&audma0 0xa7>, <&audma1 0xa8>; dma-names = "rx", "tx"; }; ssiu97: ssiu-51 { - dmas = <&audma0 0xA9>, <&audma1 0xAA>; + dmas = <&audma0 0xa9>, <&audma1 0xaa>; dma-names = "rx", "tx"; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 4e730144e5fd..425561e658ca 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -1911,7 +1911,7 @@ dma-names = "rx", "tx"; }; ssiu04: ssiu-4 { - dmas = <&audma0 0x3F>, <&audma1 0x40>; + dmas = <&audma0 0x3f>, <&audma1 0x40>; dma-names = "rx", "tx"; }; ssiu05: ssiu-5 { @@ -1919,7 +1919,7 @@ dma-names = "rx", "tx"; }; ssiu06: ssiu-6 { - dmas = <&audma0 0x4F>, <&audma1 0x50>; + dmas = <&audma0 0x4f>, <&audma1 0x50>; dma-names = "rx", "tx"; }; ssiu07: ssiu-7 { @@ -1931,7 +1931,7 @@ dma-names = "rx", "tx"; }; ssiu11: ssiu-9 { - dmas = <&audma0 0x4B>, <&audma1 0x4C>; + dmas = <&audma0 0x4b>, <&audma1 0x4c>; dma-names = "rx", "tx"; }; ssiu12: ssiu-10 { @@ -1939,23 +1939,23 @@ dma-names = "rx", "tx"; }; ssiu13: ssiu-11 { - dmas = <&audma0 0x59>, <&audma1 0x5A>; + dmas = <&audma0 0x59>, <&audma1 0x5a>; dma-names = "rx", "tx"; }; ssiu14: ssiu-12 { - dmas = <&audma0 0x5F>, <&audma1 0x60>; + dmas = <&audma0 0x5f>, <&audma1 0x60>; dma-names = "rx", "tx"; }; ssiu15: ssiu-13 { - dmas = <&audma0 0xC3>, <&audma1 0xC4>; + dmas = <&audma0 0xc3>, <&audma1 0xc4>; dma-names = "rx", "tx"; }; ssiu16: ssiu-14 { - dmas = <&audma0 0xC7>, <&audma1 0xC8>; + dmas = <&audma0 0xc7>, <&audma1 0xc8>; dma-names = "rx", "tx"; }; ssiu17: ssiu-15 { - dmas = <&audma0 0xCB>, <&audma1 0xCC>; + dmas = <&audma0 0xcb>, <&audma1 0xcc>; dma-names = "rx", "tx"; }; ssiu20: ssiu-16 { @@ -1967,27 +1967,27 @@ dma-names = "rx", "tx"; }; ssiu22: ssiu-18 { - dmas = <&audma0 0x6B>, <&audma1 0x6C>; + dmas = <&audma0 0x6b>, <&audma1 0x6c>; dma-names = "rx", "tx"; }; ssiu23: ssiu-19 { - dmas = <&audma0 0x6D>, <&audma1 0x6E>; + dmas = <&audma0 0x6d>, <&audma1 0x6e>; dma-names = "rx", "tx"; }; ssiu24: ssiu-20 { - dmas = <&audma0 0xCF>, <&audma1 0xCE>; + dmas = <&audma0 0xcf>, <&audma1 0xce>; dma-names = "rx", "tx"; }; ssiu25: ssiu-21 { - dmas = <&audma0 0xEB>, <&audma1 0xEC>; + dmas = <&audma0 0xeb>, <&audma1 0xec>; dma-names = "rx", "tx"; }; ssiu26: ssiu-22 { - dmas = <&audma0 0xED>, <&audma1 0xEE>; + dmas = <&audma0 0xed>, <&audma1 0xee>; dma-names = "rx", "tx"; }; ssiu27: ssiu-23 { - dmas = <&audma0 0xEF>, <&audma1 0xF0>; + dmas = <&audma0 0xef>, <&audma1 0xf0>; dma-names = "rx", "tx"; }; ssiu30: ssiu-24 { @@ -2011,15 +2011,15 @@ dma-names = "rx", "tx"; }; ssiu35: ssiu-29 { - dmas = <&audma0 0x29>, <&audma1 0x2A>; + dmas = <&audma0 0x29>, <&audma1 0x2a>; dma-names = "rx", "tx"; }; ssiu36: ssiu-30 { - dmas = <&audma0 0x2B>, <&audma1 0x2C>; + dmas = <&audma0 0x2b>, <&audma1 0x2c>; dma-names = "rx", "tx"; }; ssiu37: ssiu-31 { - dmas = <&audma0 0x2D>, <&audma1 0x2E>; + dmas = <&audma0 0x2d>, <&audma1 0x2e>; dma-names = "rx", "tx"; }; ssiu40: ssiu-32 { @@ -2031,19 +2031,19 @@ dma-names = "rx", "tx"; }; ssiu42: ssiu-34 { - dmas = <&audma0 0x19>, <&audma1 0x1A>; + dmas = <&audma0 0x19>, <&audma1 0x1a>; dma-names = "rx", "tx"; }; ssiu43: ssiu-35 { - dmas = <&audma0 0x1B>, <&audma1 0x1C>; + dmas = <&audma0 0x1b>, <&audma1 0x1c>; dma-names = "rx", "tx"; }; ssiu44: ssiu-36 { - dmas = <&audma0 0x1D>, <&audma1 0x1E>; + dmas = <&audma0 0x1d>, <&audma1 0x1e>; dma-names = "rx", "tx"; }; ssiu45: ssiu-37 { - dmas = <&audma0 0x1F>, <&audma1 0x20>; + dmas = <&audma0 0x1f>, <&audma1 0x20>; dma-names = "rx", "tx"; }; ssiu46: ssiu-38 { @@ -2075,7 +2075,7 @@ dma-names = "rx", "tx"; }; ssiu91: ssiu-45 { - dmas = <&audma0 0x7F>, <&audma1 0x80>; + dmas = <&audma0 0x7f>, <&audma1 0x80>; dma-names = "rx", "tx"; }; ssiu92: ssiu-46 { @@ -2087,19 +2087,19 @@ dma-names = "rx", "tx"; }; ssiu94: ssiu-48 { - dmas = <&audma0 0xA3>, <&audma1 0xA4>; + dmas = <&audma0 0xa3>, <&audma1 0xa4>; dma-names = "rx", "tx"; }; ssiu95: ssiu-49 { - dmas = <&audma0 0xA5>, <&audma1 0xA6>; + dmas = <&audma0 0xa5>, <&audma1 0xa6>; dma-names = "rx", "tx"; }; ssiu96: ssiu-50 { - dmas = <&audma0 0xA7>, <&audma1 0xA8>; + dmas = <&audma0 0xa7>, <&audma1 0xa8>; dma-names = "rx", "tx"; }; ssiu97: ssiu-51 { - dmas = <&audma0 0xA9>, <&audma1 0xAA>; + dmas = <&audma0 0xa9>, <&audma1 0xaa>; dma-names = "rx", "tx"; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts index b7328f9f7d4b..b26c5a709777 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts +++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts @@ -364,7 +364,7 @@ reg = <0x00040000 0x080000>; read-only; }; - cert_header_sa3@c0000 { + cert-header-sa3@c0000 { reg = <0x000c0000 0x080000>; read-only; }; @@ -372,7 +372,7 @@ reg = <0x00140000 0x040000>; read-only; }; - cert_header_sa6@180000 { + cert-header-sa6@180000 { reg = <0x00180000 0x040000>; read-only; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts index f18d26360610..343f9610f892 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts +++ b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts @@ -255,7 +255,7 @@ reg = <0x00040000 0x080000>; read-only; }; - cert_header_sa3@c0000 { + cert-header-sa3@c0000 { reg = <0x000c0000 0x080000>; read-only; }; @@ -263,7 +263,7 @@ reg = <0x00140000 0x040000>; read-only; }; - cert_header_sa6@180000 { + cert-header-sa6@180000 { reg = <0x00180000 0x040000>; read-only; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index 1007ee48adc3..1f6676e2795a 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -1209,6 +1209,38 @@ }; }; + wwdt0: watchdog@ffc90000 { + compatible = "renesas,r8a77970-wwdt", + "renesas,rcar-gen3-wwdt"; + reg = <0 0xffc90000 0 0x10>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A77970_CLK_R>, + <&cpg CPG_CORE R8A77970_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 325>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt1: watchdog@ffca0000 { + compatible = "renesas,r8a77970-wwdt", + "renesas,rcar-gen3-wwdt"; + reg = <0 0xffca0000 0 0x10>; + interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A77970_CLK_R>, + <&cpg CPG_CORE R8A77970_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 324>; + reset-names = "cnt"; + status = "disabled"; + }; + prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; diff --git a/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts b/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts index 2da63b4daa0a..e3725304fed0 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts +++ b/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts @@ -236,7 +236,7 @@ reg = <0x00040000 0x080000>; read-only; }; - cert_header_sa3@c0000 { + cert-header-sa3@c0000 { reg = <0x000c0000 0x080000>; read-only; }; @@ -244,7 +244,7 @@ reg = <0x00140000 0x040000>; read-only; }; - cert_header_sa6@180000 { + cert-header-sa6@180000 { reg = <0x00180000 0x040000>; read-only; }; @@ -289,3 +289,8 @@ &scif_clk { clock-frequency = <14745600>; }; + +/* Firmware should reserve it but sadly doesn't */ +&swdt { + status = "reserved"; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index 8cd7f68d026b..86b7792d68fa 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -139,6 +139,15 @@ status = "disabled"; }; + swdt: watchdog@e6030000 { + compatible = "renesas,r8a77980-wdt", "renesas,rcar-gen3-wdt"; + reg = <0 0xe6030000 0 0x0c>; + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_CORE R8A77980_CLK_OSC>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + status = "disabled"; + }; + gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a77980", "renesas,rcar-gen3-gpio"; @@ -1582,6 +1591,86 @@ }; }; + wwdt0: watchdog@ffc90000 { + compatible = "renesas,r8a77980-wwdt", + "renesas,rcar-gen3-wwdt"; + reg = <0 0xffc90000 0 0x10>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A77980_CLK_R>, + <&cpg CPG_CORE R8A77980_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 325>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt1: watchdog@ffca0000 { + compatible = "renesas,r8a77980-wwdt", + "renesas,rcar-gen3-wwdt"; + reg = <0 0xffca0000 0 0x10>; + interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A77980_CLK_R>, + <&cpg CPG_CORE R8A77980_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 324>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt2: watchdog@ffcb0000 { + compatible = "renesas,r8a77980-wwdt", + "renesas,rcar-gen3-wwdt"; + reg = <0 0xffcb0000 0 0x10>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A77980_CLK_R>, + <&cpg CPG_CORE R8A77980_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 321>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt3: watchdog@ffcc0000 { + compatible = "renesas,r8a77980-wwdt", + "renesas,rcar-gen3-wwdt"; + reg = <0 0xffcc0000 0 0x10>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A77980_CLK_R>, + <&cpg CPG_CORE R8A77980_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 309>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt4: watchdog@ffcf0000 { + compatible = "renesas,r8a77980-wwdt", + "renesas,rcar-gen3-wwdt"; + reg = <0 0xffcf0000 0 0x10>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A77980_CLK_R>, + <&cpg CPG_CORE R8A77980_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 403>; + reset-names = "cnt"; + status = "disabled"; + }; + prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index 4b101a6dc49d..0483a5d0714a 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -3032,6 +3032,166 @@ }; }; + wwdt0: watchdog@ffc90000 { + compatible = "renesas,r8a779a0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffc90000 0 0x10>; + interrupts = <GIC_SPI 480 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779A0_CLK_R>, + <&cpg CPG_CORE R8A779A0_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 1200>, <&cpg 1318>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt1: watchdog@ffca0000 { + compatible = "renesas,r8a779a0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffca0000 0 0x10>; + interrupts = <GIC_SPI 482 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 483 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779A0_CLK_R>, + <&cpg CPG_CORE R8A779A0_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 1201>, <&cpg 1319>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt2: watchdog@ffcb0000 { + compatible = "renesas,r8a779a0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffcb0000 0 0x10>; + interrupts = <GIC_SPI 484 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 485 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779A0_CLK_R>, + <&cpg CPG_CORE R8A779A0_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 1202>, <&cpg 1320>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt3: watchdog@ffcc0000 { + compatible = "renesas,r8a779a0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffcc0000 0 0x10>; + interrupts = <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779A0_CLK_R>, + <&cpg CPG_CORE R8A779A0_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 1203>, <&cpg 1321>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt4: watchdog@ffcf0000 { + compatible = "renesas,r8a779a0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffcf0000 0 0x10>; + interrupts = <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779A0_CLK_R>, + <&cpg CPG_CORE R8A779A0_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 1204>, <&cpg 1322>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt5: watchdog@ffef0000 { + compatible = "renesas,r8a779a0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffef0000 0 0x10>; + interrupts = <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779A0_CLK_R>, + <&cpg CPG_CORE R8A779A0_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 1205>, <&cpg 1323>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt6: watchdog@fff10000 { + compatible = "renesas,r8a779a0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xfff10000 0 0x10>; + interrupts = <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779A0_CLK_R>, + <&cpg CPG_CORE R8A779A0_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 1206>, <&cpg 1324>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt7: watchdog@fff20000 { + compatible = "renesas,r8a779a0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xfff20000 0 0x10>; + interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779A0_CLK_R>, + <&cpg CPG_CORE R8A779A0_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 1207>, <&cpg 1325>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt8: watchdog@fff30000 { + compatible = "renesas,r8a779a0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xfff30000 0 0x10>; + interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779A0_CLK_R>, + <&cpg CPG_CORE R8A779A0_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 1208>, <&cpg 1326>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt9: watchdog@fff40000 { + compatible = "renesas,r8a779a0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xfff40000 0 0x10>; + interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779A0_CLK_R>, + <&cpg CPG_CORE R8A779A0_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 1209>, <&cpg 1327>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index 0ebf8e5dd2f9..cbb161c863ac 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -1297,6 +1297,166 @@ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; }; + wwdt0: watchdog@ffc90000 { + compatible = "renesas,r8a779f0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffc90000 0 0x10>; + interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779F0_CLK_R>, + <&cpg CPG_CORE R8A779F0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 1200>, <&cpg 1318>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt1: watchdog@ffca0000 { + compatible = "renesas,r8a779f0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffca0000 0 0x10>; + interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779F0_CLK_R>, + <&cpg CPG_CORE R8A779F0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 1201>, <&cpg 1319>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt2: watchdog@ffcb0000 { + compatible = "renesas,r8a779f0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffcb0000 0 0x10>; + interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779F0_CLK_R>, + <&cpg CPG_CORE R8A779F0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 1202>, <&cpg 1320>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt3: watchdog@ffcc0000 { + compatible = "renesas,r8a779f0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffcc0000 0 0x10>; + interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779F0_CLK_R>, + <&cpg CPG_CORE R8A779F0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 1203>, <&cpg 1321>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt4: watchdog@ffcf0000 { + compatible = "renesas,r8a779f0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffcf0000 0 0x10>; + interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779F0_CLK_R>, + <&cpg CPG_CORE R8A779F0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 1204>, <&cpg 1322>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt5: watchdog@ffef0000 { + compatible = "renesas,r8a779f0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffef0000 0 0x10>; + interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779F0_CLK_R>, + <&cpg CPG_CORE R8A779F0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 1205>, <&cpg 1323>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt6: watchdog@fff10000 { + compatible = "renesas,r8a779f0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xfff10000 0 0x10>; + interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779F0_CLK_R>, + <&cpg CPG_CORE R8A779F0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 1206>, <&cpg 1324>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt7: watchdog@fff20000 { + compatible = "renesas,r8a779f0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xfff20000 0 0x10>; + interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779F0_CLK_R>, + <&cpg CPG_CORE R8A779F0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 1207>, <&cpg 1325>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt8: watchdog@fff30000 { + compatible = "renesas,r8a779f0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xfff30000 0 0x10>; + interrupts = <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779F0_CLK_R>, + <&cpg CPG_CORE R8A779F0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 1208>, <&cpg 1326>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt9: watchdog@fff40000 { + compatible = "renesas,r8a779f0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xfff40000 0 0x10>; + interrupts = <GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779F0_CLK_R>, + <&cpg CPG_CORE R8A779F0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 1209>, <&cpg 1327>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index ff2bd1908a45..82a7278836e5 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -2544,6 +2544,118 @@ }; }; + wwdt0: watchdog@ffc90000 { + compatible = "renesas,r8a779g0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffc90000 0 0x10>; + interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779G0_CLK_R>, + <&cpg CPG_CORE R8A779G0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 1200>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt1: watchdog@ffca0000 { + compatible = "renesas,r8a779g0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffca0000 0 0x10>; + interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779G0_CLK_R>, + <&cpg CPG_CORE R8A779G0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 1201>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt2: watchdog@ffcb0000 { + compatible = "renesas,r8a779g0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffcb0000 0 0x10>; + interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779G0_CLK_R>, + <&cpg CPG_CORE R8A779G0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 1202>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt3: watchdog@ffcc0000 { + compatible = "renesas,r8a779g0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffcc0000 0 0x10>; + interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779G0_CLK_R>, + <&cpg CPG_CORE R8A779G0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 1203>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt4: watchdog@ffcf0000 { + compatible = "renesas,r8a779g0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffcf0000 0 0x10>; + interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779G0_CLK_R>, + <&cpg CPG_CORE R8A779G0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 1204>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt5: watchdog@ffef0000 { + compatible = "renesas,r8a779g0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffef0000 0 0x10>; + interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779G0_CLK_R>, + <&cpg CPG_CORE R8A779G0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 1205>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt6: watchdog@fff10000 { + compatible = "renesas,r8a779g0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xfff10000 0 0x10>; + interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779G0_CLK_R>, + <&cpg CPG_CORE R8A779G0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 1206>; + reset-names = "cnt"; + status = "disabled"; + }; + prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi index 4dc0e5304f72..74bc4c4854ec 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi @@ -2183,6 +2183,118 @@ }; }; + wwdt0: watchdog@ffc90000 { + compatible = "renesas,r8a779h0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffc90000 0 0x10>; + interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779H0_CLK_R>, + <&cpg CPG_CORE R8A779H0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 1200>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt1: watchdog@ffca0000 { + compatible = "renesas,r8a779h0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffca0000 0 0x10>; + interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779H0_CLK_R>, + <&cpg CPG_CORE R8A779H0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 1201>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt2: watchdog@ffcb0000 { + compatible = "renesas,r8a779h0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffcb0000 0 0x10>; + interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779H0_CLK_R>, + <&cpg CPG_CORE R8A779H0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 1202>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt3: watchdog@ffcc0000 { + compatible = "renesas,r8a779h0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffcc0000 0 0x10>; + interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779H0_CLK_R>, + <&cpg CPG_CORE R8A779H0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 1203>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt4: watchdog@ffcf0000 { + compatible = "renesas,r8a779h0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffcf0000 0 0x10>; + interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779H0_CLK_R>, + <&cpg CPG_CORE R8A779H0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 1204>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt5: watchdog@ffef0000 { + compatible = "renesas,r8a779h0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffef0000 0 0x10>; + interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779H0_CLK_R>, + <&cpg CPG_CORE R8A779H0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 1205>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt6: watchdog@fff10000 { + compatible = "renesas,r8a779h0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xfff10000 0 0x10>; + interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779H0_CLK_R>, + <&cpg CPG_CORE R8A779H0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 1206>; + reset-names = "cnt"; + status = "disabled"; + }; + prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; diff --git a/arch/arm64/boot/dts/renesas/r8a779m0.dtsi b/arch/arm64/boot/dts/renesas/r8a779m0.dtsi deleted file mode 100644 index 38978360e722..000000000000 --- a/arch/arm64/boot/dts/renesas/r8a779m0.dtsi +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree Source for the R-Car H3e (R8A779M0) SoC - * - * Copyright (C) 2021 Glider bv - */ - -#include "r8a77951.dtsi" - -/ { - compatible = "renesas,r8a779m0", "renesas,r8a7795"; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a779m2.dtsi b/arch/arm64/boot/dts/renesas/r8a779m2.dtsi deleted file mode 100644 index bced12764c69..000000000000 --- a/arch/arm64/boot/dts/renesas/r8a779m2.dtsi +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree Source for the R-Car M3e (R8A779M2) SoC - * - * Copyright (C) 2021 Glider bv - */ - -#include "r8a77961.dtsi" - -/ { - compatible = "renesas,r8a779m2", "renesas,r8a77961"; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a779m4.dtsi b/arch/arm64/boot/dts/renesas/r8a779m4.dtsi deleted file mode 100644 index ae8486056962..000000000000 --- a/arch/arm64/boot/dts/renesas/r8a779m4.dtsi +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree Source for the R-Car M3Ne (R8A779M4) SoC - * - * Copyright (C) 2021 Glider bv - */ - -#include "r8a77965.dtsi" - -/ { - compatible = "renesas,r8a779m4", "renesas,r8a77965"; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a779m6.dtsi b/arch/arm64/boot/dts/renesas/r8a779m6.dtsi deleted file mode 100644 index 94d6a6cf503e..000000000000 --- a/arch/arm64/boot/dts/renesas/r8a779m6.dtsi +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree Source for the R-Car E3e (R8A779M6) SoC - * - * Copyright (C) 2021 Glider bv - */ - -#include "r8a77990.dtsi" - -/ { - compatible = "renesas,r8a779m6", "renesas,r8a77990"; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a779m7.dtsi b/arch/arm64/boot/dts/renesas/r8a779m7.dtsi deleted file mode 100644 index 0580fa614034..000000000000 --- a/arch/arm64/boot/dts/renesas/r8a779m7.dtsi +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree Source for the R-Car D3e (R8A779M7) SoC - * - * Copyright (C) 2021 Glider bv - */ - -#include "r8a77995.dtsi" - -/ { - compatible = "renesas,r8a779m7", "renesas,r8a77995"; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a779m8.dtsi b/arch/arm64/boot/dts/renesas/r8a779m8.dtsi deleted file mode 100644 index dfccc080fb3e..000000000000 --- a/arch/arm64/boot/dts/renesas/r8a779m8.dtsi +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree Source for the R-Car H3Ne (R8A779M8) SoC - * - * Copyright (C) 2021 Glider bv - */ - -#include "r8a77951.dtsi" - -/ { - compatible = "renesas,r8a779m8", "renesas,r8a7795"; -}; - -&cluster0_opp { - /delete-node/ opp-1600000000; - /delete-node/ opp-1700000000; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a779mb.dtsi b/arch/arm64/boot/dts/renesas/r8a779mb.dtsi deleted file mode 100644 index 181b737c91cd..000000000000 --- a/arch/arm64/boot/dts/renesas/r8a779mb.dtsi +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree Source for the R-Car H3Ne-1.7G (R8A779MB) SoC - * - * Copyright (C) 2022 Glider bv - */ - -#include "r8a77951.dtsi" - -/ { - compatible = "renesas,r8a779mb", "renesas,r8a7795"; -}; diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index bd52d60bafb9..29273da81995 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -1371,7 +1371,7 @@ wdt1: watchdog@12800c00 { compatible = "renesas,r9a07g044-wdt", "renesas,rzg2l-wdt"; - reg = <0 0x12800C00 0 0x400>; + reg = <0 0x12800c00 0 0x400>; clocks = <&cpg CPG_MOD R9A07G044_WDT1_PCLK>, <&cpg CPG_MOD R9A07G044_WDT1_CLK>; clock-names = "pclk", "oscclk"; diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi deleted file mode 100644 index 56a979e82c4f..000000000000 --- a/arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Device Tree Source for the RZ/G2LC R9A07G044C1 SoC specific parts - * - * Copyright (C) 2021 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r9a07g044.dtsi" - -/ { - compatible = "renesas,r9a07g044c1", "renesas,r9a07g044"; - - cpus { - /delete-node/ cpu-map; - /delete-node/ cpu@100; - }; -}; - -&soc { - /delete-node/ ssi@1004a800; - /delete-node/ serial@1004c800; - /delete-node/ adc@10059000; - /delete-node/ ethernet@11c30000; -}; diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi deleted file mode 100644 index 9cf27ca9f1d2..000000000000 --- a/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Device Tree Source for the RZ/G2L R9A07G044L1 SoC specific parts - * - * Copyright (C) 2021 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r9a07g044.dtsi" - -/ { - compatible = "renesas,r9a07g044l1", "renesas,r9a07g044"; - - cpus { - /delete-node/ cpu-map; - /delete-node/ cpu@100; - }; -}; diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 4e0256d3201d..0dee48c4f1e4 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -1379,7 +1379,7 @@ wdt1: watchdog@12800c00 { compatible = "renesas,r9a07g054-wdt", "renesas,rzg2l-wdt"; - reg = <0 0x12800C00 0 0x400>; + reg = <0 0x12800c00 0 0x400>; clocks = <&cpg CPG_MOD R9A07G054_WDT1_PCLK>, <&cpg CPG_MOD R9A07G054_WDT1_CLK>; clock-names = "pclk", "oscclk"; diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi deleted file mode 100644 index d85a6ac0f024..000000000000 --- a/arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Device Tree Source for the RZ/V2L R9A07G054L1 SoC specific parts - * - * Copyright (C) 2021 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r9a07g054.dtsi" - -/ { - compatible = "renesas,r9a07g054l1", "renesas,r9a07g054"; - - cpus { - /delete-node/ cpu-map; - /delete-node/ cpu@100; - }; -}; diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 876de634908e..997e6cf0bb82 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -845,6 +845,71 @@ status = "disabled"; }; + pcie: pcie@11e40000 { + compatible = "renesas,r9a08g045-pcie"; + reg = <0 0x11e40000 0 0x10000>; + ranges = <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>; + /* Map all possible DRAM ranges (4 GB). */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 1 0x00000000>; + bus-range = <0x0 0xff>; + interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "serr", "serr_cor", "serr_nonfatal", + "serr_fatal", "axi_err", "inta", + "intb", "intc", "intd", "msi", + "link_bandwidth", "pm_pme", "dma", + "pcie_evt", "msg", "all"; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie 0 0 0 0>, /* INTA */ + <0 0 0 2 &pcie 0 0 0 1>, /* INTB */ + <0 0 0 3 &pcie 0 0 0 2>, /* INTC */ + <0 0 0 4 &pcie 0 0 0 3>; /* INTD */ + clocks = <&cpg CPG_MOD R9A08G045_PCI_ACLK>, + <&cpg CPG_MOD R9A08G045_PCI_CLKL1PM>; + clock-names = "aclk", "pm"; + resets = <&cpg R9A08G045_PCI_ARESETN>, + <&cpg R9A08G045_PCI_RST_B>, + <&cpg R9A08G045_PCI_RST_GP_B>, + <&cpg R9A08G045_PCI_RST_PS_B>, + <&cpg R9A08G045_PCI_RST_RSM_B>, + <&cpg R9A08G045_PCI_RST_CFG_B>, + <&cpg R9A08G045_PCI_RST_LOAD_B>; + reset-names = "aresetn", "rst_b", "rst_gp_b", "rst_ps_b", + "rst_rsm_b", "rst_cfg_b", "rst_load_b"; + power-domains = <&cpg>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + renesas,sysc = <&sysc>; + status = "disabled"; + + pcie_port0: pcie@0,0 { + reg = <0x0 0x0 0x0 0x0 0x0>; + ranges; + device_type = "pci"; + vendor-id = <0x1912>; + device-id = <0x0033>; + #address-cells = <3>; + #size-cells = <2>; + }; + }; + gic: interrupt-controller@12400000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index 7a469de3bb62..cbb48ff5028f 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -591,6 +591,226 @@ }; }; + rsci0: serial@12800c00 { + compatible = "renesas,r9a09g047-rsci"; + reg = <0 0x12800c00 0 0x400>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x5d>, <&cpg CPG_MOD 0x5e>, + <&cpg CPG_MOD 0x61>, <&cpg CPG_MOD 0x60>, + <&cpg CPG_MOD 0x5f>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x81>, <&cpg 0x82>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci1: serial@12801000 { + compatible = "renesas,r9a09g047-rsci"; + reg = <0 0x12801000 0 0x400>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x62>, <&cpg CPG_MOD 0x63>, + <&cpg CPG_MOD 0x66>, <&cpg CPG_MOD 0x65>, + <&cpg CPG_MOD 0x64>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x83>, <&cpg 0x84>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci2: serial@12801400 { + compatible = "renesas,r9a09g047-rsci"; + reg = <0 0x12801400 0 0x400>; + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x67>, <&cpg CPG_MOD 0x68>, + <&cpg CPG_MOD 0x6b>, <&cpg CPG_MOD 0x6a>, + <&cpg CPG_MOD 0x69>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x85>, <&cpg 0x86>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci3: serial@12801800 { + compatible = "renesas,r9a09g047-rsci"; + reg = <0 0x12801800 0 0x400>; + interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x6c>, <&cpg CPG_MOD 0x6d>, + <&cpg CPG_MOD 0x70>, <&cpg CPG_MOD 0x6f>, + <&cpg CPG_MOD 0x6e>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x87>, <&cpg 0x88>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci4: serial@12801c00 { + compatible = "renesas,r9a09g047-rsci"; + reg = <0 0x12801c00 0 0x400>; + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x71>, <&cpg CPG_MOD 0x72>, + <&cpg CPG_MOD 0x75>, <&cpg CPG_MOD 0x74>, + <&cpg CPG_MOD 0x73>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x89>, <&cpg 0x8a>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci5: serial@12802000 { + compatible = "renesas,r9a09g047-rsci"; + reg = <0 0x12802000 0 0x400>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x76>, <&cpg CPG_MOD 0x77>, + <&cpg CPG_MOD 0x7a>, <&cpg CPG_MOD 0x79>, + <&cpg CPG_MOD 0x78>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x8b>, <&cpg 0x8c>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci6: serial@12802400 { + compatible = "renesas,r9a09g047-rsci"; + reg = <0 0x12802400 0 0x400>; + interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 154 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x7b>, <&cpg CPG_MOD 0x7c>, + <&cpg CPG_MOD 0x7f>, <&cpg CPG_MOD 0x7e>, + <&cpg CPG_MOD 0x7d>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x8d>, <&cpg 0x8e>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci7: serial@12802800 { + compatible = "renesas,r9a09g047-rsci"; + reg = <0 0x12802800 0 0x400>; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 160 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x80>, <&cpg CPG_MOD 0x81>, + <&cpg CPG_MOD 0x84>, <&cpg CPG_MOD 0x83>, + <&cpg CPG_MOD 0x82>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x8f>, <&cpg 0x90>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci8: serial@12802c00 { + compatible = "renesas,r9a09g047-rsci"; + reg = <0 0x12802c00 0 0x400>; + interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 164 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x85>, <&cpg CPG_MOD 0x86>, + <&cpg CPG_MOD 0x89>, <&cpg CPG_MOD 0x88>, + <&cpg CPG_MOD 0x87>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x91>, <&cpg 0x92>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci9: serial@12803000 { + compatible = "renesas,r9a09g047-rsci"; + reg = <0 0x12803000 0 0x400>; + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x8a>, <&cpg CPG_MOD 0x8b>, + <&cpg CPG_MOD 0x8e>, <&cpg CPG_MOD 0x8d>, + <&cpg CPG_MOD 0x8c>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x93>, <&cpg 0x94>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + wdt1: watchdog@14400000 { compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt"; reg = <0 0x14400000 0 0x400>; @@ -853,6 +1073,36 @@ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; }; + xhci: usb@15850000 { + compatible = "renesas,r9a09g047-xhci"; + reg = <0 0x15850000 0 0x10000>; + interrupts = <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "all", "smi", "hse", "pme", "xhc"; + clocks = <&cpg CPG_MOD 0xaf>; + power-domains = <&cpg>; + resets = <&cpg 0xaa>; + phys = <&usb3_phy>, <&usb3_phy>; + phy-names = "usb2-phy", "usb3-phy"; + status = "disabled"; + }; + + usb3_phy: usb-phy@15870000 { + compatible = "renesas,r9a09g047-usb3-phy"; + reg = <0 0x15870000 0 0x10000>; + clocks = <&cpg CPG_MOD 0xb0>, + <&cpg CPG_CORE R9A09G047_USB3_0_CLKCORE>, + <&cpg CPG_CORE R9A09G047_USB3_0_REF_ALT_CLK_P>; + clock-names = "pclk", "core", "ref_alt_clk_p"; + power-domains = <&cpg>; + resets = <&cpg 0xaa>; + #phy-cells = <0>; + status = "disabled"; + }; + sdhi0: mmc@15c00000 { compatible = "renesas,sdhi-r9a09g047", "renesas,sdhi-r9a09g057"; reg = <0x0 0x15c00000 0 0x10000>; diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi deleted file mode 100644 index e50d9159e832..000000000000 --- a/arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Device Tree Source for the RZ/G3E R9A09G047E37 SoC specific parts - * - * Copyright (C) 2024 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r9a09g047.dtsi" - -/ { - compatible = "renesas,r9a09g047e37", "renesas,r9a09g047"; - - cpus { - /delete-node/ cpu@200; - /delete-node/ cpu@300; - }; -}; diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts index 08e814c03fa8..696903dc7a63 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts @@ -8,11 +8,12 @@ /dts-v1/; /* Switch selection settings */ -#define SW_LCD_EN 0 #define SW_GPIO8_CAN0_STB 0 #define SW_GPIO9_CAN1_STB 0 #define SW_LCD_EN 0 #define SW_PDM_EN 0 +#define SW_SER0_PMOD 1 +#define SW_SER2_EN 1 #define SW_SD0_DEV_SEL 0 #define SW_SDIO_M2E 0 @@ -36,6 +37,15 @@ compatible = "renesas,smarc2-evk", "renesas,rzg3e-smarcm", "renesas,r9a09g047e57", "renesas,r9a09g047"; + aliases { + i2c0 = &i2c0; + serial0 = &rsci4; + serial1 = &rsci9; + serial2 = &rsci2; + serial3 = &scif0; + mmc1 = &sdhi1; + }; + vqmmc_sd1_pvdd: regulator-vqmmc-sd1-pvdd { compatible = "regulator-gpio"; regulator-name = "SD1_PVDD"; @@ -135,6 +145,28 @@ input-schmitt-enable; }; + rsci2_pins: rsci2 { + pinmux = <RZG3E_PORT_PINMUX(1, 0, 1)>, /* RXD2 */ + <RZG3E_PORT_PINMUX(1, 1, 1)>, /* TXD2 */ + <RZG3E_PORT_PINMUX(1, 2, 6)>, /* CTS2N */ + <RZG3E_PORT_PINMUX(1, 3, 1)>; /* RTS2N */ + bias-pull-up; + }; + + rsci4_pins: rsci4 { + pinmux = <RZG3E_PORT_PINMUX(7, 6, 5)>, /* RXD4 */ + <RZG3E_PORT_PINMUX(7, 7, 5)>, /* TXD4 */ + <RZG3E_PORT_PINMUX(8, 0, 6)>, /* CTS4N */ + <RZG3E_PORT_PINMUX(8, 1, 5)>; /* RTS4N */ + bias-pull-up; + }; + + rsci9_pins: rsci9 { + pinmux = <RZG3E_PORT_PINMUX(8, 2, 5)>, /* RXD9 */ + <RZG3E_PORT_PINMUX(8, 3, 5)>; /* TXD9 */ + bias-pull-up; + }; + scif_pins: scif { pins = "SCIF_TXD", "SCIF_RXD"; renesas,output-impedance = <1>; @@ -164,8 +196,44 @@ <RZG3E_PORT_PINMUX(G, 5, 1)>; /* SD1DAT3 */ }; }; + + usb3_pins: usb3 { + pinmux = <RZG3E_PORT_PINMUX(4, 1, 12)>, /* USB30_VBUSEN */ + <RZG3E_PORT_PINMUX(4, 0, 12)>; /* USB30_OVRCURN */ + }; }; +#if SW_SER0_PMOD && SW_SER2_EN +&rsci2 { + pinctrl-0 = <&rsci2_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + + status = "okay"; +}; +#endif + +#if (!SW_LCD_EN) && (SW_SER0_PMOD) +&rsci4 { + pinctrl-0 = <&rsci4_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + + status = "okay"; +}; +#endif + +#if (!SW_LCD_EN) +&rsci9 { + pinctrl-0 = <&rsci9_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; +#endif + &scif0 { pinctrl-0 = <&scif_pins>; pinctrl-names = "default"; @@ -179,3 +247,8 @@ vmmc-supply = <®_3p3v>; vqmmc-supply = <&vqmmc_sd1_pvdd>; }; + +&xhci { + pinctrl-0 = <&usb3_pins>; + pinctrl-names = "default"; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi index 8781c2fa7313..9fb15ca24984 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi @@ -83,6 +83,7 @@ next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK0>; + #cooling-cells = <2>; operating-points-v2 = <&cluster0_opp>; }; @@ -93,6 +94,7 @@ next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK1>; + #cooling-cells = <2>; operating-points-v2 = <&cluster0_opp>; }; @@ -103,6 +105,7 @@ next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK2>; + #cooling-cells = <2>; operating-points-v2 = <&cluster0_opp>; }; @@ -113,6 +116,7 @@ next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK3>; + #cooling-cells = <2>; operating-points-v2 = <&cluster0_opp>; }; @@ -183,12 +187,104 @@ #size-cells = <2>; ranges; + icu: interrupt-controller@10400000 { + compatible = "renesas,r9a09g056-icu"; + reg = <0 0x10400000 0 0x10000>; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "nmi", + "port_irq0", "port_irq1", "port_irq2", + "port_irq3", "port_irq4", "port_irq5", + "port_irq6", "port_irq7", "port_irq8", + "port_irq9", "port_irq10", "port_irq11", + "port_irq12", "port_irq13", "port_irq14", + "port_irq15", + "tint0", "tint1", "tint2", "tint3", + "tint4", "tint5", "tint6", "tint7", + "tint8", "tint9", "tint10", "tint11", + "tint12", "tint13", "tint14", "tint15", + "tint16", "tint17", "tint18", "tint19", + "tint20", "tint21", "tint22", "tint23", + "tint24", "tint25", "tint26", "tint27", + "tint28", "tint29", "tint30", "tint31", + "int-ca55-0", "int-ca55-1", + "int-ca55-2", "int-ca55-3", + "icu-error-ca55", + "gpt-u0-gtciada", "gpt-u0-gtciadb", + "gpt-u1-gtciada", "gpt-u1-gtciadb"; + clocks = <&cpg CPG_MOD 0x5>; + power-domains = <&cpg>; + resets = <&cpg 0x36>; + }; + pinctrl: pinctrl@10410000 { compatible = "renesas,r9a09g056-pinctrl"; reg = <0 0x10410000 0 0x10000>; clocks = <&cpg CPG_CORE R9A09G056_IOTOP_0_SHCLK>; gpio-controller; #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&icu>; gpio-ranges = <&pinctrl 0 0 96>; power-domains = <&cpg>; resets = <&cpg 0xa5>, <&cpg 0xa6>; @@ -211,6 +307,32 @@ resets = <&cpg 0x30>; }; + tsu0: thermal@11000000 { + compatible = "renesas,r9a09g056-tsu", "renesas,r9a09g047-tsu"; + reg = <0 0x11000000 0 0x1000>; + interrupts = <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "adi", "adcmpi"; + clocks = <&cpg CPG_MOD 0x109>; + resets = <&cpg 0xf7>; + power-domains = <&cpg>; + #thermal-sensor-cells = <0>; + renesas,tsu-trim = <&sys 0x320>; + }; + + tsu1: thermal@14002000 { + compatible = "renesas,r9a09g056-tsu", "renesas,r9a09g047-tsu"; + reg = <0 0x14002000 0 0x1000>; + interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "adi", "adcmpi"; + clocks = <&cpg CPG_MOD 0x10a>; + resets = <&cpg 0xf8>; + power-domains = <&cpg>; + #thermal-sensor-cells = <0>; + renesas,tsu-trim = <&sys 0x330>; + }; + xspi: spi@11030000 { compatible = "renesas,r9a09g056-xspi", "renesas,r9a09g047-xspi"; reg = <0 0x11030000 0 0x10000>, @@ -232,6 +354,171 @@ status = "disabled"; }; + dmac0: dma-controller@11400000 { + compatible = "renesas,r9a09g056-dmac", "renesas,r9a09g057-dmac"; + reg = <0 0x11400000 0 0x10000>; + interrupts = <GIC_SPI 499 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 91 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 92 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 94 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 95 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 96 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 98 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 101 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 104 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 0x0>; + power-domains = <&cpg>; + resets = <&cpg 0x31>; + #dma-cells = <1>; + dma-channels = <16>; + renesas,icu = <&icu 4>; + }; + + dmac1: dma-controller@14830000 { + compatible = "renesas,r9a09g056-dmac", "renesas,r9a09g057-dmac"; + reg = <0 0x14830000 0 0x10000>; + interrupts = <GIC_SPI 495 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 0x1>; + power-domains = <&cpg>; + resets = <&cpg 0x32>; + #dma-cells = <1>; + dma-channels = <16>; + renesas,icu = <&icu 0>; + }; + + dmac2: dma-controller@14840000 { + compatible = "renesas,r9a09g056-dmac", "renesas,r9a09g057-dmac"; + reg = <0 0x14840000 0 0x10000>; + interrupts = <GIC_SPI 496 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 0x2>; + power-domains = <&cpg>; + resets = <&cpg 0x33>; + #dma-cells = <1>; + dma-channels = <16>; + renesas,icu = <&icu 1>; + }; + + dmac3: dma-controller@12000000 { + compatible = "renesas,r9a09g056-dmac", "renesas,r9a09g057-dmac"; + reg = <0 0x12000000 0 0x10000>; + interrupts = <GIC_SPI 497 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 64 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 65 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 69 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 71 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 0x3>; + power-domains = <&cpg>; + resets = <&cpg 0x34>; + #dma-cells = <1>; + dma-channels = <16>; + renesas,icu = <&icu 2>; + }; + + dmac4: dma-controller@12010000 { + compatible = "renesas,r9a09g056-dmac", "renesas,r9a09g057-dmac"; + reg = <0 0x12010000 0 0x10000>; + interrupts = <GIC_SPI 498 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 81 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 0x4>; + power-domains = <&cpg>; + resets = <&cpg 0x35>; + #dma-cells = <1>; + dma-channels = <16>; + renesas,icu = <&icu 3>; + }; + ostm0: timer@11800000 { compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; reg = <0x0 0x11800000 0x0 0x1000>; @@ -407,6 +694,349 @@ status = "disabled"; }; + canfd: can@12440000 { + compatible = "renesas,r9a09g056-canfd", "renesas,r9a09g047-canfd"; + reg = <0 0x12440000 0 0x40000>; + interrupts = <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 698 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 705 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 701 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "g_err", "g_recc", + "ch0_err", "ch0_rec", "ch0_trx", + "ch1_err", "ch1_rec", "ch1_trx", + "ch2_err", "ch2_rec", "ch2_trx", + "ch3_err", "ch3_rec", "ch3_trx", + "ch4_err", "ch4_rec", "ch4_trx", + "ch5_err", "ch5_rec", "ch5_trx"; + clocks = <&cpg CPG_MOD 0x9c>, <&cpg CPG_MOD 0x9d>, + <&cpg CPG_MOD 0x9e>; + clock-names = "fck", "ram_clk", "can_clk"; + assigned-clocks = <&cpg CPG_MOD 0x9e>; + assigned-clock-rates = <80000000>; + resets = <&cpg 0xa1>, <&cpg 0xa2>; + reset-names = "rstp_n", "rstc_n"; + power-domains = <&cpg>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + channel1 { + status = "disabled"; + }; + channel2 { + status = "disabled"; + }; + channel3 { + status = "disabled"; + }; + channel4 { + status = "disabled"; + }; + channel5 { + status = "disabled"; + }; + }; + + rspi0: spi@12800000 { + compatible = "renesas,r9a09g056-rspi", "renesas,r9a09g057-rspi"; + reg = <0x0 0x12800000 0x0 0x400>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 500 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 501 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "idle", "error", "end", "rx", "tx"; + clocks = <&cpg CPG_MOD 0x54>, + <&cpg CPG_MOD 0x55>, + <&cpg CPG_MOD 0x56>; + clock-names = "pclk", "pclk_sfr", "tclk"; + resets = <&cpg 0x7b>, <&cpg 0x7c>; + reset-names = "presetn", "tresetn"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rspi1: spi@12800400 { + compatible = "renesas,r9a09g056-rspi", "renesas,r9a09g057-rspi"; + reg = <0x0 0x12800400 0x0 0x400>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 502 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 503 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "idle", "error", "end", "rx", "tx"; + clocks = <&cpg CPG_MOD 0x57>, + <&cpg CPG_MOD 0x58>, + <&cpg CPG_MOD 0x59>; + clock-names = "pclk", "pclk_sfr", "tclk"; + resets = <&cpg 0x7d>, <&cpg 0x7e>; + reset-names = "presetn", "tresetn"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rspi2: spi@12800800 { + compatible = "renesas,r9a09g056-rspi", "renesas,r9a09g057-rspi"; + reg = <0x0 0x12800800 0x0 0x400>; + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 504 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 505 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "idle", "error", "end", "rx", "tx"; + clocks = <&cpg CPG_MOD 0x5a>, + <&cpg CPG_MOD 0x5b>, + <&cpg CPG_MOD 0x5c>; + clock-names = "pclk", "pclk_sfr", "tclk"; + resets = <&cpg 0x7f>, <&cpg 0x80>; + reset-names = "presetn", "tresetn"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rsci0: serial@12800c00 { + compatible = "renesas,r9a09g056-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12800c00 0 0x400>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x5d>, <&cpg CPG_MOD 0x5e>, + <&cpg CPG_MOD 0x61>, <&cpg CPG_MOD 0x60>, + <&cpg CPG_MOD 0x5f>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x81>, <&cpg 0x82>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci1: serial@12801000 { + compatible = "renesas,r9a09g056-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12801000 0 0x400>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x62>, <&cpg CPG_MOD 0x63>, + <&cpg CPG_MOD 0x66>, <&cpg CPG_MOD 0x65>, + <&cpg CPG_MOD 0x64>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x83>, <&cpg 0x84>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci2: serial@12801400 { + compatible = "renesas,r9a09g056-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12801400 0 0x400>; + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x67>, <&cpg CPG_MOD 0x68>, + <&cpg CPG_MOD 0x6b>, <&cpg CPG_MOD 0x6a>, + <&cpg CPG_MOD 0x69>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x85>, <&cpg 0x86>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci3: serial@12801800 { + compatible = "renesas,r9a09g056-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12801800 0 0x400>; + interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x6c>, <&cpg CPG_MOD 0x6d>, + <&cpg CPG_MOD 0x70>, <&cpg CPG_MOD 0x6f>, + <&cpg CPG_MOD 0x6e>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x87>, <&cpg 0x88>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci4: serial@12801c00 { + compatible = "renesas,r9a09g056-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12801c00 0 0x400>; + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x71>, <&cpg CPG_MOD 0x72>, + <&cpg CPG_MOD 0x75>, <&cpg CPG_MOD 0x74>, + <&cpg CPG_MOD 0x73>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x89>, <&cpg 0x8a>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci5: serial@12802000 { + compatible = "renesas,r9a09g056-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12802000 0 0x400>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x76>, <&cpg CPG_MOD 0x77>, + <&cpg CPG_MOD 0x7a>, <&cpg CPG_MOD 0x79>, + <&cpg CPG_MOD 0x78>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x8b>, <&cpg 0x8c>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci6: serial@12802400 { + compatible = "renesas,r9a09g056-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12802400 0 0x400>; + interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 154 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x7b>, <&cpg CPG_MOD 0x7c>, + <&cpg CPG_MOD 0x7f>, <&cpg CPG_MOD 0x7e>, + <&cpg CPG_MOD 0x7d>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x8d>, <&cpg 0x8e>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci7: serial@12802800 { + compatible = "renesas,r9a09g056-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12802800 0 0x400>; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 160 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x80>, <&cpg CPG_MOD 0x81>, + <&cpg CPG_MOD 0x84>, <&cpg CPG_MOD 0x83>, + <&cpg CPG_MOD 0x82>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x8f>, <&cpg 0x90>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci8: serial@12802c00 { + compatible = "renesas,r9a09g056-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12802c00 0 0x400>; + interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 164 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x85>, <&cpg CPG_MOD 0x86>, + <&cpg CPG_MOD 0x89>, <&cpg CPG_MOD 0x88>, + <&cpg CPG_MOD 0x87>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x91>, <&cpg 0x92>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci9: serial@12803000 { + compatible = "renesas,r9a09g056-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12803000 0 0x400>; + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x8a>, <&cpg CPG_MOD 0x8b>, + <&cpg CPG_MOD 0x8e>, <&cpg CPG_MOD 0x8d>, + <&cpg CPG_MOD 0x8c>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x93>, <&cpg 0x94>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + i2c0: i2c@14400400 { compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; reg = <0 0x14400400 0 0x400>; @@ -694,6 +1324,36 @@ status = "disabled"; }; + xhci: usb@15850000 { + compatible = "renesas,r9a09g056-xhci", "renesas,r9a09g047-xhci"; + reg = <0 0x15850000 0 0x10000>; + interrupts = <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "all", "smi", "hse", "pme", "xhc"; + clocks = <&cpg CPG_MOD 0xaf>; + power-domains = <&cpg>; + resets = <&cpg 0xaa>; + phys = <&usb3_phy>, <&usb3_phy>; + phy-names = "usb2-phy", "usb3-phy"; + status = "disabled"; + }; + + usb3_phy: usb-phy@15870000 { + compatible = "renesas,r9a09g056-usb3-phy", "renesas,r9a09g047-usb3-phy"; + reg = <0 0x15870000 0 0x10000>; + clocks = <&cpg CPG_MOD 0xb0>, + <&cpg CPG_CORE R9A09G056_USB3_0_CLKCORE>, + <&cpg CPG_CORE R9A09G056_USB3_0_REF_ALT_CLK_P>; + clock-names = "pclk", "core", "ref_alt_clk_p"; + power-domains = <&cpg>; + resets = <&cpg 0xaa>; + #phy-cells = <0>; + status = "disabled"; + }; + sdhi0: mmc@15c00000 { compatible = "renesas,sdhi-r9a09g056", "renesas,sdhi-r9a09g057"; reg = <0x0 0x15c00000 0 0x10000>; @@ -955,6 +1615,95 @@ }; }; }; + + dsi: dsi@16430000 { + compatible = "renesas,r9a09g056-mipi-dsi", "renesas,r9a09g057-mipi-dsi"; + reg = <0 0x16430000 0 0x20000>; + interrupts = <GIC_SPI 874 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 875 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 876 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 877 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 878 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 879 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 880 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "seq0", "seq1", "vin1", "rcv", + "ferr", "ppi", "debug"; + clocks = <&cpg CPG_MOD 0xec>, <&cpg CPG_MOD 0xe9>, + <&cpg CPG_MOD 0xe8>, <&cpg CPG_MOD 0xea>, + <&cpg CPG_MOD 0xeb>; + clock-names = "pllrefclk", "aclk", "pclk", "vclk", "lpclk"; + resets = <&cpg 0xd8>, <&cpg 0xd7>; + reset-names = "arst", "prst"; + power-domains = <&cpg>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <&du_out_dsi>; + }; + }; + + port@1 { + reg = <1>; + dsi_out: endpoint { + }; + }; + }; + }; + + du: display@16460000 { + compatible = "renesas,r9a09g056-du", "renesas,r9a09g057-du"; + reg = <0 0x16460000 0 0x10000>; + interrupts = <GIC_SPI 882 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 0xed>, <&cpg CPG_MOD 0xee>, + <&cpg CPG_MOD 0xef>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg 0xdc>; + renesas,vsps = <&vspd 0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_dsi: endpoint { + remote-endpoint = <&dsi_in>; + }; + }; + }; + }; + + fcpvd: fcp@16470000 { + compatible = "renesas,r9a09g056-fcpvd", "renesas,fcpv"; + reg = <0 0x16470000 0 0x10000>; + clocks = <&cpg CPG_MOD 0xed>, + <&cpg CPG_MOD 0xee>, + <&cpg CPG_MOD 0xef>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg 0xdc>; + }; + + vspd: vsp@16480000 { + compatible = "renesas,r9a09g056-vsp2", "renesas,r9a07g044-vsp2"; + reg = <0 0x16480000 0 0x10000>; + interrupts = <GIC_SPI 881 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 0xed>, + <&cpg CPG_MOD 0xee>, + <&cpg CPG_MOD 0xef>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg 0xdc>; + renesas,fcp = <&fcpvd>; + }; }; stmmac_axi_setup: stmmac-axi-config { @@ -964,6 +1713,51 @@ snps,blen = <16 8 4 0 0 0 0>; }; + thermal-zones { + sensor1_thermal: sensor1-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&tsu0>; + + trips { + sensor1_crit: sensor1-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + sensor2_thermal: sensor2-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&tsu1>; + + cooling-maps { + map0 { + trip = <&sensor2_target>; + cooling-device = <&cpu0 0 3>, <&cpu1 0 3>, + <&cpu2 0 3>, <&cpu3 0 3>; + contribution = <1024>; + }; + }; + + trips { + sensor2_target: trip-point { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; + }; + + sensor2_crit: sensor2-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, diff --git a/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts index 066e66b5d51a..9af50198d2f1 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts @@ -8,6 +8,7 @@ /dts-v1/; #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> #include "r9a09g056.dtsi" / { @@ -33,6 +34,29 @@ stdout-path = "serial0:115200n8"; }; + hdmi-out { + compatible = "hdmi-connector"; + type = "d"; + + port { + hdmi_con_out: endpoint { + remote-endpoint = <&adv7535_out>; + }; + }; + }; + + keys: keys { + compatible = "gpio-keys"; + + key-wakeup { + interrupts-extended = <&icu 0 IRQ_TYPE_EDGE_FALLING>; + linux,code = <KEY_WAKEUP>; + label = "NMI_SW"; + debounce-interval = <20>; + wakeup-source; + }; + }; + memory@48000000 { device_type = "memory"; /* first 128MB is reserved for secure area. */ @@ -82,12 +106,36 @@ #clock-cells = <0>; clock-frequency = <32768>; }; + + /* 12MHz oscillator for ADV7535 */ + y1: y1-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; }; &audio_extal_clk { clock-frequency = <22579200>; }; +&dsi { + status = "okay"; + + ports { + port@1 { + dsi_out: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&adv7535_in>; + }; + }; + }; +}; + +&du { + status = "okay"; +}; + &ehci0 { dr_mode = "otg"; status = "okay"; @@ -145,6 +193,40 @@ pinctrl-names = "default"; clock-frequency = <400000>; status = "okay"; + + adv7535: hdmi@3d { + compatible = "adi,adv7535"; + reg = <0x3d>, <0x3f>, <0x3c>, <0x38>; + reg-names = "main", "edid", "cec", "packet"; + clocks = <&y1>; + clock-names = "cec"; + avdd-supply = <®_1p8v>; + dvdd-supply = <®_1p8v>; + pvdd-supply = <®_1p8v>; + a2vdd-supply = <®_1p8v>; + v3p3-supply = <®_3p3v>; + v1p2-supply = <®_1p8v>; + adi,dsi-lanes = <4>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7535_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + + port@1 { + reg = <1>; + adv7535_out: endpoint { + remote-endpoint = <&hdmi_con_out>; + }; + }; + }; + }; }; &i2c6 { @@ -342,6 +424,11 @@ }; }; + usb3_pins: usb3 { + pinmux = <RZV2N_PORT_PINMUX(B, 0, 14)>, /* USB30_VBUSEN */ + <RZV2N_PORT_PINMUX(B, 1, 14)>; /* USB30_OVRCURN */ + }; + xspi_pins: xspi0 { ctrl { pins = "XSPI0_RESET0N", "XSPI0_CS0N", "XSPI0_CKP"; @@ -392,10 +479,20 @@ status = "okay"; }; +&usb3_phy { + status = "okay"; +}; + &wdt1 { status = "okay"; }; +&xhci { + pinctrl-0 = <&usb3_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + &xspi { pinctrl-0 = <&xspi_pins>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi index 4df32d7e9998..80cba9fcfe7b 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -690,6 +690,66 @@ status = "disabled"; }; + canfd: can@12440000 { + compatible = "renesas,r9a09g057-canfd", "renesas,r9a09g047-canfd"; + reg = <0 0x12440000 0 0x40000>; + interrupts = <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 698 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 705 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 701 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "g_err", "g_recc", + "ch0_err", "ch0_rec", "ch0_trx", + "ch1_err", "ch1_rec", "ch1_trx", + "ch2_err", "ch2_rec", "ch2_trx", + "ch3_err", "ch3_rec", "ch3_trx", + "ch4_err", "ch4_rec", "ch4_trx", + "ch5_err", "ch5_rec", "ch5_trx"; + clocks = <&cpg CPG_MOD 0x9c>, <&cpg CPG_MOD 0x9d>, + <&cpg CPG_MOD 0x9e>; + clock-names = "fck", "ram_clk", "can_clk"; + assigned-clocks = <&cpg CPG_MOD 0x9e>; + assigned-clock-rates = <80000000>; + resets = <&cpg 0xa1>, <&cpg 0xa2>; + reset-names = "rstp_n", "rstc_n"; + power-domains = <&cpg>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + channel1 { + status = "disabled"; + }; + channel2 { + status = "disabled"; + }; + channel3 { + status = "disabled"; + }; + channel4 { + status = "disabled"; + }; + channel5 { + status = "disabled"; + }; + }; + rspi0: spi@12800000 { compatible = "renesas,r9a09g057-rspi"; reg = <0x0 0x12800000 0x0 0x400>; @@ -753,6 +813,226 @@ status = "disabled"; }; + rsci0: serial@12800c00 { + compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12800c00 0 0x400>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x5d>, <&cpg CPG_MOD 0x5e>, + <&cpg CPG_MOD 0x61>, <&cpg CPG_MOD 0x60>, + <&cpg CPG_MOD 0x5f>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x81>, <&cpg 0x82>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci1: serial@12801000 { + compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12801000 0 0x400>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x62>, <&cpg CPG_MOD 0x63>, + <&cpg CPG_MOD 0x66>, <&cpg CPG_MOD 0x65>, + <&cpg CPG_MOD 0x64>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x83>, <&cpg 0x84>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci2: serial@12801400 { + compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12801400 0 0x400>; + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x67>, <&cpg CPG_MOD 0x68>, + <&cpg CPG_MOD 0x6b>, <&cpg CPG_MOD 0x6a>, + <&cpg CPG_MOD 0x69>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x85>, <&cpg 0x86>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci3: serial@12801800 { + compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12801800 0 0x400>; + interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x6c>, <&cpg CPG_MOD 0x6d>, + <&cpg CPG_MOD 0x70>, <&cpg CPG_MOD 0x6f>, + <&cpg CPG_MOD 0x6e>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x87>, <&cpg 0x88>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci4: serial@12801c00 { + compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12801c00 0 0x400>; + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x71>, <&cpg CPG_MOD 0x72>, + <&cpg CPG_MOD 0x75>, <&cpg CPG_MOD 0x74>, + <&cpg CPG_MOD 0x73>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x89>, <&cpg 0x8a>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci5: serial@12802000 { + compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12802000 0 0x400>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x76>, <&cpg CPG_MOD 0x77>, + <&cpg CPG_MOD 0x7a>, <&cpg CPG_MOD 0x79>, + <&cpg CPG_MOD 0x78>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x8b>, <&cpg 0x8c>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci6: serial@12802400 { + compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12802400 0 0x400>; + interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 154 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x7b>, <&cpg CPG_MOD 0x7c>, + <&cpg CPG_MOD 0x7f>, <&cpg CPG_MOD 0x7e>, + <&cpg CPG_MOD 0x7d>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x8d>, <&cpg 0x8e>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci7: serial@12802800 { + compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12802800 0 0x400>; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 160 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x80>, <&cpg CPG_MOD 0x81>, + <&cpg CPG_MOD 0x84>, <&cpg CPG_MOD 0x83>, + <&cpg CPG_MOD 0x82>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x8f>, <&cpg 0x90>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci8: serial@12802c00 { + compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12802c00 0 0x400>; + interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 164 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x85>, <&cpg CPG_MOD 0x86>, + <&cpg CPG_MOD 0x89>, <&cpg CPG_MOD 0x88>, + <&cpg CPG_MOD 0x87>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x91>, <&cpg 0x92>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci9: serial@12803000 { + compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12803000 0 0x400>; + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x8a>, <&cpg CPG_MOD 0x8b>, + <&cpg CPG_MOD 0x8e>, <&cpg CPG_MOD 0x8d>, + <&cpg CPG_MOD 0x8c>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x93>, <&cpg 0x94>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + i2c0: i2c@14400400 { compatible = "renesas,riic-r9a09g057"; reg = <0 0x14400400 0 0x400>; @@ -1087,6 +1367,66 @@ status = "disabled"; }; + xhci0: usb@15850000 { + compatible = "renesas,r9a09g057-xhci", "renesas,r9a09g047-xhci"; + reg = <0 0x15850000 0 0x10000>; + interrupts = <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "all", "smi", "hse", "pme", "xhc"; + clocks = <&cpg CPG_MOD 0xaf>; + power-domains = <&cpg>; + resets = <&cpg 0xaa>; + phys = <&usb3_phy0>, <&usb3_phy0>; + phy-names = "usb2-phy", "usb3-phy"; + status = "disabled"; + }; + + xhci1: usb@15860000 { + compatible = "renesas,r9a09g057-xhci", "renesas,r9a09g047-xhci"; + reg = <0 0x15860000 0 0x10000>; + interrupts = <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 763 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "all", "smi", "hse", "pme", "xhc"; + clocks = <&cpg CPG_MOD 0xb1>; + power-domains = <&cpg>; + resets = <&cpg 0xab>; + phys = <&usb3_phy1>, <&usb3_phy1>; + phy-names = "usb2-phy", "usb3-phy"; + status = "disabled"; + }; + + usb3_phy0: usb-phy@15870000 { + compatible = "renesas,r9a09g057-usb3-phy", "renesas,r9a09g047-usb3-phy"; + reg = <0 0x15870000 0 0x10000>; + clocks = <&cpg CPG_MOD 0xb0>, + <&cpg CPG_CORE R9A09G057_USB3_0_CLKCORE>, + <&cpg CPG_CORE R9A09G057_USB3_0_REF_ALT_CLK_P>; + clock-names = "pclk", "core", "ref_alt_clk_p"; + power-domains = <&cpg>; + resets = <&cpg 0xaa>; + #phy-cells = <0>; + status = "disabled"; + }; + + usb3_phy1: usb-phy@15880000 { + compatible = "renesas,r9a09g057-usb3-phy", "renesas,r9a09g047-usb3-phy"; + reg = <0 0x15880000 0 0x10000>; + clocks = <&cpg CPG_MOD 0xb2>, + <&cpg CPG_CORE R9A09G057_USB3_1_CLKCORE>, + <&cpg CPG_CORE R9A09G057_USB3_1_REF_ALT_CLK_P>; + clock-names = "pclk", "core", "ref_alt_clk_p"; + power-domains = <&cpg>; + resets = <&cpg 0xab>; + #phy-cells = <0>; + status = "disabled"; + }; + sdhi0: mmc@15c00000 { compatible = "renesas,sdhi-r9a09g057"; reg = <0x0 0x15c00000 0 0x10000>; @@ -1348,6 +1688,95 @@ }; }; }; + + dsi: dsi@16430000 { + compatible = "renesas,r9a09g057-mipi-dsi"; + reg = <0 0x16430000 0 0x20000>; + interrupts = <GIC_SPI 874 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 875 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 876 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 877 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 878 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 879 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 880 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "seq0", "seq1", "vin1", "rcv", + "ferr", "ppi", "debug"; + clocks = <&cpg CPG_MOD 0xec>, <&cpg CPG_MOD 0xe9>, + <&cpg CPG_MOD 0xe8>, <&cpg CPG_MOD 0xea>, + <&cpg CPG_MOD 0xeb>; + clock-names = "pllrefclk", "aclk", "pclk", "vclk", "lpclk"; + resets = <&cpg 0xd8>, <&cpg 0xd7>; + reset-names = "arst", "prst"; + power-domains = <&cpg>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <&du_out_dsi>; + }; + }; + + port@1 { + reg = <1>; + dsi_out: endpoint { + }; + }; + }; + }; + + du: display@16460000 { + compatible = "renesas,r9a09g057-du"; + reg = <0 0x16460000 0 0x10000>; + interrupts = <GIC_SPI 882 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 0xed>, <&cpg CPG_MOD 0xee>, + <&cpg CPG_MOD 0xef>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg 0xdc>; + renesas,vsps = <&vspd 0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_dsi: endpoint { + remote-endpoint = <&dsi_in>; + }; + }; + }; + }; + + fcpvd: fcp@16470000 { + compatible = "renesas,r9a09g057-fcpvd", "renesas,fcpv"; + reg = <0 0x16470000 0 0x10000>; + clocks = <&cpg CPG_MOD 0xed>, + <&cpg CPG_MOD 0xee>, + <&cpg CPG_MOD 0xef>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg 0xdc>; + }; + + vspd: vsp@16480000 { + compatible = "renesas,r9a09g057-vsp2", "renesas,r9a07g044-vsp2"; + reg = <0 0x16480000 0 0x10000>; + interrupts = <GIC_SPI 881 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 0xed>, + <&cpg CPG_MOD 0xee>, + <&cpg CPG_MOD 0xef>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg 0xdc>; + renesas,fcp = <&fcpvd>; + }; }; stmmac_axi_setup: stmmac-axi-config { diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts index 445fce156f73..dc4577ebf2e9 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts @@ -35,6 +35,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-out { + compatible = "hdmi-connector"; + type = "d"; + + port { + hdmi_con_out: endpoint { + remote-endpoint = <&adv7535_out>; + }; + }; + }; + keys: keys { compatible = "gpio-keys"; @@ -50,7 +61,7 @@ memory@48000000 { device_type = "memory"; /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x1 0xF8000000>; + reg = <0x0 0x48000000 0x1 0xf8000000>; }; memory@240000000 { @@ -103,12 +114,36 @@ #clock-cells = <0>; clock-frequency = <32768>; }; + + /* 12MHz crystal for ADV7535 */ + y1: y1-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; }; &audio_extal_clk { clock-frequency = <22579200>; }; +&dsi { + status = "okay"; + + ports { + port@1 { + dsi_out: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&adv7535_in>; + }; + }; + }; +}; + +&du { + status = "okay"; +}; + &ehci0 { dr_mode = "otg"; status = "okay"; @@ -174,6 +209,42 @@ clock-frequency = <400000>; status = "okay"; + + adv7535: hdmi@3d { + compatible = "adi,adv7535"; + reg = <0x3d>, <0x3f>, <0x3c>, <0x38>; + reg-names = "main", "edid", "cec", "packet"; + interrupt-parent = <&pinctrl>; + interrupts = <RZV2H_GPIO(7, 1) IRQ_TYPE_EDGE_FALLING>; + clocks = <&y1>; + clock-names = "cec"; + avdd-supply = <®_1p8v>; + dvdd-supply = <®_1p8v>; + pvdd-supply = <®_1p8v>; + a2vdd-supply = <®_1p8v>; + v3p3-supply = <®_3p3v>; + v1p2-supply = <®_1p8v>; + adi,dsi-lanes = <4>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7535_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + + port@1 { + reg = <1>; + adv7535_out: endpoint { + remote-endpoint = <&hdmi_con_out>; + }; + }; + }; + }; }; &i2c6 { @@ -384,6 +455,16 @@ }; }; + usb30_pins: usb30 { + pinmux = <RZV2H_PORT_PINMUX(B, 0, 14)>, /* USB30_VBUSEN */ + <RZV2H_PORT_PINMUX(B, 1, 14)>; /* USB30_OVRCURN */ + }; + + usb31_pins: usb31 { + pinmux = <RZV2H_PORT_PINMUX(6, 2, 14)>, /* USB31_VBUSEN */ + <RZV2H_PORT_PINMUX(6, 3, 14)>; /* USB31_OVRCURN */ + }; + xspi_pins: xspi0 { ctrl { pins = "XSPI0_RESET0N", "XSPI0_CS0N", "XSPI0_CKP"; @@ -450,10 +531,30 @@ status = "okay"; }; +&usb3_phy0 { + status = "okay"; +}; + +&usb3_phy1 { + status = "okay"; +}; + &wdt1 { status = "okay"; }; +&xhci0 { + pinctrl-0 = <&usb30_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&xhci1 { + pinctrl-0 = <&usb31_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + &xspi { pinctrl-0 = <&xspi_pins>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h48-kakip.dts b/arch/arm64/boot/dts/renesas/r9a09g057h48-kakip.dts index adf3ab8aef2b..3028ed406306 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057h48-kakip.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g057h48-kakip.dts @@ -27,7 +27,16 @@ memory@48000000 { device_type = "memory"; /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x1 0xF8000000>; + reg = <0x0 0x48000000 0x1 0xf8000000>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; }; reg_3p3v: regulator-3v3 { @@ -112,6 +121,18 @@ pinmux = <RZV2H_PORT_PINMUX(A, 5, 15)>; /* SD0_CD */ }; }; + + xspi_pins: xspi0 { + ctrl { + pins = "XSPI0_RESET0N", "XSPI0_CS0N", "XSPI0_CKP"; + output-enable; + }; + + io { + pins = "XSPI0_IO0", "XSPI0_IO1", "XSPI0_IO2", "XSPI0_IO3"; + renesas,output-impedance = <3>; + }; + }; }; &qextal_clk { @@ -134,3 +155,21 @@ status = "okay"; }; + +&xspi { + pinctrl-0 = <&xspi_pins>; + pinctrl-names = "default"; + assigned-clocks = <&cpg CPG_CORE R9A09G057_SPI_CLK_SPI>; + assigned-clock-rates = <133333334>; + status = "okay"; + + flash@0 { + /* W25Q256JWPIM */ + compatible = "jedec,spi-nor"; + reg = <0>; + vcc-supply = <®_1p8v>; + m25p,fast-read; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi index e5c98388023f..14d7fb6f8952 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi @@ -14,6 +14,17 @@ #size-cells = <2>; interrupt-parent = <&gic>; + cluster0_opp: opp-table-0 { + compatible = "operating-points-v2"; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -24,6 +35,9 @@ device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A09G077_CLK_CA55C0>; + #cooling-cells = <2>; + operating-points-v2 = <&cluster0_opp>; }; cpu1: cpu@100 { @@ -32,6 +46,9 @@ device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A09G077_CLK_CA55C1>; + #cooling-cells = <2>; + operating-points-v2 = <&cluster0_opp>; }; cpu2: cpu@200 { @@ -40,6 +57,9 @@ device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A09G077_CLK_CA55C2>; + #cooling-cells = <2>; + operating-points-v2 = <&cluster0_opp>; }; cpu3: cpu@300 { @@ -48,6 +68,9 @@ device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A09G077_CLK_CA55C3>; + #cooling-cells = <2>; + operating-points-v2 = <&cluster0_opp>; }; L3_CA55: cache-controller-0 { @@ -165,6 +188,109 @@ status = "disabled"; }; + rspi0: spi@80007000 { + compatible = "renesas,r9a09g077-rspi"; + reg = <0x0 0x80007000 0x0 0x400>; + interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 637 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 638 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 634 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 635 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "idle", "error", "end", "rx", "tx"; + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>, + <&cpg CPG_MOD 104>; + clock-names = "pclk", "pclkspi"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rspi1: spi@80007400 { + compatible = "renesas,r9a09g077-rspi"; + reg = <0x0 0x80007400 0x0 0x400>; + interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 643 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 639 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "idle", "error", "end", "rx", "tx"; + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>, + <&cpg CPG_MOD 105>; + clock-names = "pclk", "pclkspi"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rspi2: spi@80007800 { + compatible = "renesas,r9a09g077-rspi"; + reg = <0x0 0x80007800 0x0 0x400>; + interrupts = <GIC_SPI 646 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 648 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 644 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 645 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "idle", "error", "end", "rx", "tx"; + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>, + <&cpg CPG_MOD 106>; + clock-names = "pclk", "pclkspi"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rspi3: spi@81007000 { + compatible = "renesas,r9a09g077-rspi"; + reg = <0x0 0x81007000 0x0 0x400>; + interrupts = <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 653 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 649 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 650 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "idle", "error", "end", "rx", "tx"; + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>, + <&cpg CPG_MOD 602>; + clock-names = "pclk", "pclkspi"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + canfd: can@80040000 { + compatible = "renesas,r9a09g077-canfd"; + reg = <0 0x80040000 0 0x20000>; + interrupts = <GIC_SPI 633 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 632 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 627 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 628 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 626 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 629 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "g_err", "g_recc", + "ch0_err", "ch0_rec", "ch0_trx", + "ch1_err", "ch1_rec", "ch1_trx"; + clocks = <&cpg CPG_MOD 310>, + <&cpg CPG_CORE R9A09G077_CLK_PCLKH>, + <&cpg CPG_CORE R9A09G077_PCLKCAN>; + clock-names = "fck", "ram_clk", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R9A09G077_PCLKCAN>; + assigned-clock-rates = <80000000>; + power-domains = <&cpg>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + channel1 { + status = "disabled"; + }; + }; + wdt0: watchdog@80082000 { compatible = "renesas,r9a09g077-wdt"; reg = <0 0x80082000 0 0x400>, @@ -225,6 +351,17 @@ status = "disabled"; }; + tsu: thermal@80086000 { + compatible = "renesas,r9a09g077-tsu"; + reg = <0 0x80086000 0 0x1000>; + interrupts = <GIC_SPI 713 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "adi", "adcmpi"; + clocks = <&cpg CPG_MOD 307>; + power-domains = <&cpg>; + #thermal-sensor-cells = <0>; + }; + i2c0: i2c@80088000 { compatible = "renesas,riic-r9a09g077"; reg = <0 0x80088000 0 0x400>; @@ -270,6 +407,96 @@ status = "disabled"; }; + dmac0: dma-controller@800c0000 { + compatible = "renesas,r9a09g077-dmac"; + reg = <0 0x800c0000 0 0x1000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKH>; + power-domains = <&cpg>; + #dma-cells = <1>; + dma-channels = <16>; + renesas,icu = <&icu 0>; + }; + + dmac1: dma-controller@800c1000 { + compatible = "renesas,r9a09g077-dmac"; + reg = <0 0x800c1000 0 0x1000>; + interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKH>; + power-domains = <&cpg>; + #dma-cells = <1>; + dma-channels = <16>; + renesas,icu = <&icu 1>; + }; + + dmac2: dma-controller@800c2000 { + compatible = "renesas,r9a09g077-dmac"; + reg = <0 0x800c2000 0 0x1000>; + interrupts = <GIC_SPI 64 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 65 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 69 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 71 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKH>; + power-domains = <&cpg>; + #dma-cells = <1>; + dma-channels = <16>; + renesas,icu = <&icu 2>; + }; + gmac0: ethernet@80100000 { compatible = "renesas,r9a09g077-gbeth", "snps,dwmac-5.20"; reg = <0 0x80100000 0 0x10000>; @@ -759,7 +986,7 @@ icu: interrupt-controller@802a0000 { compatible = "renesas,r9a09g077-icu"; reg = <0 0x802a0000 0 0x10000>, - <0 0x812a0000 0 0x50>; + <0 0x812a0000 0 0x10000>; #interrupt-cells = <2>; #address-cells = <0>; interrupt-controller; @@ -839,6 +1066,9 @@ gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pinctrl 0 0 288>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&icu>; power-domains = <&cpg>; }; @@ -1013,6 +1243,37 @@ snps,blen = <16 8 4 0 0 0 0>; }; + thermal-zones { + cpu-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&tsu>; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&cpu0 0 1>, <&cpu1 0 1>, + <&cpu2 0 1>, <&cpu3 0 1>; + contribution = <1024>; + }; + }; + + trips { + target: trip-point { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; + }; + + sensor_crit: sensor-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts index b7706d0bc3aa..e9639bbb2d70 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts @@ -7,6 +7,8 @@ /dts-v1/; +#include <dt-bindings/input/input.h> + #include "r9a09g077m44.dtsi" /* @@ -26,6 +28,9 @@ * P17_4 = SD1_CD; SW2[3] = ON * P08_5 = SD1_PWEN; SW2[3] = ON * P08_6 = SD1_IOVS; SW2[3] = ON; SW5[3] = OFF; SW5[4] = ON + * To enable proper operation in 1.8V modes, CN77 must have pins 2 and 3 + * connected by the jumper. This connects SD1 power-supply control IC output + * back to VCC1833_7. */ #define SD1_MICRO_SD 1 @@ -57,6 +62,37 @@ model = "Renesas RZ/T2H EVK Board based on r9a09g077m44"; compatible = "renesas,rzt2h-evk", "renesas,r9a09g077m44", "renesas,r9a09g077"; + keys { + compatible = "gpio-keys"; + +#if (!SD1_MICRO_SD) + /* SW2-3: OFF */ + key-1 { + interrupts-extended = <&pinctrl RZT2H_GPIO(8, 6) IRQ_TYPE_EDGE_FALLING>; + linux,code = <KEY_1>; + label = "SW9"; + wakeup-source; + debounce-interval = <20>; + }; +#endif + + key-2 { + interrupts-extended = <&pinctrl RZT2H_GPIO(0, 3) IRQ_TYPE_EDGE_FALLING>; + linux,code = <KEY_2>; + label = "SW10"; + wakeup-source; + debounce-interval = <20>; + }; + + key-3 { + interrupts-extended = <&pinctrl RZT2H_GPIO(8, 7) IRQ_TYPE_EDGE_FALLING>; + linux,code = <KEY_3>; + label = "SW11"; + wakeup-source; + debounce-interval = <20>; + }; + }; + leds { compatible = "gpio-leds"; @@ -135,6 +171,44 @@ }; }; +&adc2 { + status = "okay"; + + channel@0 { + reg = <0x0>; + }; + + channel@1 { + reg = <0x1>; + }; + + channel@2 { + reg = <0x2>; + }; + + channel@3 { + reg = <0x3>; + }; + + channel@4 { + reg = <0x4>; + }; + + channel@5 { + reg = <0x5>; + }; +}; + +&canfd { + pinctrl-0 = <&can0_pins>; + pinctrl-names = "default"; + status = "okay"; + + channel0 { + status = "okay"; + }; +}; + &i2c0 { pinctrl-0 = <&i2c0_pins>; pinctrl-names = "default"; @@ -164,6 +238,17 @@ &pinctrl { /* + * CAN0 Pin Configuration: + * + * SW7[1] OFF; SW7[2] ON - Use P24_4 as CANTX0. + * SW7[3] OFF; SW7[4] ON - Use P24_3 as CANRX0. + */ + can0_pins: can0-pins { + pinmux = <RZT2H_PORT_PINMUX(24, 3, 0x19)>, /* CANRX0 */ + <RZT2H_PORT_PINMUX(24, 4, 0x19)>; /* CANTX0 */ + }; + + /* * GMAC2 Pin Configuration: * * SW2[6] OFF - connect MDC/MDIO of Ethernet port 2 to GMAC2 @@ -253,30 +338,3 @@ }; }; -&adc2 { - status = "okay"; - - channel@0 { - reg = <0x0>; - }; - - channel@1 { - reg = <0x1>; - }; - - channel@2 { - reg = <0x2>; - }; - - channel@3 { - reg = <0x3>; - }; - - channel@4 { - reg = <0x4>; - }; - - channel@5 { - reg = <0x5>; - }; -}; diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi index 0e0a9c1bc885..4a1339561332 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi @@ -14,6 +14,17 @@ #size-cells = <2>; interrupt-parent = <&gic>; + cluster0_opp: opp-table-0 { + compatible = "operating-points-v2"; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -24,6 +35,9 @@ device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A09G087_CLK_CA55C0>; + #cooling-cells = <2>; + operating-points-v2 = <&cluster0_opp>; }; cpu1: cpu@100 { @@ -32,6 +46,9 @@ device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A09G087_CLK_CA55C1>; + #cooling-cells = <2>; + operating-points-v2 = <&cluster0_opp>; }; cpu2: cpu@200 { @@ -40,6 +57,9 @@ device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A09G087_CLK_CA55C2>; + #cooling-cells = <2>; + operating-points-v2 = <&cluster0_opp>; }; cpu3: cpu@300 { @@ -48,6 +68,9 @@ device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A09G087_CLK_CA55C3>; + #cooling-cells = <2>; + operating-points-v2 = <&cluster0_opp>; }; L3_CA55: cache-controller-0 { @@ -165,6 +188,109 @@ status = "disabled"; }; + rspi0: spi@80007000 { + compatible = "renesas,r9a09g087-rspi", "renesas,r9a09g077-rspi"; + reg = <0x0 0x80007000 0x0 0x400>; + interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 637 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 638 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 634 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 635 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "idle", "error", "end", "rx", "tx"; + clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKM>, + <&cpg CPG_MOD 104>; + clock-names = "pclk", "pclkspi"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rspi1: spi@80007400 { + compatible = "renesas,r9a09g087-rspi", "renesas,r9a09g077-rspi"; + reg = <0x0 0x80007400 0x0 0x400>; + interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 643 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 639 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "idle", "error", "end", "rx", "tx"; + clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKM>, + <&cpg CPG_MOD 105>; + clock-names = "pclk", "pclkspi"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rspi2: spi@80007800 { + compatible = "renesas,r9a09g087-rspi", "renesas,r9a09g077-rspi"; + reg = <0x0 0x80007800 0x0 0x400>; + interrupts = <GIC_SPI 646 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 648 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 644 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 645 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "idle", "error", "end", "rx", "tx"; + clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKM>, + <&cpg CPG_MOD 106>; + clock-names = "pclk", "pclkspi"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rspi3: spi@81007000 { + compatible = "renesas,r9a09g087-rspi", "renesas,r9a09g077-rspi"; + reg = <0x0 0x81007000 0x0 0x400>; + interrupts = <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 653 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 649 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 650 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "idle", "error", "end", "rx", "tx"; + clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKM>, + <&cpg CPG_MOD 602>; + clock-names = "pclk", "pclkspi"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + canfd: can@80040000 { + compatible = "renesas,r9a09g087-canfd", "renesas,r9a09g077-canfd"; + reg = <0 0x80040000 0 0x20000>; + interrupts = <GIC_SPI 633 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 632 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 627 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 628 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 626 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 629 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "g_err", "g_recc", + "ch0_err", "ch0_rec", "ch0_trx", + "ch1_err", "ch1_rec", "ch1_trx"; + clocks = <&cpg CPG_MOD 310>, + <&cpg CPG_CORE R9A09G087_CLK_PCLKH>, + <&cpg CPG_CORE R9A09G087_PCLKCAN>; + clock-names = "fck", "ram_clk", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R9A09G087_PCLKCAN>; + assigned-clock-rates = <80000000>; + power-domains = <&cpg>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + channel1 { + status = "disabled"; + }; + }; + wdt0: watchdog@80082000 { compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt"; reg = <0 0x80082000 0 0x400>, @@ -225,6 +351,17 @@ status = "disabled"; }; + tsu: thermal@80086000 { + compatible = "renesas,r9a09g087-tsu", "renesas,r9a09g077-tsu"; + reg = <0 0x80086000 0 0x1000>; + interrupts = <GIC_SPI 713 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "adi", "adcmpi"; + clocks = <&cpg CPG_MOD 307>; + power-domains = <&cpg>; + #thermal-sensor-cells = <0>; + }; + i2c0: i2c@80088000 { compatible = "renesas,riic-r9a09g087", "renesas,riic-r9a09g077"; reg = <0 0x80088000 0 0x400>; @@ -270,6 +407,96 @@ status = "disabled"; }; + dmac0: dma-controller@800c0000 { + compatible = "renesas,r9a09g087-dmac", "renesas,r9a09g077-dmac"; + reg = <0 0x800c0000 0 0x1000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKH>; + power-domains = <&cpg>; + #dma-cells = <1>; + dma-channels = <16>; + renesas,icu = <&icu 0>; + }; + + dmac1: dma-controller@800c1000 { + compatible = "renesas,r9a09g087-dmac", "renesas,r9a09g077-dmac"; + reg = <0 0x800c1000 0 0x1000>; + interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKH>; + power-domains = <&cpg>; + #dma-cells = <1>; + dma-channels = <16>; + renesas,icu = <&icu 1>; + }; + + dmac2: dma-controller@800c2000 { + compatible = "renesas,r9a09g087-dmac", "renesas,r9a09g077-dmac"; + reg = <0 0x800c2000 0 0x1000>; + interrupts = <GIC_SPI 64 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 65 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 69 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 71 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKH>; + power-domains = <&cpg>; + #dma-cells = <1>; + dma-channels = <16>; + renesas,icu = <&icu 2>; + }; + gmac0: ethernet@80100000 { compatible = "renesas,r9a09g087-gbeth", "renesas,r9a09g077-gbeth", "snps,dwmac-5.20"; @@ -762,7 +989,7 @@ icu: interrupt-controller@802a0000 { compatible = "renesas,r9a09g087-icu", "renesas,r9a09g077-icu"; reg = <0 0x802a0000 0 0x10000>, - <0 0x812a0000 0 0x50>; + <0 0x812a0000 0 0x10000>; #interrupt-cells = <2>; #address-cells = <0>; interrupt-controller; @@ -842,6 +1069,9 @@ gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pinctrl 0 0 280>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&icu>; power-domains = <&cpg>; }; @@ -1016,6 +1246,37 @@ snps,blen = <16 8 4 0 0 0 0>; }; + thermal-zones { + cpu-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&tsu>; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&cpu0 0 1>, <&cpu1 0 1>, + <&cpu2 0 1>, <&cpu3 0 1>; + contribution = <1024>; + }; + }; + + trips { + target: trip-point { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; + }; + + sensor_crit: sensor-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, diff --git a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts index 17c0c79fbd96..19f0a2c06753 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts @@ -7,6 +7,8 @@ /dts-v1/; +#include <dt-bindings/input/input.h> + #include "r9a09g087m44.dtsi" /* @@ -28,8 +30,18 @@ #define SD0_SD (!SD0_EMMC) /* + * To enable CANFD interface disable both eMMC and SD card on SDHI0 by + * setting SD0_EMMC and SD0_SD macros to 0 as pins P12_0 and P12_1 + * will be used for CANFD interface. + */ +#define CANFD_ENABLE (!SD0_EMMC && !SD0_SD) + +/* * P17_4 = SD1_CD; DSW5[3] = ON; DSW19[1] = OFF; DSW19[2] = ON * P08_6 = SD1_IOVS; DSW5[3] = ON + * To enable proper operation in 1.8V modes, JP21 must have pins 2 and 3 + * connected by the jumper. This connects SD1 power-supply control IC output + * back to VCC1833_7. */ #define SD1_MICRO_SD 1 @@ -74,6 +86,34 @@ model = "Renesas RZ/N2H EVK Board based on r9a09g087m44"; compatible = "renesas,rzn2h-evk", "renesas,r9a09g087m44", "renesas,r9a09g087"; + keys { + compatible = "gpio-keys"; + + key-1 { + interrupts-extended = <&pinctrl RZT2H_GPIO(18, 2) IRQ_TYPE_EDGE_FALLING>; + linux,code = <KEY_1>; + label = "SW2"; + wakeup-source; + debounce-interval = <20>; + }; + + key-2 { + interrupts-extended = <&pinctrl RZT2H_GPIO(0, 4) IRQ_TYPE_EDGE_FALLING>; + linux,code = <KEY_2>; + label = "SW3"; + wakeup-source; + debounce-interval = <20>; + }; + + key-3 { + interrupts-extended = <&pinctrl RZT2H_GPIO(18, 7) IRQ_TYPE_EDGE_FALLING>; + linux,code = <KEY_3>; + label = "SW4"; + wakeup-source; + debounce-interval = <20>; + }; + }; + leds { compatible = "gpio-leds"; @@ -170,6 +210,82 @@ }; }; +&adc2 { + status = "okay"; + + channel@0 { + reg = <0x0>; + }; + + channel@1 { + reg = <0x1>; + }; + + channel@2 { + reg = <0x2>; + }; + + channel@3 { + reg = <0x3>; + }; + + channel@4 { + reg = <0x4>; + }; + + channel@5 { + reg = <0x5>; + }; + + channel@6 { + reg = <0x6>; + }; + + channel@7 { + reg = <0x7>; + }; + + channel@8 { + reg = <0x8>; + }; + + channel@9 { + reg = <0x9>; + }; + + channel@a { + reg = <0xa>; + }; + + channel@b { + reg = <0xb>; + }; + + channel@c { + reg = <0xc>; + }; + + channel@d { + reg = <0xd>; + }; + + channel@e { + reg = <0xe>; + }; +}; + +#if CANFD_ENABLE +&canfd { + pinctrl-0 = <&can1_pins>; + pinctrl-names = "default"; + status = "okay"; + + channel1 { + status = "okay"; + }; +}; +#endif + #if I2C0 &i2c0 { pinctrl-0 = <&i2c0_pins>; @@ -207,6 +323,16 @@ &pinctrl { /* + * CAN1 Pin Configuration: + * + * DSW5[1] ON; DSW5[2] OFF - Use P12_0 and P12_1 for CAN1 interface. + */ + can1_pins: can1-pins { + pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x19)>, /* CANRX1 */ + <RZT2H_PORT_PINMUX(12, 1, 0x19)>; /* CANTX1 */ + }; + + /* * GMAC2 Pin Configuration: * * DSW5[6] OFF - connect MDC/MDIO of Ethernet port 2 to GMAC2 @@ -306,66 +432,3 @@ }; }; -&adc2 { - status = "okay"; - - channel@0 { - reg = <0x0>; - }; - - channel@1 { - reg = <0x1>; - }; - - channel@2 { - reg = <0x2>; - }; - - channel@3 { - reg = <0x3>; - }; - - channel@4 { - reg = <0x4>; - }; - - channel@5 { - reg = <0x5>; - }; - - channel@6 { - reg = <0x6>; - }; - - channel@7 { - reg = <0x7>; - }; - - channel@8 { - reg = <0x8>; - }; - - channel@9 { - reg = <0x9>; - }; - - channel@a { - reg = <0xa>; - }; - - channel@b { - reg = <0xb>; - }; - - channel@c { - reg = <0xc>; - }; - - channel@d { - reg = <0xd>; - }; - - channel@e { - reg = <0xe>; - }; -}; diff --git a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi index 58561da3007a..b607b5d6c259 100644 --- a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi +++ b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi @@ -13,6 +13,13 @@ * 0 - SMARC SDIO signal is connected to uSD1 * 1 - SMARC SDIO signal is connected to M.2 Key E connector * + * Please set the switch position SW_OPT_MUX.4 on the carrier board and the + * corresponding macro SW_SER0_PMOD on the board DTS: + * + * SW_SER0_PMOD: + * 0 - SER0 signals connect to M.2 Key-E, SER2 signals are unconnected + * 1 - SER0 signals connect to PMOD, SER2 signals connect to M.2 Key-E + * * Please set the switch position SW_GPIO_CAN_PMOD on the carrier board and the * corresponding macro SW_GPIO8_CAN0_STB/SW_GPIO8_CAN0_STB on the board DTS: * @@ -37,12 +44,6 @@ stdout-path = "serial3:115200n8"; }; - aliases { - i2c0 = &i2c0; - serial3 = &scif0; - mmc1 = &sdhi1; - }; - can_transceiver0: can-phy0 { compatible = "ti,tcan1042"; #phy-cells = <0>; @@ -106,3 +107,11 @@ status = "okay"; }; + +&usb3_phy { + status = "okay"; +}; + +&xhci { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi index 7faa44510d98..3b571c096752 100644 --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi @@ -13,6 +13,10 @@ * 0 - SD0 is connected to eMMC (default) * 1 - SD0 is connected to uSD0 card * + * Switch position SYS.4, Macro SW_SER2_EN: + * 0 - Select Module DSI connector(GPIO) + * 1 - Select SER2 + * * Switch position SYS.5, Macro SW_LCD_EN: * 0 - Select Misc. Signals routing * 1 - Select LCD @@ -122,6 +126,14 @@ }; }; +&i3c { + pinctrl-0 = <&i3c_pins>; + pinctrl-names = "default"; + i2c-scl-hz = <400000>; + i3c-scl-hz = <12500000>; + status = "okay"; +}; + &mdio0 { phy0: ethernet-phy@7 { compatible = "ethernet-phy-id0022.1640", @@ -219,6 +231,12 @@ <RZG3E_PORT_PINMUX(3, 5, 1)>; /* SDA2 */ }; + i3c_pins: i3c { + pinmux = <RZG3E_PORT_PINMUX(2, 0, 2)>, /* I3C0_SCL */ + <RZG3E_PORT_PINMUX(2, 1, 2)>; /* I3C0_SDA */ + drive-push-pull; + }; + rtc_irq_pin: rtc-irq { pins = "PS1"; bias-pull-up; diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index 6f25ab617982..982f17aafbc5 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -168,6 +168,11 @@ }; }; +&pcie_port0 { + clocks = <&versa3 5>; + clock-names = "ref"; +}; + #if SW_CONFIG2 == SW_ON /* SD0 slot */ &sdhi0 { diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi index 6b0bb2c441af..70af605168b0 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi @@ -155,6 +155,12 @@ status = "okay"; }; +&pcie { + pinctrl-0 = <&pcie_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + &phyrst { status = "okay"; }; @@ -186,6 +192,11 @@ line-name = "key-3-gpio-irq"; }; + pcie_pins: pcie { + pinmux = <RZG2L_PORT_PINMUX(13, 2, 2)>, /* PCIE_RST_OUT_B */ + <RZG2L_PORT_PINMUX(13, 3, 2)>; /* PCIE_CLKREQ_B */ + }; + scif0_pins: scif0 { pinmux = <RZG2L_PORT_PINMUX(6, 3, 1)>, /* RXD */ <RZG2L_PORT_PINMUX(6, 4, 1)>; /* TXD */ diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi index 3eed1f3948e8..510399febf29 100644 --- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi +++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi @@ -69,6 +69,85 @@ #endif }; +/* + * ADC0 AN000 can be connected to a potentiometer on the board or + * exposed on ADC header. + * + * T2H: + * SW17[1] = ON, SW17[2] = OFF - Potentiometer + * SW17[1] = OFF, SW17[2] = ON - CN41 header + * N2H: + * DSW6[1] = OFF, DSW6[2] = ON - Potentiometer + * DSW6[1] = ON, DSW6[2] = OFF - CN3 header + */ +&adc0 { + status = "okay"; + + channel@0 { + reg = <0x0>; + }; + + channel@1 { + reg = <0x1>; + }; + + channel@2 { + reg = <0x2>; + }; + + channel@3 { + reg = <0x3>; + }; +}; + +/* + * ADC1 AN100 can be exposed on ADC header or on mikroBUS connector. + * + * T2H: + * SW18[1] = ON, SW18[2] = OFF - CN42 header + * SW18[1] = OFF, SW18[2] = ON - mikroBUS + * N2H: + * DSW6[3] = ON, DSW6[4] = OFF - CN4 header + * DSW6[3] = OFF, DSW6[4] = ON - mikroBUS + * + * ADC1 AN101 can be exposed on ADC header or on Grove2 connector. + * + * T2H: + * SW18[3] = ON, SW18[4] = OFF - CN42 header + * SW18[3] = OFF, SW18[4] = ON - Grove2 + * N2H: + * DSW6[5] = ON, DSW6[6] = OFF - CN4 header + * DSW6[5] = OFF, DSW6[6] = ON - Grove2 + * + * ADC1 AN102 can be exposed on ADC header or on Grove2 connector. + * + * T2H: + * SW18[5] = ON, SW18[6] = OFF - CN42 header + * SW18[5] = OFF, SW18[6] = ON - Grove2 + * N2H: + * DSW6[7] = ON, DSW6[8] = OFF - CN4 header + * DSW6[7] = OFF, DSW6[8] = ON - Grove2 + */ +&adc1 { + status = "okay"; + + channel@0 { + reg = <0x0>; + }; + + channel@1 { + reg = <0x1>; + }; + + channel@2 { + reg = <0x2>; + }; + + channel@3 { + reg = <0x3>; + }; +}; + &ehci { dr_mode = "otg"; status = "okay"; @@ -224,8 +303,7 @@ ctrl-pins { pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>, /* SD0_CLK */ <RZT2H_PORT_PINMUX(12, 1, 0x29)>, /* SD0_CMD */ - <RZT2H_PORT_PINMUX(22, 5, 0x29)>, /* SD0_CD */ - <RZT2H_PORT_PINMUX(22, 6, 0x29)>; /* SD0_WP */ + <RZT2H_PORT_PINMUX(22, 5, 0x29)>; /* SD0_CD */ }; }; @@ -282,6 +360,7 @@ pinctrl-names = "default", "state_uhs"; vmmc-supply = <®_3p3v>; vqmmc-supply = <&vqmmc_sdhi0>; + wp-gpios = <&pinctrl RZT2H_GPIO(22, 6) GPIO_ACTIVE_HIGH>; bus-width = <4>; sd-uhs-sdr50; sd-uhs-sdr104; @@ -315,81 +394,3 @@ timeout-sec = <60>; }; -/* - * ADC0 AN000 can be connected to a potentiometer on the board or - * exposed on ADC header. - * - * T2H: - * SW17[1] = ON, SW17[2] = OFF - Potentiometer - * SW17[1] = OFF, SW17[2] = ON - CN41 header - * N2H: - * DSW6[1] = OFF, DSW6[2] = ON - Potentiometer - * DSW6[1] = ON, DSW6[2] = OFF - CN3 header - */ -&adc0 { - status = "okay"; - - channel@0 { - reg = <0x0>; - }; - - channel@1 { - reg = <0x1>; - }; - - channel@2 { - reg = <0x2>; - }; - - channel@3 { - reg = <0x3>; - }; -}; - -/* - * ADC1 AN100 can be exposed on ADC header or on mikroBUS connector. - * - * T2H: - * SW18[1] = ON, SW18[2] = OFF - CN42 header - * SW18[1] = OFF, SW18[2] = ON - mikroBUS - * N2H: - * DSW6[3] = ON, DSW6[4] = OFF - CN4 header - * DSW6[3] = OFF, DSW6[4] = ON - mikroBUS - * - * ADC1 AN101 can be exposed on ADC header or on Grove2 connector. - * - * T2H: - * SW18[3] = ON, SW18[4] = OFF - CN42 header - * SW18[3] = OFF, SW18[4] = ON - Grove2 - * N2H: - * DSW6[5] = ON, DSW6[6] = OFF - CN4 header - * DSW6[5] = OFF, DSW6[6] = ON - Grove2 - * - * ADC1 AN102 can be exposed on ADC header or on Grove2 connector. - * - * T2H: - * SW18[5] = ON, SW18[6] = OFF - CN42 header - * SW18[5] = OFF, SW18[6] = ON - Grove2 - * N2H: - * DSW6[7] = ON, DSW6[8] = OFF - CN4 header - * DSW6[7] = OFF, DSW6[8] = ON - Grove2 - */ -&adc1 { - status = "okay"; - - channel@0 { - reg = <0x0>; - }; - - channel@1 { - reg = <0x1>; - }; - - channel@2 { - reg = <0x2>; - }; - - channel@3 { - reg = <0x3>; - }; -}; diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi index fa8bfee07b3c..d4a921bed4c3 100644 --- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi +++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi @@ -501,7 +501,7 @@ }; }; - cs2000: clk_multiplier@4f { + cs2000: clk-multiplier@4f { #clock-cells = <0>; compatible = "cirrus,cs2000-cp"; reg = <0x4f>; @@ -890,7 +890,7 @@ reg = <0x00040000 0x140000>; read-only; }; - cert_header_sa6@180000 { + cert-header-sa6@180000 { reg = <0x00180000 0x040000>; read-only; }; diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi index a9e53b36f1d9..241caf737abb 100644 --- a/arch/arm64/boot/dts/renesas/ulcb.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi @@ -413,7 +413,7 @@ reg = <0x00040000 0x140000>; read-only; }; - cert_header_sa6@180000 { + cert-header-sa6@180000 { reg = <0x00180000 0x040000>; read-only; }; diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index dbdda9783e93..4d384f153c13 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -42,6 +42,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-geekbox.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-lba3368.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-lion-haikou.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-lion-haikou-video-demo.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-orion-r68-meta.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-px5-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb @@ -114,6 +115,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-powkiddy-rgb20sx.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-powkiddy-rgb30.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-powkiddy-rk2023.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-powkiddy-x55.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-qnap-ts133.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-radxa-cm3-io.dtb @@ -133,6 +135,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-bigtreetech-pi2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-tinker-board-3.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-tinker-board-3s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-9tripod-x3568-v4.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-anbernic-rg-ds.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-easepi-r1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb @@ -148,6 +151,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-odroid-m1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-photonicat.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-qnap-ts233.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-qnap-ts433.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-cm3j-rpi-cm4.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-roc-pc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb @@ -159,6 +163,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-100ask-dshanpi-a1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-armsom-sige5.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-armsom-sige5-v1.2-wifibt.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-evb1-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-evb1-v10-pcie1.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-luckfox-omni3576.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-nanopi-m5.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-nanopi-r76s.dtb @@ -209,6 +214,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-odroid-m2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5b.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-cm5-base.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-radxa-cm5-io.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-roc-pc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5c.dtb @@ -238,6 +245,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-ringneck-haikou-haikou-video-demo.dtb px30-ringneck-haikou-haikou-video-demo-dtbs := px30-ringneck-haikou.dtb \ px30-ringneck-haikou-video-demo.dtbo +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-lion-haikou-haikou-video-demo.dtb +rk3368-lion-haikou-haikou-video-demo-dtbs := rk3368-lion-haikou.dtb \ + rk3368-lion-haikou-video-demo.dtbo + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou-haikou-video-demo.dtb rk3399-puma-haikou-haikou-video-demo-dtbs := rk3399-puma-haikou.dtb \ rk3399-puma-haikou-video-demo.dtbo @@ -259,6 +270,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-armsom-sige5-v1.2-wifibt.dtb rk3576-armsom-sige5-v1.2-wifibt-dtbs := rk3576-armsom-sige5.dtb \ rk3576-armsom-sige5-v1.2-wifibt.dtbo +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-evb1-v10-pcie1.dtb +rk3576-evb1-v10-pcie1-dtbs := rk3576-evb1-v10.dtb \ + rk3576-evb1-v10-pcie1.dtbo + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-wifi.dtb rk3588-edgeble-neu6a-wifi-dtbs := rk3588-edgeble-neu6a-io.dtb \ rk3588-edgeble-neu6a-wifi.dtbo diff --git a/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou-video-demo.dtso b/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou-video-demo.dtso new file mode 100644 index 000000000000..2db0f3d9495b --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou-video-demo.dtso @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Cherry Embedded Solutions GmbH + * + * DEVKIT ADDON CAM-TS-A01 + * https://embedded.cherry.de/product/development-kit/ + * + * DT-overlay for the camera / DSI demo appliance for Haikou boards. + * In the flavour for use with a Lion system-on-module. + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/clock/rk3368-cru.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> + +&{/} { + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <&dc_12v>; + pwms = <&pwm1 0 25000 0>; + }; + + cam_afvdd_2v8: regulator-cam-afvdd-2v8 { + compatible = "regulator-fixed"; + gpio = <&pca9670 2 GPIO_ACTIVE_LOW>; + regulator-max-microvolt = <2800000>; + regulator-min-microvolt = <2800000>; + regulator-name = "cam-afvdd-2v8"; + vin-supply = <&vcc2v8_video>; + }; + + cam_avdd_2v8: regulator-cam-avdd-2v8 { + compatible = "regulator-fixed"; + gpio = <&pca9670 4 GPIO_ACTIVE_LOW>; + regulator-max-microvolt = <2800000>; + regulator-min-microvolt = <2800000>; + regulator-name = "cam-avdd-2v8"; + vin-supply = <&vcc2v8_video>; + }; + + cam_dovdd_1v8: regulator-cam-dovdd-1v8 { + compatible = "regulator-fixed"; + gpio = <&pca9670 3 GPIO_ACTIVE_LOW>; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "cam-dovdd-1v8"; + vin-supply = <&vcc1v8_video>; + }; + + cam_dvdd_1v2: regulator-cam-dvdd-1v2 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&pca9670 5 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1200000>; + regulator-name = "cam-dvdd-1v2"; + vin-supply = <&vcc3v3_baseboard>; + }; + + vcc1v8_video: regulator-vcc1v8-video { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vcc1v8-video"; + vin-supply = <&vcc3v3_baseboard>; + }; + + vcc2v8_video: regulator-vcc2v8-video { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2800000>; + regulator-min-microvolt = <2800000>; + regulator-name = "vcc2v8-video"; + vin-supply = <&vcc3v3_baseboard>; + }; + + video-adapter-leds { + compatible = "gpio-leds"; + + video-adapter-led { + color = <LED_COLOR_ID_BLUE>; + gpios = <&pca9670 7 GPIO_ACTIVE_HIGH>; + label = "video-adapter-led"; + linux,default-trigger = "none"; + }; + }; +}; + +&dphy { + status = "okay"; +}; + +&i2c_gp2 { + #address-cells = <1>; + #size-cells = <0>; + /* OV5675, GT911, DW9714 are limited to 400KHz */ + clock-frequency = <400000>; + + touchscreen@14 { + compatible = "goodix,gt911"; + reg = <0x14>; + interrupt-parent = <&gpio1>; + interrupts = <RK_PB5 IRQ_TYPE_LEVEL_LOW>; + irq-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&touch_int>; + pinctrl-names = "default"; + reset-gpios = <&pca9670 1 GPIO_ACTIVE_HIGH>; + AVDD28-supply = <&vcc2v8_video>; + VDDIO-supply = <&vcc3v3_baseboard>; + }; + + pca9670: gpio@27 { + compatible = "nxp,pca9670"; + reg = <0x27>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-0 = <&pca9670_resetn>; + pinctrl-names = "default"; + reset-gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_LOW>; + }; +}; + +&mipi_dsi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + panel@0 { + compatible = "leadtek,ltk050h3148w"; + reg = <0>; + backlight = <&backlight>; + iovcc-supply = <&vcc1v8_video>; + reset-gpios = <&pca9670 0 GPIO_ACTIVE_LOW>; + vci-supply = <&vcc2v8_video>; + + port { + mipi_in_panel: endpoint { + remote-endpoint = <&mipi_out_panel>; + }; + }; + }; +}; + +&mipi_out { + mipi_out_panel: endpoint { + remote-endpoint = <&mipi_in_panel>; + }; +}; + +&pinctrl { + pca9670 { + pca9670_resetn: pca9670-resetn { + rockchip,pins = <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + touch { + touch_int: touch-int { + rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts b/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts index ab70ee5f561a..1b3a498d3624 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts +++ b/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts @@ -18,16 +18,6 @@ stdout-path = "serial0:115200n8"; }; - i2cmux2 { - i2c@0 { - eeprom: eeprom@50 { - compatible = "atmel,24c01"; - pagesize = <8>; - reg = <0x50>; - }; - }; - }; - leds { pinctrl-0 = <&module_led_pins>, <&sd_card_led_pin>; @@ -68,6 +58,26 @@ }; }; +&display_subsystem { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&i2c_lvds_blc { + eeprom: eeprom@50 { + compatible = "atmel,24c01"; + pagesize = <8>; + reg = <0x50>; + }; +}; + +&pwm1 { + status = "okay"; +}; + &sdmmc { bus-width = <4>; cap-mmc-highspeed; @@ -103,6 +113,14 @@ status = "disabled"; }; +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + &pinctrl { pinctrl-names = "default"; pinctrl-0 = <&haikou_pin_hog>; diff --git a/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi b/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi index 8ccc3184a836..4b4305b90055 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi @@ -154,18 +154,21 @@ assigned-clocks = <&cru SCLK_MAC>; assigned-clock-parents = <&ext_gmac>; clock_in_out = "input"; + phy-handle = <&vsc8531_2>; phy-supply = <&vcc33_io>; phy-mode = "rgmii"; pinctrl-names = "default"; pinctrl-0 = <&rgmii_pins>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - snps,reset-gpio = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>; tx_delay = <0x10>; rx_delay = <0x10>; status = "okay"; }; +&hdmi { + avdd-0v9-supply = <&vdd10_video>; + avdd-1v8-supply = <&vcc18_video>; +}; + &i2c0 { status = "okay"; @@ -285,7 +288,25 @@ status = "okay"; }; +&mdio { + vsc8531_2: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + pinctrl-names = "default"; + pinctrl-0 = <&phy_rst>; + reset-assert-us = <10000>; + reset-deassert-us = <50000>; + reset-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>; + }; +}; + &pinctrl { + ethernet { + phy_rst: phy-rst { + rockchip,pins = <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + leds { module_led_pins: module-led-pins { rockchip,pins = diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi index ce4b112b082b..98d350768fd2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -498,7 +498,15 @@ "mac_clk_rx", "mac_clk_tx", "clk_mac_ref", "clk_mac_refout", "aclk_mac", "pclk_mac"; + resets = <&cru SRST_MAC>; + reset-names = "stmmaceth"; status = "disabled"; + + mdio: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; }; usb_host0_ehci: usb@ff500000 { @@ -875,6 +883,11 @@ reg = <0>; remote-endpoint = <&dsi_in_vop>; }; + + vop_out_hdmi: endpoint@1 { + reg = <1>; + remote-endpoint = <&hdmi_in_vop>; + }; }; }; @@ -933,6 +946,37 @@ status = "disabled"; }; + hdmi: hdmi@ff980000 { + compatible = "rockchip,rk3368-dw-hdmi"; + reg = <0x0 0xff980000 0x0 0x20000>; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>; + clock-names = "iahb", "isfr", "cec"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_i2c_xfer>; + power-domains = <&power RK3368_PD_VIO>; + reg-io-width = <4>; + rockchip,grf = <&grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + reg = <0>; + + hdmi_in_vop: endpoint { + remote-endpoint = <&vop_out_hdmi>; + }; + }; + + hdmi_out: port@1 { + reg = <1>; + }; + }; + }; + hevc_mmu: iommu@ff9a0440 { compatible = "rockchip,iommu"; reg = <0x0 0xff9a0440 0x0 0x40>, @@ -1196,6 +1240,13 @@ }; }; + hdmi { + hdmi_i2c_xfer: hdmi-i2c-xfer { + rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>, + <3 RK_PD3 1 &pcfg_pull_none>; + }; + }; + i2c0 { i2c0_xfer: i2c0-xfer { rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts index 810ab6ff4e67..753d51344954 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts @@ -421,10 +421,6 @@ status = "okay"; }; -&hdmi_sound { - status = "okay"; -}; - &i2c0 { clock-frequency = <400000>; i2c-scl-falling-time-ns = <4>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts index 5de964d369b0..8d26bd9b7500 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts @@ -451,7 +451,7 @@ status = "okay"; wcam: camera@1a { - compatible = "sony,imx258"; + compatible = "sony,imx258-pdaf"; reg = <0x1a>; clocks = <&cru SCLK_CIF_OUT>; /* MIPI_MCLK0, derived from CIF_CLKO */ lens-focus = <&wcam_lens>; @@ -520,6 +520,16 @@ touchscreen-size-x = <720>; touchscreen-size-y = <1440>; }; + + light-sensor@48 { + compatible = "sensortek,stk3311"; + reg = <0x48>; + interrupt-parent = <&gpio4>; + interrupts = <RK_PD3 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&light_int_l>; + proximity-near-level = <300>; + }; }; &i2c4 { @@ -533,7 +543,30 @@ reg = <0x68>; interrupt-parent = <&gpio1>; interrupts = <RK_PC6 IRQ_TYPE_LEVEL_LOW>; + vdd-supply = <&vcc_1v8>; vddio-supply = <&vcc_1v8>; + + mount-matrix = + "1", "0", "0", + "0", "-1", "0", + "0", "0", "-1"; + }; +}; + +&i2c4 { + af8133j: compass@1c { + compatible = "voltafield,af8133j"; + reg = <0x1c>; + avdd-supply = <&vcc_3v0>; + dvdd-supply = <&vcc_1v8>; + pinctrl-names = "default"; + pinctrl-0 = <&compass_rst_l>; + reset-gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_LOW>; + + mount-matrix = + "0", "1", "0", + "-1", "0", "0", + "0", "0", "1"; }; }; @@ -649,6 +682,12 @@ }; }; + compass { + compass_rst_l: compass-rst-l { + rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + leds { red_led_pin: red-led-pin { rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; @@ -689,6 +728,12 @@ }; }; + stk3311 { + light_int_l: light-int-l { + rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_input_pull_up>; + }; + }; + wifi { wifi_host_wake_l: wifi-host-wake-l { rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts index 8e3858cf988c..4f2831097624 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts @@ -116,6 +116,10 @@ reg = <0x11>; clocks = <&cru SCLK_I2S_8CH_OUT>; #sound-dai-cells = <0>; + AVDD-supply = <&vcca3v0_codec>; + DVDD-supply = <&vcca1v8_codec>; + HPVDD-supply = <&vcca3v0_codec>; + PVDD-supply = <&vcca1v8_codec>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi index fc9279627ef6..ac62e8f5d9f5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi @@ -408,7 +408,6 @@ vcca3v0_codec: LDO_REG5 { regulator-name = "vcca3v0_codec"; - regulator-always-on; regulator-boot-on; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts index 6d52e3723a4e..d9ff777b4913 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts @@ -453,6 +453,14 @@ regulator-off-in-suspend; }; }; + + eeprom@50 { + compatible = "belling,bl24c04a", "atmel,24c04"; + reg = <0x50>; + pagesize = <16>; + read-only; + vcc-supply = <&vcc_3v0_s0>; + }; }; &i2c3 { diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-4se.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-4se.dts index a8b8d4acc337..c0b931b3c640 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-4se.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-4se.dts @@ -8,6 +8,8 @@ #include "rk3399-t.dtsi" #include "rk3399-rock-pi-4.dtsi" +/delete-node/ &eeprom; + / { model = "Radxa ROCK 4SE"; compatible = "radxa,rock-4se", "rockchip,rk3399"; @@ -17,6 +19,16 @@ }; }; +&i2c0 { + eeprom@50 { + compatible = "belling,bl24c16a", "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + read-only; + vcc-supply = <&vcc_3v0>; + }; +}; + &sdio0 { status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi index 046dbe329017..a8ab043e4062 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi @@ -456,6 +456,14 @@ regulator-off-in-suspend; }; }; + + eeprom: eeprom@50 { + compatible = "belling,bl24c04a", "atmel,24c04"; + reg = <0x50>; + pagesize = <16>; + read-only; + vcc-supply = <&vcc_3v0>; + }; }; &i2c1 { diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64-v2.dts b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64-v2.dts index 304e3c51391c..883d9bcfe792 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64-v2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64-v2.dts @@ -28,3 +28,10 @@ }; }; }; + +&uart0 { + bluetooth { + compatible = "brcm,bcm4345c5"; + max-speed = <1500000>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts index 4b42717800f7..ae3ee91dba2f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts @@ -28,3 +28,10 @@ }; }; }; + +&uart0 { + bluetooth { + compatible = "brcm,bcm4345c5"; + max-speed = <1500000>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3528-armsom-sige1.dts b/arch/arm64/boot/dts/rockchip/rk3528-armsom-sige1.dts index 6e21579365a5..c41af8fc0c8d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528-armsom-sige1.dts +++ b/arch/arm64/boot/dts/rockchip/rk3528-armsom-sige1.dts @@ -232,6 +232,10 @@ }; }; +&combphy { + status = "okay"; +}; + &cpu0 { cpu-supply = <&vdd_arm>; }; @@ -293,6 +297,14 @@ }; }; +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pcie20_perstn>; + reset-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3>; + status = "okay"; +}; + &pinctrl { bluetooth { bt_reg_on_h: bt-reg-on-h { @@ -324,6 +336,12 @@ }; }; + pcie { + pcie20_perstn: pcie20-perstn { + rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + rtc { rtc_int_l: rtc-int-l { rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi index 5c6f8cc401c9..791719acb9dd 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi @@ -499,6 +499,40 @@ }; }; }; + + ebc_pmic: pmic@68 { + compatible = "ti,tps65185"; + reg = <0x68>; + interrupt-parent = <&gpio3>; + interrupts = <RK_PA6 IRQ_TYPE_LEVEL_LOW>; + enable-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&ebc_pmic_pins>; + pinctrl-names = "default"; + pwr-good-gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; + vcom-ctrl-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc_bat>; + wakeup-gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; + + regulators { + v3p3: v3p3 { + regulator-name = "v3p3"; + /* Keep it always on because IRQ is pulled up against this line */ + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcom: vcom { + regulator-name = "vcom"; + }; + + vposneg: vposneg { + regulator-name = "vposneg"; + regulator-min-microvolt = <15000000>; + regulator-max-microvolt = <15000000>; + }; + }; + }; }; &i2c5 { @@ -563,6 +597,21 @@ }; }; + ebc-pmic { + ebc_pmic_pins: ebc-pmic-pins { + rockchip,pins = /* wakeup */ + <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>, + /* int */ + <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, + /* pwr_good */ + <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>, + /* pwrup */ + <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>, + /* vcom_ctrl */ + <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + led { led_pin: led-pin { rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-qnap-ts133.dts b/arch/arm64/boot/dts/rockchip/rk3566-qnap-ts133.dts new file mode 100644 index 000000000000..d605a712de5b --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-qnap-ts133.dts @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Copyright (c) 2024 Heiko Stuebner <heiko@sntech.de> + */ + +/dts-v1/; + +#include "rk3566.dtsi" +#include "rk3568-qnap-tsx33.dtsi" + +/ { + model = "Qnap TS-133-2G NAS System 1-Bay"; + compatible = "qnap,ts133", "rockchip,rk3566"; + + aliases { + ethernet0 = &gmac1; + }; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "output"; + phy-handle = <&rgmii_phy0>; + phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus>; + status = "okay"; +}; + +&mcu { + compatible = "qnap,ts133-mcu"; +}; + +&mdio1 { + rgmii_phy0: ethernet-phy@3 { + /* Motorcomm YT8521 phy */ + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x3>; + pinctrl-0 = <ð_phy0_reset_pin>; + pinctrl-names = "default"; + reset-assert-us = <10000>; + reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + gmac1 { + eth_phy0_reset_pin: eth-phy0-reset-pin { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +/* connected to usb_host1_xhci */ +&usb2phy0_host { + phy-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +/* USB3 port on backside */ +&usb_host1_xhci { + dr_mode = "host"; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts b/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts index 80ac40555e02..fa28b32f6910 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts @@ -466,6 +466,7 @@ compatible = "belling,bl24c16a", "atmel,24c16"; reg = <0x50>; pagesize = <16>; + read-only; vcc-supply = <&vcca1v8_pmu>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-anbernic-rg-ds.dts b/arch/arm64/boot/dts/rockchip/rk3568-anbernic-rg-ds.dts new file mode 100644 index 000000000000..6ac1fe0d3c98 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-anbernic-rg-ds.dts @@ -0,0 +1,1237 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/gpio-keys.h> +#include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,vop2.h> +#include "rk3568.dtsi" + +/ { + model = "Anbernic RG DS"; + chassis-type = "handset"; + compatible = "anbernic,rg-ds", "rockchip,rk3568"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc0; + mmc2 = &sdmmc2; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + adc_keys_home: adc-keys-home { + compatible = "adc-keys"; + io-channel-names = "buttons"; + io-channels = <&saradc 0>; + keyup-threshold-microvolt = <1800000>; + poll-interval = <60>; + + button-home { + label = "HOME"; + linux,code = <BTN_MODE>; + press-threshold-microvolt = <1750>; + }; + }; + + adc_keys_play: adc-keys-play { + compatible = "adc-keys"; + io-channel-names = "buttons"; + io-channels = <&saradc 2>; + keyup-threshold-microvolt = <1300000>; + poll-interval = <60>; + + button-play { + label = "PLAY"; + linux,code = <KEY_PLAYPAUSE>; + press-threshold-microvolt = <1750>; + }; + }; + + adc_mux: adc-mux { + compatible = "io-channel-mux"; + channels = "left_x", "right_x", "left_y", "right_y"; + #io-channel-cells = <1>; + io-channels = <&saradc 3>; + io-channel-names = "parent"; + mux-controls = <&gpio_mux>; + settle-time-us = <100>; + }; + + adc-joystick { + compatible = "adc-joystick"; + #address-cells = <1>; + io-channels = <&adc_mux 0>, + <&adc_mux 1>, + <&adc_mux 2>, + <&adc_mux 3>; + pinctrl-0 = <&joy_mux_en>; + pinctrl-names = "default"; + poll-interval = <60>; + #size-cells = <0>; + + axis@0 { + reg = <0>; + abs-flat = <32>; + abs-fuzz = <32>; + abs-range = <1023 15>; + linux,code = <ABS_X>; + }; + + axis@1 { + reg = <1>; + abs-flat = <32>; + abs-fuzz = <32>; + abs-range = <15 1023>; + linux,code = <ABS_RY>; + }; + + axis@2 { + reg = <2>; + abs-flat = <32>; + abs-fuzz = <32>; + abs-range = <15 1023>; + linux,code = <ABS_Y>; + }; + + axis@3 { + reg = <3>; + abs-flat = <32>; + abs-fuzz = <32>; + abs-range = <15 1023>; + linux,code = <ABS_RX>; + }; + }; + + backlight0: backlight0 { + compatible = "pwm-backlight"; + enable-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + pwms = <&pwm12 0 25000 0>; + }; + + backlight1: backlight1 { + compatible = "pwm-backlight"; + enable-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; + pwms = <&pwm13 0 25000 0>; + }; + + /* + * Values taken from BSP device-tree except for + * "charge-full-design-microamp-hours" which was set + * incorrectly at 2500000 (based on markings on the battery it + * should be 4000000), "factory-internal-resistance-micro-ohms" + * which was set at 8 but based on context should likely be 80000. + * + * "constant-charge-current-max-microamp" is set at 10 AMPs + * which is likely incorrect but I cannot validate; furthermore + * the onboard charger of the rk817 cannot charge past 3.5A + * anyway. + */ + battery: battery { + compatible = "simple-battery"; + charge-full-design-microamp-hours = <4000000>; + charge-term-current-microamp = <300000>; + constant-charge-current-max-microamp = <10000000>; + constant-charge-voltage-max-microvolt = <4350000>; + factory-internal-resistance-micro-ohms = <80000>; + precharge-current-microamp = <180000>; + precharge-upper-limit-microvolt = <3600000>; + voltage-max-design-microvolt = <4350000>; + voltage-min-design-microvolt = <3000000>; + + /* + * BSP device-tree missing value for 5 percent, so I + * picked a value between 10 and 0. + */ + ocv-capacity-celsius = <20>; + ocv-capacity-table-0 = <4338000 100>, <4251000 95>, + <4191000 90>, <4136000 85>, + <4083000 80>, <4039000 75>, + <3978000 70>, <3947000 65>, + <3908000 60>, <3861000 55>, + <3826000 50>, <3786000 45>, + <3772000 40>, <3761000 35>, + <3749000 30>, <3731000 25>, + <3707000 20>, <3677000 15>, + <3663000 10>, <3446000 5>, + <3400000 0>; + }; + + gpio_keys_control: gpio-keys-control { + compatible = "gpio-keys"; + pinctrl-0 = <&gamepad_keys_l>; + pinctrl-names = "default"; + + button-a { + gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + label = "EAST"; + linux,code = <BTN_EAST>; + }; + + button-b { + gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; + label = "SOUTH"; + linux,code = <BTN_SOUTH>; + }; + + button-down { + gpios = <&gpio2 RK_PD5 GPIO_ACTIVE_LOW>; + label = "DPAD-DOWN"; + linux,code = <BTN_DPAD_DOWN>; + }; + + button-l1 { + gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_LOW>; + label = "TL"; + linux,code = <BTN_TL>; + }; + + button-l2 { + gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; + label = "TL2"; + linux,code = <BTN_TL2>; + }; + + button-left { + gpios = <&gpio2 RK_PD7 GPIO_ACTIVE_LOW>; + label = "DPAD-LEFT"; + linux,code = <BTN_DPAD_LEFT>; + }; + + button-menu { + gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; + label = "HOME"; + linux,code = <KEY_HOME>; + }; + + button-right { + gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_LOW>; + label = "DPAD-RIGHT"; + linux,code = <BTN_DPAD_RIGHT>; + }; + + button-r1 { + gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>; + label = "T2"; + linux,code = <BTN_TR>; + }; + + button-r2 { + gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>; + label = "TR2"; + linux,code = <BTN_TR2>; + }; + + button-select { + gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>; + label = "SELECT"; + linux,code = <BTN_SELECT>; + }; + + button-start { + gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_LOW>; + label = "START"; + linux,code = <BTN_START>; + }; + + button-thumbl { + gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_LOW>; + label = "THUMBL"; + linux,code = <BTN_THUMBL>; + }; + + button-thumbr { + gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; + label = "THUMBR"; + linux,code = <BTN_THUMBR>; + }; + + button-up { + gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_LOW>; + label = "DPAD-UP"; + linux,code = <BTN_DPAD_UP>; + }; + + button-x { + gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>; + label = "NORTH"; + linux,code = <BTN_NORTH>; + }; + + button-y { + gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; + label = "WEST"; + linux,code = <BTN_WEST>; + }; + }; + + gpio_keys_hall: gpio-keys-hall { + compatible = "gpio-keys"; + pinctrl-0 = <&hall_int_l>; + pinctrl-names = "default"; + + lid-switch { + gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>; + label = "LID"; + linux,code = <SW_LID>; + linux,input-type = <EV_SW>; + wakeup-event-action = <EV_ACT_DEASSERTED>; + wakeup-source; + }; + }; + + gpio_keys_volume: gpio-keys-volume { + compatible = "gpio-keys"; + autorepeat; + pinctrl-0 = <&vol_keys_l>; + pinctrl-names = "default"; + + vol-down-key { + gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>; + label = "VOLUMEDOWN"; + linux,code = <KEY_VOLUMEDOWN>; + }; + + vol-up-key { + gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>; + label = "VOLUMEUP"; + linux,code = <KEY_VOLUMEUP>; + }; + }; + + gpio_mux: mux-controller { + compatible = "gpio-mux"; + #mux-control-cells = <0>; + mux-gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>, + <&gpio3 RK_PC3 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&joy_mux_config>; + pinctrl-names = "default"; + }; + + leds: pwm-leds { + compatible = "pwm-leds"; + + green_led: led-0 { + color = <LED_COLOR_ID_GREEN>; + default-state = "on"; + function = LED_FUNCTION_POWER; + max-brightness = <255>; + pwms = <&pwm5 0 25000 0>; + }; + + amber_led: led-1 { + color = <LED_COLOR_ID_AMBER>; + function = LED_FUNCTION_CHARGING; + max-brightness = <255>; + pwms = <&pwm6 0 25000 0>; + }; + + red_led: led-2 { + color = <LED_COLOR_ID_RED>; + default-state = "off"; + function = LED_FUNCTION_STATUS; + max-brightness = <255>; + pwms = <&pwm7 0 25000 0>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clock-names = "ext_clock"; + clocks = <&rk817 1>; + pinctrl-0 = <&wifi_enable_h>; + pinctrl-names = "default"; + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_LOW>; + }; + + sound { + compatible = "simple-audio-card"; + pinctrl-0 = <&hp_det>; + pinctrl-names = "default"; + simple-audio-card,format = "i2s"; + simple-audio-card,hp-det-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rk817_ext"; + simple-audio-card,pin-switches = "Internal Speakers"; + simple-audio-card,routing = + "MICL", "Mic Jack", + "Headphones", "HPOL", + "Headphones", "HPOR", + "Internal Speakers", "HPOL", + "Internal Speakers", "HPOR"; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphones", + "Speaker", "Internal Speakers"; + + simple-audio-card,codec { + sound-dai = <&rk817>; + }; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + }; + + vdd_lcd0: regulator-vdd-lcd0 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&vdd_lcd0_h>; + pinctrl-names = "default"; + regulator-name = "vdd_lcd0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_lcd0: regulator-vccio-lcd0 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&vccio_lcd0_h>; + pinctrl-names = "default"; + regulator-name = "vccio_lcd0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_lcd1: regulator-vdd-lcd1 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&vdd_lcd1_h>; + pinctrl-names = "default"; + regulator-name = "vdd_lcd1"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_lcd1: regulator-vccio-lcd1 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&vccio_lcd1_h>; + pinctrl-names = "default"; + regulator-name = "vccio_lcd1"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: regulator-vcc3v3-sd { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&sdmmc_pwren_l>; + pinctrl-names = "default"; + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vccio_sd>; + }; + + vcc_sys: regulator-vcc-sys { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + regulator-name = "vcc_sys"; + }; + + vibrator: pwm-vibrator { + compatible = "pwm-vibrator"; + pwm-names = "enable"; + pwms = <&pwm14 0 100000 0>; + vcc-supply = <&vcc_sys>; + }; + + vcc_wifi: regulator-vcc-wifi { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&vcc_wifi_h>; + pinctrl-names = "default"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_wifi"; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&cru { + assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, + <&pmucru PLL_PPLL>, <&cru PLL_VPLL>; + assigned-clock-rates = <32768>, <1200000000>, + <200000000>, <292500000>; +}; + +&dsi0 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + ports { + dsi0_in: port@0 { + reg = <0>; + dsi0_in_vp0: endpoint { + remote-endpoint = <&vp0_out_dsi0>; + }; + }; + + dsi0_out: port@1 { + reg = <1>; + mipi_out_panel0: endpoint { + remote-endpoint = <&mipi_in_panel0>; + }; + }; + }; + + panel0: panel@0 { + compatible = "anbernic,rg-ds-display-bottom", "jadard,jd9365da-h3"; + reg = <0>; + backlight = <&backlight0>; + pinctrl-0 = <&lcd0_rst>; + pinctrl-names = "default"; + reset-gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_LOW>; + vdd-supply = <&vdd_lcd0>; + vccio-supply = <&vccio_lcd0>; + + port { + mipi_in_panel0: endpoint { + remote-endpoint = <&mipi_out_panel0>; + }; + }; + }; +}; + +&dsi1 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + ports { + dsi1_in: port@0 { + reg = <0>; + dsi1_in_vp1: endpoint { + remote-endpoint = <&vp1_out_dsi1>; + }; + }; + + dsi1_out: port@1 { + reg = <1>; + mipi_out_panel1: endpoint { + remote-endpoint = <&mipi_in_panel1>; + }; + }; + }; + + panel1: panel@0 { + compatible = "anbernic,rg-ds-display-top", "jadard,jd9365da-h3"; + reg = <0>; + backlight = <&backlight1>; + pinctrl-0 = <&lcd1_rst>; + pinctrl-names = "default"; + reset-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_LOW>; + vdd-supply = <&vdd_lcd1>; + vccio-supply = <&vccio_lcd1>; + + port { + mipi_in_panel1: endpoint { + remote-endpoint = <&mipi_out_panel1>; + }; + }; + }; +}; + +&dsi_dphy0 { + status = "okay"; +}; + +&dsi_dphy1 { + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk817: pmic@20 { + compatible = "rockchip,rk817"; + reg = <0x20>; + assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; + assigned-clocks = <&cru I2S1_MCLKOUT_TX>; + #clock-cells = <1>; + clock-names = "mclk"; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + clocks = <&cru I2S1_MCLKOUT_TX>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&i2s1m0_mclk &pmic_int_l>; + pinctrl-names = "default"; + #sound-dai-cells = <0>; + system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_sys>; + vcc9-supply = <&dcdc_boost>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-max-microvolt = <1350000>; + regulator-min-microvolt = <900000>; + regulator-name = "vdd_logic"; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-max-microvolt = <1350000>; + regulator-min-microvolt = <825000>; + regulator-name = "vdd_gpu"; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v3: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca1v8_pmu: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <900000>; + regulator-min-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <900000>; + regulator-min-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc2v8_dvp: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2800000>; + regulator-min-microvolt = <2800000>; + regulator-name = "vcc2v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + dcdc_boost: BOOST { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <5400000>; + regulator-min-microvolt = <4700000>; + regulator-name = "boost"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + otg_switch: OTG_SWITCH { + regulator-name = "otg_switch"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + rk817_charger: charger { + monitored-battery = <&battery>; + rockchip,resistor-sense-micro-ohms = <10000>; + rockchip,sleep-enter-current-microamp = <150000>; + rockchip,sleep-filter-current-microamp = <100000>; + }; + }; + + vdd_cpu: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1390000>; + regulator-min-microvolt = <712500>; + regulator-name = "vdd_cpu"; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc_sys>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* + * Currently the rk817_charger and the cw2015 don't work together. + * Disable the cw2015 for now because it performs the same function + * as the rk817_charger for battery monitoring. + */ + cw2015: battery@62 { + compatible = "cellwise,cw2015"; + reg = <0x62>; + cellwise,battery-profile = /bits/ 8 + < 0x17 0x67 0x81 0x6F 0x69 0x65 0x63 0x54 + 0x75 0x50 0x57 0x56 0x4E 0x4F 0x44 0x35 + 0x2C 0x24 0x1E 0x1B 0x24 0x32 0x41 0x4D + 0x1C 0x57 0x0B 0x85 0x34 0x54 0x59 0x6D + 0x85 0x81 0x81 0x84 0x3C 0x1B 0x6C 0x6C + 0x0B 0x41 0x1C 0x4D 0x80 0x95 0xA0 0x14 + 0x38 0x7E 0x98 0xA3 0x80 0x89 0x97 0xCB + 0x2F 0x00 0x64 0xA5 0xB5 0xC1 0x46 0xAE>; + cellwise,monitor-interval-ms = <5000>; + monitored-battery = <&battery>; + power-supplies = <&rk817_charger>; + status = "disabled"; + }; +}; + +&i2c2 { + clock-frequency = <200000>; + pinctrl-0 = <&i2c2m1_xfer>; + pinctrl-names = "default"; + status = "okay"; + + /* awinic,aw87391 at 0x58 */ + /* awinic,aw87391 at 0x5b */ + /* invensense,icm42607p at 0x68 */ +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-0 = <&i2c3m1_xfer>; + pinctrl-names = "default"; + status = "okay"; + + touch1: touchscreen@14 { + compatible = "goodix,gt911"; + reg = <0x14>; + AVDD28-supply = <&vcc2v8_dvp>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PC0 IRQ_TYPE_LEVEL_LOW>; + irq-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + panel = <&panel1>; + reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + touchscreen-size-x = <640>; + touchscreen-size-y = <480>; + touchscreen-inverted-x; + touchscreen-inverted-y; + pinctrl-0 = <&touch1_rst &touch1_irq>; + pinctrl-names = "default"; + VDDIO-supply = <&vcc3v3_pmu>; + }; +}; + +&i2c5 { + clock-frequency = <400000>; + pinctrl-0 = <&i2c5m0_xfer>; + pinctrl-names = "default"; + status = "okay"; + + touch0: touchscreen@14 { + compatible = "goodix,gt911"; + reg = <0x14>; + AVDD28-supply = <&vcc2v8_dvp>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PB6 IRQ_TYPE_LEVEL_LOW>; + irq-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + panel = <&panel0>; + reset-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; + touchscreen-size-x = <640>; + touchscreen-size-y = <480>; + pinctrl-0 = <&touch0_rst &touch0_irq>; + pinctrl-names = "default"; + VDDIO-supply = <&vcc3v3_pmu>; + }; + + /* Unused iSmartWare SW2001 encryption device at 0x3c */ +}; + +&i2s1_8ch { + pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_lrcktx &i2s1m0_sdi0 &i2s1m0_sdo0>; + pinctrl-names = "default"; + rockchip,trcm-sync-tx-only; + status = "okay"; +}; + +&pinctrl { + gpio-keys { + vol_keys_l: vol-keys_l { + rockchip,pins = + <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + gamepad_keys_l: gamepad-keys-l { + rockchip,pins = + <2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PD7 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gpio-lcd { + lcd0_rst: lcd0-rst { + rockchip,pins = + <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lcd1_rst: lcd1-rst { + rockchip,pins = + <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hall-sensor { + hall_int_l: hal-int-l { + rockchip,pins = + <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hp-detect { + hp_det: hp-det { + rockchip,pins = + <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + joy-mux { + joy_mux_en: joy-mux-en { + rockchip,pins = + <3 RK_PC1 RK_FUNC_GPIO &pcfg_output_low>; + }; + + joy_mux_config: joy-mux-config { + rockchip,pins = + <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>, + <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = + <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc { + sdmmc_pwren_l: sdmmc-pwren-l { + rockchip,pins = + <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + touch { + touch0_rst: touch0-rst { + rockchip,pins = + <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + touch0_irq: touch0-irq { + rockchip,pins = + <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + touch1_rst: touch1-rst { + rockchip,pins = + <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + touch1_irq: touch1-irq { + rockchip,pins = + <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + vcc-lcd { + vdd_lcd0_h: vdd-lcd0-h { + rockchip,pins = + <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vccio_lcd0_h: vccio-lcd0-h { + rockchip,pins = + <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vdd_lcd1_h: vdd-lcd1-h { + rockchip,pins = + <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vccio_lcd1_h: vccio-lcd1-h { + rockchip,pins = + <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + vcc-wifi { + vcc_wifi_h: vcc-wifi-h { + rockchip,pins = + <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi-irq { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = + <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&pmu_io_domains { + status = "okay"; + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_3v3>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; +}; + +&pwm5 { + pinctrl-0 = <&pwm5_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pwm6 { + pinctrl-0 = <&pwm6_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pwm7 { + pinctrl-0 = <&pwm7_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pwm12 { + pinctrl-0 = <&pwm12m1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pwm13 { + pinctrl-0 = <&pwm13m1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pwm14 { + pinctrl-0 = <&pwm14m0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + no-sd; + no-sdio; + non-removable; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe &emmc_rstnout>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + pinctrl-names = "default"; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&sdmmc2 { + #address-cells = <1>; + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + max-frequency = <100000000>; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_clk &sdmmc2m0_cmd>; + pinctrl-names = "default"; + sd-uhs-sdr104; + #size-cells = <0>; + vmmc-supply = <&vcc_wifi>; + status = "okay"; + + sdio_wifi: wifi@1 { + reg = <1>; + interrupt-parent = <&gpio4>; + interrupts = <RK_PA1 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "host-wake"; + pinctrl-0 = <&wifi_host_wake_irq>; + pinctrl-names = "default"; + }; +}; + +&tsadc { + rockchip,hw-tshut-mode = <0>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart1 { + pinctrl-0 = <&uart1m1_xfer &uart1m1_ctsn &uart1m1_rtsn>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "realtek,rtl8821cs-bt", "realtek,rtl8723bs-bt"; + device-wake-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + host-wake-gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + }; +}; + +/* No DMA for a debug serial console. */ +&uart2 { + /delete-property/ dmas; + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "peripheral"; + phy-names = "usb2-phy"; + phys = <&usb2phy0_otg>; + maximum-speed = "high-speed"; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_otg { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_otg { + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&cru PLL_VPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_dsi0: endpoint@ROCKCHIP_VOP2_EP_MIPI0 { + reg = <ROCKCHIP_VOP2_EP_MIPI0>; + remote-endpoint = <&dsi0_in_vp0>; + }; +}; + +&vp1 { + vp1_out_dsi1: endpoint@ROCKCHIP_VOP2_EP_MIPI1 { + reg = <ROCKCHIP_VOP2_EP_MIPI1>; + remote-endpoint = <&dsi1_in_vp1>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts233.dts b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts233.dts index f16d1c628793..52b741376ef5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts233.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts233.dts @@ -6,6 +6,7 @@ /dts-v1/; +#include "rk3568.dtsi" #include "rk3568-qnap-tsx33.dtsi" / { @@ -17,8 +18,8 @@ }; }; -/* connected to sata2 */ -&combphy2 { +/* Connected to usb_host0_xhci */ +&combphy0 { status = "okay"; }; @@ -50,6 +51,17 @@ }; }; +&keys { + pinctrl-names = "default"; + pinctrl-0 = <©_button_pin>, <&reset_button_pin>; + + key-copy { + label = "copy"; + gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>; + linux,code = <KEY_COPY>; + }; +}; + &leds { led-1 { color = <LED_COLOR_ID_GREEN>; @@ -92,7 +104,7 @@ }; }; -&sata2 { +&sata1 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts index d1e3b7e7a280..7d2aedfe616d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts @@ -6,6 +6,7 @@ /dts-v1/; +#include "rk3568.dtsi" #include "rk3568-qnap-tsx33.dtsi" / { @@ -27,8 +28,8 @@ }; }; -/* connected to sata2 */ -&combphy2 { +/* Connected to usb_host0_xhci */ +&combphy0 { status = "okay"; }; @@ -60,6 +61,17 @@ }; }; +&keys { + pinctrl-names = "default"; + pinctrl-0 = <©_button_pin>, <&reset_button_pin>; + + key-copy { + label = "copy"; + gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>; + linux,code = <KEY_COPY>; + }; +}; + &leds { led-1 { color = <LED_COLOR_ID_GREEN>; @@ -150,7 +162,7 @@ }; }; -&sata2 { +&sata1 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-qnap-tsx33.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-qnap-tsx33.dtsi index f009275c72c8..cca7b7d0685f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-qnap-tsx33.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568-qnap-tsx33.dtsi @@ -1,7 +1,6 @@ #include <dt-bindings/input/input.h> #include <dt-bindings/leds/common.h> #include <dt-bindings/gpio/gpio.h> -#include "rk3568.dtsi" / { aliases { @@ -13,17 +12,11 @@ stdout-path = "serial2:115200n8"; }; - keys { + keys: keys { compatible = "gpio-keys"; - pinctrl-0 = <©_button_pin>, <&reset_button_pin>; + pinctrl-0 = <&reset_button_pin>; pinctrl-names = "default"; - key-copy { - label = "copy"; - gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>; - linux,code = <KEY_COPY>; - }; - key-reset { label = "reset"; gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_LOW>; @@ -113,13 +106,13 @@ }; }; -/* connected to usb_host0_xhci */ -&combphy0 { +/* Connected USB3 on TS133 / SATA1 on all the others */ +&combphy1 { status = "okay"; }; -/* connected to sata1 */ -&combphy1 { +/* Connected to SATA2 */ +&combphy2 { status = "okay"; }; @@ -485,7 +478,7 @@ status = "okay"; }; -&sata1 { +&sata2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi index 729e38b9f620..f97a0eb7f7c0 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi @@ -321,7 +321,7 @@ }; }; - vcc_3v3: SWITCH_REG1 { + gpio_vref: vcc_3v3: SWITCH_REG1 { regulator-name = "vcc_3v3"; regulator-always-on; regulator-boot-on; @@ -340,6 +340,14 @@ }; }; }; + + eeprom@50 { + compatible = "belling,bl24c16a", "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + read-only; + vcc-supply = <&gpio_vref>; + }; }; &pinctrl { diff --git a/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3j-rpi-cm4.dts b/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3j-rpi-cm4.dts new file mode 100644 index 000000000000..b91ac0ca854c --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3j-rpi-cm4.dts @@ -0,0 +1,204 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Radxa Computer (Shenzhen) Co., Ltd. + */ + +/dts-v1/; + +#include <dt-bindings/leds/common.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "rk3568-radxa-cm3j.dtsi" + +/ { + model = "Radxa CM3J on RPi CM4 IO Board"; + compatible = "radxa,cm3j-rpi-cm4", "radxa,cm3j", "rockchip,rk3568"; + + aliases { + ethernet0 = &gmac1; + mmc1 = &sdmmc0; + rtc0 = &pcf85063; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds-1 { + compatible = "gpio-leds"; + + led-1 { + color = <LED_COLOR_ID_RED>; + default-state = "on"; + function = LED_FUNCTION_POWER; + gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&npwr_led>; + }; + + led-2 { + color = <LED_COLOR_ID_GREEN>; + default-state = "on"; + function = LED_FUNCTION_STATUS; + gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&pi_nled_activity>; + }; + }; + + dc12v: regulator-12v0 { + compatible = "regulator-fixed"; + regulator-name = "dc12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + dc3v3_pcie: regulator-3v3-2 { + compatible = "regulator-fixed"; + regulator-name = "dc3v3_pcie"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc12v>; + }; + + gpio_vref: regulator-3v3-3 { + compatible = "regulator-fixed"; + regulator-name = "gpio_vref"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc3v3>; + }; + + dc5v: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "dc5v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc12v>; + }; +}; + +&combphy0 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&gmac1 { + status = "okay"; +}; + +&gpio0 { + nextrst-hog { + gpio-hog; + /* + * GPIO_ACTIVE_LOW + output-low here means that the pin is set + * to high, because output-low decides the value pre-inversion. + */ + gpios = <RK_PC0 GPIO_ACTIVE_LOW>; + line-name = "nEXTRST"; + output-low; + }; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + emc2301: fan-controller@2f { + compatible = "microchip,emc2301", "microchip,emc2305"; + reg = <0x2f>; + #address-cells = <1>; + #size-cells = <0>; + #pwm-cells = <3>; + + fan@0 { + reg = <0x0>; + pwms = <&emc2301 26000 0 1>; + #cooling-cells = <2>; + }; + }; + + pcf85063: rtc@51 { + compatible = "nxp,pcf85063a"; + reg = <0x51>; + wakeup-source; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&pinctrl { + leds { + npwr_led: npwr-led { + rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pi_nled_activity: pi-nled-activity { + rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pcie2x1 { + vpcie3v3-supply = <&dc3v3_pcie>; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + broken-cd; + disable-wp; + no-mmc; + no-sdio; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>; + vmmc-supply = <&dc3v3>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_otg { + status = "okay"; +}; + +&usb_host0_xhci { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3j.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3j.dtsi new file mode 100644 index 000000000000..f21e84955948 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3j.dtsi @@ -0,0 +1,558 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Radxa Computer (Shenzhen) Co., Ltd. + */ + +#include <dt-bindings/leds/common.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,vop2.h> +#include "rk3568.dtsi" + +/ { + aliases { + mmc0 = &sdhci; + mmc2 = &sdmmc2; + }; + + gmac1_clkin: clock-125m { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac1_clkin"; + #clock-cells = <0>; + }; + + leds-0 { + compatible = "gpio-leds"; + + led-0 { + color = <LED_COLOR_ID_GREEN>; + default-state = "on"; + function = LED_FUNCTION_POWER; + gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&gpio0_b4_led>; + }; + }; + + vcc3v3_sys: regulator-3v3-0 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc5v>; + }; + + vcc_3v3_1: regulator-3v3-1 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_1"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_reg_on_h_gpio3_d4>; + reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>; + clock_in_out = "input"; + phy-handle = <&rgmii_phy1>; + phy-mode = "rgmii-id"; + phy-supply = <&vcc_3v3_1>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_clkinout + &gmac1m1_rx_bus2 + &gmac1m1_tx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus>; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&i2c0 { + status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + #clock-cells = <1>; + clock-output-names = "rk809-clkout1", "rk809-clkout2"; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + system-power-controller; + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + wakeup-source; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + dc1v8: vccio_flash: vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + dc3v3: vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + vdd_cpu: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-ramp-delay = <2300>; + vin-supply = <&dc5v>; + }; +}; + +&i2c2 { + status = "okay"; + + eeprom@50 { + compatible = "belling,bl24c16a", "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + read-only; + vcc-supply = <&gpio_vref>; + }; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@0 { + compatible = "ethernet-phy-id001c.c916"; + reg = <0x0>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_rstn_gpio3_b0>; // GPIO4_C3 + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio4 RK_PC3 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + bluetooth { + bt_reg_on_h_gpio4_b2: bt-reg-on-h-gpio4-b2 { + rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_host_h_gpio4_b4: bt-wake-host-h-gpio4-b4 { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + host_wake_bt_h_gpio4_b5: host-wake-bt-h-gpio4-b5 { + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + ethernet { + gmac1_rstn_gpio3_b0: gmac1-rstn-gpio3-b0 { + rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + gpio0_b4_led: gpio0-b4-led { + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie20_clkreqnm2: pcie20_clkreqnm2 { + rockchip,pins = <1 RK_PB0 4 &pcfg_pull_none>; + }; + + pcie_nrst: pcie-nrst { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + wifi { + wifi_reg_on_h_gpio3_d4: wifi-reg-on-h-gpio3-d4 { + rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pcie2x1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie20_clkreqnm2 &pcie_nrst>; + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + supports-clkreq; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc_3v3>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vccio_flash>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + max-frequency = <200000000>; + no-sd; + no-sdio; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vccio_flash>; + status = "okay"; +}; + +&sdmmc2 { + #address-cells = <1>; + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + disable-wp; + keep-power-in-suspend; + max-frequency = <200000000>; + mmc-pwrseq = <&sdio_pwrseq>; + no-mmc; + no-sd; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_clk &sdmmc2m0_cmd>; + sd-uhs-sdr104; + #size-cells = <0>; + status = "okay"; + + wifi@1 { + compatible = "brcm,bcm43456-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + }; +}; + +&sfc { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <104000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + vcc-supply = <&vccio_flash>; + }; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart8 { + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn &uart8m0_rtsn>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4345c5"; + clocks = <&rk809 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + max-speed = <1500000>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_reg_on_h_gpio4_b2 + &bt_wake_host_h_gpio4_b4 + &host_wake_bt_h_gpio4_b5>; + shutdown-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + vbat-supply = <&vcc_3v3_1>; + vddio-supply = <&vcc_1v8>; + }; +}; + +&usb_host0_xhci { + extcon = <&usb2phy0>; + maximum-speed = "high-speed"; + phys = <&usb2phy0_otg>; + phy-names = "usb2-phy"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts index 44cfdfeed668..9214e38648f2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts @@ -532,6 +532,14 @@ }; }; }; + + eeprom@50 { + compatible = "belling,bl24c16a", "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + read-only; + vcc-supply = <&vcc3v3_pmu>; + }; }; &i2c3 { diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts index 3d0c1ccfaa79..69001e453732 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts @@ -480,6 +480,14 @@ }; }; }; + + eeprom@50 { + compatible = "belling,bl24c16a", "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + read-only; + vcc-supply = <&vcc3v3_sys>; + }; }; &i2c5 { diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi index e719a3df126c..658097ed6971 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -185,7 +185,7 @@ <0x0 0xf2000000 0x0 0x00100000>; ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>, <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x01e00000>, - <0x03000000 0x0 0x40000000 0x3 0x40000000 0x0 0x40000000>; + <0x03000000 0x3 0x40000000 0x3 0x40000000 0x0 0x40000000>; reg-names = "dbi", "apb", "config"; resets = <&cru SRST_PCIE30X1_POWERUP>; reset-names = "pipe"; @@ -238,7 +238,7 @@ <0x0 0xf0000000 0x0 0x00100000>; ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>, <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x01e00000>, - <0x03000000 0x0 0x40000000 0x3 0x80000000 0x0 0x40000000>; + <0x03000000 0x3 0x80000000 0x3 0x80000000 0x0 0x40000000>; reg-names = "dbi", "apb", "config"; resets = <&cru SRST_PCIE30X2_POWERUP>; reset-names = "pipe"; diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi index 8893b7b6cc9f..a2c4957a5899 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi @@ -1022,7 +1022,7 @@ power-domains = <&power RK3568_PD_PIPE>; ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>, - <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>; + <0x03000000 0x3 0x00000000 0x3 0x00000000 0x0 0x40000000>; resets = <&cru SRST_PCIE20_POWERUP>; reset-names = "pipe"; #address-cells = <3>; diff --git a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts index 3386084f6318..d372ba252af8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts @@ -156,16 +156,6 @@ vin-supply = <&vcc_5v0_sys>; }; - vcc_3v3_rtc_s5: regulator-vcc-3v3-rtc-s5 { - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_rtc_s5"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_5v0_sys>; - }; - vcc_3v3_s0: regulator-vcc-3v3-s0 { compatible = "regulator-fixed"; regulator-name = "vcc_3v3_s0"; @@ -822,8 +812,8 @@ }; headphone { - hp_det: hp-det { - rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + hp_det_l: hp-det-l { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; }; }; @@ -907,6 +897,11 @@ status = "okay"; }; +&saradc { + vref-supply = <&vcca_1v8_s0>; + status = "okay"; +}; + &sdhci { bus-width = <8>; full-pwr-cycle-in-suspend; diff --git a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10-pcie1.dtso b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10-pcie1.dtso new file mode 100644 index 000000000000..dccf4a5debdb --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10-pcie1.dtso @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * DT-overlay to enable the onboard PCIe x1 slot, which shares pins and the PHY + * with the USB3 host port. + * To use the PCIe slot, apply this overlay and flip the Dial_Switch_1 right + * next to the PCIe slot to low state (labeled "ON - PCIe1"). USB3 host port + * will be unusable (not even in 2.0 mode) + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/pinctrl/rockchip.h> + +&pcie1 { + pinctrl-0 = <&pcie1m0_pins &pcie1_rst>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pinctrl { + pcie1 { + pcie1_rst: pcie1-rst { + rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&usb_drd1_dwc3 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts index db8fef7a4f1b..f5746bc2970b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts @@ -223,6 +223,18 @@ vin-supply = <&vcc_3v3_s3>; }; + vcc3v3_sd: regulator-vcc-3v3-sd { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pwren>; + regulator-name = "vcc3v3_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s0>; + }; + vcc_ufs_s0: regulator-vcc-ufs-s0 { compatible = "regulator-fixed"; regulator-name = "vcc_ufs_s0"; @@ -246,6 +258,63 @@ regulator-max-microvolt = <1800000>; vin-supply = <&vcc_1v8_s3>; }; + + sound { + compatible = "simple-audio-card"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + simple-audio-card,name = "On-board Analog ES8388"; + simple-audio-card,aux-devs = <&hp_power>, <&spk_power>; + simple-audio-card,bitclock-master = <&masterdai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&masterdai>; + simple-audio-card,hp-det-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,routing = + "Headphone Power INL", "LOUT1", + "Headphone Power INR", "ROUT1", + "Speaker Power INL", "LOUT2", + "Speaker Power INR", "ROUT2", + "Headphones", "Headphone Power OUTL", + "Headphones", "Headphone Power OUTR", + "Speaker", "Speaker Power OUTL", + "Speaker", "Speaker Power OUTR", + "LINPUT1", "Main Mic", + "LINPUT2", "Main Mic", + "RINPUT1", "Headset Mic", + "RINPUT2", "Headset Mic"; + simple-audio-card,widgets = + "Microphone", "Main Mic", + "Microphone", "Headset Mic", + "Headphone", "Headphones", + "Speaker", "Speaker"; + + simple-audio-card,cpu { + sound-dai = <&sai1>; + }; + + masterdai: simple-audio-card,codec { + sound-dai = <&es8388>; + system-clock-frequency = <12288000>; + }; + }; + + hp_power: headphone-amplifier { + compatible = "simple-audio-amplifier"; + enable-gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_ctl>; + sound-name-prefix = "Headphone Power"; + }; + + spk_power: speaker-amplifier { + compatible = "simple-audio-amplifier"; + enable-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&spk_ctl>; + sound-name-prefix = "Speaker Power"; + VCC-supply = <&vcc5v0_device>; + }; }; &cpu_l0 { @@ -315,6 +384,10 @@ }; }; +&hdmi_sound { + status = "okay"; +}; + &hdptxphy { status = "okay"; }; @@ -708,6 +781,25 @@ }; }; +&i2c3 { + status = "okay"; + + es8388: audio-codec@10 { + compatible = "everest,es8388", "everest,es8328"; + reg = <0x10>; + AVDD-supply = <&vcca_3v3_s0>; + DVDD-supply = <&vcc_1v8_s0>; + HPVDD-supply = <&vcca_3v3_s0>; + PVDD-supply = <&vcc_1v8_s0>; + assigned-clocks = <&cru CLK_SAI1_MCLKOUT_TO_IO>; + assigned-clock-rates = <12288000>; + clocks = <&cru CLK_SAI1_MCLKOUT_TO_IO>; + pinctrl-names = "default"; + pinctrl-0 = <&sai1m0_mclk>; + #sound-dai-cells = <0>; + }; +}; + &mdio0 { rgmii_phy0: ethernet-phy@1 { compatible = "ethernet-phy-id001c.c916"; @@ -774,6 +866,20 @@ }; &pinctrl { + audio { + hp_det: hp-det { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + hp_ctl: hp-ctl { + rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + spk_ctl: spk-ctl { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + bluetooth { bt_reg_on: bt-reg-on { rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; @@ -810,6 +916,12 @@ }; }; + sdmmc { + sdmmc_pwren: sdmmc-pwren { + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + usb { usb_host_pwren: usb-host-pwren { rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; @@ -835,6 +947,19 @@ }; }; +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&sai1m0_lrck + &sai1m0_sclk + &sai1m0_sdi0 + &sai1m0_sdo0>; + status = "okay"; +}; + +&sai6 { + status = "okay"; +}; + &sdhci { bus-width = <8>; full-pwr-cycle-in-suspend; @@ -851,11 +976,15 @@ bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; disable-wp; max-frequency = <200000000>; no-sdio; no-mmc; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>; sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; vqmmc-supply = <&vccio_sd_s0>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3576-luckfox-core3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576-luckfox-core3576.dtsi index 9187012d6fa4..749f0a54b478 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-luckfox-core3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576-luckfox-core3576.dtsi @@ -246,6 +246,10 @@ }; }; +&hdmi_sound { + status = "okay"; +}; + &hdptxphy { status = "okay"; }; @@ -691,6 +695,10 @@ status = "okay"; }; +&sai6 { + status = "okay"; +}; + &saradc { vref-supply = <&vcca_1v8_s0>; status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts b/arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts index bb2cc2814b83..7406a4adf810 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts @@ -110,6 +110,22 @@ regulator-name = "vcc12v_dcin"; }; + vcc1v2_ufs_vccq: regulator-vcc1v2-ufs-vccq { + compatible = "regulator-fixed"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc1v2_ufs_vccq"; + vin-supply = <&vcc5v0_sys_s5>; + }; + + vcc1v8_ufs_vccq2: regulator-vcc1v8-ufs-vccq2 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_ufs_vccq2"; + vin-supply = <&vcc_1v8_s3>; + }; + vcc3v3_m2_keym: regulator-vcc3v3-m2-keym { compatible = "regulator-fixed"; enable-active-high; @@ -205,7 +221,7 @@ simple-audio-card,format = "i2s"; simple-audio-card,hp-det-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_LOW>; simple-audio-card,mclk-fs = <256>; - simple-audio-card,name = "realtek,rt5616-codec"; + simple-audio-card,name = "Onboard Analog RT5616"; simple-audio-card,routing = "Headphones", "HPOL", @@ -326,6 +342,10 @@ }; }; +&hdmi_sound { + status = "okay"; +}; + &hdptxphy { status = "okay"; }; @@ -852,6 +872,10 @@ status = "okay"; }; +&sai6 { + status = "okay"; +}; + &saradc { vref-supply = <&vcca_1v8_s0>; status = "okay"; @@ -910,6 +934,14 @@ status = "okay"; }; +&ufshc { + vcc-supply = <&vcc_3v3_s3>; + vccq-supply = <&vcc1v2_ufs_vccq>; + vccq2-supply = <&vcc1v8_ufs_vccq2>; + vdd-hba-supply = <&vdda_1v2_s0>; + status = "okay"; +}; + &usbdp_phy { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3576-nanopi-r76s.dts b/arch/arm64/boot/dts/rockchip/rk3576-nanopi-r76s.dts index 31fbefaeceab..7ec27b05ff10 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-nanopi-r76s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-nanopi-r76s.dts @@ -192,6 +192,18 @@ regulator-name = "vcc_3v3_s0"; vin-supply = <&vcc_3v3_s3>; }; + + vcc3v3_sd: regulator-vcc-3v3-sd { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pwren>; + regulator-name = "vcc3v3_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s0>; + }; }; &combphy0_ps { @@ -726,6 +738,12 @@ }; }; + sdmmc { + sdmmc_pwren: sdmmc-pwren { + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + usb { usb_otg0_pwren_h: usb-otg0-pwren-h { rockchip,pins = <0 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; @@ -751,11 +769,14 @@ bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; disable-wp; no-mmc; no-sdio; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>; sd-uhs-sdr104; - vmmc-supply = <&vcc_3v3_s3>; + vmmc-supply = <&vcc3v3_sd>; vqmmc-supply = <&vccio_sd_s0>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3576-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3576-pinctrl.dtsi index 0b0851a7e4ea..98c9f8013158 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-pinctrl.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576-pinctrl.dtsi @@ -5228,6 +5228,13 @@ /* ufs_rstn */ <4 RK_PD0 1 &pcfg_pull_none>; }; + + /omit-if-no-ref/ + ufs_rstgpio: ufs-rstgpio { + rockchip,pins = + /* ufs_rstn */ + <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_down>; + }; }; ufs_testdata0 { diff --git a/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts b/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts index 7023dc326d0e..899a84b1fbf9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts @@ -682,6 +682,20 @@ }; }; +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m3_xfer>; + status = "okay"; + + eeprom@50 { + compatible = "belling,bl24c16f", "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + read-only; + vcc-supply = <&vcc_3v3_s3>; + }; +}; + &mdio0 { rgmii_phy0: ethernet-phy@1 { compatible = "ethernet-phy-id001c.c916"; diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi index c72343e7a045..49ccdf12ef7e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -680,6 +680,7 @@ "aclk_dbi", "pclk", "aux"; device_type = "pci"; + dma-coherent; interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, @@ -734,6 +735,7 @@ "aclk_dbi", "pclk", "aux"; device_type = "pci"; + dma-coherent; interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, @@ -1277,6 +1279,41 @@ status = "disabled"; }; + vdec: video-codec@27b00000 { + compatible = "rockchip,rk3576-vdec"; + reg = <0x0 0x27b00100 0x0 0x500>, + <0x0 0x27b00000 0x0 0x100>, + <0x0 0x27b00600 0x0 0x100>; + reg-names = "function", "link", "cache"; + interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_RKVDEC_ROOT>, <&cru HCLK_RKVDEC>, + <&cru ACLK_RKVDEC_ROOT_BAK>, <&cru CLK_RKVDEC_CORE>, + <&cru CLK_RKVDEC_HEVC_CA>; + clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; + assigned-clocks = <&cru ACLK_RKVDEC_ROOT>, <&cru CLK_RKVDEC_CORE>, + <&cru ACLK_RKVDEC_ROOT_BAK>, <&cru CLK_RKVDEC_HEVC_CA>; + assigned-clock-rates = <600000000>, <600000000>, + <500000000>, <1000000000>; + iommus = <&vdec_mmu>; + power-domains = <&power RK3576_PD_VDEC>; + resets = <&cru SRST_A_RKVDEC_BIU>, <&cru SRST_H_RKVDEC_BIU>, + <&cru SRST_H_RKVDEC>, <&cru SRST_RKVDEC_CORE>, + <&cru SRST_RKVDEC_HEVC_CA>; + reset-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; + sram = <&rkvdec_sram>; + }; + + vdec_mmu: iommu@27b00800 { + compatible = "rockchip,rk3576-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0x27b00800 0x0 0x40>, <0x0 0x27b00900 0x0 0x40>; + interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru CLK_RKVDEC_CORE>, <&cru HCLK_RKVDEC>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3576_PD_VDEC>; + rockchip,disable-mmu-reset; + #iommu-cells = <0>; + }; + vop: vop@27d00000 { compatible = "rockchip,rk3576-vop"; reg = <0x0 0x27d00000 0x0 0x3000>, <0x0 0x27d05000 0x0 0x1000>; @@ -1696,6 +1733,7 @@ clock-names = "stmmaceth", "clk_mac_ref", "pclk_mac", "aclk_mac", "ptp_ref"; + dma-coherent; interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq", "eth_wake_irq"; @@ -1743,6 +1781,7 @@ clock-names = "stmmaceth", "clk_mac_ref", "pclk_mac", "aclk_mac", "ptp_ref"; + dma-coherent; interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq", "eth_wake_irq"; @@ -1826,7 +1865,7 @@ assigned-clock-parents = <&cru CLK_REF_MPHY_26M>; interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&power RK3576_PD_USB>; - pinctrl-0 = <&ufs_refclk>; + pinctrl-0 = <&ufs_refclk &ufs_rstgpio>; pinctrl-names = "default"; resets = <&cru SRST_A_UFS_BIU>, <&cru SRST_A_UFS_SYS>, <&cru SRST_A_UFS>, <&cru SRST_P_UFS_GRF>; @@ -2680,6 +2719,7 @@ /* start address and size should be 4k align */ rkvdec_sram: rkvdec-sram@0 { reg = <0x0 0x78000>; + pool; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index 7ab12d1054a7..7fe9593d8c19 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -1353,6 +1353,70 @@ #iommu-cells = <0>; }; + vdec0: video-codec@fdc38000 { + compatible = "rockchip,rk3588-vdec"; + reg = <0x0 0xfdc38100 0x0 0x500>, + <0x0 0xfdc38000 0x0 0x100>, + <0x0 0xfdc38600 0x0 0x100>; + reg-names = "function", "link", "cache"; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>, <&cru CLK_RKVDEC0_CA>, + <&cru CLK_RKVDEC0_CORE>, <&cru CLK_RKVDEC0_HEVC_CA>; + clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; + assigned-clocks = <&cru ACLK_RKVDEC0>, <&cru CLK_RKVDEC0_CORE>, + <&cru CLK_RKVDEC0_CA>, <&cru CLK_RKVDEC0_HEVC_CA>; + assigned-clock-rates = <800000000>, <600000000>, + <600000000>, <1000000000>; + iommus = <&vdec0_mmu>; + power-domains = <&power RK3588_PD_RKVDEC0>; + resets = <&cru SRST_A_RKVDEC0>, <&cru SRST_H_RKVDEC0>, <&cru SRST_RKVDEC0_CA>, + <&cru SRST_RKVDEC0_CORE>, <&cru SRST_RKVDEC0_HEVC_CA>; + reset-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; + sram = <&vdec0_sram>; + }; + + vdec0_mmu: iommu@fdc38700 { + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0xfdc38700 0x0 0x40>, <0x0 0xfdc38740 0x0 0x40>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3588_PD_RKVDEC0>; + #iommu-cells = <0>; + }; + + vdec1: video-codec@fdc40000 { + compatible = "rockchip,rk3588-vdec"; + reg = <0x0 0xfdc40100 0x0 0x500>, + <0x0 0xfdc40000 0x0 0x100>, + <0x0 0xfdc40600 0x0 0x100>; + reg-names = "function", "link", "cache"; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>, <&cru CLK_RKVDEC1_CA>, + <&cru CLK_RKVDEC1_CORE>, <&cru CLK_RKVDEC1_HEVC_CA>; + clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; + assigned-clocks = <&cru ACLK_RKVDEC1>, <&cru CLK_RKVDEC1_CORE>, + <&cru CLK_RKVDEC1_CA>, <&cru CLK_RKVDEC1_HEVC_CA>; + assigned-clock-rates = <800000000>, <600000000>, + <600000000>, <1000000000>; + iommus = <&vdec1_mmu>; + power-domains = <&power RK3588_PD_RKVDEC1>; + resets = <&cru SRST_A_RKVDEC1>, <&cru SRST_H_RKVDEC1>, <&cru SRST_RKVDEC1_CA>, + <&cru SRST_RKVDEC1_CORE>, <&cru SRST_RKVDEC1_HEVC_CA>; + reset-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; + sram = <&vdec1_sram>; + }; + + vdec1_mmu: iommu@fdc40700 { + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0xfdc40700 0x0 0x40>, <0x0 0xfdc40740 0x0 0x40>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3588_PD_RKVDEC1>; + #iommu-cells = <0>; + }; + av1d: video-codec@fdc70000 { compatible = "rockchip,rk3588-av1-vpu"; reg = <0x0 0xfdc70000 0x0 0x800>; @@ -1955,7 +2019,7 @@ power-domains = <&power RK3588_PD_PCIE>; ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>, <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>, - <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>; + <0x03000000 0x9 0xc0000000 0x9 0xc0000000 0x0 0x40000000>; reg = <0xa 0x40c00000 0x0 0x00400000>, <0x0 0xfe180000 0x0 0x00010000>, <0x0 0xf3000000 0x0 0x00100000>; @@ -2007,7 +2071,7 @@ power-domains = <&power RK3588_PD_PCIE>; ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>, - <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>; + <0x03000000 0xa 0x00000000 0xa 0x00000000 0x0 0x40000000>; reg = <0xa 0x41000000 0x0 0x00400000>, <0x0 0xfe190000 0x0 0x00010000>, <0x0 0xf4000000 0x0 0x00100000>; @@ -3249,6 +3313,16 @@ ranges = <0x0 0x0 0xff001000 0xef000>; #address-cells = <1>; #size-cells = <1>; + + vdec0_sram: codec-sram@0 { + reg = <0x0 0x78000>; + pool; + }; + + vdec1_sram: codec-sram@78000 { + reg = <0x78000 0x77000>; + pool; + }; }; pinctrl: pinctrl { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts index ff1ba5ed56ef..c9d284cb738b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts @@ -522,6 +522,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pcie2_0_rst>, <&pcie2_0_wake>, <&pcie2_0_clkreq>, <&wifi_host_wake_irq>; reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + supports-clkreq; vpcie3v3-supply = <&vcc3v3_wlan>; status = "okay"; @@ -545,7 +546,8 @@ &pcie2x1l1 { reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; - pinctrl-0 = <&pcie2_1_rst>, <&rtl8111_isolate>; + pinctrl-0 = <&pcie2_1_rst>, <&rtl8111_isolate>, <&pcie30x1m1_1_clkreqn>; + supports-clkreq; status = "okay"; }; @@ -555,7 +557,8 @@ &pcie3x4 { pinctrl-names = "default"; - pinctrl-0 = <&pcie3_reset>; + pinctrl-0 = <&pcie3_reset>, <&pcie30x4m1_clkreqn>; + supports-clkreq; reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie30>; status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi index 6e5a58428bba..a2640014ee04 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi @@ -375,7 +375,7 @@ power-domains = <&power RK3588_PD_PCIE>; ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>, <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>, - <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>; + <0x03000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>; reg = <0xa 0x40000000 0x0 0x00400000>, <0x0 0xfe150000 0x0 0x00010000>, <0x0 0xf0000000 0x0 0x00100000>; @@ -462,7 +462,7 @@ power-domains = <&power RK3588_PD_PCIE>; ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>, <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>, - <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>; + <0x03000000 0x9 0x40000000 0x9 0x40000000 0x0 0x40000000>; reg = <0xa 0x40400000 0x0 0x00400000>, <0x0 0xfe160000 0x0 0x00010000>, <0x0 0xf1000000 0x0 0x00100000>; @@ -512,7 +512,7 @@ power-domains = <&power RK3588_PD_PCIE>; ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>, <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>, - <0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>; + <0x03000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>; reg = <0xa 0x40800000 0x0 0x00400000>, <0x0 0xfe170000 0x0 0x00010000>, <0x0 0xf2000000 0x0 0x00100000>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts index 5fbbeb6f5a93..10a7d3691a26 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts @@ -101,6 +101,17 @@ }; }; + hdmi1-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi1_con_in: endpoint { + remote-endpoint = <&hdmi1_out_con>; + }; + }; + }; + ir-receiver { compatible = "gpio-ir-receiver"; gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_LOW>; @@ -335,6 +346,22 @@ }; }; +&hdmi1 { + status = "okay"; +}; + +&hdmi1_in { + hdmi1_in_vp1: endpoint { + remote-endpoint = <&vp1_out_hdmi1>; + }; +}; + +&hdmi1_out { + hdmi1_out_con: endpoint { + remote-endpoint = <&hdmi1_con_in>; + }; +}; + &hdmi_receiver_cma { status = "okay"; }; @@ -350,6 +377,10 @@ status = "okay"; }; +&hdptxphy1 { + status = "okay"; +}; + /* Connected to MIPI-DSI0 */ &i2c5 { pinctrl-names = "default"; @@ -840,3 +871,10 @@ remote-endpoint = <&hdmi0_in_vp0>; }; }; + +&vp1 { + vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { + reg = <ROCKCHIP_VOP2_EP_HDMI1>; + remote-endpoint = <&hdmi1_in_vp1>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi index af431fdcbea7..49cf4b85c4e9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi @@ -182,7 +182,6 @@ reg = <0x42>; fcs,suspend-voltage-selector = <1>; regulator-name = "vdd_npu_s0"; - regulator-always-on; regulator-boot-on; regulator-min-microvolt = <550000>; regulator-max-microvolt = <950000>; @@ -264,6 +263,10 @@ domain-supply = <&vdd_gpu_s0>; }; +&pd_npu { + domain-supply = <&vdd_npu_s0>; +}; + &pinctrl { gpio-leds { led_sys_pin: led-sys-pin { @@ -294,6 +297,36 @@ }; }; +&rknn_core_0 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_1 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_2 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_mmu_0 { + status = "okay"; +}; + +&rknn_mmu_1 { + status = "okay"; +}; + +&rknn_mmu_2 { + status = "okay"; +}; + &saradc { vref-supply = <&avcc_1v8_s0>; status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts index 176925d0a1a8..952affaf455c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts @@ -393,7 +393,6 @@ reg = <0x42>; fcs,suspend-voltage-selector = <1>; regulator-name = "vdd_npu_s0"; - regulator-always-on; regulator-boot-on; regulator-min-microvolt = <550000>; regulator-max-microvolt = <950000>; @@ -564,6 +563,10 @@ domain-supply = <&vdd_gpu_s0>; }; +&pd_npu { + domain-supply = <&vdd_npu_s0>; +}; + &pinctrl { emmc { emmc_reset: emmc-reset { @@ -618,6 +621,36 @@ }; }; +&rknn_core_0 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_1 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_2 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_mmu_0 { + status = "okay"; +}; + +&rknn_mmu_1 { + status = "okay"; +}; + +&rknn_mmu_2 { + status = "okay"; +}; + &saradc { vref-supply = <&vcc_1v8_s0>; status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi index fafeabe9adf9..90e7fe254491 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi @@ -458,7 +458,6 @@ reg = <0x42>; fcs,suspend-voltage-selector = <1>; regulator-name = "vdd_npu_s0"; - regulator-always-on; regulator-boot-on; regulator-min-microvolt = <550000>; regulator-max-microvolt = <950000>; @@ -629,6 +628,10 @@ domain-supply = <&vdd_gpu_s0>; }; +&pd_npu { + domain-supply = <&vdd_npu_s0>; +}; + &pinctrl { gpio-leds { sys_led_pin: sys-led-pin { @@ -706,6 +709,37 @@ status = "okay"; }; +&rknn_core_0 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_1 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_2 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_mmu_0 { + status = "okay"; +}; + +&rknn_mmu_1 { + status = "okay"; +}; + +&rknn_mmu_2 { + status = "okay"; +}; + + &saradc { vref-supply = <&avcc_1v8_s0>; status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts index 172aeabba72a..de154adb1497 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts @@ -147,6 +147,24 @@ reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; }; + spdif_dit: spdif-dit { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + spdif_sound: spdif-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "SPDIF"; + + simple-audio-card,cpu { + sound-dai = <&spdif_tx1>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_dit>; + }; + }; + typec_vin: regulator-typec-vin { compatible = "regulator-fixed"; enable-active-high; @@ -854,6 +872,11 @@ }; }; +&spdif_tx1 { + pinctrl-0 = <&spdif1m2_tx>; + status = "okay"; +}; + &spi2 { status = "okay"; assigned-clocks = <&cru CLK_SPI2>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts index 07a840d9b385..30d15c7e860a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts @@ -69,6 +69,16 @@ }; }; +&i2c1 { + eeprom@50 { + compatible = "belling,bl24c16a", "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + read-only; + vcc-supply = <&vcc_3v3_s3>; + }; +}; + &pcie30phy { data-lanes = <1 1 2 2>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts index 0dd90c744380..425036146b6d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts @@ -60,6 +60,16 @@ status = "okay"; }; +&i2c1 { + eeprom@50 { + compatible = "belling,bl24c16a", "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + read-only; + vcc-supply = <&vcc_3v3_s3>; + }; +}; + &pcie2x1l1 { pinctrl-names = "default"; pinctrl-0 = <&pcie2_1_rst>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi index 365c1d958f2d..27269b7b08aa 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi @@ -197,7 +197,6 @@ reg = <0x42>; fcs,suspend-voltage-selector = <1>; regulator-name = "vdd_npu_s0"; - regulator-always-on; regulator-boot-on; regulator-min-microvolt = <550000>; regulator-max-microvolt = <950000>; @@ -340,6 +339,10 @@ domain-supply = <&vdd_gpu_s0>; }; +&pd_npu { + domain-supply = <&vdd_npu_s0>; +}; + &pinctrl { emmc { emmc_reset: emmc-reset { @@ -372,6 +375,36 @@ pinctrl-names = "default"; }; +&rknn_core_0 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_1 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_2 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_mmu_0 { + status = "okay"; +}; + +&rknn_mmu_1 { + status = "okay"; +}; + +&rknn_mmu_2 { + status = "okay"; +}; + &saradc { vref-supply = <&vcc_1v8_s0>; status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi index 6daea8961fdd..b11d24dcc180 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi @@ -171,7 +171,6 @@ reg = <0x42>; fcs,suspend-voltage-selector = <1>; regulator-name = "vdd_npu_s0"; - regulator-always-on; regulator-boot-on; regulator-min-microvolt = <550000>; regulator-max-microvolt = <950000>; @@ -293,6 +292,10 @@ domain-supply = <&vdd_gpu_s0>; }; +&pd_npu { + domain-supply = <&vdd_npu_s0>; +}; + &pinctrl { fan { fan_int: fan-int { @@ -333,6 +336,36 @@ status = "okay"; }; +&rknn_core_0 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_1 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_2 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_mmu_0 { + status = "okay"; +}; + +&rknn_mmu_1 { + status = "okay"; +}; + +&rknn_mmu_2 { + status = "okay"; +}; + &sdhci { bus-width = <8>; no-sdio; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts b/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts index 21eb003198fe..e8ad525ba3f9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts @@ -300,6 +300,20 @@ sound-name-prefix = "Headphones Amplifier"; }; + hdmi0-con { + compatible = "hdmi-connector"; + ddc-en-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&hdmi0_en>; + pinctrl-names = "default"; + type = "d"; + + port { + hdmi0_con_in: endpoint { + remote-endpoint = <&hdmi0_out_con>; + }; + }; + }; + pwm_fan: pwm-fan { compatible = "pwm-fan"; #cooling-cells = <2>; @@ -498,6 +512,34 @@ status = "okay"; }; +&hdmi0 { + no-hpd; + pinctrl-0 = <&hdmim0_tx0_cec>, <&hdmim0_tx0_scl>, + <&hdmim0_tx0_sda>; + pinctrl-names = "default"; + status = "okay"; +}; + +&hdmi0_in { + hdmi0_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi0>; + }; +}; + +&hdmi0_out { + hdmi0_out_con: endpoint { + remote-endpoint = <&hdmi0_con_in>; + }; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdptxphy0 { + status = "okay"; +}; + &i2c0 { pinctrl-0 = <&i2c0m2_xfer>; pinctrl-names = "default"; @@ -746,6 +788,10 @@ status = "okay"; }; +&i2s5_8ch { + status = "okay"; +}; + &mipidcphy0 { status = "okay"; }; @@ -846,6 +892,13 @@ }; }; + hdmi { + hdmi0_en: hdmi0-en { + rockchip,pins = + <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + hym8563 { hym8563_int: hym8563-int { rockchip,pins = @@ -1450,6 +1503,16 @@ status = "okay"; }; +&vp0 { + #address-cells = <1>; + #size-cells = <0>; + + vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi0_in_vp0>; + }; +}; + &vp3 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5-base.dts b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5-base.dts new file mode 100644 index 000000000000..06120b2db690 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5-base.dts @@ -0,0 +1,355 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/soc/rockchip,vop2.h> + +#include "rk3588s-orangepi-cm5.dtsi" + +/ { + model = "Xunlong Orange Pi CM5 Base"; + compatible = "xunlong,orangepi-cm5-base", "xunlong,orangepi-cm5", "rockchip,rk3588s"; + + aliases { + ethernet0 = &gmac1; + mmc1 = &sdmmc; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&key1_pin>; + + button { + debounce-interval = <50>; + gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>; + label = "USERKEY"; + linux,code = <BTN_MISC>; + wakeup-source; + }; + }; + + hdmi0-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi0_con_in: endpoint { + remote-endpoint = <&hdmi0_out_con>; + }; + }; + }; + + pwm-leds { + compatible = "pwm-leds"; + + led-1 { + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_STATUS; + linux,default-trigger = "heartbeat"; + max-brightness = <255>; + pwms = <&pwm2 0 25000 0>; + }; + + led-2 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_WAN; + max-brightness = <255>; + pwms = <&pwm4 0 25000 PWM_POLARITY_INVERTED>; + }; + + led-3 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_LAN; + function-enumerator = <0>; + max-brightness = <255>; + pwms = <&pwm5 0 25000 PWM_POLARITY_INVERTED>; + }; + + led-4 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_LAN; + function-enumerator = <1>; + max-brightness = <255>; + pwms = <&pwm6 0 25000 0>; + }; + }; + + vbus_5v0: regulator-vbus-5v0 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vbus_5v0_en_pin>; + regulator-name = "vbus_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_3v3: regulator-vcc-3v3 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_3v3_en_pin>; + regulator-name = "vcc_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <50000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: regulator-vcc-5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&gmac1 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-id"; + phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_miim + &gmac1_rx_bus2 + &gmac1_tx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + status = "okay"; +}; + +&hdmi0 { + pinctrl-names = "default"; + pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd + &hdmim0_tx0_scl &hdmim0_tx0_sda + &hdmi_frl_pin>; + status = "okay"; +}; + +&hdmi0_in { + hdmi0_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi0>; + }; +}; + +&hdmi0_out { + hdmi0_out_con: endpoint { + remote-endpoint = <&hdmi0_con_in>; + }; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdptxphy0 { + status = "okay"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1m2_xfer>; + status = "okay"; + + rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + interrupt-parent = <&gpio0>; + interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int_pin>; + wakeup-source; + }; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&mdio1 { + rgmii_phy: ethernet-phy@1 { + /* YT8531C */ + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_phy_pin>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_LOW>; + }; +}; + +&pcie2x1l1 { + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3>; + status = "okay"; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3>; + status = "okay"; +}; + +&pinctrl { + camera { + cam1_reset_pin: cam1-reset-pin { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + cam2_reset_pin: cam2-reset-pin { + rockchip,pins = <1 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + cam3_reset_pin: cam3-reset-pin { + rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + cam4_reset_pin: cam4-reset-pin { + rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + ethernet { + rgmii_phy_pin: rgmii-phy-pin { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + gpio-key { + key1_pin: key1-pin { + rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + hdmi { + hdmi_frl_pin: hdmi-frl-pin { + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + power { + vcc_3v3_en_pin: vcc-3v3-en-pin { + rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + rtc { + rtc_int_pin: rtc-int-pin { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vbus_5v0_en_pin: vbus-5v0-en-pin { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +&pwm5 { + pinctrl-0 = <&pwm5m1_pins>; + status = "okay"; +}; + +&pwm6 { + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + no-mmc; + no-sdio; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + phy-supply = <&vbus_5v0>; + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vbus_5v0>; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "host"; + status = "okay"; +}; + +&usbdp_phy0 { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi0_in_vp0>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5.dtsi new file mode 100644 index 000000000000..32357eba4b78 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5.dtsi @@ -0,0 +1,472 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <dt-bindings/clock/rockchip,rk3588-cru.h> +#include <dt-bindings/interrupt-controller/irq.h> + +#include "rk3588s.dtsi" +#include "rk8xx.h" + +/ { + aliases { + mmc0 = &sdhci; + }; + + /* Can't be verified due to missing schematics for the CM5. */ + vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + status = "okay"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + vdd_npu_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_npu_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&spi2 { + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + status = "okay"; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency = <1000000>; + system-power-controller; + rockchip,reset-mode = <RK806_RESET>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: dcdc-reg1 { + regulator-name = "vdd_gpu_s0"; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg2 { + regulator-name = "vdd_cpu_lit_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-name = "vdd_log_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: dcdc-reg4 { + regulator-name = "vdd_vdenc_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-name = "vdd_ddr_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-name = "vdd2_ddr_s3"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1100000>; + regulator-min-microvolt = <1100000>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-name = "vdd_2v0_pldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-name = "vcc_3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-name = "vddq_ddr_s0"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-name = "vcc_1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-name = "avcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-name = "vcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-name = "avdd_1v2_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-name = "vcc_3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-name = "vccio_sd_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-name = "pldo6_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-name = "vdd_0v75_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-name = "vdd_ddr_pll_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-name = "avdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-name = "vdd_0v85_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-name = "vdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&tsadc { + /* + * The TSADC_SHUT pin is exposed to carrier boards as a signal named + * PMIC_RESET_L, meant to be driven externally. Reference carrier + * boards connect it to a reset button that pulls the signal to GND + * through a 100Ω resistor. This is too weak to overcome even the + * minimum drive strength of the TSADC_SHUT pin when driven in + * push-pull mode. Configure it as a GPIO, reset will be generated + * through the CRU. + */ + pinctrl-0 = <&tsadc_gpio_func>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5-io.dts b/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5-io.dts new file mode 100644 index 000000000000..f80d5a00a4bd --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5-io.dts @@ -0,0 +1,339 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Joseph Kogut <joseph.kogut@gmail.com> + */ + +/* + * CM5 IO board data sheet + * https://dl.radxa.com/cm5/v2200/radxa_cm5_io_v2200_schematic.pdf + */ + +/dts-v1/; +#include "rk3588s.dtsi" +#include "rk3588s-radxa-cm5.dtsi" + +/ { + model = "Radxa Compute Module 5 (CM5) IO Board"; + compatible = "radxa,cm5-io", "radxa,cm5", "rockchip,rk3588s"; + + aliases { + ethernet0 = &gmac1; + mmc1 = &sdmmc; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi0_out_con>; + }; + }; + }; + + vcc12v_dcin: regulator-12v0-vcc-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: regulator-5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vbus5v0_typec: vbus5v0-typec { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec"; + gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vbus5v0_typec_en>; + enable-active-high; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie: regulator-3v3-vcc-pcie { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie2x1l0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; + startup-delay-us = <50000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_3v3_s0: pldo-reg4 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&gmac1 { + status = "okay"; +}; + +&hdmi0 { + status = "okay"; +}; + +&hdmi0_in { + hdmi0_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi0>; + }; +}; + +&hdmi0_out { + hdmi0_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdptxphy0 { + status = "okay"; +}; + +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m3_xfer>; + status = "okay"; + + fusb302: usb-typec@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PC4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec>; + + connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + power-role = "dual"; + try-power-role = "sink"; + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + sink-pdos = <PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>; + op-sink-microwatt = <1000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orientation_switch: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + usbc0_role_switch: endpoint { + remote-endpoint = <&usb_host0_xhci_role_switch>; + }; + }; + + port@2 { + reg = <2>; + usbc0_dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pinctrl { + fusb302 { + vbus5v0_typec_en: vbus5v0-typec-en { + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usbc0_int: usbc0-int { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + no-sdio; + sd-uhs-sdr104; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "otg"; + usb-role-switch; + status = "okay"; + + port { + usb_host0_xhci_role_switch: endpoint { + remote-endpoint = <&usbc0_role_switch>; + }; + }; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host2_xhci { + status = "okay"; +}; + +&usbdp_phy0 { + mode-switch; + orientation-switch; + sbu1-dc-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orientation_switch>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&usbc0_dp_altmode_mux>; + }; + }; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi0_in_vp0>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5.dtsi new file mode 100644 index 000000000000..d307e19052c6 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5.dtsi @@ -0,0 +1,280 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Joseph Kogut <joseph.kogut@gmail.com> + */ + +/* + * CM5 data sheet + * https://dl.radxa.com/cm5/v2210/radxa_cm5_v2210_schematic.pdf + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/soc/rockchip,vop2.h> +#include <dt-bindings/usb/pd.h> + +/ { + compatible = "radxa,cm5", "rockchip,rk3588s"; + + aliases { + mmc0 = &sdhci; + }; + + leds { + compatible = "gpio-leds"; + + led_sys: led-0 { + color = <LED_COLOR_ID_BLUE>; + default-state = "on"; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&gmac1 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy1>; + phy-mode = "rgmii-id"; + phy-supply = <&vcc_3v3_s0>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus + &gmac1_clkinout>; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&mdio1 { + rgmii_phy1: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + mmc-hs200-1_8v; + status = "okay"; +}; + +&spi2 { + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + status = "okay"; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency = <1000000>; + system-power-controller; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vdd2_ddr_s3>; + vcc14-supply = <&vdd2_ddr_s3>; + vcca-supply = <&vcc5v0_sys>; + + gpio-controller; + #gpio-cells = <2>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: dcdc-reg1 { + regulator-name = "vdd_gpu_s0"; + regulator-boot-on; + regulator-enable-ramp-delay = <400>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg2 { + regulator-name = "vdd_cpu_lit_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-name = "vdd2_ddr_s3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-name = "vdd_2v0_pldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-name = "vcc_3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts index 045a853d39ec..0991f6a21190 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts @@ -233,6 +233,7 @@ compatible = "belling,bl24c16a", "atmel,24c16"; reg = <0x50>; pagesize = <16>; + read-only; vcc-supply = <&vcc_3v3_pmu>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts index b837c4e08cec..7fe42f4ff827 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts @@ -325,6 +325,7 @@ compatible = "belling,bl24c16a", "atmel,24c16"; reg = <0x50>; pagesize = <16>; + read-only; vcc-supply = <&vcc_3v3_pmu>; }; }; diff --git a/arch/arm64/boot/dts/sprd/sc9860.dtsi b/arch/arm64/boot/dts/sprd/sc9860.dtsi index 864ef0a17425..765acde4867c 100644 --- a/arch/arm64/boot/dts/sprd/sc9860.dtsi +++ b/arch/arm64/boot/dts/sprd/sc9860.dtsi @@ -115,7 +115,7 @@ idle-states { entry-method = "psci"; - CORE_PD: core_pd { + CORE_PD: cpu-pd { compatible = "arm,idle-state"; entry-latency-us = <1000>; exit-latency-us = <700>; @@ -124,7 +124,7 @@ arm,psci-suspend-param = <0x00010002>; }; - CLUSTER_PD: cluster_pd { + CLUSTER_PD: cluster-pd { compatible = "arm,idle-state"; entry-latency-us = <1000>; exit-latency-us = <1000>; @@ -276,7 +276,8 @@ reg = <0 0x10003000 0 0x1000>; clocks = <&ext_26m>; clock-names = "apb_pclk"; - out-ports { + + in-ports { port { etb_in: endpoint { remote-endpoint = diff --git a/arch/arm64/boot/dts/sprd/sc9863a.dtsi b/arch/arm64/boot/dts/sprd/sc9863a.dtsi index e97000e560e7..31799579d7f2 100644 --- a/arch/arm64/boot/dts/sprd/sc9863a.dtsi +++ b/arch/arm64/boot/dts/sprd/sc9863a.dtsi @@ -110,7 +110,7 @@ idle-states { entry-method = "psci"; - CORE_PD: core-pd { + CORE_PD: cpu-pd { compatible = "arm,idle-state"; entry-latency-us = <4000>; exit-latency-us = <4000>; @@ -545,7 +545,7 @@ }; }; - ap-ahb { + ahb { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; diff --git a/arch/arm64/boot/dts/sprd/sharkl64.dtsi b/arch/arm64/boot/dts/sprd/sharkl64.dtsi index bf58702c4e07..1c8c23e04136 100644 --- a/arch/arm64/boot/dts/sprd/sharkl64.dtsi +++ b/arch/arm64/boot/dts/sprd/sharkl64.dtsi @@ -16,7 +16,7 @@ #size-cells = <2>; ranges; - ap-apb { + apb { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; diff --git a/arch/arm64/boot/dts/sprd/whale2.dtsi b/arch/arm64/boot/dts/sprd/whale2.dtsi index 2ecaa56001b8..87a834d4640c 100644 --- a/arch/arm64/boot/dts/sprd/whale2.dtsi +++ b/arch/arm64/boot/dts/sprd/whale2.dtsi @@ -81,7 +81,7 @@ #clock-cells = <1>; }; - ap-apb@70000000 { + apb@70000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -136,7 +136,7 @@ }; }; - ap-ahb { + ahb { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; @@ -183,7 +183,7 @@ }; }; - aon { + aon-bus { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; @@ -285,7 +285,7 @@ }; }; - agcp { + agcp-bus { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; diff --git a/arch/arm64/boot/dts/st/stm32mp21xc.dtsi b/arch/arm64/boot/dts/st/stm32mp21xc.dtsi deleted file mode 100644 index e33b00b424e1..000000000000 --- a/arch/arm64/boot/dts/st/stm32mp21xc.dtsi +++ /dev/null @@ -1,8 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2025 - All Rights Reserved - * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. - */ - -/ { -}; diff --git a/arch/arm64/boot/dts/st/stm32mp231.dtsi b/arch/arm64/boot/dts/st/stm32mp231.dtsi index 88e214d395ab..b5d81d1ee153 100644 --- a/arch/arm64/boot/dts/st/stm32mp231.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp231.dtsi @@ -251,6 +251,7 @@ <&hpdma 52 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 23>; + power-domains = <&cluster_pd>; status = "disabled"; }; @@ -281,6 +282,7 @@ <&hpdma 54 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 24>; + power-domains = <&cluster_pd>; status = "disabled"; }; @@ -359,6 +361,8 @@ <&hpdma 28 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 41>; + power-domains = <&cluster_pd>; + i2c-analog-filter; status = "disabled"; }; @@ -375,6 +379,8 @@ <&hpdma 31 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 42>; + power-domains = <&cluster_pd>; + i2c-analog-filter; status = "disabled"; }; @@ -391,6 +397,8 @@ <&hpdma 46 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 47>; + power-domains = <&cluster_pd>; + i2c-analog-filter; status = "disabled"; }; @@ -433,6 +441,7 @@ <&hpdma 50 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 22>; + power-domains = <&cluster_pd>; status = "disabled"; }; @@ -448,6 +457,7 @@ <&hpdma 56 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 25>; + power-domains = <&cluster_pd>; status = "disabled"; }; @@ -463,6 +473,7 @@ <&hpdma 58 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 26>; + power-domains = <&cluster_pd>; status = "disabled"; }; @@ -664,6 +675,8 @@ <&hpdma 169 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 48>; + power-domains = <&cluster_pd>; + i2c-analog-filter; status = "disabled"; }; @@ -676,6 +689,7 @@ <&rcc CK_KER_CSIPHY>; clock-names = "pclk", "txesc", "csi2phy"; access-controllers = <&rifsc 86>; + power-domains = <&cluster_pd>; status = "disabled"; }; @@ -687,6 +701,7 @@ clocks = <&rcc CK_BUS_DCMIPP>, <&rcc CK_KER_CSI>; clock-names = "kclk", "mclk"; access-controllers = <&rifsc 87>; + power-domains = <&cluster_pd>; status = "disabled"; }; @@ -761,11 +776,11 @@ #address-cells = <1>; #size-cells = <1>; - part_number_otp@24 { + part-number-otp@24 { reg = <0x24 0x4>; }; - package_otp@1e8 { + package-otp@1e8 { reg = <0x1e8 0x1>; bits = <0 3>; }; diff --git a/arch/arm64/boot/dts/st/stm32mp235f-dk.dts b/arch/arm64/boot/dts/st/stm32mp235f-dk.dts index c3e688068223..5ecc5ef61590 100644 --- a/arch/arm64/boot/dts/st/stm32mp235f-dk.dts +++ b/arch/arm64/boot/dts/st/stm32mp235f-dk.dts @@ -46,13 +46,23 @@ gpio-leds { compatible = "gpio-leds"; - led-blue { + led_blue: led-blue { function = LED_FUNCTION_HEARTBEAT; color = <LED_COLOR_ID_BLUE>; gpios = <&gpioh 7 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; default-state = "off"; }; + + led-green { + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioh 5 GPIO_ACTIVE_HIGH>; + }; + + led-orange { + color = <LED_COLOR_ID_ORANGE>; + gpios = <&gpioh 6 GPIO_ACTIVE_HIGH>; + }; }; memory@80000000 { @@ -60,6 +70,13 @@ reg = <0x0 0x80000000 0x0 0x80000000>; }; + options { + u-boot { + compatible = "u-boot,config"; + boot-led = <&led_blue>; + }; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -93,7 +110,7 @@ phy1_eth1: ethernet-phy@1 { compatible = "ethernet-phy-id001c.c916"; reg = <1>; - reset-gpios = <&gpioa 2 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpioa 2 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; reset-deassert-us = <80000>; }; diff --git a/arch/arm64/boot/dts/st/stm32mp23xc.dtsi b/arch/arm64/boot/dts/st/stm32mp23xc.dtsi deleted file mode 100644 index e33b00b424e1..000000000000 --- a/arch/arm64/boot/dts/st/stm32mp23xc.dtsi +++ /dev/null @@ -1,8 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2025 - All Rights Reserved - * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. - */ - -/ { -}; diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index a8e6e0f77b83..8b925ed0d881 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -672,6 +672,7 @@ <&hpdma 52 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 23>; + power-domains = <&CLUSTER_PD>; status = "disabled"; }; @@ -702,6 +703,7 @@ <&hpdma 54 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 24>; + power-domains = <&CLUSTER_PD>; status = "disabled"; }; @@ -780,6 +782,8 @@ <&hpdma 28 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 41>; + power-domains = <&CLUSTER_PD>; + i2c-analog-filter; status = "disabled"; }; @@ -796,6 +800,8 @@ <&hpdma 31 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 42>; + power-domains = <&CLUSTER_PD>; + i2c-analog-filter; status = "disabled"; }; @@ -812,6 +818,8 @@ <&hpdma 34 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 43>; + power-domains = <&CLUSTER_PD>; + i2c-analog-filter; status = "disabled"; }; @@ -828,6 +836,8 @@ <&hpdma 37 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 44>; + power-domains = <&CLUSTER_PD>; + i2c-analog-filter; status = "disabled"; }; @@ -844,6 +854,8 @@ <&hpdma 40 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 45>; + power-domains = <&CLUSTER_PD>; + i2c-analog-filter; status = "disabled"; }; @@ -860,6 +872,8 @@ <&hpdma 43 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 46>; + power-domains = <&CLUSTER_PD>; + i2c-analog-filter; status = "disabled"; }; @@ -876,6 +890,8 @@ <&hpdma 46 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 47>; + power-domains = <&CLUSTER_PD>; + i2c-analog-filter; status = "disabled"; }; @@ -1048,6 +1064,7 @@ <&hpdma 50 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 22>; + power-domains = <&CLUSTER_PD>; status = "disabled"; }; @@ -1063,6 +1080,7 @@ <&hpdma 56 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 25>; + power-domains = <&CLUSTER_PD>; status = "disabled"; }; @@ -1171,6 +1189,7 @@ <&hpdma 58 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 26>; + power-domains = <&CLUSTER_PD>; status = "disabled"; }; @@ -1380,6 +1399,7 @@ <&hpdma 60 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 27>; + power-domains = <&CLUSTER_PD>; status = "disabled"; }; @@ -1395,6 +1415,7 @@ <&hpdma 62 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 28>; + power-domains = <&CLUSTER_PD>; status = "disabled"; }; @@ -1444,6 +1465,7 @@ <&hpdma 172 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 29>; + power-domains = <&CLUSTER_PD>; status = "disabled"; }; @@ -1460,6 +1482,8 @@ <&hpdma 169 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 48>; + power-domains = <&CLUSTER_PD>; + i2c-analog-filter; status = "disabled"; }; @@ -1589,6 +1613,7 @@ <&rcc CK_KER_CSIPHY>; clock-names = "pclk", "txesc", "csi2phy"; access-controllers = <&rifsc 86>; + power-domains = <&CLUSTER_PD>; status = "disabled"; }; @@ -1600,6 +1625,7 @@ clocks = <&rcc CK_BUS_DCMIPP>, <&rcc CK_KER_CSI>; clock-names = "kclk", "mclk"; access-controllers = <&rifsc 87>; + power-domains = <&CLUSTER_PD>; status = "disabled"; }; @@ -1739,11 +1765,11 @@ #address-cells = <1>; #size-cells = <1>; - part_number_otp@24 { + part-number-otp@24 { reg = <0x24 0x4>; }; - package_otp@1e8 { + package-otp@1e8 { reg = <0x1e8 0x1>; bits = <0 3>; }; diff --git a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts b/arch/arm64/boot/dts/st/stm32mp257f-dk.dts index e718d888ce21..4135e7c0d9a3 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-dk.dts @@ -46,13 +46,30 @@ gpio-leds { compatible = "gpio-leds"; - led-blue { + led_blue: led-blue { function = LED_FUNCTION_HEARTBEAT; color = <LED_COLOR_ID_BLUE>; gpios = <&gpioh 7 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; default-state = "off"; }; + + led-green { + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioh 5 GPIO_ACTIVE_HIGH>; + }; + + led-orange { + color = <LED_COLOR_ID_ORANGE>; + gpios = <&gpioh 6 GPIO_ACTIVE_HIGH>; + }; + }; + + lpddr_channel: sdram-channel-0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "jedec,lpddr4-channel"; + io-width = <32>; }; memory@80000000 { @@ -60,6 +77,13 @@ reg = <0x0 0x80000000 0x1 0x0>; }; + options { + u-boot { + compatible = "u-boot,config"; + boot-led = <&led_blue>; + }; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -93,7 +117,7 @@ phy1_eth1: ethernet-phy@1 { compatible = "ethernet-phy-id001c.c916"; reg = <1>; - reset-gpios = <&gpioa 2 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpioa 2 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; reset-deassert-us = <80000>; }; diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts index bb6d6393d2e4..852a73b0c516 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -7,6 +7,7 @@ /dts-v1/; #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> #include <dt-bindings/regulator/st,stm32mp25-regulator.h> #include "stm32mp257.dtsi" #include "stm32mp25xf.dtsi" @@ -42,6 +43,35 @@ }; }; + gpio-leds { + compatible = "gpio-leds"; + + led_blue: led-blue { + function = LED_FUNCTION_HEARTBEAT; + color = <LED_COLOR_ID_BLUE>; + gpios = <&gpioj 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led-green { + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpiod 8 GPIO_ACTIVE_HIGH>; + }; + + led-orange { + color = <LED_COLOR_ID_ORANGE>; + gpios = <&gpioj 6 GPIO_ACTIVE_HIGH>; + }; + }; + + ddr_channel: sdram-channel-0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "jedec,ddr4-channel"; + io-width = <32>; + }; + imx335_2v9: regulator-2v9 { compatible = "regulator-fixed"; regulator-name = "imx335-avdd"; @@ -71,6 +101,13 @@ reg = <0x0 0x80000000 0x1 0x0>; }; + options { + u-boot { + compatible = "u-boot,config"; + boot-led = <&led_blue>; + }; + }; + panel_lvds: display { compatible = "edt,etml0700z9ndha", "panel-lvds"; enable-gpios = <&gpiog 15 GPIO_ACTIVE_HIGH>; @@ -186,7 +223,7 @@ phy1_eth1: ethernet-phy@4 { compatible = "ethernet-phy-id001c.c916"; reg = <4>; - reset-gpios = <&gpioj 9 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpioj 9 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; reset-deassert-us = <80000>; }; diff --git a/arch/arm64/boot/dts/st/stm32mp25xc.dtsi b/arch/arm64/boot/dts/st/stm32mp25xc.dtsi deleted file mode 100644 index 5e83a6926485..000000000000 --- a/arch/arm64/boot/dts/st/stm32mp25xc.dtsi +++ /dev/null @@ -1,8 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2023 - All Rights Reserved - * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. - */ - -/ { -}; diff --git a/arch/arm64/boot/dts/st/stm32mp25xxal-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25xxal-pinctrl.dtsi deleted file mode 100644 index 2406e972554c..000000000000 --- a/arch/arm64/boot/dts/st/stm32mp25xxal-pinctrl.dtsi +++ /dev/null @@ -1,71 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2023 - All Rights Reserved - * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. - */ - -&pinctrl { - st,package = <STM32MP_PKG_AL>; - - gpioa: gpio@44240000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 0 16>; - }; - - gpiob: gpio@44250000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 16 16>; - }; - - gpioc: gpio@44260000 { - status = "okay"; - ngpios = <14>; - gpio-ranges = <&pinctrl 0 32 14>; - }; - - gpiod: gpio@44270000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 48 16>; - }; - - gpioe: gpio@44280000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 64 16>; - }; - - gpiof: gpio@44290000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 80 16>; - }; - - gpiog: gpio@442a0000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 96 16>; - }; - - gpioh: gpio@442b0000 { - status = "okay"; - ngpios = <12>; - gpio-ranges = <&pinctrl 2 114 12>; - }; - - gpioi: gpio@442c0000 { - status = "okay"; - ngpios = <12>; - gpio-ranges = <&pinctrl 0 128 12>; - }; -}; - -&pinctrl_z { - gpioz: gpio@46200000 { - status = "okay"; - ngpios = <10>; - gpio-ranges = <&pinctrl_z 0 400 10>; - }; -}; diff --git a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi index 878d267bc663..e15da771bc07 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi @@ -220,6 +220,10 @@ bootph-all; }; +&cpsw_mac_syscon { + bootph-all; +}; + &cpsw3g_mdio { pinctrl-names = "default"; pinctrl-0 = <&main_mdio1_pins_default>; @@ -359,6 +363,10 @@ }; }; +&phy_gmii_sel { + bootph-all; +}; + &sdhci0 { pinctrl-names = "default"; pinctrl-0 = <&main_mmc0_pins_default>; diff --git a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi index b24a63feeab8..de4048a3564b 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi @@ -197,6 +197,10 @@ bootph-all; }; +&cpsw_mac_syscon { + bootph-all; +}; + &cpsw3g_mdio { pinctrl-names = "default"; pinctrl-0 = <&main_mdio1_pins_default>; @@ -350,6 +354,10 @@ }; }; +&phy_gmii_sel { + bootph-all; +}; + &sdhci0 { pinctrl-names = "default"; pinctrl-0 = <&main_mmc0_pins_default>; diff --git a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts index 2b233bc0323d..a5d5dc0a7bec 100644 --- a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts @@ -669,7 +669,7 @@ pinctrl-0 = <&ospi0_pins_default>; status = "okay"; - flash@0{ + flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <8>; diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi index 3cf7c2b3ce2d..0e1af2a69ca2 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi @@ -1117,4 +1117,21 @@ clocks = <&k3_clks 204 2>; power-domains = <&k3_pds 204 TI_SCI_PD_EXCLUSIVE>; }; + + hsm: remoteproc@43c00000 { + compatible = "ti,hsm-m4fss"; + /* contiguous regions but instantiated separately in HW */ + reg = <0x00 0x43c00000 0x00 0x20000>, + <0x00 0x43c20000 0x00 0x10000>, + <0x00 0x43c30000 0x00 0x10000>; + reg-names = "sram0_0", "sram0_1", "sram1"; + resets = <&k3_reset 225 1>; + firmware-name = "am62p-hsm-m4f-fw"; + bootph-pre-ram; + ti,sci = <&dmsc>; + ti,sci-dev-id = <225>; + ti,sci-proc-ids = <0x80 0xff>; + /* reserved for early-stage bootloader */ + status = "reserved"; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi index 5e050cbb9eaf..34954df692a3 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi @@ -112,7 +112,7 @@ regulator-max-microvolt = <3300000>; regulator-min-microvolt = <3300000>; regulator-name = "+V3.3_SD"; - startup-delay-us = <2000>; + startup-delay-us = <20000>; }; reg_sd1_vqmmc: regulator-sdhci1-vqmmc { @@ -514,7 +514,7 @@ pinctrl-single,pins = < AM62PX_IOPAD(0x0120, PIN_INPUT, 0) /* (K24) MMC2_CMD */ /* SODIMM 160, WiFi_SDIO_CMD */ AM62PX_IOPAD(0x0118, PIN_OUTPUT, 0) /* (K21) MMC2_CLK */ /* SODIMM 156, WiFi_SDIO_CLK */ - AM62PX_IOPAD(0x011C, PIN_INPUT, 0) /* () MMC2_CLKLB */ + AM62PX_IOPAD(0x011c, PIN_INPUT, 0) /* () MMC2_CLKLB */ AM62PX_IOPAD(0x0114, PIN_INPUT, 0) /* (K23) MMC2_DAT0 */ /* SODIMM 162, WiFi_SDIO_DATA0 */ AM62PX_IOPAD(0x0110, PIN_INPUT, 0) /* (K22) MMC2_DAT1 */ /* SODIMM 164, WiFi_SDIO_DATA1 */ AM62PX_IOPAD(0x010c, PIN_INPUT, 0) /* (L20) MMC2_DAT2 */ /* SODIMM 166, WiFi_SDIO_DATA2 */ diff --git a/arch/arm64/boot/dts/ti/k3-am62p.dtsi b/arch/arm64/boot/dts/ti/k3-am62p.dtsi index e2c01328eb29..9d6266d6ddb8 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p.dtsi @@ -96,6 +96,7 @@ <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */ <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */ <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */ + <0x00 0x43c00000 0x00 0x43c00000 0x00 0x00040000>, /* HSM SRAM ranges */ <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */ <0x00 0x48000000 0x00 0x48000000 0x00 0x06408000>, /* DMSS */ diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts index ef719c6334fc..4f7f6f95b02e 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -283,7 +283,7 @@ pinctrl-single,pins = < AM62PX_IOPAD(0x0120, PIN_INPUT, 0) /* (K24) MMC2_CMD */ AM62PX_IOPAD(0x0118, PIN_OUTPUT, 0) /* (K21) MMC2_CLK */ - AM62PX_IOPAD(0x011C, PIN_INPUT, 0) /* () MMC2_CLKLB */ + AM62PX_IOPAD(0x011c, PIN_INPUT, 0) /* () MMC2_CLKLB */ AM62PX_IOPAD(0x0114, PIN_INPUT, 0) /* (K23) MMC2_DAT0 */ AM62PX_IOPAD(0x0110, PIN_INPUT_PULLUP, 0) /* (K22) MMC2_DAT1 */ AM62PX_IOPAD(0x010c, PIN_INPUT_PULLUP, 0) /* (L20) MMC2_DAT2 */ diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts b/arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts index 4bb92fde6ab8..5ba4ed56755b 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts @@ -224,7 +224,7 @@ status = "okay"; }; -&main_i2c0{ +&main_i2c0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; clock-frequency = <400000>; @@ -466,7 +466,7 @@ pinctrl-0 = <&pinctrl_mmc1>; disable-wp; bootph-all; - status="okay"; + status = "okay"; }; &ti_csi2rx0 { diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index d872cc671094..1b1d3970888b 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -84,7 +84,7 @@ #interrupt-cells = <3>; interrupt-controller; reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ - <0x00 0x01840000 0x00 0xC0000>, /* GICR */ + <0x00 0x01840000 0x00 0xc0000>, /* GICR */ <0x01 0x00000000 0x00 0x2000>, /* GICC */ <0x01 0x00010000 0x00 0x1000>, /* GICH */ <0x01 0x00020000 0x00 0x2000>; /* GICV */ @@ -685,14 +685,14 @@ power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; - dmas = <&main_pktdma 0xC500 15>, - <&main_pktdma 0xC501 15>, - <&main_pktdma 0xC502 15>, - <&main_pktdma 0xC503 15>, - <&main_pktdma 0xC504 15>, - <&main_pktdma 0xC505 15>, - <&main_pktdma 0xC506 15>, - <&main_pktdma 0xC507 15>, + dmas = <&main_pktdma 0xc500 15>, + <&main_pktdma 0xc501 15>, + <&main_pktdma 0xc502 15>, + <&main_pktdma 0xc503 15>, + <&main_pktdma 0xc504 15>, + <&main_pktdma 0xc505 15>, + <&main_pktdma 0xc506 15>, + <&main_pktdma 0xc507 15>, <&main_pktdma 0x4500 15>; dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", "rx"; diff --git a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts index e4afa8c0a8ca..793538f94942 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts @@ -206,8 +206,8 @@ pinctrl-single,pins = < AM64X_IOPAD(0x0200, PIN_INPUT, 0) /* (P2) PRG0_MDIO0_MDIO */ AM64X_IOPAD(0x0204, PIN_OUTPUT, 0) /* (P3) PRG0_MDIO0_MDC */ - AM64X_IOPAD(0x01A8, PIN_OUTPUT, 7) /* (V1) PRG0_PRU0_GPO18.GPIO1_18 */ - AM64X_IOPAD(0x01AC, PIN_OUTPUT, 7) /* (W1) PRG0_PRU0_GPO19.GPIO1_19 */ + AM64X_IOPAD(0x01a8, PIN_OUTPUT, 7) /* (V1) PRG0_PRU0_GPO18.GPIO1_18 */ + AM64X_IOPAD(0x01ac, PIN_OUTPUT, 7) /* (W1) PRG0_PRU0_GPO19.GPIO1_19 */ >; }; @@ -300,7 +300,7 @@ main_uart1_pins_default: main-uart1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */ - AM64X_IOPAD(0x024C, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */ + AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */ AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */ AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */ >; diff --git a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-x27-gpio1-spi1-uart3.dtso b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-x27-gpio1-spi1-uart3.dtso index bea8efa3e909..39306bf8eec1 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-x27-gpio1-spi1-uart3.dtso +++ b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-x27-gpio1-spi1-uart3.dtso @@ -29,9 +29,9 @@ main_spi1_pins_default: main-spi1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0224, PIN_INPUT, 0) /* (C14) SPI1_CLK */ - AM64X_IOPAD(0x021C, PIN_OUTPUT, 0) /* (B14) SPI1_CS0 */ + AM64X_IOPAD(0x021c, PIN_OUTPUT, 0) /* (B14) SPI1_CS0 */ AM64X_IOPAD(0x0228, PIN_OUTPUT, 0) /* (B15) SPI1_D0 */ - AM64X_IOPAD(0x022C, PIN_INPUT, 0) /* (A15) SPI1_D1 */ + AM64X_IOPAD(0x022c, PIN_INPUT, 0) /* (A15) SPI1_D1 */ >; }; diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-arduino-connector.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-arduino-connector.dtsi index 7ff0abd7c62e..6c7fdaf1f2c4 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-arduino-connector.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-arduino-connector.dtsi @@ -138,28 +138,28 @@ d2_uart0_ctsn: d2-uart0-ctsn-pins { pinctrl-single,pins = < /* (P1) MCU_UART0_CTSn */ - AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 4) + AM65X_WKUP_IOPAD(0x004c, PIN_INPUT, 4) >; }; d2_gpio: d2-gpio-pins { pinctrl-single,pins = < /* (P5) WKUP_GPIO0_31 */ - AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 7) + AM65X_WKUP_IOPAD(0x004c, PIN_INPUT, 7) >; }; d2_gpio_pullup: d2-gpio-pullup-pins { pinctrl-single,pins = < /* (P5) WKUP_GPIO0_31 */ - AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 7) + AM65X_WKUP_IOPAD(0x004c, PIN_INPUT, 7) >; }; d2_gpio_pulldown: d2-gpio-pulldown-pins { pinctrl-single,pins = < /* (P5) WKUP_GPIO0_31 */ - AM65X_WKUP_IOPAD(0x004C, PIN_INPUT_PULLDOWN, 7) + AM65X_WKUP_IOPAD(0x004c, PIN_INPUT_PULLDOWN, 7) >; }; @@ -348,42 +348,42 @@ a2_gpio: a2-gpio-pins { pinctrl-single,pins = < /* (L5) WKUP_GPIO0_43 */ - AM65X_WKUP_IOPAD(0x007C, PIN_INPUT, 7) + AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 7) >; }; a2_gpio_pullup: a2-gpio-pullup-pins { pinctrl-single,pins = < /* (L5) WKUP_GPIO0_43 */ - AM65X_WKUP_IOPAD(0x007C, PIN_INPUT, 7) + AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 7) >; }; a2_gpio_pulldown: a2-gpio-pulldown-pins { pinctrl-single,pins = < /* (L5) WKUP_GPIO0_43 */ - AM65X_WKUP_IOPAD(0x007C, PIN_INPUT_PULLDOWN, 7) + AM65X_WKUP_IOPAD(0x007c, PIN_INPUT_PULLDOWN, 7) >; }; a3_gpio: a3-gpio-pins { pinctrl-single,pins = < /* (M5) WKUP_GPIO0_39 */ - AM65X_WKUP_IOPAD(0x006C, PIN_INPUT, 7) + AM65X_WKUP_IOPAD(0x006c, PIN_INPUT, 7) >; }; a3_gpio_pullup: a3-gpio-pullup-pins { pinctrl-single,pins = < /* (M5) WKUP_GPIO0_39 */ - AM65X_WKUP_IOPAD(0x006C, PIN_INPUT, 7) + AM65X_WKUP_IOPAD(0x006c, PIN_INPUT, 7) >; }; a3_gpio_pulldown: a3-gpio-pulldown-pins { pinctrl-single,pins = < /* (M5) WKUP_GPIO0_39 */ - AM65X_WKUP_IOPAD(0x006C, PIN_INPUT_PULLDOWN, 7) + AM65X_WKUP_IOPAD(0x006c, PIN_INPUT_PULLDOWN, 7) >; }; @@ -411,21 +411,21 @@ a5_gpio: a5-gpio-pins { pinctrl-single,pins = < /* (N5) WKUP_GPIO0_35 */ - AM65X_WKUP_IOPAD(0x005C, PIN_INPUT, 7) + AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 7) >; }; a5_gpio_pullup: a5-gpio-pullup-pins { pinctrl-single,pins = < /* (N5) WKUP_GPIO0_35 */ - AM65X_WKUP_IOPAD(0x005C, PIN_INPUT_PULLUP, 7) + AM65X_WKUP_IOPAD(0x005c, PIN_INPUT_PULLUP, 7) >; }; a5_gpio_pulldown: a5-gpio-pulldown-pins { pinctrl-single,pins = < /* (N5) WKUP_GPIO0_35 */ - AM65X_WKUP_IOPAD(0x005C, PIN_INPUT_PULLDOWN, 7) + AM65X_WKUP_IOPAD(0x005c, PIN_INPUT_PULLDOWN, 7) >; }; @@ -533,28 +533,28 @@ d5_ehrpwm1_a: d5-ehrpwm1-a-pins { pinctrl-single,pins = < /* (AF17) EHRPWM1_A */ - AM65X_IOPAD(0x008C, PIN_OUTPUT, 5) + AM65X_IOPAD(0x008c, PIN_OUTPUT, 5) >; }; d5_gpio: d5-gpio-pins { pinctrl-single,pins = < /* (AF17) GPIO0_35 */ - AM65X_IOPAD(0x008C, PIN_INPUT, 7) + AM65X_IOPAD(0x008c, PIN_INPUT, 7) >; }; d5_gpio_pullup: d5-gpio-pullup-pins { pinctrl-single,pins = < /* (AF17) GPIO0_35 */ - AM65X_IOPAD(0x008C, PIN_INPUT_PULLUP, 7) + AM65X_IOPAD(0x008c, PIN_INPUT_PULLUP, 7) >; }; d5_gpio_pulldown: d5-gpio-pulldown-pins { pinctrl-single,pins = < /* (AF17) GPIO0_35 */ - AM65X_IOPAD(0x008C, PIN_INPUT_PULLDOWN, 7) + AM65X_IOPAD(0x008c, PIN_INPUT_PULLDOWN, 7) >; }; @@ -589,84 +589,84 @@ d7_ehrpwm3_a: d7-ehrpwm3-a-pins { pinctrl-single,pins = < /* (AH15) EHRPWM3_A */ - AM65X_IOPAD(0x00AC, PIN_OUTPUT, 5) + AM65X_IOPAD(0x00ac, PIN_OUTPUT, 5) >; }; d7_gpio: d7-gpio-pins { pinctrl-single,pins = < /* (AH15) GPIO0_43 */ - AM65X_IOPAD(0x00AC, PIN_INPUT, 7) + AM65X_IOPAD(0x00ac, PIN_INPUT, 7) >; }; d7_gpio_pullup: d7-gpio-pullup-pins { pinctrl-single,pins = < /* (AH15) GPIO0_43 */ - AM65X_IOPAD(0x00AC, PIN_INPUT_PULLUP, 7) + AM65X_IOPAD(0x00ac, PIN_INPUT_PULLUP, 7) >; }; d7_gpio_pulldown: d7-gpio-pulldown-pins { pinctrl-single,pins = < /* (AH15) GPIO0_43 */ - AM65X_IOPAD(0x00AC, PIN_INPUT_PULLDOWN, 7) + AM65X_IOPAD(0x00ac, PIN_INPUT_PULLDOWN, 7) >; }; d8_ehrpwm4_a: d8-ehrpwm4-a-pins { pinctrl-single,pins = < /* (AG15) EHRPWM4_A */ - AM65X_IOPAD(0x00C0, PIN_OUTPUT, 5) + AM65X_IOPAD(0x00c0, PIN_OUTPUT, 5) >; }; d8_gpio: d8-gpio-pins { pinctrl-single,pins = < /* (AG15) GPIO0_48 */ - AM65X_IOPAD(0x00C0, PIN_INPUT, 7) + AM65X_IOPAD(0x00c0, PIN_INPUT, 7) >; }; d8_gpio_pullup: d8-gpio-pullup-pins { pinctrl-single,pins = < /* (AG15) GPIO0_48 */ - AM65X_IOPAD(0x00C0, PIN_INPUT_PULLUP, 7) + AM65X_IOPAD(0x00c0, PIN_INPUT_PULLUP, 7) >; }; d8_gpio_pulldown: d8-gpio-pulldown-pins { pinctrl-single,pins = < /* (AG15) GPIO0_48 */ - AM65X_IOPAD(0x00C0, PIN_INPUT_PULLDOWN, 7) + AM65X_IOPAD(0x00c0, PIN_INPUT_PULLDOWN, 7) >; }; d9_ehrpwm5_a: d9-ehrpwm5-a-pins { pinctrl-single,pins = < /* (AD15) EHRPWM5_A */ - AM65X_IOPAD(0x00CC, PIN_OUTPUT, 5) + AM65X_IOPAD(0x00cc, PIN_OUTPUT, 5) >; }; d9_gpio: d9-gpio-pins { pinctrl-single,pins = < /* (AD15) GPIO0_51 */ - AM65X_IOPAD(0x00CC, PIN_INPUT, 7) + AM65X_IOPAD(0x00cc, PIN_INPUT, 7) >; }; d9_gpio_pullup: d9-gpio-pullup-pins { pinctrl-single,pins = < /* (AD15) GPIO0_51 */ - AM65X_IOPAD(0x00CC, PIN_INPUT_PULLUP, 7) + AM65X_IOPAD(0x00cc, PIN_INPUT_PULLUP, 7) >; }; d9_gpio_pulldown: d9-gpio-pulldown-pins { pinctrl-single,pins = < /* (AD15) GPIO0_51 */ - AM65X_IOPAD(0x00CC, PIN_INPUT_PULLDOWN, 7) + AM65X_IOPAD(0x00cc, PIN_INPUT_PULLDOWN, 7) >; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi index a9a4e7401a49..f3ee73e64d69 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -266,7 +266,7 @@ minipcie_pins_default: minipcie-default-pins { pinctrl-single,pins = < /* (P2) MCU_OSPI1_DQS.WKUP_GPIO0_27 */ - AM65X_WKUP_IOPAD(0x003C, PIN_OUTPUT, 7) + AM65X_WKUP_IOPAD(0x003c, PIN_OUTPUT, 7) >; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 61c11dc92d9c..d6ee7b9a6b68 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -884,7 +884,7 @@ #address-cells = <3>; #size-cells = <2>; ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000>, - <0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>; + <0x82000000 0 0x10030000 0x0 0x10030000 0 0x07fd0000>; ti,syscon-pcie-id = <&scm_conf 0x210>; ti,syscon-pcie-mode = <&scm_conf 0x4060>; bus-range = <0x0 0xff>; @@ -905,7 +905,7 @@ #address-cells = <3>; #size-cells = <2>; ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000>, - <0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>; + <0x82000000 0 0x18030000 0x0 0x18030000 0 0x07fd0000>; ti,syscon-pcie-id = <&scm_conf 0x210>; ti,syscon-pcie-mode = <&scm_conf 0x4070>; bus-range = <0x0 0xff>; diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 46c58162eca0..e0262c2743eb 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -190,7 +190,7 @@ pinctrl-single,pins = < AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4) /* (P4) MCU_OSPI1_D1.MCU_UART0_RXD */ AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4) /* (P5) MCU_OSPI1_D2.MCU_UART0_TXD */ - AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 4) /* (P1) MCU_OSPI1_D3.MCU_UART0_CTSn */ + AM65X_WKUP_IOPAD(0x004c, PIN_INPUT, 4) /* (P1) MCU_OSPI1_D3.MCU_UART0_CTSn */ AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 4) /* (N3) MCU_OSPI1_CSn1.MCU_UART0_RTSn */ >; bootph-all; diff --git a/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts b/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts index 7169d934adac..95234c8460ed 100644 --- a/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts +++ b/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts @@ -85,8 +85,7 @@ linux,cma { compatible = "shared-dma-pool"; reusable; - size = <0x10000000>; - alignment = <0x2000>; + size = <0x00 0x10000000>; linux,cma-default; }; @@ -174,6 +173,7 @@ regulator-max-microvolt = <3300000>; vin-supply = <&vcc_3p3_s0>; regulator-boot-on; + enable-active-high; enable-gpios = <&main_gpio0 7 GPIO_ACTIVE_HIGH>; gpios = <&main_gpio0 8 GPIO_ACTIVE_HIGH>; states = <3300000 0x0>, diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts index 88f202f266c6..8178333fb2b4 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -359,15 +359,15 @@ mcu_cpsw_pins_default: mcu-cpsw-default-pins { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x02C, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */ + J721S2_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */ J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */ J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */ J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */ - J721S2_WKUP_IOPAD(0x01C, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */ + J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */ J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */ J721S2_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */ J721S2_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */ - J721S2_WKUP_IOPAD(0x00C, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */ + J721S2_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */ J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */ J721S2_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */ J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */ @@ -392,7 +392,7 @@ mcu_mcan1_pins_default: mcu-mcan1-default-pins { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x06C, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */ + J721S2_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */ J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX*/ >; }; @@ -422,13 +422,13 @@ mcu_rpi_header_gpio0_pins0_default: mcu-rpi-header-gpio0-default-pins-0 { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x118, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_66 */ - J721S2_WKUP_IOPAD(0x05C, PIN_INPUT, 7) /* (E24) MCU_SPI1_D0.WKUP_GPIO0_1 */ + J721S2_WKUP_IOPAD(0x05c, PIN_INPUT, 7) /* (E24) MCU_SPI1_D0.WKUP_GPIO0_1 */ J721S2_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (C28) MCU_SPI1_D1.WKUP_GPIO0_2 */ J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (D26) MCU_SPI1_CLK.WKUP_GPIO0_0 */ J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 7) /* (D25) MCU_SPI1_CS2.WKUP_GPIO0_15*/ - J721S2_WKUP_IOPAD(0x0B8, PIN_INPUT, 7) /* (G27) WKUP_GPIO0_56 */ + J721S2_WKUP_IOPAD(0x0b8, PIN_INPUT, 7) /* (G27) WKUP_GPIO0_56 */ J721S2_WKUP_IOPAD(0x114, PIN_INPUT, 7) /* (J26) WKUP_GPIO0_57 */ - J721S2_WKUP_IOPAD(0x11C, PIN_INPUT, 7) /* (J27) WKUP_GPIO0_67 */ + J721S2_WKUP_IOPAD(0x11c, PIN_INPUT, 7) /* (J27) WKUP_GPIO0_67 */ J721S2_WKUP_IOPAD(0x064, PIN_INPUT, 7) /* (C27) MCU_SPI1_CS0.WKUP_GPIO0_3 */ >; }; diff --git a/arch/arm64/boot/dts/ti/k3-am69-aquila-clover.dts b/arch/arm64/boot/dts/ti/k3-am69-aquila-clover.dts index 55fd214a82e4..ec8ff4587715 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-aquila-clover.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-aquila-clover.dts @@ -208,7 +208,8 @@ pinctrl-0 = <&pinctrl_main_spi2>, <&pinctrl_main_spi2_cs0>, <&pinctrl_gpio_05>; - cs-gpios = <0>, <&wkup_gpio0 29 GPIO_ACTIVE_LOW>; + cs-gpios = <&main_gpio0 39 GPIO_ACTIVE_LOW>, + <&wkup_gpio0 29 GPIO_ACTIVE_LOW>; status = "okay"; tpm@1 { @@ -280,8 +281,8 @@ try-power-role = "sink"; self-powered; source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; - sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; - op-sink-microwatt = <1000000>; + sink-pdos = <PDO_FIXED(5000, 0, PDO_FIXED_USB_COMM)>; + op-sink-microwatt = <0>; ports { #address-cells = <1>; diff --git a/arch/arm64/boot/dts/ti/k3-am69-aquila-dev.dts b/arch/arm64/boot/dts/ti/k3-am69-aquila-dev.dts index c7ce804eac70..f48601ae38b7 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-aquila-dev.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-aquila-dev.dts @@ -399,8 +399,8 @@ try-power-role = "sink"; self-powered; source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; - sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; - op-sink-microwatt = <1000000>; + sink-pdos = <PDO_FIXED(5000, 0, PDO_FIXED_USB_COMM)>; + op-sink-microwatt = <0>; ports { #address-cells = <1>; diff --git a/arch/arm64/boot/dts/ti/k3-am69-aquila.dtsi b/arch/arm64/boot/dts/ti/k3-am69-aquila.dtsi index 0866eb8a6f34..5119baf62a4c 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-aquila.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am69-aquila.dtsi @@ -479,7 +479,7 @@ /* Aquila SPI_2 CS */ pinctrl_main_spi0_cs0: main-spi0-cs0-default-pins { pinctrl-single,pins = < - J784S4_IOPAD(0x0cc, PIN_OUTPUT, 0) /* (AM37) SPI0_CS0 */ /* AQUILA D16 */ + J784S4_IOPAD(0x0cc, PIN_OUTPUT, 7) /* (AM37) SPI0_CS0.GPIO0_51 */ /* AQUILA D16 */ >; }; @@ -495,7 +495,7 @@ /* Aquila SPI_1 CS */ pinctrl_main_spi2_cs0: main-spi2-cs0-default-pins { pinctrl-single,pins = < - J784S4_IOPAD(0x09c, PIN_OUTPUT, 10) /* (AF35) MCASP0_AXR11.SPI2_CS1 */ /* AQUILA D9 */ + J784S4_IOPAD(0x09c, PIN_OUTPUT, 7) /* (AF35) MCASP0_AXR11.GPIO0_39 */ /* AQUILA D9 */ >; }; @@ -1204,6 +1204,7 @@ &main_spi0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_main_spi0>, <&pinctrl_main_spi0_cs0>; + cs-gpios = <&main_gpio0 51 GPIO_ACTIVE_LOW>; status = "disabled"; }; @@ -1211,6 +1212,7 @@ &main_spi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_main_spi2>, <&pinctrl_main_spi2_cs0>; + cs-gpios = <&main_gpio0 39 GPIO_ACTIVE_LOW>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts index abe2f21e0e1d..e56772a334c5 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -264,24 +264,24 @@ vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { pinctrl-single,pins = < - J784S4_IOPAD(0x0C4, PIN_INPUT, 7) /* (AD36) ECAP0_IN_APWM_OUT.GPIO0_49 */ + J784S4_IOPAD(0x0c4, PIN_INPUT, 7) /* (AD36) ECAP0_IN_APWM_OUT.GPIO0_49 */ >; }; rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins { pinctrl-single,pins = < - J784S4_IOPAD(0x0BC, PIN_INPUT, 7) /* (AD33) MCASP1_AFSX.GPIO0_47 */ - J784S4_IOPAD(0x06C, PIN_INPUT, 7) /* (AJ37) MCASP4_AFSX.GPIO0_27 */ - J784S4_IOPAD(0x0B4, PIN_INPUT, 7) /* (AL34) MCASP1_AXR4.GPIO0_45 */ - J784S4_IOPAD(0x0C0, PIN_INPUT, 7) /* (AD38) MCASP1_AXR0.GPIO0_48 */ - J784S4_IOPAD(0x00C, PIN_INPUT, 7) /* (AF33) MCAN13_TX.GPIO0_3 */ - J784S4_IOPAD(0x0B8, PIN_INPUT, 7) /* (AC34) MCASP1_ACLKX.GPIO0_46 */ + J784S4_IOPAD(0x0bc, PIN_INPUT, 7) /* (AD33) MCASP1_AFSX.GPIO0_47 */ + J784S4_IOPAD(0x06c, PIN_INPUT, 7) /* (AJ37) MCASP4_AFSX.GPIO0_27 */ + J784S4_IOPAD(0x0b4, PIN_INPUT, 7) /* (AL34) MCASP1_AXR4.GPIO0_45 */ + J784S4_IOPAD(0x0c0, PIN_INPUT, 7) /* (AD38) MCASP1_AXR0.GPIO0_48 */ + J784S4_IOPAD(0x00c, PIN_INPUT, 7) /* (AF33) MCAN13_TX.GPIO0_3 */ + J784S4_IOPAD(0x0b8, PIN_INPUT, 7) /* (AC34) MCASP1_ACLKX.GPIO0_46 */ J784S4_IOPAD(0x090, PIN_INPUT, 7) /* (AC35) MCASP0_AXR8.GPIO0_36 */ - J784S4_IOPAD(0x0A8, PIN_INPUT, 7) /* (AF34) MCASP0_AXR14.GPIO0_42 */ - J784S4_IOPAD(0x0A4, PIN_INPUT, 7) /* (AJ36) MCASP0_AXR13.GPIO0_41 */ + J784S4_IOPAD(0x0a8, PIN_INPUT, 7) /* (AF34) MCASP0_AXR14.GPIO0_42 */ + J784S4_IOPAD(0x0a4, PIN_INPUT, 7) /* (AJ36) MCASP0_AXR13.GPIO0_41 */ J784S4_IOPAD(0x034, PIN_INPUT, 7) /* (AJ34) PMIC_WAKE0n.GPIO0_13 */ - J784S4_IOPAD(0x0CC, PIN_INPUT, 7) /* (AM37) SPI0_CS0.GPIO0_51 */ - J784S4_IOPAD(0x08C, PIN_INPUT, 7) /* (AE35) MCASP0_AXR7.GPIO0_35 */ + J784S4_IOPAD(0x0cc, PIN_INPUT, 7) /* (AM37) SPI0_CS0.GPIO0_51 */ + J784S4_IOPAD(0x08c, PIN_INPUT, 7) /* (AE35) MCASP0_AXR7.GPIO0_35 */ J784S4_IOPAD(0x008, PIN_INPUT, 7) /* (AJ33) MCAN12_RX.GPIO0_2 */ J784S4_IOPAD(0x004, PIN_INPUT, 7) /* (AG36) MCAN12_TX.GPIO0_1 */ >; @@ -347,8 +347,8 @@ main_mcan7_pins_default: main-mcan7-default-pins { pinctrl-single,pins = < - J784S4_IOPAD(0x0A0, PIN_INPUT, 0) /* (AD34) MCAN7_RX */ - J784S4_IOPAD(0x09C, PIN_OUTPUT, 0) /* (AF35) MCAN7_TX */ + J784S4_IOPAD(0x0a0, PIN_INPUT, 0) /* (AD34) MCAN7_RX */ + J784S4_IOPAD(0x09c, PIN_OUTPUT, 0) /* (AF35) MCAN7_TX */ >; }; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index fec1db8b133d..dc5c02a025f8 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -212,7 +212,7 @@ reg = <0x0 0x40f04200 0x0 0x28>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x0000000F>; + pinctrl-single,function-mask = <0x0000000f>; status = "reserved"; }; @@ -222,7 +222,7 @@ reg = <0x0 0x40f04280 0x0 0x28>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x0000000F>; + pinctrl-single,function-mask = <0x0000000f>; status = "reserved"; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index 050776cb4df8..689ba2ff81f7 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -443,29 +443,29 @@ rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins { pinctrl-single,pins = < - J721E_IOPAD(0x01C, PIN_INPUT, 7) /* (AD22) PRG1_PRU0_GPO6.GPIO0_7 */ + J721E_IOPAD(0x01c, PIN_INPUT, 7) /* (AD22) PRG1_PRU0_GPO6.GPIO0_7 */ J721E_IOPAD(0x120, PIN_INPUT, 7) /* (AA28) PRG0_PRU1_GPO8.GPIO0_71 */ - J721E_IOPAD(0x14C, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */ - J721E_IOPAD(0x02C, PIN_INPUT, 7) /* (AD21) PRG1_PRU0_GPO10.GPIO0_11 */ + J721E_IOPAD(0x14c, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */ + J721E_IOPAD(0x02c, PIN_INPUT, 7) /* (AD21) PRG1_PRU0_GPO10.GPIO0_11 */ J721E_IOPAD(0x198, PIN_INPUT, 7) /* (V25) RGMII6_TD1.GPIO0_101 */ - J721E_IOPAD(0x1B0, PIN_INPUT, 7) /* (W24) RGMII6_RD1.GPIO0_107 */ - J721E_IOPAD(0x1A0, PIN_INPUT, 7) /* (W29) RGMII6_TXC.GPIO0_103 */ + J721E_IOPAD(0x1b0, PIN_INPUT, 7) /* (W24) RGMII6_RD1.GPIO0_107 */ + J721E_IOPAD(0x1a0, PIN_INPUT, 7) /* (W29) RGMII6_TXC.GPIO0_103 */ J721E_IOPAD(0x008, PIN_INPUT, 7) /* (AG22) PRG1_PRU0_GPO1.GPIO0_2 */ - J721E_IOPAD(0x1D0, PIN_INPUT, 7) /* (AA3) SPI0_D1.GPIO0_115 */ - J721E_IOPAD(0x11C, PIN_INPUT, 7) /* (AA24) PRG0_PRU1_GPO7.GPIO0_70 */ + J721E_IOPAD(0x1d0, PIN_INPUT, 7) /* (AA3) SPI0_D1.GPIO0_115 */ + J721E_IOPAD(0x11c, PIN_INPUT, 7) /* (AA24) PRG0_PRU1_GPO7.GPIO0_70 */ J721E_IOPAD(0x148, PIN_INPUT, 7) /* (AA26) PRG0_PRU1_GPO18.GPIO0_81 */ J721E_IOPAD(0x004, PIN_INPUT, 7) /* (AC23) PRG1_PRU0_GPO0.GPIO0_1 */ J721E_IOPAD(0x014, PIN_INPUT, 7) /* (AH23) PRG1_PRU0_GPO4.GPIO0_5 */ J721E_IOPAD(0x020, PIN_INPUT, 7) /* (AE20) PRG1_PRU0_GPO7.GPIO0_8 */ - J721E_IOPAD(0x19C, PIN_INPUT, 7) /* (W27) RGMII6_TD0.GPIO0_102 */ - J721E_IOPAD(0x1B4, PIN_INPUT, 7) /* (W25) RGMII6_RD0.GPIO0_108 */ + J721E_IOPAD(0x19c, PIN_INPUT, 7) /* (W27) RGMII6_TD0.GPIO0_102 */ + J721E_IOPAD(0x1b4, PIN_INPUT, 7) /* (W25) RGMII6_RD0.GPIO0_108 */ J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */ - J721E_IOPAD(0x00C, PIN_INPUT, 7) /* (AF22) PRG1_PRU0_GPO2.GPIO0_3 */ + J721E_IOPAD(0x00c, PIN_INPUT, 7) /* (AF22) PRG1_PRU0_GPO2.GPIO0_3 */ J721E_IOPAD(0x010, PIN_INPUT, 7) /* (AJ23) PRG1_PRU0_GPO3.GPIO0_4 */ J721E_IOPAD(0x178, PIN_INPUT, 7) /* (U27) RGMII5_RD3.GPIO0_93 */ - J721E_IOPAD(0x17C, PIN_INPUT, 7) /* (U24) RGMII5_RD2.GPIO0_94 */ + J721E_IOPAD(0x17c, PIN_INPUT, 7) /* (U24) RGMII5_RD2.GPIO0_94 */ J721E_IOPAD(0x190, PIN_INPUT, 7) /* (W23) RGMII6_TD3.GPIO0_99 */ - J721E_IOPAD(0x18C, PIN_INPUT, 7) /* (V23) RGMII6_RX_CTL.GPIO0_98 */ + J721E_IOPAD(0x18c, PIN_INPUT, 7) /* (V23) RGMII6_RX_CTL.GPIO0_98 */ >; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi index b6e22c242951..ba109cc5b2bc 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi @@ -41,7 +41,7 @@ reg = <0x000>; device_type = "cpu"; enable-method = "psci"; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <256>; d-cache-size = <0x8000>; @@ -55,7 +55,7 @@ reg = <0x001>; device_type = "cpu"; enable-method = "psci"; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <256>; d-cache-size = <0x8000>; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index 2a7f9c519735..32ee8031cfcb 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -87,7 +87,7 @@ wkup_pmx1: pinctrl@4301c038 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ - reg = <0x00 0x4301c038 0x00 0x02C>; + reg = <0x00 0x4301c038 0x00 0x02c>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; @@ -766,4 +766,21 @@ /* reserved for MCU_R5F0_1 */ status = "reserved"; }; + + hsm: remoteproc@43c00000 { + compatible = "ti,hsm-m4fss"; + /* contiguous regions but instantiated separately in HW */ + reg = <0x00 0x43c00000 0x00 0x20000>, + <0x00 0x43c20000 0x00 0x10000>, + <0x00 0x43c30000 0x00 0x10000>; + reg-names = "sram0_0", "sram0_1", "sram1"; + resets = <&k3_reset 304 1>; + firmware-name = "j721s2-hsm-m4f-fw"; + bootph-pre-ram; + ti,sci = <&sms>; + ti,sci-dev-id = <304>; + ti,sci-proc-ids = <0x80 0xff>; + /* reserved for early-stage bootloader */ + status = "reserved"; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts index 7baf5764862b..e66330c71593 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -436,7 +436,7 @@ mcu_mcan1_pins_default: mcu-mcan1-default-pins { pinctrl-single,pins = < J722S_MCU_IOPAD(0x040, PIN_INPUT, 0) /* (B1) MCU_MCAN1_RX */ - J722S_MCU_IOPAD(0x03C, PIN_OUTPUT, 0) /*(C1) MCU_MCAN1_TX */ + J722S_MCU_IOPAD(0x03c, PIN_OUTPUT, 0) /*(C1) MCU_MCAN1_TX */ >; }; diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi index 873415ec4fa3..9ee5d0c8ffd1 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi @@ -429,6 +429,11 @@ firmware-name = "j722s-wkup-r5f0_0-fw"; }; +/* MAIN domain overrides */ +&hsm { + firmware-name = "j722s-hsm-m4f-fw"; +}; + &main_conf { serdes_ln_ctrl: mux-controller@4080 { compatible = "reg-mux"; diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/k3-j722s.dtsi index cdc8570e54b2..059c65ece183 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi @@ -162,7 +162,7 @@ <0x00 0x0fd20200 0x00 0x0fd20200 0x00 0x00000200>, /* JPEGENC0_CORE_MMU */ <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */ <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */ - <0x00 0x301C0000 0x00 0x301C0000 0x00 0x00001000>, /* DPHY-TX */ + <0x00 0x301c0000 0x00 0x301c0000 0x00 0x00001000>, /* DPHY-TX */ <0x00 0x30101000 0x00 0x30101000 0x00 0x00080100>, /* CSI window */ <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */ <0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */ @@ -173,6 +173,7 @@ <0x00 0x31200000 0x00 0x31200000 0x00 0x00040000>, /* USB1 DWC3 Core window */ <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */ <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */ + <0x00 0x43c00000 0x00 0x43c00000 0x00 0x00040000>, /* HSM SRAM ranges */ <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */ <0x00 0x48000000 0x00 0x48000000 0x00 0x06408000>, /* DMSS */ diff --git a/arch/arm64/boot/dts/ti/k3-j742s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j742s2-mcu-wakeup.dtsi index 61db2348d6a4..2f40afcfa67c 100644 --- a/arch/arm64/boot/dts/ti/k3-j742s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j742s2-mcu-wakeup.dtsi @@ -15,3 +15,7 @@ &mcu_r5fss0_core1 { firmware-name = "j742s2-mcu-r5f0_1-fw"; }; + +&hsm { + firmware-name = "j742s2-hsm-m4f-fw"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi index e50735577737..ff3a85cbc524 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi @@ -509,10 +509,10 @@ J784S4_WKUP_IOPAD(0x024, PIN_OUTPUT, 0) /* (G32) MCU_OSPI1_CSn0 */ J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (E35) MCU_OSPI1_D0 */ J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (D31) MCU_OSPI1_D1 */ - J784S4_WKUP_IOPAD(0x01C, PIN_INPUT, 0) /* (G31) MCU_OSPI1_D2 */ + J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (G31) MCU_OSPI1_D2 */ J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (F33) MCU_OSPI1_D3 */ J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F31) MCU_OSPI1_DQS */ - J784S4_WKUP_IOPAD(0x00C, PIN_INPUT, 0) /* (C31) MCU_OSPI1_LBCLKO */ + J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C31) MCU_OSPI1_LBCLKO */ >; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi index 9cc0901d58fb..c2636e624f18 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi @@ -2378,42 +2378,6 @@ assigned-clock-parents = <&k3_clks 351 4>; }; - watchdog4: watchdog@2240000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x2240000 0x00 0x100>; - clocks = <&k3_clks 352 0>; - power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 352 0>; - assigned-clock-parents = <&k3_clks 352 4>; - }; - - watchdog5: watchdog@2250000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x2250000 0x00 0x100>; - clocks = <&k3_clks 353 0>; - power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 353 0>; - assigned-clock-parents = <&k3_clks 353 4>; - }; - - watchdog6: watchdog@2260000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x2260000 0x00 0x100>; - clocks = <&k3_clks 354 0>; - power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 354 0>; - assigned-clock-parents = <&k3_clks 354 4>; - }; - - watchdog7: watchdog@2270000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x2270000 0x00 0x100>; - clocks = <&k3_clks 355 0>; - power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 355 0>; - assigned-clock-parents = <&k3_clks 355 4>; - }; - /* * The following RTI instances are coupled with MCU R5Fs, c7x and * GPU so keeping them reserved as these will be used by their diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi index cc22bfb5f599..df37902c963f 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi @@ -762,4 +762,21 @@ /* reserved for MCU_R5F0_1 */ status = "reserved"; }; + + hsm: remoteproc@43c00000 { + compatible = "ti,hsm-m4fss"; + /* contiguous regions but instantiated separately in HW */ + reg = <0x00 0x43c00000 0x00 0x20000>, + <0x00 0x43c20000 0x00 0x10000>, + <0x00 0x43c30000 0x00 0x10000>; + reg-names = "sram0_0", "sram0_1", "sram1"; + resets = <&k3_reset 371 1>; + firmware-name = "j784s4-hsm-m4f-fw"; + bootph-pre-ram; + ti,sci = <&sms>; + ti,sci-dev-id = <371>; + ti,sci-proc-ids = <0x80 0xff>; + /* reserved for early-stage bootloader */ + status = "reserved"; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index 0160fe0da983..78fcd0c40abc 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -6,17 +6,40 @@ */ &cbass_main { - c71_3: dsp@67800000 { - compatible = "ti,j721s2-c71-dsp"; - reg = <0x00 0x67800000 0x00 0x00080000>, - <0x00 0x67e00000 0x00 0x0000c000>; - reg-names = "l2sram", "l1dram"; - resets = <&k3_reset 40 1>; - firmware-name = "j784s4-c71_3-fw"; - ti,sci = <&sms>; - ti,sci-dev-id = <40>; - ti,sci-proc-ids = <0x33 0xff>; - status = "disabled"; + watchdog4: watchdog@2240000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2240000 0x00 0x100>; + clocks = <&k3_clks 352 0>; + power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 352 0>; + assigned-clock-parents = <&k3_clks 352 4>; + }; + + watchdog5: watchdog@2250000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2250000 0x00 0x100>; + clocks = <&k3_clks 353 0>; + power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 353 0>; + assigned-clock-parents = <&k3_clks 353 4>; + }; + + watchdog6: watchdog@2260000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2260000 0x00 0x100>; + clocks = <&k3_clks 354 0>; + power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 354 0>; + assigned-clock-parents = <&k3_clks 354 4>; + }; + + watchdog7: watchdog@2270000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2270000 0x00 0x100>; + clocks = <&k3_clks 355 0>; + power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 355 0>; + assigned-clock-parents = <&k3_clks 355 4>; }; pcie2_rc: pcie@2920000 { @@ -113,6 +136,19 @@ status = "disabled"; }; }; + + c71_3: dsp@67800000 { + compatible = "ti,j721s2-c71-dsp"; + reg = <0x00 0x67800000 0x00 0x00080000>, + <0x00 0x67e00000 0x00 0x0000c000>; + reg-names = "l2sram", "l1dram"; + resets = <&k3_reset 40 1>; + firmware-name = "j784s4-c71_3-fw"; + ti,sci = <&sms>; + ti,sci-dev-id = <40>; + ti,sci-proc-ids = <0x33 0xff>; + status = "disabled"; + }; }; &scm_conf { diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts b/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts index d209fdc98597..8d099b237025 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts +++ b/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts @@ -43,7 +43,7 @@ phy-handle = <&phy0>; phy-mode = "rgmii-id"; - mdio0 { + mdio { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio"; diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrb.dts b/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrb.dts index ed7aa7e457b1..4439b3e8acbb 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrb.dts +++ b/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrb.dts @@ -43,7 +43,7 @@ phy-handle = <&phy0>; phy-mode = "rgmii-id"; - mdio0 { + mdio { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio"; diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi index 0c8321022a73..af406f7285c4 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi +++ b/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi @@ -26,7 +26,7 @@ &spi0 { status = "okay"; - mmc-slot@0 { + mmc@0 { compatible = "mmc-spi-slot"; reg = <0>; gpios = <&gpio 15 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi index 9aa7b1872bd6..88e38d6efcaa 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi +++ b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi @@ -161,7 +161,7 @@ <0 0x24006000 0 0x2000>; }; - pmux: pmux@24190000 { + pmux: pinctrl@24190000 { compatible = "toshiba,tmpv7708-pinctrl"; reg = <0 0x24190000 0 0x10000>; }; @@ -463,7 +463,7 @@ status = "disabled"; }; - wdt: wdt@28330000 { + wdt: watchdog@28330000 { compatible = "toshiba,visconti-wdt"; reg = <0 0x28330000 0 0x1000>; clocks = <&pismu TMPV770X_CLK_WDTCLK>; diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708_pins.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708_pins.dtsi index a480c6ba5f5d..5ea835fe08a8 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708_pins.dtsi +++ b/arch/arm64/boot/dts/toshiba/tmpv7708_pins.dtsi @@ -91,7 +91,7 @@ bias-pull-up; }; - pwm_mux: pwm_mux { + pwm_mux: pwm-pins { function = "pwm"; }; diff --git a/arch/arm64/boot/dts/xilinx/versal-net.dtsi b/arch/arm64/boot/dts/xilinx/versal-net.dtsi index 412af9a394aa..15f767608e67 100644 --- a/arch/arm64/boot/dts/xilinx/versal-net.dtsi +++ b/arch/arm64/boot/dts/xilinx/versal-net.dtsi @@ -1018,7 +1018,7 @@ }; spi0: spi@f1960000 { - compatible = "cdns,spi-r1p6"; + compatible = "xlnx,versal-net-spi-r1p6", "cdns,spi-r1p6"; status = "disabled"; interrupts = <0 23 4>; reg = <0 0xf1960000 0 0x1000>; @@ -1026,7 +1026,7 @@ }; spi1: spi@f1970000 { - compatible = "cdns,spi-r1p6"; + compatible = "xlnx,versal-net-spi-r1p6", "cdns,spi-r1p6"; status = "disabled"; interrupts = <0 24 4>; reg = <0 0xf1970000 0 0x1000>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi index 52e122fc7c9e..482f432ba7f3 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi @@ -14,7 +14,7 @@ bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <33333333>; + clock-frequency = <33333000>; clock-output-names = "pss_ref_clk"; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso index 02be5e1e8686..23f6695d86b4 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso @@ -26,11 +26,6 @@ ethernet0 = "/axi/ethernet@ff0c0000"; /* &gem1 */ }; - ina260-u3 { - compatible = "iio-hwmon"; - io-channels = <&u3 0>, <&u3 1>, <&u3 2>; - }; - clk_26: clock2 { /* u17 - USB */ compatible = "fixed-clock"; #clock-cells = <0>; @@ -67,7 +62,6 @@ u3: ina260@40 { /* u3 */ compatible = "ti,ina260"; - #io-channel-cells = <1>; label = "ina260-u14"; reg = <0x40>; }; @@ -75,7 +69,6 @@ slg7xl45106: gpio@11 { /* u13 - reset logic */ compatible = "dlg,slg7xl45106"; reg = <0x11>; - label = "resetchip"; gpio-controller; #gpio-cells = <2>; gpio-line-names = "USB0_PHY_RESET_B", "", diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso index b92dcb86e87e..b82a056be2f9 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso @@ -25,11 +25,6 @@ ethernet1 = "/axi/ethernet@ff0c0000"; /* &gem1 */ }; - ina260-u14 { - compatible = "iio-hwmon"; - io-channels = <&u14 0>, <&u14 1>, <&u14 2>; - }; - clk_27: clock0 { /* u86 - DP */ compatible = "fixed-clock"; #clock-cells = <0>; @@ -95,7 +90,6 @@ u14: ina260@40 { /* u14 */ compatible = "ti,ina260"; - #io-channel-cells = <1>; label = "ina260-u14"; reg = <0x40>; }; @@ -103,7 +97,6 @@ slg7xl45106: gpio@11 { /* u19 - reset logic */ compatible = "dlg,slg7xl45106"; reg = <0x11>; - label = "resetchip"; gpio-controller; #gpio-cells = <2>; gpio-line-names = "USB0_PHY_RESET_B", "USB1_PHY_RESET_B", diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso index 99ad220d13d6..4dcf92a2158f 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso @@ -25,11 +25,6 @@ ethernet1 = "/axi/ethernet@ff0c0000"; /* &gem1 */ }; - ina260-u14 { - compatible = "iio-hwmon"; - io-channels = <&u14 0>, <&u14 1>, <&u14 2>; - }; - clk_125: clock0 { /* u87 - GEM0/1 */ compatible = "fixed-clock"; #clock-cells = <0>; @@ -96,7 +91,6 @@ u14: ina260@40 { /* u14 */ compatible = "ti,ina260"; - #io-channel-cells = <1>; label = "ina260-u14"; reg = <0x40>; }; @@ -104,7 +98,6 @@ slg7xl45106: gpio@11 { /* u19 - reset logic */ compatible = "dlg,slg7xl45106"; reg = <0x11>; - label = "resetchip"; gpio-controller; #gpio-cells = <2>; gpio-line-names = "USB0_PHY_RESET_B", "USB1_PHY_RESET_B", diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso index d7351a17d3e8..923a70d750bf 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso @@ -32,11 +32,6 @@ ethernet0 = "/axi/ethernet@ff0e0000"; /* &gem3 */ }; - ina260-u14 { - compatible = "iio-hwmon"; - io-channels = <&u14 0>, <&u14 1>, <&u14 2>; - }; - si5332_0: si5332-0 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; @@ -96,7 +91,6 @@ u14: ina260@40 { /* u14 */ compatible = "ti,ina260"; - #io-channel-cells = <1>; label = "ina260-u14"; reg = <0x40>; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso index a4ae37ebaccf..563e750b0e08 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso @@ -27,11 +27,6 @@ ethernet0 = "/axi/ethernet@ff0e0000"; /* &gem3 */ }; - ina260-u14 { - compatible = "iio-hwmon"; - io-channels = <&u14 0>, <&u14 1>, <&u14 2>; - }; - si5332_0: si5332-0 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; @@ -92,7 +87,6 @@ u14: ina260@40 { /* u14 */ compatible = "ti,ina260"; - #io-channel-cells = <1>; label = "ina260-u14"; reg = <0x40>; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 938b014ca923..29058e633fe9 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -103,23 +103,23 @@ cpu_opp_table: opp-table-cpu { compatible = "operating-points-v2"; opp-shared; - opp00 { - opp-hz = /bits/ 64 <1199999988>; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; - opp01 { - opp-hz = /bits/ 64 <599999994>; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; - opp02 { - opp-hz = /bits/ 64 <399999996>; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; - opp03 { - opp-hz = /bits/ 64 <299999997>; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; @@ -192,11 +192,6 @@ }; firmware { - optee: optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - zynqmp_firmware: zynqmp-firmware { compatible = "xlnx,zynqmp-firmware"; #power-domain-cells = <1>; @@ -1080,7 +1075,7 @@ }; spi0: spi@ff040000 { - compatible = "cdns,spi-r1p6"; + compatible = "xlnx,zynqmp-spi-r1p6", "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; @@ -1092,7 +1087,7 @@ }; spi1: spi@ff050000 { - compatible = "cdns,spi-r1p6"; + compatible = "xlnx,zynqmp-spi-r1p6", "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts index 08cf716328a0..feaa75d5aead 100644 --- a/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts @@ -59,6 +59,18 @@ status = "okay"; }; +&ledc { + pinctrl-0 = <&ledc_pc0_pin>; + pinctrl-names = "default"; + status = "okay"; + + multi-led@0 { + reg = <0x0>; + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_STATUS; + }; +}; + &mmc1 { bus-width = <4>; mmc-pwrseq = <&wifi_pwrseq>; diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts index 8dbe717c79ce..73840ea300f0 100644 --- a/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts @@ -22,6 +22,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> /dts-v1/; @@ -121,6 +122,18 @@ }; }; +&ledc { + pinctrl-0 = <&ledc_pc0_pin>; + pinctrl-names = "default"; + status = "okay"; + + multi-led@0 { + reg = <0x0>; + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_STATUS; + }; +}; + &mdio { ext_rgmii_phy: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi index b18f368e06e0..b0fb0ea377bc 100644 --- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi @@ -59,6 +59,12 @@ }; /omit-if-no-ref/ + ledc_pc0_pin: ledc-pc0-pin { + pins = "PC0"; + function = "ledc"; + }; + + /omit-if-no-ref/ uart0_pb8_pins: uart0-pb8-pins { pins = "PB8", "PB9"; function = "uart0"; diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi index a7442a508433..3f4ee820ef56 100644 --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi @@ -1,6 +1,8 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) // Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org> +#include <dt-bindings/thermal/thermal.h> + #define SOC_PERIPHERAL_IRQ(nr) (nr + 16) #include "sunxi-d1s-t113.dtsi" @@ -115,4 +117,33 @@ <0x00000000 0x0000000e 0xffffffff 0xffffffff 0x00010000>, <0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>; }; + + thermal-zones { + cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths>; + + cooling-maps { + map0 { + trip = <&cpu_alert>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu_alert: cpu-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-crit { + temperature = <100000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; }; diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi index 63e252b44973..82cc85acccb1 100644 --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi @@ -204,6 +204,21 @@ #reset-cells = <1>; }; + ledc: led-controller@2008000 { + compatible = "allwinner,sun20i-d1-ledc", + "allwinner,sun50i-a100-ledc"; + reg = <0x2008000 0x400>; + interrupts = <SOC_PERIPHERAL_IRQ(20) IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_LEDC>, <&ccu CLK_LEDC>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_LEDC>; + dmas = <&dma 42>; + dma-names = "tx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gpadc: adc@2009000 { compatible = "allwinner,sun20i-d1-gpadc"; reg = <0x2009000 0x400>; @@ -214,6 +229,18 @@ #io-channel-cells = <1>; }; + ths: thermal-sensor@2009400 { + compatible = "allwinner,sun20i-d1-ths"; + reg = <0x2009400 0x400>; + interrupts = <SOC_PERIPHERAL_IRQ(58) IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_THS>; + clock-names = "bus"; + resets = <&ccu RST_BUS_THS>; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; + #thermal-sensor-cells = <0>; + }; + dmic: dmic@2031000 { compatible = "allwinner,sun20i-d1-dmic", "allwinner,sun50i-h6-dmic"; @@ -474,6 +501,10 @@ reg = <0x3006000 0x1000>; #address-cells = <1>; #size-cells = <1>; + + ths_calibration: thermal-sensor-calibration@14 { + reg = <0x14 0x8>; + }; }; crypto: crypto@3040000 { diff --git a/arch/riscv/boot/dts/anlogic/dr1v90.dtsi b/arch/riscv/boot/dts/anlogic/dr1v90.dtsi index a5d0765ade32..9fe183f5f5c8 100644 --- a/arch/riscv/boot/dts/anlogic/dr1v90.dtsi +++ b/arch/riscv/boot/dts/anlogic/dr1v90.dtsi @@ -27,8 +27,9 @@ mmu-type = "riscv,sv39"; reg = <0>; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zbc", - "zbkc", "zbs", "zicntr", "zicsr", "zifencei", + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", + "zba", "zbb", "zbc", "zbkc", "zbs", + "zicntr", "zicsr", "zifencei", "zihintpause", "zihpm"; cpu0_intc: interrupt-controller { diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index 9883ca3554c5..5c2963e269b8 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -251,14 +251,17 @@ #dma-cells = <1>; }; - clkcfg: clkcfg@20002000 { - compatible = "microchip,mpfs-clkcfg"; - reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>; - clocks = <&refclk>; - #clock-cells = <1>; + mss_top_sysreg: syscon@20002000 { + compatible = "microchip,mpfs-mss-top-sysreg", "syscon", "simple-mfd"; + reg = <0x0 0x20002000 0x0 0x1000>; #reset-cells = <1>; }; + sysreg_scb: syscon@20003000 { + compatible = "microchip,mpfs-sysreg-scb", "syscon"; + reg = <0x0 0x20003000 0x0 0x1000>; + }; + ccc_se: clock-controller@38010000 { compatible = "microchip,mpfs-ccc"; reg = <0x0 0x38010000 0x0 0x1000>, <0x0 0x38020000 0x0 0x1000>, @@ -447,7 +450,7 @@ local-mac-address = [00 00 00 00 00 00]; clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>; clock-names = "pclk", "hclk"; - resets = <&clkcfg CLK_MAC0>; + resets = <&mss_top_sysreg CLK_MAC0>; status = "disabled"; }; @@ -461,7 +464,7 @@ local-mac-address = [00 00 00 00 00 00]; clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>; clock-names = "pclk", "hclk"; - resets = <&clkcfg CLK_MAC1>; + resets = <&mss_top_sysreg CLK_MAC1>; status = "disabled"; }; @@ -521,10 +524,14 @@ status = "disabled"; }; - mbox: mailbox@37020000 { + control_scb: syscon@37020000 { + compatible = "microchip,mpfs-control-scb", "syscon"; + reg = <0x0 0x37020000 0x0 0x100>; + }; + + mbox: mailbox@37020800 { compatible = "microchip,mpfs-mailbox"; - reg = <0x0 0x37020000 0x0 0x58>, <0x0 0x2000318C 0x0 0x40>, - <0x0 0x37020800 0x0 0x100>; + reg = <0x0 0x37020800 0x0 0x1000>; interrupt-parent = <&plic>; interrupts = <96>; #mbox-cells = <1>; @@ -541,5 +548,12 @@ clocks = <&scbclk>; status = "disabled"; }; + + clkcfg: clkcfg@3e001000 { + compatible = "microchip,mpfs-clkcfg"; + reg = <0x0 0x3e001000 0x0 0x1000>; + clocks = <&refclk>; + #clock-cells = <1>; + }; }; }; diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi index a8bcb26f4270..571de3cafa82 100644 --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi @@ -12,6 +12,8 @@ #include <arm64/renesas/r9a07g043.dtsi> / { + interrupt-parent = <&plic>; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -52,7 +54,6 @@ &soc { dma-noncoherent; - interrupt-parent = <&plic>; irqc: interrupt-controller@110a0000 { compatible = "renesas,r9a07g043f-irqc"; diff --git a/arch/riscv/boot/dts/sophgo/cv180x.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi index 1b2b1969a648..06b0ce5a2db7 100644 --- a/arch/riscv/boot/dts/sophgo/cv180x.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi @@ -438,8 +438,8 @@ clocks = <&clk CLK_AXI4_USB>, <&clk CLK_APB_USB>; clock-names = "otg", "utmi"; g-np-tx-fifo-size = <32>; - g-rx-fifo-size = <536>; - g-tx-fifo-size = <768 512 512 384 128 128>; + g-rx-fifo-size = <1536>; + g-tx-fifo-size = <128 128 64 64 64 64 32 32>; interrupts = <SOC_PERIPHERAL_IRQ(14) IRQ_TYPE_LEVEL_HIGH>; phys = <&usbphy>; phy-names = "usb2-phy"; diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi index 94a4b71acad3..509488eee432 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi @@ -2189,4 +2189,309 @@ cache-unified; }; }; + + soc { + intc: interrupt-controller@7090000000 { + compatible = "sophgo,sg2042-plic", "thead,c900-plic"; + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x00000070 0x90000000 0x00000000 0x04000000>; + interrupt-controller; + interrupts-extended = + <&cpu0_intc 11>, <&cpu0_intc 9>, + <&cpu1_intc 11>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu2_intc 9>, + <&cpu3_intc 11>, <&cpu3_intc 9>, + <&cpu4_intc 11>, <&cpu4_intc 9>, + <&cpu5_intc 11>, <&cpu5_intc 9>, + <&cpu6_intc 11>, <&cpu6_intc 9>, + <&cpu7_intc 11>, <&cpu7_intc 9>, + <&cpu8_intc 11>, <&cpu8_intc 9>, + <&cpu9_intc 11>, <&cpu9_intc 9>, + <&cpu10_intc 11>, <&cpu10_intc 9>, + <&cpu11_intc 11>, <&cpu11_intc 9>, + <&cpu12_intc 11>, <&cpu12_intc 9>, + <&cpu13_intc 11>, <&cpu13_intc 9>, + <&cpu14_intc 11>, <&cpu14_intc 9>, + <&cpu15_intc 11>, <&cpu15_intc 9>, + <&cpu16_intc 11>, <&cpu16_intc 9>, + <&cpu17_intc 11>, <&cpu17_intc 9>, + <&cpu18_intc 11>, <&cpu18_intc 9>, + <&cpu19_intc 11>, <&cpu19_intc 9>, + <&cpu20_intc 11>, <&cpu20_intc 9>, + <&cpu21_intc 11>, <&cpu21_intc 9>, + <&cpu22_intc 11>, <&cpu22_intc 9>, + <&cpu23_intc 11>, <&cpu23_intc 9>, + <&cpu24_intc 11>, <&cpu24_intc 9>, + <&cpu25_intc 11>, <&cpu25_intc 9>, + <&cpu26_intc 11>, <&cpu26_intc 9>, + <&cpu27_intc 11>, <&cpu27_intc 9>, + <&cpu28_intc 11>, <&cpu28_intc 9>, + <&cpu29_intc 11>, <&cpu29_intc 9>, + <&cpu30_intc 11>, <&cpu30_intc 9>, + <&cpu31_intc 11>, <&cpu31_intc 9>, + <&cpu32_intc 11>, <&cpu32_intc 9>, + <&cpu33_intc 11>, <&cpu33_intc 9>, + <&cpu34_intc 11>, <&cpu34_intc 9>, + <&cpu35_intc 11>, <&cpu35_intc 9>, + <&cpu36_intc 11>, <&cpu36_intc 9>, + <&cpu37_intc 11>, <&cpu37_intc 9>, + <&cpu38_intc 11>, <&cpu38_intc 9>, + <&cpu39_intc 11>, <&cpu39_intc 9>, + <&cpu40_intc 11>, <&cpu40_intc 9>, + <&cpu41_intc 11>, <&cpu41_intc 9>, + <&cpu42_intc 11>, <&cpu42_intc 9>, + <&cpu43_intc 11>, <&cpu43_intc 9>, + <&cpu44_intc 11>, <&cpu44_intc 9>, + <&cpu45_intc 11>, <&cpu45_intc 9>, + <&cpu46_intc 11>, <&cpu46_intc 9>, + <&cpu47_intc 11>, <&cpu47_intc 9>, + <&cpu48_intc 11>, <&cpu48_intc 9>, + <&cpu49_intc 11>, <&cpu49_intc 9>, + <&cpu50_intc 11>, <&cpu50_intc 9>, + <&cpu51_intc 11>, <&cpu51_intc 9>, + <&cpu52_intc 11>, <&cpu52_intc 9>, + <&cpu53_intc 11>, <&cpu53_intc 9>, + <&cpu54_intc 11>, <&cpu54_intc 9>, + <&cpu55_intc 11>, <&cpu55_intc 9>, + <&cpu56_intc 11>, <&cpu56_intc 9>, + <&cpu57_intc 11>, <&cpu57_intc 9>, + <&cpu58_intc 11>, <&cpu58_intc 9>, + <&cpu59_intc 11>, <&cpu59_intc 9>, + <&cpu60_intc 11>, <&cpu60_intc 9>, + <&cpu61_intc 11>, <&cpu61_intc 9>, + <&cpu62_intc 11>, <&cpu62_intc 9>, + <&cpu63_intc 11>, <&cpu63_intc 9>; + riscv,ndev = <224>; + }; + + clint_mswi: interrupt-controller@7094000000 { + compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi"; + reg = <0x00000070 0x94000000 0x00000000 0x00004000>; + interrupts-extended = <&cpu0_intc 3>, + <&cpu1_intc 3>, + <&cpu2_intc 3>, + <&cpu3_intc 3>, + <&cpu4_intc 3>, + <&cpu5_intc 3>, + <&cpu6_intc 3>, + <&cpu7_intc 3>, + <&cpu8_intc 3>, + <&cpu9_intc 3>, + <&cpu10_intc 3>, + <&cpu11_intc 3>, + <&cpu12_intc 3>, + <&cpu13_intc 3>, + <&cpu14_intc 3>, + <&cpu15_intc 3>, + <&cpu16_intc 3>, + <&cpu17_intc 3>, + <&cpu18_intc 3>, + <&cpu19_intc 3>, + <&cpu20_intc 3>, + <&cpu21_intc 3>, + <&cpu22_intc 3>, + <&cpu23_intc 3>, + <&cpu24_intc 3>, + <&cpu25_intc 3>, + <&cpu26_intc 3>, + <&cpu27_intc 3>, + <&cpu28_intc 3>, + <&cpu29_intc 3>, + <&cpu30_intc 3>, + <&cpu31_intc 3>, + <&cpu32_intc 3>, + <&cpu33_intc 3>, + <&cpu34_intc 3>, + <&cpu35_intc 3>, + <&cpu36_intc 3>, + <&cpu37_intc 3>, + <&cpu38_intc 3>, + <&cpu39_intc 3>, + <&cpu40_intc 3>, + <&cpu41_intc 3>, + <&cpu42_intc 3>, + <&cpu43_intc 3>, + <&cpu44_intc 3>, + <&cpu45_intc 3>, + <&cpu46_intc 3>, + <&cpu47_intc 3>, + <&cpu48_intc 3>, + <&cpu49_intc 3>, + <&cpu50_intc 3>, + <&cpu51_intc 3>, + <&cpu52_intc 3>, + <&cpu53_intc 3>, + <&cpu54_intc 3>, + <&cpu55_intc 3>, + <&cpu56_intc 3>, + <&cpu57_intc 3>, + <&cpu58_intc 3>, + <&cpu59_intc 3>, + <&cpu60_intc 3>, + <&cpu61_intc 3>, + <&cpu62_intc 3>, + <&cpu63_intc 3>; + }; + + clint_mtimer0: timer@70ac004000 { + compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; + reg = <0x00000070 0xac004000 0x00000000 0x0000c000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu0_intc 7>, + <&cpu1_intc 7>, + <&cpu2_intc 7>, + <&cpu3_intc 7>; + }; + + clint_mtimer1: timer@70ac014000 { + compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; + reg = <0x00000070 0xac014000 0x00000000 0x0000c000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu4_intc 7>, + <&cpu5_intc 7>, + <&cpu6_intc 7>, + <&cpu7_intc 7>; + }; + + clint_mtimer2: timer@70ac024000 { + compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; + reg = <0x00000070 0xac024000 0x00000000 0x0000c000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu8_intc 7>, + <&cpu9_intc 7>, + <&cpu10_intc 7>, + <&cpu11_intc 7>; + }; + + clint_mtimer3: timer@70ac034000 { + compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; + reg = <0x00000070 0xac034000 0x00000000 0x0000c000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu12_intc 7>, + <&cpu13_intc 7>, + <&cpu14_intc 7>, + <&cpu15_intc 7>; + }; + + clint_mtimer4: timer@70ac044000 { + compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; + reg = <0x00000070 0xac044000 0x00000000 0x0000c000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu16_intc 7>, + <&cpu17_intc 7>, + <&cpu18_intc 7>, + <&cpu19_intc 7>; + }; + + clint_mtimer5: timer@70ac054000 { + compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; + reg = <0x00000070 0xac054000 0x00000000 0x0000c000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu20_intc 7>, + <&cpu21_intc 7>, + <&cpu22_intc 7>, + <&cpu23_intc 7>; + }; + + clint_mtimer6: timer@70ac064000 { + compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; + reg = <0x00000070 0xac064000 0x00000000 0x0000c000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu24_intc 7>, + <&cpu25_intc 7>, + <&cpu26_intc 7>, + <&cpu27_intc 7>; + }; + + clint_mtimer7: timer@70ac074000 { + compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; + reg = <0x00000070 0xac074000 0x00000000 0x0000c000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu28_intc 7>, + <&cpu29_intc 7>, + <&cpu30_intc 7>, + <&cpu31_intc 7>; + }; + + clint_mtimer8: timer@70ac084000 { + compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; + reg = <0x00000070 0xac084000 0x00000000 0x0000c000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu32_intc 7>, + <&cpu33_intc 7>, + <&cpu34_intc 7>, + <&cpu35_intc 7>; + }; + + clint_mtimer9: timer@70ac094000 { + compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; + reg = <0x00000070 0xac094000 0x00000000 0x0000c000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu36_intc 7>, + <&cpu37_intc 7>, + <&cpu38_intc 7>, + <&cpu39_intc 7>; + }; + + clint_mtimer10: timer@70ac0a4000 { + compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; + reg = <0x00000070 0xac0a4000 0x00000000 0x0000c000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu40_intc 7>, + <&cpu41_intc 7>, + <&cpu42_intc 7>, + <&cpu43_intc 7>; + }; + + clint_mtimer11: timer@70ac0b4000 { + compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; + reg = <0x00000070 0xac0b4000 0x00000000 0x0000c000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu44_intc 7>, + <&cpu45_intc 7>, + <&cpu46_intc 7>, + <&cpu47_intc 7>; + }; + + clint_mtimer12: timer@70ac0c4000 { + compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; + reg = <0x00000070 0xac0c4000 0x00000000 0x0000c000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu48_intc 7>, + <&cpu49_intc 7>, + <&cpu50_intc 7>, + <&cpu51_intc 7>; + }; + + clint_mtimer13: timer@70ac0d4000 { + compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; + reg = <0x00000070 0xac0d4000 0x00000000 0x0000c000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu52_intc 7>, + <&cpu53_intc 7>, + <&cpu54_intc 7>, + <&cpu55_intc 7>; + }; + + clint_mtimer14: timer@70ac0e4000 { + compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; + reg = <0x00000070 0xac0e4000 0x00000000 0x0000c000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu56_intc 7>, + <&cpu57_intc 7>, + <&cpu58_intc 7>, + <&cpu59_intc 7>; + }; + + clint_mtimer15: timer@70ac0f4000 { + compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; + reg = <0x00000070 0xac0f4000 0x00000000 0x0000c000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu60_intc 7>, + <&cpu61_intc 7>, + <&cpu62_intc 7>, + <&cpu63_intc 7>; + }; + }; }; diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts index 54d8386bf9c0..ecf8c1e29079 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts +++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts @@ -52,6 +52,17 @@ status = "okay"; }; +&i2c0 { + pinctrl-0 = <&i2c0_cfg>; + pinctrl-names = "default"; + status = "okay"; + + rtc: rtc@68 { + compatible = "dallas,ds1307"; + reg = <0x68>; + }; +}; + &i2c1 { pinctrl-0 = <&i2c1_cfg>; pinctrl-names = "default"; @@ -89,6 +100,16 @@ }; }; + i2c0_cfg: i2c0-cfg { + i2c0-pins { + pinmux = <PINMUX(PIN_IIC0_SDA, 0)>, + <PINMUX(PIN_IIC0_SCL, 0)>; + bias-pull-up; + drive-strength-microamp = <26800>; + input-schmitt-enable; + }; + }; + i2c1_cfg: i2c1-cfg { i2c1-pins { pinmux = <PINMUX(PIN_IIC1_SDA, 0)>, diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi index ec99da39150f..9fddf3f0b3b9 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -264,397 +264,6 @@ #clock-cells = <1>; }; - pcie_rc0: pcie@7060000000 { - compatible = "sophgo,sg2042-pcie-host"; - device_type = "pci"; - reg = <0x70 0x60000000 0x0 0x00800000>, - <0x40 0x00000000 0x0 0x00001000>; - reg-names = "reg", "cfg"; - linux,pci-domain = <0>; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x01000000 0x0 0x00000000 0x40 0xc0000000 0x0 0x00400000>, - <0x42000000 0x0 0xd0000000 0x40 0xd0000000 0x0 0x10000000>, - <0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>, - <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>, - <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>; - bus-range = <0x0 0xff>; - vendor-id = <0x1f1c>; - device-id = <0x2042>; - cdns,no-bar-match-nbits = <48>; - msi-parent = <&msi>; - status = "disabled"; - }; - - pcie_rc1: pcie@7060800000 { - compatible = "sophgo,sg2042-pcie-host"; - device_type = "pci"; - reg = <0x70 0x60800000 0x0 0x00800000>, - <0x44 0x00000000 0x0 0x00001000>; - reg-names = "reg", "cfg"; - linux,pci-domain = <1>; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x01000000 0x0 0x00000000 0x44 0xc0400000 0x0 0x00400000>, - <0x42000000 0x0 0xd0000000 0x44 0xd0000000 0x0 0x10000000>, - <0x02000000 0x0 0xe0000000 0x44 0xe0000000 0x0 0x20000000>, - <0x43000000 0x46 0x00000000 0x46 0x00000000 0x2 0x00000000>, - <0x03000000 0x45 0x00000000 0x45 0x00000000 0x1 0x00000000>; - bus-range = <0x0 0xff>; - vendor-id = <0x1f1c>; - device-id = <0x2042>; - cdns,no-bar-match-nbits = <48>; - msi-parent = <&msi>; - status = "disabled"; - }; - - pcie_rc2: pcie@7062000000 { - compatible = "sophgo,sg2042-pcie-host"; - device_type = "pci"; - reg = <0x70 0x62000000 0x0 0x00800000>, - <0x48 0x00000000 0x0 0x00001000>; - reg-names = "reg", "cfg"; - linux,pci-domain = <2>; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x01000000 0x0 0x00000000 0x48 0xc0800000 0x0 0x00400000>, - <0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>, - <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>, - <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>, - <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>; - bus-range = <0x0 0xff>; - vendor-id = <0x1f1c>; - device-id = <0x2042>; - cdns,no-bar-match-nbits = <48>; - msi-parent = <&msi>; - status = "disabled"; - }; - - pcie_rc3: pcie@7062800000 { - compatible = "sophgo,sg2042-pcie-host"; - device_type = "pci"; - reg = <0x70 0x62800000 0x0 0x00800000>, - <0x4c 0x00000000 0x0 0x00001000>; - reg-names = "reg", "cfg"; - linux,pci-domain = <3>; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x01000000 0x0 0x00000000 0x4c 0xc0c00000 0x0 0x00400000>, - <0x42000000 0x0 0xf8000000 0x4c 0xf8000000 0x0 0x04000000>, - <0x02000000 0x0 0xfc000000 0x4c 0xfc000000 0x0 0x04000000>, - <0x43000000 0x4e 0x00000000 0x4e 0x00000000 0x2 0x00000000>, - <0x03000000 0x4d 0x00000000 0x4d 0x00000000 0x1 0x00000000>; - bus-range = <0x0 0xff>; - vendor-id = <0x1f1c>; - device-id = <0x2042>; - cdns,no-bar-match-nbits = <48>; - msi-parent = <&msi>; - status = "disabled"; - }; - - clint_mswi: interrupt-controller@7094000000 { - compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi"; - reg = <0x00000070 0x94000000 0x00000000 0x00004000>; - interrupts-extended = <&cpu0_intc 3>, - <&cpu1_intc 3>, - <&cpu2_intc 3>, - <&cpu3_intc 3>, - <&cpu4_intc 3>, - <&cpu5_intc 3>, - <&cpu6_intc 3>, - <&cpu7_intc 3>, - <&cpu8_intc 3>, - <&cpu9_intc 3>, - <&cpu10_intc 3>, - <&cpu11_intc 3>, - <&cpu12_intc 3>, - <&cpu13_intc 3>, - <&cpu14_intc 3>, - <&cpu15_intc 3>, - <&cpu16_intc 3>, - <&cpu17_intc 3>, - <&cpu18_intc 3>, - <&cpu19_intc 3>, - <&cpu20_intc 3>, - <&cpu21_intc 3>, - <&cpu22_intc 3>, - <&cpu23_intc 3>, - <&cpu24_intc 3>, - <&cpu25_intc 3>, - <&cpu26_intc 3>, - <&cpu27_intc 3>, - <&cpu28_intc 3>, - <&cpu29_intc 3>, - <&cpu30_intc 3>, - <&cpu31_intc 3>, - <&cpu32_intc 3>, - <&cpu33_intc 3>, - <&cpu34_intc 3>, - <&cpu35_intc 3>, - <&cpu36_intc 3>, - <&cpu37_intc 3>, - <&cpu38_intc 3>, - <&cpu39_intc 3>, - <&cpu40_intc 3>, - <&cpu41_intc 3>, - <&cpu42_intc 3>, - <&cpu43_intc 3>, - <&cpu44_intc 3>, - <&cpu45_intc 3>, - <&cpu46_intc 3>, - <&cpu47_intc 3>, - <&cpu48_intc 3>, - <&cpu49_intc 3>, - <&cpu50_intc 3>, - <&cpu51_intc 3>, - <&cpu52_intc 3>, - <&cpu53_intc 3>, - <&cpu54_intc 3>, - <&cpu55_intc 3>, - <&cpu56_intc 3>, - <&cpu57_intc 3>, - <&cpu58_intc 3>, - <&cpu59_intc 3>, - <&cpu60_intc 3>, - <&cpu61_intc 3>, - <&cpu62_intc 3>, - <&cpu63_intc 3>; - }; - - clint_mtimer0: timer@70ac004000 { - compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; - reg = <0x00000070 0xac004000 0x00000000 0x0000c000>; - reg-names = "mtimecmp"; - interrupts-extended = <&cpu0_intc 7>, - <&cpu1_intc 7>, - <&cpu2_intc 7>, - <&cpu3_intc 7>; - }; - - clint_mtimer1: timer@70ac014000 { - compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; - reg = <0x00000070 0xac014000 0x00000000 0x0000c000>; - reg-names = "mtimecmp"; - interrupts-extended = <&cpu4_intc 7>, - <&cpu5_intc 7>, - <&cpu6_intc 7>, - <&cpu7_intc 7>; - }; - - clint_mtimer2: timer@70ac024000 { - compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; - reg = <0x00000070 0xac024000 0x00000000 0x0000c000>; - reg-names = "mtimecmp"; - interrupts-extended = <&cpu8_intc 7>, - <&cpu9_intc 7>, - <&cpu10_intc 7>, - <&cpu11_intc 7>; - }; - - clint_mtimer3: timer@70ac034000 { - compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; - reg = <0x00000070 0xac034000 0x00000000 0x0000c000>; - reg-names = "mtimecmp"; - interrupts-extended = <&cpu12_intc 7>, - <&cpu13_intc 7>, - <&cpu14_intc 7>, - <&cpu15_intc 7>; - }; - - clint_mtimer4: timer@70ac044000 { - compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; - reg = <0x00000070 0xac044000 0x00000000 0x0000c000>; - reg-names = "mtimecmp"; - interrupts-extended = <&cpu16_intc 7>, - <&cpu17_intc 7>, - <&cpu18_intc 7>, - <&cpu19_intc 7>; - }; - - clint_mtimer5: timer@70ac054000 { - compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; - reg = <0x00000070 0xac054000 0x00000000 0x0000c000>; - reg-names = "mtimecmp"; - interrupts-extended = <&cpu20_intc 7>, - <&cpu21_intc 7>, - <&cpu22_intc 7>, - <&cpu23_intc 7>; - }; - - clint_mtimer6: timer@70ac064000 { - compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; - reg = <0x00000070 0xac064000 0x00000000 0x0000c000>; - reg-names = "mtimecmp"; - interrupts-extended = <&cpu24_intc 7>, - <&cpu25_intc 7>, - <&cpu26_intc 7>, - <&cpu27_intc 7>; - }; - - clint_mtimer7: timer@70ac074000 { - compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; - reg = <0x00000070 0xac074000 0x00000000 0x0000c000>; - reg-names = "mtimecmp"; - interrupts-extended = <&cpu28_intc 7>, - <&cpu29_intc 7>, - <&cpu30_intc 7>, - <&cpu31_intc 7>; - }; - - clint_mtimer8: timer@70ac084000 { - compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; - reg = <0x00000070 0xac084000 0x00000000 0x0000c000>; - reg-names = "mtimecmp"; - interrupts-extended = <&cpu32_intc 7>, - <&cpu33_intc 7>, - <&cpu34_intc 7>, - <&cpu35_intc 7>; - }; - - clint_mtimer9: timer@70ac094000 { - compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; - reg = <0x00000070 0xac094000 0x00000000 0x0000c000>; - reg-names = "mtimecmp"; - interrupts-extended = <&cpu36_intc 7>, - <&cpu37_intc 7>, - <&cpu38_intc 7>, - <&cpu39_intc 7>; - }; - - clint_mtimer10: timer@70ac0a4000 { - compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; - reg = <0x00000070 0xac0a4000 0x00000000 0x0000c000>; - reg-names = "mtimecmp"; - interrupts-extended = <&cpu40_intc 7>, - <&cpu41_intc 7>, - <&cpu42_intc 7>, - <&cpu43_intc 7>; - }; - - clint_mtimer11: timer@70ac0b4000 { - compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; - reg = <0x00000070 0xac0b4000 0x00000000 0x0000c000>; - reg-names = "mtimecmp"; - interrupts-extended = <&cpu44_intc 7>, - <&cpu45_intc 7>, - <&cpu46_intc 7>, - <&cpu47_intc 7>; - }; - - clint_mtimer12: timer@70ac0c4000 { - compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; - reg = <0x00000070 0xac0c4000 0x00000000 0x0000c000>; - reg-names = "mtimecmp"; - interrupts-extended = <&cpu48_intc 7>, - <&cpu49_intc 7>, - <&cpu50_intc 7>, - <&cpu51_intc 7>; - }; - - clint_mtimer13: timer@70ac0d4000 { - compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; - reg = <0x00000070 0xac0d4000 0x00000000 0x0000c000>; - reg-names = "mtimecmp"; - interrupts-extended = <&cpu52_intc 7>, - <&cpu53_intc 7>, - <&cpu54_intc 7>, - <&cpu55_intc 7>; - }; - - clint_mtimer14: timer@70ac0e4000 { - compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; - reg = <0x00000070 0xac0e4000 0x00000000 0x0000c000>; - reg-names = "mtimecmp"; - interrupts-extended = <&cpu56_intc 7>, - <&cpu57_intc 7>, - <&cpu58_intc 7>, - <&cpu59_intc 7>; - }; - - clint_mtimer15: timer@70ac0f4000 { - compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; - reg = <0x00000070 0xac0f4000 0x00000000 0x0000c000>; - reg-names = "mtimecmp"; - interrupts-extended = <&cpu60_intc 7>, - <&cpu61_intc 7>, - <&cpu62_intc 7>, - <&cpu63_intc 7>; - }; - - intc: interrupt-controller@7090000000 { - compatible = "sophgo,sg2042-plic", "thead,c900-plic"; - #address-cells = <0>; - #interrupt-cells = <2>; - reg = <0x00000070 0x90000000 0x00000000 0x04000000>; - interrupt-controller; - interrupts-extended = - <&cpu0_intc 11>, <&cpu0_intc 9>, - <&cpu1_intc 11>, <&cpu1_intc 9>, - <&cpu2_intc 11>, <&cpu2_intc 9>, - <&cpu3_intc 11>, <&cpu3_intc 9>, - <&cpu4_intc 11>, <&cpu4_intc 9>, - <&cpu5_intc 11>, <&cpu5_intc 9>, - <&cpu6_intc 11>, <&cpu6_intc 9>, - <&cpu7_intc 11>, <&cpu7_intc 9>, - <&cpu8_intc 11>, <&cpu8_intc 9>, - <&cpu9_intc 11>, <&cpu9_intc 9>, - <&cpu10_intc 11>, <&cpu10_intc 9>, - <&cpu11_intc 11>, <&cpu11_intc 9>, - <&cpu12_intc 11>, <&cpu12_intc 9>, - <&cpu13_intc 11>, <&cpu13_intc 9>, - <&cpu14_intc 11>, <&cpu14_intc 9>, - <&cpu15_intc 11>, <&cpu15_intc 9>, - <&cpu16_intc 11>, <&cpu16_intc 9>, - <&cpu17_intc 11>, <&cpu17_intc 9>, - <&cpu18_intc 11>, <&cpu18_intc 9>, - <&cpu19_intc 11>, <&cpu19_intc 9>, - <&cpu20_intc 11>, <&cpu20_intc 9>, - <&cpu21_intc 11>, <&cpu21_intc 9>, - <&cpu22_intc 11>, <&cpu22_intc 9>, - <&cpu23_intc 11>, <&cpu23_intc 9>, - <&cpu24_intc 11>, <&cpu24_intc 9>, - <&cpu25_intc 11>, <&cpu25_intc 9>, - <&cpu26_intc 11>, <&cpu26_intc 9>, - <&cpu27_intc 11>, <&cpu27_intc 9>, - <&cpu28_intc 11>, <&cpu28_intc 9>, - <&cpu29_intc 11>, <&cpu29_intc 9>, - <&cpu30_intc 11>, <&cpu30_intc 9>, - <&cpu31_intc 11>, <&cpu31_intc 9>, - <&cpu32_intc 11>, <&cpu32_intc 9>, - <&cpu33_intc 11>, <&cpu33_intc 9>, - <&cpu34_intc 11>, <&cpu34_intc 9>, - <&cpu35_intc 11>, <&cpu35_intc 9>, - <&cpu36_intc 11>, <&cpu36_intc 9>, - <&cpu37_intc 11>, <&cpu37_intc 9>, - <&cpu38_intc 11>, <&cpu38_intc 9>, - <&cpu39_intc 11>, <&cpu39_intc 9>, - <&cpu40_intc 11>, <&cpu40_intc 9>, - <&cpu41_intc 11>, <&cpu41_intc 9>, - <&cpu42_intc 11>, <&cpu42_intc 9>, - <&cpu43_intc 11>, <&cpu43_intc 9>, - <&cpu44_intc 11>, <&cpu44_intc 9>, - <&cpu45_intc 11>, <&cpu45_intc 9>, - <&cpu46_intc 11>, <&cpu46_intc 9>, - <&cpu47_intc 11>, <&cpu47_intc 9>, - <&cpu48_intc 11>, <&cpu48_intc 9>, - <&cpu49_intc 11>, <&cpu49_intc 9>, - <&cpu50_intc 11>, <&cpu50_intc 9>, - <&cpu51_intc 11>, <&cpu51_intc 9>, - <&cpu52_intc 11>, <&cpu52_intc 9>, - <&cpu53_intc 11>, <&cpu53_intc 9>, - <&cpu54_intc 11>, <&cpu54_intc 9>, - <&cpu55_intc 11>, <&cpu55_intc 9>, - <&cpu56_intc 11>, <&cpu56_intc 9>, - <&cpu57_intc 11>, <&cpu57_intc 9>, - <&cpu58_intc 11>, <&cpu58_intc 9>, - <&cpu59_intc 11>, <&cpu59_intc 9>, - <&cpu60_intc 11>, <&cpu60_intc 9>, - <&cpu61_intc 11>, <&cpu61_intc 9>, - <&cpu62_intc 11>, <&cpu62_intc 9>, - <&cpu63_intc 11>, <&cpu63_intc 9>; - riscv,ndev = <224>; - }; - rstgen: reset-controller@7030013000 { compatible = "sophgo,sg2042-reset"; reg = <0x00000070 0x30013000 0x00000000 0x0000000c>; @@ -789,5 +398,93 @@ "timer"; status = "disabled"; }; + + pcie_rc0: pcie@7060000000 { + compatible = "sophgo,sg2042-pcie-host"; + device_type = "pci"; + reg = <0x70 0x60000000 0x0 0x00800000>, + <0x40 0x00000000 0x0 0x00001000>; + reg-names = "reg", "cfg"; + linux,pci-domain = <0>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x40 0xc0000000 0x0 0x00400000>, + <0x42000000 0x0 0xd0000000 0x40 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>, + <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>, + <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>; + bus-range = <0x0 0xff>; + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; + msi-parent = <&msi>; + status = "disabled"; + }; + + pcie_rc1: pcie@7060800000 { + compatible = "sophgo,sg2042-pcie-host"; + device_type = "pci"; + reg = <0x70 0x60800000 0x0 0x00800000>, + <0x44 0x00000000 0x0 0x00001000>; + reg-names = "reg", "cfg"; + linux,pci-domain = <1>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x44 0xc0400000 0x0 0x00400000>, + <0x42000000 0x0 0xd0000000 0x44 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x44 0xe0000000 0x0 0x20000000>, + <0x43000000 0x46 0x00000000 0x46 0x00000000 0x2 0x00000000>, + <0x03000000 0x45 0x00000000 0x45 0x00000000 0x1 0x00000000>; + bus-range = <0x0 0xff>; + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; + msi-parent = <&msi>; + status = "disabled"; + }; + + pcie_rc2: pcie@7062000000 { + compatible = "sophgo,sg2042-pcie-host"; + device_type = "pci"; + reg = <0x70 0x62000000 0x0 0x00800000>, + <0x48 0x00000000 0x0 0x00001000>; + reg-names = "reg", "cfg"; + linux,pci-domain = <2>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x48 0xc0800000 0x0 0x00400000>, + <0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>, + <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>, + <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>; + bus-range = <0x0 0xff>; + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; + msi-parent = <&msi>; + status = "disabled"; + }; + + pcie_rc3: pcie@7062800000 { + compatible = "sophgo,sg2042-pcie-host"; + device_type = "pci"; + reg = <0x70 0x62800000 0x0 0x00800000>, + <0x4c 0x00000000 0x0 0x00001000>; + reg-names = "reg", "cfg"; + linux,pci-domain = <3>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x4c 0xc0c00000 0x0 0x00400000>, + <0x42000000 0x0 0xf8000000 0x4c 0xf8000000 0x0 0x04000000>, + <0x02000000 0x0 0xfc000000 0x4c 0xfc000000 0x0 0x04000000>, + <0x43000000 0x4e 0x00000000 0x4e 0x00000000 0x2 0x00000000>, + <0x03000000 0x4d 0x00000000 0x4d 0x00000000 0x1 0x00000000>; + bus-range = <0x0 0xff>; + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; + msi-parent = <&msi>; + status = "disabled"; + }; }; }; diff --git a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi index 523799a1a8b8..3135409c2149 100644 --- a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi @@ -24,10 +24,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache0>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -60,10 +60,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache0>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -96,10 +96,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache0>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -132,10 +132,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache0>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -168,10 +168,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache1>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -204,10 +204,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache1>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -240,10 +240,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache1>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -276,10 +276,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache1>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -312,10 +312,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache2>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -348,10 +348,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache2>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -384,10 +384,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache2>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -420,10 +420,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache2>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -456,10 +456,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache3>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -492,10 +492,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache3>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -528,10 +528,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache3>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -564,10 +564,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache3>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -600,10 +600,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache4>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -636,10 +636,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache4>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -672,10 +672,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache4>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -708,10 +708,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache4>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -744,10 +744,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache5>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -780,10 +780,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache5>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -816,10 +816,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache5>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -852,10 +852,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache5>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -888,10 +888,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache6>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -924,10 +924,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache6>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -960,10 +960,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache6>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -996,10 +996,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache6>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1032,10 +1032,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache7>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1068,10 +1068,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache7>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1104,10 +1104,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache7>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1140,10 +1140,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache7>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1176,10 +1176,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache8>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1212,10 +1212,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache8>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1248,10 +1248,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache8>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1284,10 +1284,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache8>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1320,10 +1320,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache9>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1356,10 +1356,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache9>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1392,10 +1392,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache9>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1428,10 +1428,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache9>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1464,10 +1464,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache10>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1500,10 +1500,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache10>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1536,10 +1536,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache10>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1572,10 +1572,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache10>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1608,10 +1608,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache11>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1644,10 +1644,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache11>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1680,10 +1680,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache11>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1716,10 +1716,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache11>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1752,10 +1752,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache12>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1788,10 +1788,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache12>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1824,10 +1824,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache12>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1860,10 +1860,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache12>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1896,10 +1896,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache13>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1932,10 +1932,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache13>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1968,10 +1968,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache13>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -2004,10 +2004,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache13>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -2040,10 +2040,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache14>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -2076,10 +2076,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache14>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -2112,10 +2112,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache14>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -2148,10 +2148,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache14>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -2184,10 +2184,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache15>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -2220,10 +2220,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache15>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -2256,10 +2256,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache15>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -2292,10 +2292,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache15>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", diff --git a/arch/riscv/boot/dts/spacemit/Makefile b/arch/riscv/boot/dts/spacemit/Makefile index 95889e7269d1..7e2b87702571 100644 --- a/arch/riscv/boot/dts/spacemit/Makefile +++ b/arch/riscv/boot/dts/spacemit/Makefile @@ -4,3 +4,4 @@ dtb-$(CONFIG_ARCH_SPACEMIT) += k1-milkv-jupiter.dtb dtb-$(CONFIG_ARCH_SPACEMIT) += k1-musepi-pro.dtb dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-r2s.dtb dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-rv2.dtb +dtb-$(CONFIG_ARCH_SPACEMIT) += k3-pico-itx.dtb diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts index 02f218a16318..5971605754b3 100644 --- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts @@ -33,6 +33,14 @@ }; }; + pcie_vcc_3v3: pcie-vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "PCIE_VCC3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + reg_dc_in: dc-in-12v { compatible = "regulator-fixed"; regulator-name = "dc_in_12v"; @@ -51,6 +59,31 @@ regulator-always-on; vin-supply = <®_dc_in>; }; + + usb3-vbus-5v { + compatible = "regulator-fixed"; + regulator-name = "USB30_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + gpio = <&gpio K1_GPIO(97) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usb3_hub_5v: usb3-hub-5v { + compatible = "regulator-fixed"; + regulator-name = "USB30_HUB"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio K1_GPIO(123) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&combo_phy { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_3_cfg>; + status = "okay"; }; &emmc { @@ -264,8 +297,65 @@ }; }; +&pcie1_phy { + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_3_cfg>; + status = "okay"; +}; + +&pcie1_port { + phys = <&pcie1_phy>; +}; + +&pcie1 { + vpcie3v3-supply = <&pcie_vcc_3v3>; + status = "okay"; +}; + +&pcie2_phy { + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_4_cfg>; + status = "okay"; +}; + +&pcie2_port { + phys = <&pcie2_phy>; +}; + +&pcie2 { + vpcie3v3-supply = <&pcie_vcc_3v3>; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_2_cfg>; status = "okay"; }; + +&usbphy2 { + status = "okay"; +}; + +&usb_dwc3 { + dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + hub_2_0: hub@1 { + compatible = "usb2109,2817"; + reg = <0x1>; + vdd-supply = <&usb3_hub_5v>; + peer-hub = <&hub_3_0>; + reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>; + }; + + hub_3_0: hub@2 { + compatible = "usb2109,817"; + reg = <0x2>; + vdd-supply = <&usb3_hub_5v>; + peer-hub = <&hub_2_0>; + reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>; + }; +}; diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts index 28afd39b28da..800a112d5d70 100644 --- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts @@ -20,6 +20,25 @@ chosen { stdout-path = "serial0"; }; + + reg_dc_in: dc-in-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_in_12v"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vcc_4v: vcc-4v { + compatible = "regulator-fixed"; + regulator-name = "vcc_4v"; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <4000000>; + regulator-boot-on; + regulator-always-on; + vin-supply = <®_dc_in>; + }; }; ð0 { @@ -72,6 +91,122 @@ status = "okay"; }; +&i2c8 { + pinctrl-0 = <&i2c8_cfg>; + pinctrl-names = "default"; + status = "okay"; + + pmic@41 { + compatible = "spacemit,p1"; + reg = <0x41>; + interrupts = <64>; + vin-supply = <®_vcc_4v>; + + regulators { + buck1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck3_1v8: buck3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck5 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck6 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + aldo1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + }; + + aldo2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + aldo3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + aldo4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + dldo1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + }; + + dldo2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + dldo3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + dldo4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-always-on; + }; + + dldo5 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + dldo6 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-always-on; + }; + + dldo7 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + }; + }; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_2_cfg>; diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts index 58098c4a2aab..de75f6aac740 100644 --- a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts +++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts @@ -52,6 +52,7 @@ rgmii0: phy@1 { reg = <0x1>; + motorcomm,auto-sleep-disabled; }; }; }; @@ -75,6 +76,7 @@ rgmii1: phy@1 { reg = <0x1>; + motorcomm,auto-sleep-disabled; }; }; }; diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts index 41dc8e35e6eb..7b7331cb3c72 100644 --- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts @@ -54,6 +54,7 @@ rgmii0: phy@1 { reg = <0x1>; + motorcomm,auto-sleep-disabled; }; }; }; @@ -77,6 +78,7 @@ rgmii1: phy@1 { reg = <0x1>; + motorcomm,auto-sleep-disabled; }; }; }; diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi index e922e05ff856..b13dcb10f4d6 100644 --- a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi @@ -530,6 +530,39 @@ }; }; + pcie0_3_cfg: pcie0-3-cfg { + pcie0-3-pins { + pinmux = <K1_PADCONF(54, 3)>, /* PERST# */ + <K1_PADCONF(55, 3)>, /* WAKE# */ + <K1_PADCONF(53, 3)>; /* CLKREQ# */ + + bias-pull-up = <0>; + drive-strength = <21>; + }; + }; + + pcie1_3_cfg: pcie1-3-cfg { + pcie1-3-pins { + pinmux = <K1_PADCONF(59, 4)>, /* PERST# */ + <K1_PADCONF(60, 4)>, /* WAKE# */ + <K1_PADCONF(61, 4)>; /* CLKREQ# */ + + bias-pull-up = <0>; + drive-strength = <21>; + }; + }; + + pcie2_4_cfg: pcie2-4-cfg { + pcie2-4-pins { + pinmux = <K1_PADCONF(62, 4)>, /* PERST# */ + <K1_PADCONF(112, 3)>, /* WAKE# */ + <K1_PADCONF(117, 4)>; /* CLKREQ# */ + + bias-pull-up = <0>; + drive-strength = <21>; + }; + }; + pwm14_1_cfg: pwm14-1-cfg { pwm14-1-pins { pinmux = <K1_PADCONF(44, 4)>; diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi index 7818ca4979b6..529ec68e9c23 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -4,6 +4,7 @@ */ #include <dt-bindings/clock/spacemit,k1-syscon.h> +#include <dt-bindings/phy/phy.h> /dts-v1/; / { @@ -53,9 +54,9 @@ compatible = "spacemit,x60", "riscv"; device_type = "cpu"; reg = <0>; - riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", "zicbop", "zicboz", "zicntr", "zicond", "zicsr", "zifencei", "zihintpause", "zihpm", "zfh", "zba", "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", @@ -83,9 +84,9 @@ compatible = "spacemit,x60", "riscv"; device_type = "cpu"; reg = <1>; - riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", "zicbop", "zicboz", "zicntr", "zicond", "zicsr", "zifencei", "zihintpause", "zihpm", "zfh", "zba", "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", @@ -113,9 +114,9 @@ compatible = "spacemit,x60", "riscv"; device_type = "cpu"; reg = <2>; - riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", "zicbop", "zicboz", "zicntr", "zicond", "zicsr", "zifencei", "zihintpause", "zihpm", "zfh", "zba", "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", @@ -143,9 +144,9 @@ compatible = "spacemit,x60", "riscv"; device_type = "cpu"; reg = <3>; - riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", "zicbop", "zicboz", "zicntr", "zicond", "zicsr", "zifencei", "zihintpause", "zihpm", "zfh", "zba", "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", @@ -173,9 +174,9 @@ compatible = "spacemit,x60", "riscv"; device_type = "cpu"; reg = <4>; - riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", "zicbop", "zicboz", "zicntr", "zicond", "zicsr", "zifencei", "zihintpause", "zihpm", "zfh", "zba", "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", @@ -203,9 +204,9 @@ compatible = "spacemit,x60", "riscv"; device_type = "cpu"; reg = <5>; - riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", "zicbop", "zicboz", "zicntr", "zicond", "zicsr", "zifencei", "zihintpause", "zihpm", "zfh", "zba", "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", @@ -233,9 +234,9 @@ compatible = "spacemit,x60", "riscv"; device_type = "cpu"; reg = <6>; - riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", "zicbop", "zicboz", "zicntr", "zicond", "zicsr", "zifencei", "zihintpause", "zihpm", "zfh", "zba", "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", @@ -263,9 +264,9 @@ compatible = "spacemit,x60", "riscv"; device_type = "cpu"; reg = <7>; - riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", "zicbop", "zicboz", "zicntr", "zicond", "zicsr", "zifencei", "zihintpause", "zihpm", "zfh", "zba", "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", @@ -367,6 +368,7 @@ <&syscon_apbc CLK_TWSI0_BUS>; clock-names = "func", "bus"; clock-frequency = <400000>; + resets = <&syscon_apbc RESET_TWSI0>; interrupts = <36>; status = "disabled"; }; @@ -380,6 +382,7 @@ <&syscon_apbc CLK_TWSI1_BUS>; clock-names = "func", "bus"; clock-frequency = <400000>; + resets = <&syscon_apbc RESET_TWSI1>; interrupts = <37>; status = "disabled"; }; @@ -393,6 +396,7 @@ <&syscon_apbc CLK_TWSI2_BUS>; clock-names = "func", "bus"; clock-frequency = <400000>; + resets = <&syscon_apbc RESET_TWSI2>; interrupts = <38>; status = "disabled"; }; @@ -406,6 +410,7 @@ <&syscon_apbc CLK_TWSI4_BUS>; clock-names = "func", "bus"; clock-frequency = <400000>; + resets = <&syscon_apbc RESET_TWSI4>; interrupts = <40>; status = "disabled"; }; @@ -419,10 +424,65 @@ <&syscon_apbc CLK_TWSI5_BUS>; clock-names = "func", "bus"; clock-frequency = <400000>; + resets = <&syscon_apbc RESET_TWSI5>; interrupts = <41>; status = "disabled"; }; + usbphy2: phy@c0a30000 { + compatible = "spacemit,k1-usb2-phy"; + reg = <0x0 0xc0a30000 0x0 0x200>; + clocks = <&syscon_apmu CLK_USB30>; + #phy-cells = <0>; + status = "disabled"; + }; + + combo_phy: phy@c0b10000 { + compatible = "spacemit,k1-combo-phy"; + reg = <0x0 0xc0b10000 0x0 0x1000>; + clocks = <&vctcxo_24m>, + <&syscon_apmu CLK_PCIE0_DBI>, + <&syscon_apmu CLK_PCIE0_MASTER>, + <&syscon_apmu CLK_PCIE0_SLAVE>; + clock-names = "refclk", + "dbi", + "mstr", + "slv"; + resets = <&syscon_apmu RESET_PCIE0_GLOBAL>, + <&syscon_apmu RESET_PCIE0_DBI>, + <&syscon_apmu RESET_PCIE0_MASTER>, + <&syscon_apmu RESET_PCIE0_SLAVE>; + reset-names = "phy", + "dbi", + "mstr", + "slv"; + #phy-cells = <1>; + spacemit,apmu = <&syscon_apmu>; + status = "disabled"; + }; + + pcie1_phy: phy@c0c10000 { + compatible = "spacemit,k1-pcie-phy"; + reg = <0x0 0xc0c10000 0x0 0x1000>; + clocks = <&vctcxo_24m>; + clock-names = "refclk"; + resets = <&syscon_apmu RESET_PCIE1_GLOBAL>; + reset-names = "phy"; + #phy-cells = <0>; + status = "disabled"; + }; + + pcie2_phy: phy@c0d10000 { + compatible = "spacemit,k1-pcie-phy"; + reg = <0x0 0xc0d10000 0x0 0x1000>; + clocks = <&vctcxo_24m>; + clock-names = "refclk"; + resets = <&syscon_apmu RESET_PCIE2_GLOBAL>; + reset-names = "phy"; + #phy-cells = <0>; + status = "disabled"; + }; + syscon_apbc: system-controller@d4015000 { compatible = "spacemit,k1-syscon-apbc"; reg = <0x0 0xd4015000 0x0 0x1000>; @@ -443,6 +503,7 @@ <&syscon_apbc CLK_TWSI6_BUS>; clock-names = "func", "bus"; clock-frequency = <400000>; + resets = <&syscon_apbc RESET_TWSI6>; interrupts = <70>; status = "disabled"; }; @@ -546,6 +607,7 @@ <&syscon_apbc CLK_TWSI7_BUS>; clock-names = "func", "bus"; clock-frequency = <400000>; + resets = <&syscon_apbc RESET_TWSI7>; interrupts = <18>; status = "disabled"; }; @@ -559,16 +621,18 @@ <&syscon_apbc CLK_TWSI8_BUS>; clock-names = "func", "bus"; clock-frequency = <400000>; + resets = <&syscon_apbc RESET_TWSI8>; interrupts = <19>; status = "disabled"; }; pinctrl: pinctrl@d401e000 { compatible = "spacemit,k1-pinctrl"; - reg = <0x0 0xd401e000 0x0 0x400>; + reg = <0x0 0xd401e000 0x0 0x1000>; clocks = <&syscon_apbc CLK_AIB>, <&syscon_apbc CLK_AIB_BUS>; clock-names = "func", "bus"; + spacemit,apbc = <&syscon_apbc>; }; pwm8: pwm@d4020000 { @@ -969,6 +1033,135 @@ #size-cells = <2>; dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>, <0x0 0xb8000000 0x1 0x38000000 0x3 0x48000000>; + pcie0: pcie@ca000000 { + device_type = "pci"; + compatible = "spacemit,k1-pcie"; + reg = <0x0 0xca000000 0x0 0x00001000>, + <0x0 0xca300000 0x0 0x0001ff24>, + <0x0 0x8f000000 0x0 0x00002000>, + <0x0 0xc0b20000 0x0 0x00001000>; + reg-names = "dbi", + "atu", + "config", + "link"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x8f002000 0x0 0x00100000>, + <0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x0f000000>; + interrupts = <141>; + interrupt-names = "msi"; + clocks = <&syscon_apmu CLK_PCIE0_DBI>, + <&syscon_apmu CLK_PCIE0_MASTER>, + <&syscon_apmu CLK_PCIE0_SLAVE>; + clock-names = "dbi", + "mstr", + "slv"; + resets = <&syscon_apmu RESET_PCIE0_DBI>, + <&syscon_apmu RESET_PCIE0_MASTER>, + <&syscon_apmu RESET_PCIE0_SLAVE>; + reset-names = "dbi", + "mstr", + "slv"; + spacemit,apmu = <&syscon_apmu 0x03cc>; + status = "disabled"; + + pcie0_port: pcie@0 { + device_type = "pci"; + compatible = "pciclass,0604"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; + + pcie1: pcie@ca400000 { + device_type = "pci"; + compatible = "spacemit,k1-pcie"; + reg = <0x0 0xca400000 0x0 0x00001000>, + <0x0 0xca700000 0x0 0x0001ff24>, + <0x0 0x9f000000 0x0 0x00002000>, + <0x0 0xc0c20000 0x0 0x00001000>; + reg-names = "dbi", + "atu", + "config", + "link"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x9f002000 0x0 0x00100000>, + <0x02000000 0x0 0x90000000 0x0 0x90000000 0x0 0x0f000000>; + interrupts = <142>; + interrupt-names = "msi"; + clocks = <&syscon_apmu CLK_PCIE1_DBI>, + <&syscon_apmu CLK_PCIE1_MASTER>, + <&syscon_apmu CLK_PCIE1_SLAVE>; + clock-names = "dbi", + "mstr", + "slv"; + resets = <&syscon_apmu RESET_PCIE1_DBI>, + <&syscon_apmu RESET_PCIE1_MASTER>, + <&syscon_apmu RESET_PCIE1_SLAVE>; + reset-names = "dbi", + "mstr", + "slv"; + spacemit,apmu = <&syscon_apmu 0x3d4>; + status = "disabled"; + + pcie1_port: pcie@0 { + device_type = "pci"; + compatible = "pciclass,0604"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; + + pcie2: pcie@ca800000 { + device_type = "pci"; + compatible = "spacemit,k1-pcie"; + reg = <0x0 0xca800000 0x0 0x00001000>, + <0x0 0xcab00000 0x0 0x0001ff24>, + <0x0 0xb7000000 0x0 0x00002000>, + <0x0 0xc0d20000 0x0 0x00001000>; + reg-names = "dbi", + "atu", + "config", + "link"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0xb7002000 0x0 0x00100000>, + <0x42000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x10000000>, + <0x02000000 0x0 0xb0000000 0x0 0xb0000000 0x0 0x07000000>; + interrupts = <143>; + interrupt-names = "msi"; + clocks = <&syscon_apmu CLK_PCIE2_DBI>, + <&syscon_apmu CLK_PCIE2_MASTER>, + <&syscon_apmu CLK_PCIE2_SLAVE>; + clock-names = "dbi", + "mstr", + "slv"; + resets = <&syscon_apmu RESET_PCIE2_DBI>, + <&syscon_apmu RESET_PCIE2_MASTER>, + <&syscon_apmu RESET_PCIE2_SLAVE>; + reset-names = "dbi", + "mstr", + "slv"; + spacemit,apmu = <&syscon_apmu 0x3dc>; + status = "disabled"; + + pcie2_port: pcie@0 { + device_type = "pci"; + compatible = "pciclass,0604"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; }; storage-bus { @@ -978,12 +1171,39 @@ #size-cells = <2>; dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>; + usb_dwc3: usb@c0a00000 { + compatible = "spacemit,k1-dwc3"; + reg = <0x0 0xc0a00000 0x0 0x10000>; + clocks = <&syscon_apmu CLK_USB30>; + clock-names = "usbdrd30"; + interrupts = <125>; + phys = <&usbphy2>, <&combo_phy PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi"; + resets = <&syscon_apmu RESET_USB30_AHB>, + <&syscon_apmu RESET_USB30_VCC>, + <&syscon_apmu RESET_USB30_PHY>; + reset-names = "ahb", "vcc", "phy"; + reset-delay = <2>; + snps,hsphy_interface = "utmi"; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,dis_rxdet_inp3_quirk; + status = "disabled"; + }; + emmc: mmc@d4281000 { compatible = "spacemit,k1-sdhci"; reg = <0x0 0xd4281000 0x0 0x200>; clocks = <&syscon_apmu CLK_SDH_AXI>, <&syscon_apmu CLK_SDH2>; clock-names = "core", "io"; + resets = <&syscon_apmu RESET_SDH_AXI>, + <&syscon_apmu RESET_SDH2>; + reset-names = "axi", "sdh"; interrupts = <101>; status = "disabled"; }; diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts new file mode 100644 index 000000000000..b691304d4b74 --- /dev/null +++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd + * Copyright (c) 2026 Guodong Xu <guodong@riscstar.com> + */ + +#include "k3.dtsi" + +/ { + model = "SpacemiT K3 Pico-ITX"; + compatible = "spacemit,k3-pico-itx", "spacemit,k3"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0"; + }; + + memory@100000000 { + device_type = "memory"; + reg = <0x1 0x00000000 0x4 0x00000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi new file mode 100644 index 000000000000..b69cf81b5d55 --- /dev/null +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi @@ -0,0 +1,578 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd + * Copyright (c) 2026 Guodong Xu <guodong@riscstar.com> + */ + +#include <dt-bindings/interrupt-controller/irq.h> + +/dts-v1/; + +/ { + #address-cells = <2>; + #size-cells = <2>; + model = "SpacemiT K3"; + compatible = "spacemit,k3"; + + cpus: cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <24000000>; + + cpu_0: cpu@0 { + compatible = "spacemit,x100", "riscv"; + device_type = "cpu"; + reg = <0>; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", + "sha", "shcounterenw", "shgatpa", "shtvala", + "shvsatpa", "shvstvala", "shvstvecd", "smaia", + "smstateen", "ssaia", "ssccptr", "sscofpmf", + "sscounterenw", "ssnpm", "ssstateen", "sstc", + "sstvala", "sstvecd", "ssu64xl", "svade", + "svinval", "svnapot", "svpbmt", "za64rs", + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", + "ziccamoa", "ziccif", "zicclsm", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", + "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", + "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", + "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <256>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache0>; + mmu-type = "riscv,sv39"; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + cpu_1: cpu@1 { + compatible = "spacemit,x100", "riscv"; + device_type = "cpu"; + reg = <1>; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", + "sha", "shcounterenw", "shgatpa", "shtvala", + "shvsatpa", "shvstvala", "shvstvecd", "smaia", + "smstateen", "ssaia", "ssccptr", "sscofpmf", + "sscounterenw", "ssnpm", "ssstateen", "sstc", + "sstvala", "sstvecd", "ssu64xl", "svade", + "svinval", "svnapot", "svpbmt", "za64rs", + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", + "ziccamoa", "ziccif", "zicclsm", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", + "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", + "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", + "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <256>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache0>; + mmu-type = "riscv,sv39"; + + cpu1_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + cpu_2: cpu@2 { + compatible = "spacemit,x100", "riscv"; + device_type = "cpu"; + reg = <2>; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", + "sha", "shcounterenw", "shgatpa", "shtvala", + "shvsatpa", "shvstvala", "shvstvecd", "smaia", + "smstateen", "ssaia", "ssccptr", "sscofpmf", + "sscounterenw", "ssnpm", "ssstateen", "sstc", + "sstvala", "sstvecd", "ssu64xl", "svade", + "svinval", "svnapot", "svpbmt", "za64rs", + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", + "ziccamoa", "ziccif", "zicclsm", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", + "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", + "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", + "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <256>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache0>; + mmu-type = "riscv,sv39"; + + cpu2_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + cpu_3: cpu@3 { + compatible = "spacemit,x100", "riscv"; + device_type = "cpu"; + reg = <3>; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", + "sha", "shcounterenw", "shgatpa", "shtvala", + "shvsatpa", "shvstvala", "shvstvecd", "smaia", + "smstateen", "ssaia", "ssccptr", "sscofpmf", + "sscounterenw", "ssnpm", "ssstateen", "sstc", + "sstvala", "sstvecd", "ssu64xl", "svade", + "svinval", "svnapot", "svpbmt", "za64rs", + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", + "ziccamoa", "ziccif", "zicclsm", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", + "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", + "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", + "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <256>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache0>; + mmu-type = "riscv,sv39"; + + cpu3_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + cpu_4: cpu@4 { + compatible = "spacemit,x100", "riscv"; + device_type = "cpu"; + reg = <4>; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", + "sha", "shcounterenw", "shgatpa", "shtvala", + "shvsatpa", "shvstvala", "shvstvecd", "smaia", + "smstateen", "ssaia", "ssccptr", "sscofpmf", + "sscounterenw", "ssnpm", "ssstateen", "sstc", + "sstvala", "sstvecd", "ssu64xl", "svade", + "svinval", "svnapot", "svpbmt", "za64rs", + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", + "ziccamoa", "ziccif", "zicclsm", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", + "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", + "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", + "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <256>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache1>; + mmu-type = "riscv,sv39"; + + cpu4_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + cpu_5: cpu@5 { + compatible = "spacemit,x100", "riscv"; + device_type = "cpu"; + reg = <5>; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", + "sha", "shcounterenw", "shgatpa", "shtvala", + "shvsatpa", "shvstvala", "shvstvecd", "smaia", + "smstateen", "ssaia", "ssccptr", "sscofpmf", + "sscounterenw", "ssnpm", "ssstateen", "sstc", + "sstvala", "sstvecd", "ssu64xl", "svade", + "svinval", "svnapot", "svpbmt", "za64rs", + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", + "ziccamoa", "ziccif", "zicclsm", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", + "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", + "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", + "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <256>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache1>; + mmu-type = "riscv,sv39"; + + cpu5_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + cpu_6: cpu@6 { + compatible = "spacemit,x100", "riscv"; + device_type = "cpu"; + reg = <6>; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", + "sha", "shcounterenw", "shgatpa", "shtvala", + "shvsatpa", "shvstvala", "shvstvecd", "smaia", + "smstateen", "ssaia", "ssccptr", "sscofpmf", + "sscounterenw", "ssnpm", "ssstateen", "sstc", + "sstvala", "sstvecd", "ssu64xl", "svade", + "svinval", "svnapot", "svpbmt", "za64rs", + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", + "ziccamoa", "ziccif", "zicclsm", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", + "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", + "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", + "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <256>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache1>; + mmu-type = "riscv,sv39"; + + cpu6_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + cpu_7: cpu@7 { + compatible = "spacemit,x100", "riscv"; + device_type = "cpu"; + reg = <7>; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", + "sha", "shcounterenw", "shgatpa", "shtvala", + "shvsatpa", "shvstvala", "shvstvecd", "smaia", + "smstateen", "ssaia", "ssccptr", "sscofpmf", + "sscounterenw", "ssnpm", "ssstateen", "sstc", + "sstvala", "sstvecd", "ssu64xl", "svade", + "svinval", "svnapot", "svpbmt", "za64rs", + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", + "ziccamoa", "ziccif", "zicclsm", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", + "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", + "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", + "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <256>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache1>; + mmu-type = "riscv,sv39"; + + cpu7_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + l2_cache0: cache-controller-0 { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <4194304>; + cache-sets = <4096>; + cache-unified; + }; + + l2_cache1: cache-controller-1 { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <4194304>; + cache-sets = <4096>; + cache-unified; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu_0>; + }; + core1 { + cpu = <&cpu_1>; + }; + core2 { + cpu = <&cpu_2>; + }; + core3 { + cpu = <&cpu_3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu_4>; + }; + core1 { + cpu = <&cpu_5>; + }; + core2 { + cpu = <&cpu_6>; + }; + core3 { + cpu = <&cpu_7>; + }; + }; + }; + }; + + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&saplic>; + #address-cells = <2>; + #size-cells = <2>; + dma-noncoherent; + ranges; + + uart0: serial@d4017000 { + compatible = "spacemit,k3-uart", "intel,xscale-uart"; + reg = <0x0 0xd4017000 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <14700000>; + interrupts = <42 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + uart2: serial@d4017100 { + compatible = "spacemit,k3-uart", "intel,xscale-uart"; + reg = <0x0 0xd4017100 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <14700000>; + interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + uart3: serial@d4017200 { + compatible = "spacemit,k3-uart", "intel,xscale-uart"; + reg = <0x0 0xd4017200 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <14700000>; + interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + uart4: serial@d4017300 { + compatible = "spacemit,k3-uart", "intel,xscale-uart"; + reg = <0x0 0xd4017300 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <14700000>; + interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + uart5: serial@d4017400 { + compatible = "spacemit,k3-uart", "intel,xscale-uart"; + reg = <0x0 0xd4017400 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <14700000>; + interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + uart6: serial@d4017500 { + compatible = "spacemit,k3-uart", "intel,xscale-uart"; + reg = <0x0 0xd4017500 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <14700000>; + interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + uart7: serial@d4017600 { + compatible = "spacemit,k3-uart", "intel,xscale-uart"; + reg = <0x0 0xd4017600 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <14700000>; + interrupts = <49 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + uart8: serial@d4017700 { + compatible = "spacemit,k3-uart", "intel,xscale-uart"; + reg = <0x0 0xd4017700 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <14700000>; + interrupts = <50 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + uart9: serial@d4017800 { + compatible = "spacemit,k3-uart", "intel,xscale-uart"; + reg = <0x0 0xd4017800 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <14700000>; + interrupts = <51 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + uart10: serial@d401f000 { + compatible = "spacemit,k3-uart", "intel,xscale-uart"; + reg = <0x0 0xd401f000 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <14700000>; + interrupts = <281 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + simsic: interrupt-controller@e0400000 { + compatible = "spacemit,k3-imsics", "riscv,imsics"; + reg = <0x0 0xe0400000 0x0 0x200000>; + #interrupt-cells = <0>; + #msi-cells = <0>; + interrupt-controller; + interrupts-extended = <&cpu0_intc 9>, <&cpu1_intc 9>, + <&cpu2_intc 9>, <&cpu3_intc 9>, + <&cpu4_intc 9>, <&cpu5_intc 9>, + <&cpu6_intc 9>, <&cpu7_intc 9>; + msi-controller; + riscv,guest-index-bits = <6>; + riscv,hart-index-bits = <4>; + riscv,num-guest-ids = <511>; + riscv,num-ids = <511>; + }; + + saplic: interrupt-controller@e0804000 { + compatible = "spacemit,k3-aplic", "riscv,aplic"; + reg = <0x0 0xe0804000 0x0 0x4000>; + #interrupt-cells = <2>; + interrupt-controller; + msi-parent = <&simsic>; + riscv,num-sources = <512>; + }; + + clint: timer@e081c000 { + compatible = "spacemit,k3-clint", "sifive,clint0"; + reg = <0x0 0xe081c000 0x0 0x4000>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>, + <&cpu2_intc 3>, <&cpu2_intc 7>, + <&cpu3_intc 3>, <&cpu3_intc 7>, + <&cpu4_intc 3>, <&cpu4_intc 7>, + <&cpu5_intc 3>, <&cpu5_intc 7>, + <&cpu6_intc 3>, <&cpu6_intc 7>, + <&cpu7_intc 3>, <&cpu7_intc 7>; + }; + + mimsic: interrupt-controller@f1000000 { + compatible = "spacemit,k3-imsics", "riscv,imsics"; + reg = <0x0 0xf1000000 0x0 0x10000>; + #interrupt-cells = <0>; + #msi-cells = <0>; + interrupt-controller; + interrupts-extended = <&cpu0_intc 11>, <&cpu1_intc 11>, + <&cpu2_intc 11>, <&cpu3_intc 11>, + <&cpu4_intc 11>, <&cpu5_intc 11>, + <&cpu6_intc 11>, <&cpu7_intc 11>; + msi-controller; + riscv,guest-index-bits = <6>; + riscv,hart-index-bits = <4>; + riscv,num-guest-ids = <511>; + riscv,num-ids = <511>; + status = "reserved"; + }; + + maplic: interrupt-controller@f1800000 { + compatible = "spacemit,k3-aplic", "riscv,aplic"; + reg = <0x0 0xf1800000 0x0 0x4000>; + #interrupt-cells = <2>; + interrupt-controller; + msi-parent = <&mimsic>; + riscv,children = <&saplic>; + riscv,delegation = <&saplic 1 512>; + riscv,num-sources = <512>; + status = "reserved"; + }; + }; +}; diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite-emmc.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite-emmc.dts index e27a662d4022..7544efa95de4 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite-emmc.dts +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite-emmc.dts @@ -9,7 +9,7 @@ / { model = "StarFive VisionFive 2 Lite eMMC"; - compatible = "starfive,visionfive-2-lite-emmc", "starfive,jh7110s"; + compatible = "starfive,visionfive-2-lite-emmc", "starfive,jh7110s", "starfive,jh7110"; }; &mmc0 { diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dts index b96eea4fa7d5..b9913991a1b7 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dts +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dts @@ -9,7 +9,7 @@ / { model = "StarFive VisionFive 2 Lite"; - compatible = "starfive,visionfive-2-lite", "starfive,jh7110s"; + compatible = "starfive,visionfive-2-lite", "starfive,jh7110s", "starfive,jh7110"; }; &mmc0 { diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c index 8e3c2ac40341..8fbc96693a55 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -2303,6 +2303,7 @@ static const struct of_device_id qcom_scm_qseecom_allowlist[] __maybe_unused = { { .compatible = "lenovo,thinkpad-t14s" }, { .compatible = "lenovo,thinkpad-x13s", }, { .compatible = "lenovo,yoga-slim7x" }, + { .compatible = "medion,sprchrgd14s1" }, { .compatible = "microsoft,arcata", }, { .compatible = "microsoft,blackrock" }, { .compatible = "microsoft,denali", }, diff --git a/include/dt-bindings/clock/google,gs101.h b/include/dt-bindings/clock/google,gs101.h index 442f9e9037dc..7a14dcb9f17b 100644 --- a/include/dt-bindings/clock/google,gs101.h +++ b/include/dt-bindings/clock/google,gs101.h @@ -313,6 +313,42 @@ #define CLK_APM_PLL_DIV4_APM 70 #define CLK_APM_PLL_DIV16_APM 71 +/* CMU_DPU */ +#define CLK_MOUT_DPU_BUS_USER 1 +#define CLK_DOUT_DPU_BUSP 2 +#define CLK_GOUT_DPU_PCLK 3 +#define CLK_GOUT_DPU_CLK_DPU_OSCCLK_CLK 4 +#define CLK_GOUT_DPU_AD_APB_DPU_DMA_PCLKM 5 +#define CLK_GOUT_DPU_DPUF_ACLK_DMA 6 +#define CLK_GOUT_DPU_DPUF_ACLK_DPP 7 +#define CLK_GOUT_DPU_D_TZPC_DPU_PCLK 8 +#define CLK_GOUT_DPU_GPC_DPU_PCLK 9 +#define CLK_GOUT_DPU_LHM_AXI_P_DPU_I_CLK 10 +#define CLK_GOUT_DPU_LHS_AXI_D0_DPU_I_CLK 11 +#define CLK_GOUT_DPU_LHS_AXI_D1_DPU_I_CLK 12 +#define CLK_GOUT_DPU_LHS_AXI_D2_DPU_I_CLK 13 +#define CLK_GOUT_DPU_PPMU_DPUD0_ACLK 14 +#define CLK_GOUT_DPU_PPMU_DPUD0_PCLK 15 +#define CLK_GOUT_DPU_PPMU_DPUD1_ACLK 16 +#define CLK_GOUT_DPU_PPMU_DPUD1_PCLK 17 +#define CLK_GOUT_DPU_PPMU_DPUD2_ACLK 18 +#define CLK_GOUT_DPU_PPMU_DPUD2_PCLK 19 +#define CLK_GOUT_DPU_CLK_DPU_BUSD_CLK 20 +#define CLK_GOUT_DPU_CLK_DPU_BUSP_CLK 21 +#define CLK_GOUT_DPU_SSMT_DPU0_ACLK 22 +#define CLK_GOUT_DPU_SSMT_DPU0_PCLK 23 +#define CLK_GOUT_DPU_SSMT_DPU1_ACLK 24 +#define CLK_GOUT_DPU_SSMT_DPU1_PCLK 25 +#define CLK_GOUT_DPU_SSMT_DPU2_ACLK 26 +#define CLK_GOUT_DPU_SSMT_DPU2_PCLK 27 +#define CLK_GOUT_DPU_SYSMMU_DPUD0_CLK_S1 28 +#define CLK_GOUT_DPU_SYSMMU_DPUD0_CLK_S2 29 +#define CLK_GOUT_DPU_SYSMMU_DPUD1_CLK_S1 30 +#define CLK_GOUT_DPU_SYSMMU_DPUD1_CLK_S2 31 +#define CLK_GOUT_DPU_SYSMMU_DPUD2_CLK_S1 32 +#define CLK_GOUT_DPU_SYSMMU_DPUD2_CLK_S2 33 +#define CLK_GOUT_DPU_SYSREG_DPU_PCLK 34 + /* CMU_HSI0 */ #define CLK_FOUT_USB_PLL 1 #define CLK_MOUT_PLL_USB 2 diff --git a/include/dt-bindings/clock/qcom,gcc-msm8917.h b/include/dt-bindings/clock/qcom,gcc-msm8917.h index 4e3897b3669d..4265460bfb30 100644 --- a/include/dt-bindings/clock/qcom,gcc-msm8917.h +++ b/include/dt-bindings/clock/qcom,gcc-msm8917.h @@ -194,6 +194,7 @@ #define GCC_QUSB2_PHY_BCR 2 #define GCC_USB_HS_BCR 3 #define GCC_USB2_HS_PHY_ONLY_BCR 4 +#define GCC_MDSS_BCR 5 /* GDSCs */ #define CPP_GDSC 0 diff --git a/include/dt-bindings/clock/qcom,x1e80100-gcc.h b/include/dt-bindings/clock/qcom,x1e80100-gcc.h index 62aa12425592..d905804e6465 100644 --- a/include/dt-bindings/clock/qcom,x1e80100-gcc.h +++ b/include/dt-bindings/clock/qcom,x1e80100-gcc.h @@ -387,6 +387,9 @@ #define GCC_USB4_2_PHY_RX0_CLK_SRC 377 #define GCC_USB4_2_PHY_RX1_CLK_SRC 378 #define GCC_USB4_2_PHY_SYS_CLK_SRC 379 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 380 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 381 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 382 /* GCC power domains */ #define GCC_PCIE_0_TUNNEL_GDSC 0 diff --git a/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h index 2a805e06487b..c4863e444458 100644 --- a/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h +++ b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h @@ -31,5 +31,8 @@ #define R9A09G077_ETCLKC 19 #define R9A09G077_ETCLKD 20 #define R9A09G077_ETCLKE 21 +#define R9A09G077_XSPI_CLK0 22 +#define R9A09G077_XSPI_CLK1 23 +#define R9A09G077_PCLKCAN 24 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */ diff --git a/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h b/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h index 09da0ad33be6..0d53f1e65077 100644 --- a/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h +++ b/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h @@ -31,5 +31,8 @@ #define R9A09G087_ETCLKC 19 #define R9A09G087_ETCLKD 20 #define R9A09G087_ETCLKE 21 +#define R9A09G087_XSPI_CLK0 22 +#define R9A09G087_XSPI_CLK1 23 +#define R9A09G087_PCLKCAN 24 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__ */ |