diff options
| author | Geetha sowjanya <gakula@marvell.com> | 2026-06-01 13:03:16 +0530 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2026-07-31 15:18:03 +0000 |
| commit | 6e0aa591af9948c433d239e8b3f7203a014e2513 (patch) | |
| tree | 51c8cf53ed27d9a124d9fddd55f96f020f013ca7 | |
| parent | fcc5eaea2d234162dfb8258372dd897bc2a1b862 (diff) | |
dt-bindings: perf: marvell: Add CN20K DDR PMU binding
Marvell CN20K SoCs integrate a DDR Performance Monitoring Unit (PMU)
associated with the DDR controller. The block provides hardware counters
to monitor DDR traffic and performance events and is accessed via a
dedicated MMIO region.
The CN20K DDR PMU is functionally equivalent to the CN10K DDR PMU, with
minor register offset differences.
Signed-off-by: Geetha sowjanya <gakula@marvell.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Will Deacon <will@kernel.org>
| -rw-r--r-- | Documentation/devicetree/bindings/perf/marvell-cn10k-ddr.yaml | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/perf/marvell-cn10k-ddr.yaml b/Documentation/devicetree/bindings/perf/marvell-cn10k-ddr.yaml index a18dd0a8c43a..f2f0d6b61eac 100644 --- a/Documentation/devicetree/bindings/perf/marvell-cn10k-ddr.yaml +++ b/Documentation/devicetree/bindings/perf/marvell-cn10k-ddr.yaml @@ -4,16 +4,22 @@ $id: http://devicetree.org/schemas/perf/marvell-cn10k-ddr.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Marvell CN10K DDR performance monitor +title: Marvell CN10K / CN20K DDR performance monitor + +description: + Performance Monitoring Unit (PMU) for the DDR controller on Marvell + CN10K and CN20K SoCs. The block is accessed via a dedicated MMIO region. maintainers: - Bharat Bhushan <bbhushan2@marvell.com> + - Geetha sowjanya <gakula@marvell.com> properties: compatible: items: - enum: - marvell,cn10k-ddr-pmu + - marvell,cn20k-ddr-pmu reg: maxItems: 1 |