diff options
| author | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2026-02-10 16:48:59 +0100 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2026-02-10 16:48:59 +0100 |
| commit | 720452a6d0fdc94ec3301f31ea10b43102eaeeef (patch) | |
| tree | fdfc44eeacaf102ce498824e31897fd951469886 | |
| parent | df136764e86e4d271133359e2ecd2b6717cc5040 (diff) | |
Revert "clk: microchip: core: allow driver to be compiled with COMPILE_TEST"
This reverts commit 026d70dcfe5de1543bb8edb8e50d22dc16863e6b.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| -rw-r--r-- | drivers/clk/microchip/Kconfig | 2 | ||||
| -rw-r--r-- | drivers/clk/microchip/clk-core.c | 4 |
2 files changed, 1 insertions, 5 deletions
diff --git a/drivers/clk/microchip/Kconfig b/drivers/clk/microchip/Kconfig index 1e56a057319d..1b9e43eb5497 100644 --- a/drivers/clk/microchip/Kconfig +++ b/drivers/clk/microchip/Kconfig @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 config COMMON_CLK_PIC32 - def_bool (COMMON_CLK && MACH_PIC32) || COMPILE_TEST + def_bool COMMON_CLK && MACH_PIC32 config MCHP_CLK_MPFS bool "Clk driver for PolarFire SoC" diff --git a/drivers/clk/microchip/clk-core.c b/drivers/clk/microchip/clk-core.c index ce3a24e061d1..891bec5fe1be 100644 --- a/drivers/clk/microchip/clk-core.c +++ b/drivers/clk/microchip/clk-core.c @@ -75,7 +75,6 @@ /* SoC specific clock needed during SPLL clock rate switch */ static struct clk_hw *pic32_sclk_hw; -#ifdef CONFIG_MATCH_PIC32 /* add instruction pipeline delay while CPU clock is in-transition. */ #define cpu_nop5() \ do { \ @@ -85,9 +84,6 @@ do { \ __asm__ __volatile__("nop"); \ __asm__ __volatile__("nop"); \ } while (0) -#else -#define cpu_nop5() -#endif /* Perpheral bus clocks */ struct pic32_periph_clk { |