diff options
| author | Sivansh Gupta <sivansh.gupta@oss.qualcomm.com> | 2026-09-28 10:59:39 +0530 |
|---|---|---|
| committer | Jassi Brar <jassisinghbrar@gmail.com> | 2026-10-21 18:44:41 -0500 |
| commit | 74f1cf02d9fe0fd32ca299cd4d71bc29d3bf2a54 (patch) | |
| tree | a451c501e10d977c68c33bd7a1e2654436d5234c | |
| parent | 134ef0278d4e48bcc325a7699250dfe861c11953 (diff) | |
mailbox: qcom-cpucp: read mbox hardware register using readq()
Mailbox hardware registers are 64 bit wide, but the interrupt handler
currently reads only 32 bits with readl() at offset 0x4 (upper 32
bits). This returns an incorrect value, while reading using readq()
returns the expected value.
Use readq() to access the 64 bit register and pass the expected value
to the mailbox client.
Fixes: 0e2a9a03106c ("mailbox: Add support for QTI CPUCP mailbox controller")
Signed-off-by: Sivansh Gupta <sivansh.gupta@oss.qualcomm.com>
Reviewed-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
| -rw-r--r-- | drivers/mailbox/qcom-cpucp-mbox.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/mailbox/qcom-cpucp-mbox.c b/drivers/mailbox/qcom-cpucp-mbox.c index 515d2d12c01b..b88ea2527265 100644 --- a/drivers/mailbox/qcom-cpucp-mbox.c +++ b/drivers/mailbox/qcom-cpucp-mbox.c @@ -61,7 +61,7 @@ static irqreturn_t qcom_cpucp_mbox_irq_fn(int irq, void *data) status = readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_STAT); for_each_set_bit(i, (unsigned long *)&status, cpucp->mbox.num_chans) { - u32 val = readl(cpucp->rx_base + APSS_CPUCP_RX_MBOX_CMD(i) + APSS_CPUCP_MBOX_CMD_OFF); + u64 val = readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_CMD(i)); struct mbox_chan *chan = &cpucp->chans[i]; struct mbox_client *cl; unsigned long flags; |