diff options
| author | Jia Wang <wangjia@ultrarisc.com> | 2026-08-24 13:54:14 +0800 |
|---|---|---|
| committer | Paul Walmsley <pjw@kernel.org> | 2026-09-01 19:20:18 -0600 |
| commit | 817ecd588fa5820527ee3affa43b5116276d2520 (patch) | |
| tree | 37d7192c9e8d5c7fe3131109841cca8ee1e1a742 | |
| parent | 93a27367bacdc32e2cdb478597102175db3fb80c (diff) | |
dt-bindings: riscv: cpus: Fix yamllint style issues
Wrap an overlong description line and normalize the inline dependency
lists to satisfy yamllint.
Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/20260824-ultrarisc-dts-v1-1-61ab7aebe9e5@ultrarisc.com
Signed-off-by: Paul Walmsley <pjw@kernel.org>
| -rw-r--r-- | Documentation/devicetree/bindings/riscv/cpus.yaml | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 5feeb2203050..0da219ae6769 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -117,8 +117,8 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 description: VLEN/8, the vector register length in bytes. This property is required on - thead systems where the vector register length is not identical on all harts, or - the vlenb CSR is not available. + thead systems where the vector register length is not identical on all + harts, or the vlenb CSR is not available. # RISC-V has multiple properties for cache op block sizes as the sizes # differ between individual CBO extensions @@ -151,8 +151,8 @@ anyOf: - riscv,isa-base dependencies: - riscv,isa-base: [ "riscv,isa-extensions" ] - riscv,isa-extensions: [ "riscv,isa-base" ] + riscv,isa-base: ["riscv,isa-extensions"] + riscv,isa-extensions: ["riscv,isa-base"] required: - interrupt-controller |