diff options
author | Richard Zhu <hongxing.zhu@nxp.com> | 2019-01-25 17:25:21 +0800 |
---|---|---|
committer | Dong Aisheng <aisheng.dong@nxp.com> | 2021-11-02 17:05:21 +0800 |
commit | 890f821ac38f7d656b9f7ee0142d395d43d5c4b7 (patch) | |
tree | b3378b8b38825b0023724bc77f80e14bc7ec5c7c | |
parent | ef2c6b3282543f5e75d3d794771c1ed7ef99e6e9 (diff) |
PCI: imx: enable imx8qm/qxp pcie support
Enable the imx8qm/qxp pcie support.
Verified on the imx8qxp mek board.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
-rw-r--r-- | Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 11 | ||||
-rw-r--r-- | drivers/pci/controller/dwc/pci-imx6.c | 424 | ||||
-rw-r--r-- | include/dt-bindings/soc/imx8_hsio.h | 31 |
3 files changed, 460 insertions, 6 deletions
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index acea1cd444fd..de00aec17ce8 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml @@ -25,6 +25,8 @@ properties: - fsl,imx6qp-pcie - fsl,imx7d-pcie - fsl,imx8mq-pcie + - fsl,imx8qm-pcie + - fsl,imx8qxp-pcie reg: items: @@ -148,6 +150,15 @@ properties: the three PCIe PHY powers. This regulator can be supplied by both 1.8v and 3.3v voltage supplies (optional required). + hsio-cfg: + description: hsio configuration mode when the pcie node is supported. + mode 1: pciea 2 lanes and one sata ahci port. + mode 2: pciea 1 lane, pcieb 1 lane and one sata ahci port. + mode 3: pciea 2 lanes, pcieb 1 lane. + + local-addr: + description: the local address used in hsio module. + required: - compatible - reg diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index df36b2fd576b..cb6a852ab220 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -8,6 +8,7 @@ * Author: Sean Cross <xobs@kosagi.com> */ +#include <dt-bindings/soc/imx8_hsio.h> #include <linux/bitfield.h> #include <linux/clk.h> #include <linux/delay.h> @@ -17,6 +18,7 @@ #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> #include <linux/mfd/syscon/imx7-iomuxc-gpr.h> #include <linux/module.h> +#include <linux/of_address.h> #include <linux/of_gpio.h> #include <linux/of_device.h> #include <linux/of_address.h> @@ -40,6 +42,7 @@ #define IMX8MQ_GPR_PCIE_VREG_BYPASS BIT(12) #define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE GENMASK(11, 8) #define IMX8MQ_PCIE2_BASE_ADDR 0x33c00000 +#define IMX8_HSIO_PCIEB_BASE_ADDR 0x5f010000 #define to_imx6_pcie(x) dev_get_drvdata((x)->dev) @@ -49,11 +52,14 @@ enum imx6_pcie_variants { IMX6QP, IMX7D, IMX8MQ, + IMX8QM, + IMX8QXP, }; #define IMX6_PCIE_FLAG_IMX6_PHY BIT(0) #define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1) #define IMX6_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2) +#define IMX6_PCIE_FLAG_IMX6_CPU_ADDR_FIXUP BIT(3) struct imx6_pcie_drvdata { enum imx6_pcie_variants variant; @@ -63,11 +69,13 @@ struct imx6_pcie_drvdata { struct imx6_pcie { struct dw_pcie *pci; + int clkreq_gpio; int dis_gpio; int reset_gpio; bool gpio_active_high; struct clk *pcie_bus; struct clk *pcie_phy; + struct clk *pcie_per; struct clk *pcie_inbound_axi; struct clk *pcie; struct clk *pcie_aux; @@ -81,6 +89,10 @@ struct imx6_pcie { u32 tx_deemph_gen2_6db; u32 tx_swing_full; u32 tx_swing_low; + u32 hsio_cfg; + u32 ext_osc; + u32 local_addr; + int link_gen; struct regulator *vpcie; struct regulator *vph; void __iomem *phy_base; @@ -89,6 +101,8 @@ struct imx6_pcie { struct device *pd_pcie; /* power domain for pcie phy */ struct device *pd_pcie_phy; + /* power domain for hsio gpio used by pcie */ + struct device *pd_hsio_gpio; const struct imx6_pcie_drvdata *drvdata; }; @@ -144,6 +158,43 @@ struct imx6_pcie { #define PHY_RX_OVRD_IN_LO_RX_DATA_EN BIT(5) #define PHY_RX_OVRD_IN_LO_RX_PLL_EN BIT(3) +/* iMX8 HSIO registers */ +#define IMX8QM_CSR_PHYX2_OFFSET 0x00000 +#define IMX8QM_CSR_PHYX1_OFFSET 0x10000 +#define IMX8QM_CSR_PHYX_STTS0_OFFSET 0x4 +#define IMX8QM_CSR_PCIEA_OFFSET 0x20000 +#define IMX8QM_CSR_PCIEB_OFFSET 0x30000 +#define IMX8QM_CSR_PCIE_CTRL1_OFFSET 0x4 +#define IMX8QM_CSR_PCIE_CTRL2_OFFSET 0x8 +#define IMX8QM_CSR_PCIE_STTS0_OFFSET 0xC +#define IMX8QM_CSR_MISC_OFFSET 0x50000 + +#define IMX8QM_CTRL_LTSSM_ENABLE BIT(4) +#define IMX8QM_CTRL_READY_ENTR_L23 BIT(5) +#define IMX8QM_CTRL_PM_XMT_TURNOFF BIT(9) +#define IMX8QM_CTRL_BUTTON_RST_N BIT(21) +#define IMX8QM_CTRL_PERST_N BIT(22) +#define IMX8QM_CTRL_POWER_UP_RST_N BIT(23) + +#define IMX8QM_CTRL_STTS0_PM_LINKST_IN_L2 BIT(13) +#define IMX8QM_CTRL_STTS0_PM_REQ_CORE_RST BIT(19) +#define IMX8QM_STTS0_LANE0_TX_PLL_LOCK BIT(4) +#define IMX8QM_STTS0_LANE1_TX_PLL_LOCK BIT(12) + +#define IMX8QM_PCIE_TYPE_MASK (0xF << 24) + +#define IMX8QM_PHYX2_CTRL0_APB_MASK 0x3 +#define IMX8QM_PHY_APB_RSTN_0 BIT(0) +#define IMX8QM_PHY_APB_RSTN_1 BIT(1) + +#define IMX8QM_MISC_IOB_RXENA BIT(0) +#define IMX8QM_MISC_IOB_TXENA BIT(1) +#define IMX8QM_CSR_MISC_IOB_A_0_TXOE BIT(2) +#define IMX8QM_CSR_MISC_IOB_A_0_M1M0_MASK (0x3 << 3) +#define IMX8QM_CSR_MISC_IOB_A_0_M1M0_2 BIT(4) +#define IMX8QM_MISC_PHYX1_EPCS_SEL BIT(12) +#define IMX8QM_MISC_PCIE_AB_SELECT BIT(13) + static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val) { struct dw_pcie *pci = imx6_pcie->pci; @@ -362,11 +413,34 @@ static int imx6_pcie_attach_pd(struct device *dev) return -EINVAL; } + switch (imx6_pcie->drvdata->variant) { + case IMX8QM: + case IMX8QXP: + imx6_pcie->pd_hsio_gpio = dev_pm_domain_attach_by_name(dev, "hsio_gpio"); + if (IS_ERR(imx6_pcie->pd_hsio_gpio)) + return PTR_ERR(imx6_pcie->pd_hsio_gpio); + + link = device_link_add(dev, imx6_pcie->pd_hsio_gpio, + DL_FLAG_STATELESS | + DL_FLAG_PM_RUNTIME | + DL_FLAG_RPM_ACTIVE); + if (!link) { + dev_err(dev, "Failed to add device_link to hsio_gpio pd.\n"); + return -EINVAL; + } + + break; + default: + break; + } + return 0; } static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) { + u32 val; + int i; struct device *dev = imx6_pcie->pci->dev; switch (imx6_pcie->drvdata->variant) { @@ -395,6 +469,38 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16); break; + case IMX8QXP: + val = IMX8QM_CSR_PCIEB_OFFSET; + regmap_update_bits(imx6_pcie->iomuxc_gpr, + val + IMX8QM_CSR_PCIE_CTRL2_OFFSET, + IMX8QM_CTRL_BUTTON_RST_N, + IMX8QM_CTRL_BUTTON_RST_N); + regmap_update_bits(imx6_pcie->iomuxc_gpr, + val + IMX8QM_CSR_PCIE_CTRL2_OFFSET, + IMX8QM_CTRL_PERST_N, + IMX8QM_CTRL_PERST_N); + regmap_update_bits(imx6_pcie->iomuxc_gpr, + val + IMX8QM_CSR_PCIE_CTRL2_OFFSET, + IMX8QM_CTRL_POWER_UP_RST_N, + IMX8QM_CTRL_POWER_UP_RST_N); + break; + case IMX8QM: + for (i = 0; i <= imx6_pcie->controller_id; i++) { + val = IMX8QM_CSR_PCIEA_OFFSET + i * SZ_64K; + regmap_update_bits(imx6_pcie->iomuxc_gpr, + val + IMX8QM_CSR_PCIE_CTRL2_OFFSET, + IMX8QM_CTRL_BUTTON_RST_N, + IMX8QM_CTRL_BUTTON_RST_N); + regmap_update_bits(imx6_pcie->iomuxc_gpr, + val + IMX8QM_CSR_PCIE_CTRL2_OFFSET, + IMX8QM_CTRL_PERST_N, + IMX8QM_CTRL_PERST_N); + regmap_update_bits(imx6_pcie->iomuxc_gpr, + val + IMX8QM_CSR_PCIE_CTRL2_OFFSET, + IMX8QM_CTRL_POWER_UP_RST_N, + IMX8QM_CTRL_POWER_UP_RST_N); + } + break; } if (imx6_pcie->vpcie && regulator_is_enabled(imx6_pcie->vpcie) > 0) { @@ -466,6 +572,21 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN, IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN); break; + case IMX8QXP: + case IMX8QM: + ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi); + if (ret) { + dev_err(dev, "unable to enable pcie_axi clock\n"); + break; + } + ret = clk_prepare_enable(imx6_pcie->pcie_per); + if (ret) { + dev_err(dev, "unable to enable pcie_per clock\n"); + clk_disable_unprepare(imx6_pcie->pcie_inbound_axi); + break; + } + + break; } return ret; @@ -484,11 +605,53 @@ static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie) dev_err(dev, "PCIe PLL lock timeout\n"); } +static int imx8_hsio_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie) +{ + u32 val, offset = 0, cond = 0; + int ret; + struct dw_pcie *pci = imx6_pcie->pci; + struct device *dev = pci->dev; + + if (imx6_pcie->hsio_cfg == PCIEAX1PCIEBX1SATA) { + if (imx6_pcie->controller_id == 0) /* pciea 1 lanes */ + cond = IMX8QM_STTS0_LANE0_TX_PLL_LOCK; + else /* pcieb 1 lanes */ + cond = IMX8QM_STTS0_LANE1_TX_PLL_LOCK; + offset = IMX8QM_CSR_PHYX2_OFFSET + 0x4; + } else if (imx6_pcie->hsio_cfg == PCIEAX2PCIEBX1) { + offset = IMX8QM_CSR_PHYX2_OFFSET + + imx6_pcie->controller_id * SZ_64K + + IMX8QM_CSR_PHYX_STTS0_OFFSET; + cond = IMX8QM_STTS0_LANE0_TX_PLL_LOCK; + if (imx6_pcie->controller_id == 0) /* pciea 2 lanes */ + cond |= IMX8QM_STTS0_LANE1_TX_PLL_LOCK; + } else if (imx6_pcie->hsio_cfg == PCIEAX2SATA) { + offset = IMX8QM_CSR_PHYX2_OFFSET + 0x4; + cond = IMX8QM_STTS0_LANE0_TX_PLL_LOCK; + cond |= IMX8QM_STTS0_LANE1_TX_PLL_LOCK; + } + + ret = regmap_read_poll_timeout(imx6_pcie->iomuxc_gpr, offset, + val, val & cond, + PHY_PLL_LOCK_WAIT_USLEEP_MAX, + PHY_PLL_LOCK_WAIT_TIMEOUT); + if (ret) { + dev_err(dev, "PCIe PLL lock timeout\n"); + ret = -ENODEV; + } else { + dev_info(dev, "PCIe PLL is locked.\n"); + } + + return ret; +} + + static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) { struct dw_pcie *pci = imx6_pcie->pci; struct device *dev = pci->dev; - int ret; + int ret, i; + u32 val, tmp; if (imx6_pcie->vpcie && !regulator_is_enabled(imx6_pcie->vpcie)) { ret = regulator_enable(imx6_pcie->vpcie); @@ -536,6 +699,29 @@ static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) } switch (imx6_pcie->drvdata->variant) { + case IMX8QXP: + case IMX8QM: + /* bit19 PM_REQ_CORE_RST of pciex#_stts0 should be cleared. */ + for (i = 0; i < 100; i++) { + val = IMX8QM_CSR_PCIEA_OFFSET + + imx6_pcie->controller_id * SZ_64K; + regmap_read(imx6_pcie->iomuxc_gpr, + val + IMX8QM_CSR_PCIE_STTS0_OFFSET, + &tmp); + if ((tmp & IMX8QM_CTRL_STTS0_PM_REQ_CORE_RST) == 0) + break; + udelay(10); + } + + if ((tmp & IMX8QM_CTRL_STTS0_PM_REQ_CORE_RST) != 0) + dev_err(dev, "ERROR PM_REQ_CORE_RST is still set.\n"); + + /* wait for phy pll lock firstly. */ + if (imx8_hsio_pcie_wait_for_phy_pll_lock(imx6_pcie)) { + ret = -ENODEV; + break; + } + break; case IMX8MQ: reset_control_deassert(imx6_pcie->pciephy_reset); break; @@ -598,23 +784,125 @@ static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie) { unsigned int mask, val; - if (imx6_pcie->drvdata->variant == IMX8MQ && + if (imx6_pcie->drvdata->variant == IMX8QM || + imx6_pcie->drvdata->variant == IMX8QXP) { + val = IMX8QM_CSR_PCIEA_OFFSET + + imx6_pcie->controller_id * SZ_64K; + regmap_update_bits(imx6_pcie->iomuxc_gpr, + val, IMX8QM_PCIE_TYPE_MASK, + PCI_EXP_TYPE_ROOT_PORT << 24); + } else if (imx6_pcie->drvdata->variant == IMX8MQ && imx6_pcie->controller_id == 1) { mask = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE; val = FIELD_PREP(IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT); + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, + mask, val); } else { mask = IMX6Q_GPR12_DEVICE_TYPE; val = FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT); + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, + mask, val); } - - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, mask, val); } static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie) { switch (imx6_pcie->drvdata->variant) { + case IMX8QXP: + case IMX8QM: + if (imx6_pcie->hsio_cfg == PCIEAX2SATA) { + /* + * bit 0 rx ena 1. + * bit12 PHY_X1_EPCS_SEL 1. + * bit13 phy_ab_select 0. + */ + regmap_update_bits(imx6_pcie->iomuxc_gpr, + IMX8QM_CSR_PHYX2_OFFSET, + IMX8QM_PHYX2_CTRL0_APB_MASK, + IMX8QM_PHY_APB_RSTN_0 + | IMX8QM_PHY_APB_RSTN_1); + + regmap_update_bits(imx6_pcie->iomuxc_gpr, + IMX8QM_CSR_MISC_OFFSET, + IMX8QM_MISC_PHYX1_EPCS_SEL, + IMX8QM_MISC_PHYX1_EPCS_SEL); + regmap_update_bits(imx6_pcie->iomuxc_gpr, + IMX8QM_CSR_MISC_OFFSET, + IMX8QM_MISC_PCIE_AB_SELECT, + 0); + } else if (imx6_pcie->hsio_cfg == PCIEAX1PCIEBX1SATA) { + regmap_update_bits(imx6_pcie->iomuxc_gpr, + IMX8QM_CSR_PHYX2_OFFSET, + IMX8QM_PHYX2_CTRL0_APB_MASK, + IMX8QM_PHY_APB_RSTN_0 + | IMX8QM_PHY_APB_RSTN_1); + + regmap_update_bits(imx6_pcie->iomuxc_gpr, + IMX8QM_CSR_MISC_OFFSET, + IMX8QM_MISC_PHYX1_EPCS_SEL, + IMX8QM_MISC_PHYX1_EPCS_SEL); + regmap_update_bits(imx6_pcie->iomuxc_gpr, + IMX8QM_CSR_MISC_OFFSET, + IMX8QM_MISC_PCIE_AB_SELECT, + IMX8QM_MISC_PCIE_AB_SELECT); + } else if (imx6_pcie->hsio_cfg == PCIEAX2PCIEBX1) { + /* + * bit 0 rx ena 1. + * bit12 PHY_X1_EPCS_SEL 0. + * bit13 phy_ab_select 1. + */ + if (imx6_pcie->controller_id) + regmap_update_bits(imx6_pcie->iomuxc_gpr, + IMX8QM_CSR_PHYX1_OFFSET, + IMX8QM_PHY_APB_RSTN_0, + IMX8QM_PHY_APB_RSTN_0); + else + regmap_update_bits(imx6_pcie->iomuxc_gpr, + IMX8QM_CSR_PHYX2_OFFSET, + IMX8QM_PHYX2_CTRL0_APB_MASK, + IMX8QM_PHY_APB_RSTN_0 + | IMX8QM_PHY_APB_RSTN_1); + + regmap_update_bits(imx6_pcie->iomuxc_gpr, + IMX8QM_CSR_MISC_OFFSET, + IMX8QM_MISC_PHYX1_EPCS_SEL, + 0); + regmap_update_bits(imx6_pcie->iomuxc_gpr, + IMX8QM_CSR_MISC_OFFSET, + IMX8QM_MISC_PCIE_AB_SELECT, + IMX8QM_MISC_PCIE_AB_SELECT); + } + + if (imx6_pcie->ext_osc) { + regmap_update_bits(imx6_pcie->iomuxc_gpr, + IMX8QM_CSR_MISC_OFFSET, + IMX8QM_MISC_IOB_RXENA, + IMX8QM_MISC_IOB_RXENA); + regmap_update_bits(imx6_pcie->iomuxc_gpr, + IMX8QM_CSR_MISC_OFFSET, + IMX8QM_MISC_IOB_TXENA, + 0); + } else { + /* Try to used the internal pll as ref clk */ + regmap_update_bits(imx6_pcie->iomuxc_gpr, + IMX8QM_CSR_MISC_OFFSET, + IMX8QM_MISC_IOB_RXENA, + 0); + regmap_update_bits(imx6_pcie->iomuxc_gpr, + IMX8QM_CSR_MISC_OFFSET, + IMX8QM_MISC_IOB_TXENA, + IMX8QM_MISC_IOB_TXENA); + regmap_update_bits(imx6_pcie->iomuxc_gpr, + IMX8QM_CSR_MISC_OFFSET, + IMX8QM_CSR_MISC_IOB_A_0_TXOE + | IMX8QM_CSR_MISC_IOB_A_0_M1M0_MASK, + IMX8QM_CSR_MISC_IOB_A_0_TXOE + | IMX8QM_CSR_MISC_IOB_A_0_M1M0_2); + } + + break; case IMX8MQ: /* * TODO: Currently this code assumes external @@ -742,6 +1030,7 @@ static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie) static void imx6_pcie_ltssm_enable(struct device *dev) { + u32 val; struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); switch (imx6_pcie->drvdata->variant) { @@ -756,6 +1045,16 @@ static void imx6_pcie_ltssm_enable(struct device *dev) case IMX8MQ: reset_control_deassert(imx6_pcie->apps_reset); break; + case IMX8QXP: + case IMX8QM: + /* Bit4 of the CTRL2 */ + val = IMX8QM_CSR_PCIEA_OFFSET + + imx6_pcie->controller_id * SZ_64K; + regmap_update_bits(imx6_pcie->iomuxc_gpr, + val + IMX8QM_CSR_PCIE_CTRL2_OFFSET, + IMX8QM_CTRL_LTSSM_ENABLE, + IMX8QM_CTRL_LTSSM_ENABLE); + break; } } @@ -784,11 +1083,11 @@ static int imx6_pcie_start_link(struct dw_pcie *pci) if (ret) goto err_reset_phy; - if (pci->link_gen == 2) { + if (pci->link_gen >= 2) { /* Allow Gen2 mode after the link is up. */ tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); tmp &= ~PCI_EXP_LNKCAP_SLS; - tmp |= PCI_EXP_LNKCAP_SLS_5_0GB; + tmp |= pci->link_gen; dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp); /* @@ -860,9 +1159,26 @@ static const struct dw_pcie_ops dw_pcie_ops = { .start_link = imx6_pcie_start_link, }; +static u64 imx6_pcie_cpu_addr_fixup(struct dw_pcie *pcie, u64 cpu_addr) +{ + struct pcie_port *pp = &pcie->pp; + struct imx6_pcie *imx6_pcie = to_imx6_pcie(pcie); + + if (imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_CPU_ADDR_FIXUP) + return (cpu_addr + imx6_pcie->local_addr - pp->mem_base); + else + return cpu_addr; +} + +static const struct dw_pcie_ops dw_pcie_ops = { + /* No special ops needed, but pcie-designware still expects this struct */ + .cpu_addr_fixup = imx6_pcie_cpu_addr_fixup, +}; + #ifdef CONFIG_PM_SLEEP static void imx6_pcie_ltssm_disable(struct device *dev) { + u32 val; struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); switch (imx6_pcie->drvdata->variant) { @@ -874,6 +1190,18 @@ static void imx6_pcie_ltssm_disable(struct device *dev) case IMX7D: reset_control_assert(imx6_pcie->apps_reset); break; + case IMX8QXP: + case IMX8QM: + /* Bit4 of the CTRL2 */ + val = IMX8QM_CSR_PCIEA_OFFSET + + imx6_pcie->controller_id * SZ_64K; + regmap_update_bits(imx6_pcie->iomuxc_gpr, + val + IMX8QM_CSR_PCIE_CTRL2_OFFSET, + IMX8QM_CTRL_LTSSM_ENABLE, 0); + regmap_update_bits(imx6_pcie->iomuxc_gpr, + val + IMX8QM_CSR_PCIE_CTRL2_OFFSET, + IMX8QM_CTRL_READY_ENTR_L23, 0); + break; default: dev_err(dev, "ltssm_disable not supported\n"); } @@ -881,6 +1209,8 @@ static void imx6_pcie_ltssm_disable(struct device *dev) static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie) { + int i; + u32 dst, val; struct device *dev = imx6_pcie->pci->dev; /* Some variants have a turnoff reset in DT */ @@ -899,6 +1229,34 @@ static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie) regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_PM_TURN_OFF, 0); break; + case IMX8QXP: + case IMX8QM: + dst = IMX8QM_CSR_PCIEA_OFFSET + imx6_pcie->controller_id * SZ_64K; + regmap_update_bits(imx6_pcie->iomuxc_gpr, + dst + IMX8QM_CSR_PCIE_CTRL2_OFFSET, + IMX8QM_CTRL_PM_XMT_TURNOFF, + IMX8QM_CTRL_PM_XMT_TURNOFF); + regmap_update_bits(imx6_pcie->iomuxc_gpr, + dst + IMX8QM_CSR_PCIE_CTRL2_OFFSET, + IMX8QM_CTRL_PM_XMT_TURNOFF, + 0); + regmap_update_bits(imx6_pcie->iomuxc_gpr, + dst + IMX8QM_CSR_PCIE_CTRL2_OFFSET, + IMX8QM_CTRL_READY_ENTR_L23, + IMX8QM_CTRL_READY_ENTR_L23); + /* check the L2 is entered or not. */ + for (i = 0; i < 10000; i++) { + regmap_read(imx6_pcie->iomuxc_gpr, + dst + IMX8QM_CSR_PCIE_STTS0_OFFSET, + &val); + if (val & IMX8QM_CTRL_STTS0_PM_LINKST_IN_L2) + break; + udelay(10); + } + if ((val & IMX8QM_CTRL_STTS0_PM_LINKST_IN_L2) == 0) + dev_err(dev, "PCIE%d can't enter into L2.\n", + imx6_pcie->controller_id); + break; default: dev_err(dev, "PME_Turn_Off not implemented\n"); return; @@ -933,6 +1291,11 @@ static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie) case IMX8MQ: clk_disable_unprepare(imx6_pcie->pcie_aux); break; + case IMX8QXP: + case IMX8QM: + clk_disable_unprepare(imx6_pcie->pcie_per); + clk_disable_unprepare(imx6_pcie->pcie_inbound_axi); + break; default: break; } @@ -1025,7 +1388,27 @@ static int imx6_pcie_probe(struct platform_device *pdev) if (IS_ERR(pci->dbi_base)) return PTR_ERR(pci->dbi_base); + if (of_property_read_u32(node, "hsio-cfg", &imx6_pcie->hsio_cfg)) + imx6_pcie->hsio_cfg = 0; + if (of_property_read_u32(node, "ext_osc", &imx6_pcie->ext_osc) < 0) + imx6_pcie->ext_osc = 0; + + if (of_property_read_u32(node, "local-addr", &imx6_pcie->local_addr)) + imx6_pcie->local_addr = 0; + /* Fetch GPIOs */ + imx6_pcie->clkreq_gpio = of_get_named_gpio(node, "clkreq-gpio", 0); + if (gpio_is_valid(imx6_pcie->clkreq_gpio)) { + ret = devm_gpio_request_one(&pdev->dev, imx6_pcie->clkreq_gpio, + GPIOF_OUT_INIT_LOW, "PCIe CLKREQ"); + if (ret) { + dev_err(&pdev->dev, "unable to get clkreq gpio\n"); + return ret; + } + } else if (imx6_pcie->clkreq_gpio == -EPROBE_DEFER) { + return imx6_pcie->clkreq_gpio; + } + imx6_pcie->dis_gpio = of_get_named_gpio(node, "disable-gpio", 0); if (gpio_is_valid(imx6_pcie->dis_gpio)) { ret = devm_gpio_request_one(&pdev->dev, imx6_pcie->dis_gpio, @@ -1103,6 +1486,25 @@ static int imx6_pcie_probe(struct platform_device *pdev) return PTR_ERR(imx6_pcie->apps_reset); } break; + case IMX8QM: + case IMX8QXP: + if (dbi_base->start == IMX8_HSIO_PCIEB_BASE_ADDR) + imx6_pcie->controller_id = 1; + + imx6_pcie->pcie_per = devm_clk_get(dev, "pcie_per"); + if (IS_ERR(imx6_pcie->pcie_per)) { + dev_err(dev, "pcie_per clock source missing or invalid\n"); + return PTR_ERR(imx6_pcie->pcie_per); + } + + imx6_pcie->pcie_inbound_axi = devm_clk_get(&pdev->dev, + "pcie_inbound_axi"); + if (IS_ERR(imx6_pcie->pcie_inbound_axi)) { + dev_err(&pdev->dev, + "pcie clock source missing or invalid\n"); + return PTR_ERR(imx6_pcie->pcie_inbound_axi); + } + break; default: break; } @@ -1215,6 +1617,14 @@ static const struct imx6_pcie_drvdata drvdata[] = { [IMX8MQ] = { .variant = IMX8MQ, }, + [IMX8QM] = { + .variant = IMX8QM, + .flags = IMX6_PCIE_FLAG_IMX6_CPU_ADDR_FIXUP, + }, + [IMX8QXP] = { + .variant = IMX8QXP, + .flags = IMX6_PCIE_FLAG_IMX6_CPU_ADDR_FIXUP, + }, }; static const struct of_device_id imx6_pcie_of_match[] = { @@ -1223,6 +1633,8 @@ static const struct of_device_id imx6_pcie_of_match[] = { { .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], }, { .compatible = "fsl,imx7d-pcie", .data = &drvdata[IMX7D], }, { .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], } , + { .compatible = "fsl,imx8qm-pcie", .data = &drvdata[IMX8QM], }, + { .compatible = "fsl,imx8qxp-pcie", .data = &drvdata[IMX8QXP], }, {}, }; diff --git a/include/dt-bindings/soc/imx8_hsio.h b/include/dt-bindings/soc/imx8_hsio.h new file mode 100644 index 000000000000..3cf1056b63d7 --- /dev/null +++ b/include/dt-bindings/soc/imx8_hsio.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DT_BINDINGS_IMX8_HSIO_H +#define __DT_BINDINGS_IMX8_HSIO_H + +/* + * imx8qm hsio has pciea, pcieb and sata modules, and hsio + * can be configured to the following different work modes. + * 1 - pciea 2 lanes and one sata ahci port. + * 2 - pciea 1 lane, pcieb 1 lane and one sata ahci port. + * 3 - pciea 2 lanes, pcieb 1 lane. + * Choose one mode, refer to the exact hardware board design. + */ +#define PCIEAX2SATA 1 +#define PCIEAX1PCIEBX1SATA 2 +#define PCIEAX2PCIEBX1 3 + +#endif /* __DT_BINDINGS_IMX8_HSIO_H */ |