diff options
| author | Borislav Petkov (AMD) <bp@alien8.de> | 2026-01-19 14:49:13 +0100 |
|---|---|---|
| committer | Borislav Petkov (AMD) <bp@alien8.de> | 2026-01-19 15:23:48 +0100 |
| commit | 9183c97e7e22591cfd258b5131493d5afcab4b08 (patch) | |
| tree | 513f5eac254ca7d6fb41b5390d182bfb69e279e6 | |
| parent | e21279b73ef6c7d27237912c914f2db0c5a74786 (diff) | |
x86/sev: Rename sev_es_ghcb_handle_msr() to __vc_handle_msr()
Forgot to do that during the Secure AVIC review. :-\
No functional changes.
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Tom Lendacky <thomas.lendacky@amd.com>
Link: https://patch.msgid.link/20260119141310.29605-1-bp@kernel.org
| -rw-r--r-- | arch/x86/coco/sev/core.c | 4 | ||||
| -rw-r--r-- | arch/x86/coco/sev/internal.h | 2 | ||||
| -rw-r--r-- | arch/x86/coco/sev/vc-handle.c | 4 |
3 files changed, 5 insertions, 5 deletions
diff --git a/arch/x86/coco/sev/core.c b/arch/x86/coco/sev/core.c index 379e0c09c7f3..a059e004f61b 100644 --- a/arch/x86/coco/sev/core.c +++ b/arch/x86/coco/sev/core.c @@ -989,7 +989,7 @@ u64 savic_ghcb_msr_read(u32 reg) ghcb = __sev_get_ghcb(&state); vc_ghcb_invalidate(ghcb); - res = sev_es_ghcb_handle_msr(ghcb, &ctxt, false); + res = __vc_handle_msr(ghcb, &ctxt, false); if (res != ES_OK) { pr_err("Secure AVIC MSR (0x%llx) read returned error (%d)\n", msr, res); /* MSR read failures are treated as fatal errors */ @@ -1019,7 +1019,7 @@ void savic_ghcb_msr_write(u32 reg, u64 value) ghcb = __sev_get_ghcb(&state); vc_ghcb_invalidate(ghcb); - res = sev_es_ghcb_handle_msr(ghcb, &ctxt, true); + res = __vc_handle_msr(ghcb, &ctxt, true); if (res != ES_OK) { pr_err("Secure AVIC MSR (0x%llx) write returned error (%d)\n", msr, res); /* MSR writes should never fail. Any failure is fatal error for SNP guest */ diff --git a/arch/x86/coco/sev/internal.h b/arch/x86/coco/sev/internal.h index 039326b5c799..b1d0c66a651a 100644 --- a/arch/x86/coco/sev/internal.h +++ b/arch/x86/coco/sev/internal.h @@ -85,7 +85,7 @@ static __always_inline void sev_es_wr_ghcb_msr(u64 val) native_wrmsr(MSR_AMD64_SEV_ES_GHCB, low, high); } -enum es_result sev_es_ghcb_handle_msr(struct ghcb *ghcb, struct es_em_ctxt *ctxt, bool write); +enum es_result __vc_handle_msr(struct ghcb *ghcb, struct es_em_ctxt *ctxt, bool write); u64 get_hv_features(void); diff --git a/arch/x86/coco/sev/vc-handle.c b/arch/x86/coco/sev/vc-handle.c index 43f264afd590..d98b5c08ef00 100644 --- a/arch/x86/coco/sev/vc-handle.c +++ b/arch/x86/coco/sev/vc-handle.c @@ -404,7 +404,7 @@ static enum es_result __vc_handle_secure_tsc_msrs(struct es_em_ctxt *ctxt, bool return ES_OK; } -enum es_result sev_es_ghcb_handle_msr(struct ghcb *ghcb, struct es_em_ctxt *ctxt, bool write) +enum es_result __vc_handle_msr(struct ghcb *ghcb, struct es_em_ctxt *ctxt, bool write) { struct pt_regs *regs = ctxt->regs; enum es_result ret; @@ -448,7 +448,7 @@ enum es_result sev_es_ghcb_handle_msr(struct ghcb *ghcb, struct es_em_ctxt *ctxt static enum es_result vc_handle_msr(struct ghcb *ghcb, struct es_em_ctxt *ctxt) { - return sev_es_ghcb_handle_msr(ghcb, ctxt, ctxt->insn.opcode.bytes[1] == 0x30); + return __vc_handle_msr(ghcb, ctxt, ctxt->insn.opcode.bytes[1] == 0x30); } static void __init vc_early_forward_exception(struct es_em_ctxt *ctxt) |