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authorManuel Cortez <mdjesuscv@gmail.com>2026-04-05 20:03:23 -0700
committerJonathan Corbet <corbet@lwn.net>2026-04-09 08:21:32 -0600
commit96c1f4517eb4feeae4656cf018a8d8a6156f1db3 (patch)
tree8bff6ffa48d6e7cdba651bb62420e02af11c4938
parentba0e9fdab3f8cbd1e70ecd288f3255b8b57c932a (diff)
docs: fix typos and duplicated words across documentation
Fix the following typos and duplicated words: - admin-guide/pm/intel-speed-select.rst: "weather" -> "whether" - core-api/real-time/differences.rst: "the the" -> "the" - admin-guide/bcache.rst: "to to" -> "to" Signed-off-by: Manuel Cortez <mdjesuscv@gmail.com> Acked-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Jonathan Corbet <corbet@lwn.net> Message-ID: <20260406030323.1196-1-mdjesuscv@gmail.com>
-rw-r--r--Documentation/admin-guide/bcache.rst2
-rw-r--r--Documentation/admin-guide/pm/intel-speed-select.rst2
-rw-r--r--Documentation/core-api/real-time/differences.rst2
3 files changed, 3 insertions, 3 deletions
diff --git a/Documentation/admin-guide/bcache.rst b/Documentation/admin-guide/bcache.rst
index f71f349553e4..325816edbdab 100644
--- a/Documentation/admin-guide/bcache.rst
+++ b/Documentation/admin-guide/bcache.rst
@@ -618,7 +618,7 @@ cache_replacement_policy
One of either lru, fifo or random.
freelist_percent
- Size of the freelist as a percentage of nbuckets. Can be written to to
+ Size of the freelist as a percentage of nbuckets. Can be written to
increase the number of buckets kept on the freelist, which lets you
artificially reduce the size of the cache at runtime. Mostly for testing
purposes (i.e. testing how different size caches affect your hit rate).
diff --git a/Documentation/admin-guide/pm/intel-speed-select.rst b/Documentation/admin-guide/pm/intel-speed-select.rst
index a2bfb971654f..dec2a25f10bc 100644
--- a/Documentation/admin-guide/pm/intel-speed-select.rst
+++ b/Documentation/admin-guide/pm/intel-speed-select.rst
@@ -287,7 +287,7 @@ level.
Check presence of other Intel(R) SST features
---------------------------------------------
-Each of the performance profiles also specifies weather there is support of
+Each of the performance profiles also specifies whether there is support of
other two Intel(R) SST features (Intel(R) Speed Select Technology - Base Frequency
(Intel(R) SST-BF) and Intel(R) Speed Select Technology - Turbo Frequency (Intel
SST-TF)).
diff --git a/Documentation/core-api/real-time/differences.rst b/Documentation/core-api/real-time/differences.rst
index 83ec9aa1c61a..a129570dab5a 100644
--- a/Documentation/core-api/real-time/differences.rst
+++ b/Documentation/core-api/real-time/differences.rst
@@ -213,7 +213,7 @@ to suspend until the callback completes, ensuring forward progress without
risking livelock.
In order to solve the problem at the API level, the sequence locks were extended
-to allow a proper handover between the the spinning reader and the maybe
+to allow a proper handover between the spinning reader and the maybe
blocked writer.
Sequence locks