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authorNiravkumar L Rabara <niravkumar.l.rabara@intel.com>2025-02-13 18:50:36 +0800
committerDinh Nguyen <dinguyen@kernel.org>2025-03-26 06:47:04 -0500
commita6c9896e65e555d679a4bc71c3cdfce6df4b2343 (patch)
tree11af7cb2c75e62d8b2a55fb6eb6b3e410cab7380
parentb76bca66ec3de25c3e700b7f5c37dc0c9de1e51a (diff)
arm64: dts: socfpga: agilex5: fix gpio0 address
Use the correct gpio0 address for Agilex5. Fixes: 3f7c869e143a ("arm64: dts: socfpga: agilex5: Add gpio0 node and spi dma handshake id") Cc: stable@vger.kernel.org Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
-rw-r--r--arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index 51c6e19e40b8..7d9394a04302 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -222,9 +222,9 @@
status = "disabled";
};
- gpio0: gpio@ffc03200 {
+ gpio0: gpio@10c03200 {
compatible = "snps,dw-apb-gpio";
- reg = <0xffc03200 0x100>;
+ reg = <0x10c03200 0x100>;
#address-cells = <1>;
#size-cells = <0>;
resets = <&rst GPIO0_RESET>;