summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>2025-12-18 14:38:48 -0800
committerDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>2025-12-22 10:21:58 -0800
commitb0c5cf4f5917bf562082c30879d26ccd572df5a3 (patch)
tree593bb950a301cdf856161bb0b893d81f178d1877
parent8d87fa19169eece7133db355b50767dcf0386c44 (diff)
drm/gt/guc: extract scheduler-related defines from guc_fwif.h
Some upcoming KLVs are sized based on the engine counts, so we need those defines to be moved to a separate file to include them from guc_klv_abi.h (which is already included by guc_fwif.h). Instead of moving just the engine-related defines, it is cleaner to move all scheduler-related defines (i.e., everything engine or context related). Note that the legacy GuC defines have not been moved and have instead been dropped because Xe doesn't support any GuC old enough to still use them. While at it, struct guc_ctxt_registration_info has been moved to guc_submit.c since it doesn't come from the GuC specs (we added it to make things simpler in our code). Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Link: https://patch.msgid.link/20251218223846.1146344-16-daniele.ceraolospurio@intel.com
-rw-r--r--drivers/gpu/drm/xe/abi/guc_scheduler_abi.h48
-rw-r--r--drivers/gpu/drm/xe/xe_guc_capture.h2
-rw-r--r--drivers/gpu/drm/xe/xe_guc_fwif.h54
-rw-r--r--drivers/gpu/drm/xe/xe_guc_submit.c17
4 files changed, 67 insertions, 54 deletions
diff --git a/drivers/gpu/drm/xe/abi/guc_scheduler_abi.h b/drivers/gpu/drm/xe/abi/guc_scheduler_abi.h
new file mode 100644
index 000000000000..db9c171f8b64
--- /dev/null
+++ b/drivers/gpu/drm/xe/abi/guc_scheduler_abi.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef _ABI_GUC_SCHEDULER_ABI_H
+#define _ABI_GUC_SCHEDULER_ABI_H
+
+/**
+ * Generic defines required for registration with and submissions to the GuC
+ * scheduler. Includes engine class/instance defines and context attributes
+ * (id, priority, etc)
+ */
+
+/* Engine classes/instances */
+#define GUC_RENDER_CLASS 0
+#define GUC_VIDEO_CLASS 1
+#define GUC_VIDEOENHANCE_CLASS 2
+#define GUC_BLITTER_CLASS 3
+#define GUC_COMPUTE_CLASS 4
+#define GUC_GSC_OTHER_CLASS 5
+#define GUC_LAST_ENGINE_CLASS GUC_GSC_OTHER_CLASS
+#define GUC_MAX_ENGINE_CLASSES 16
+#define GUC_MAX_INSTANCES_PER_CLASS 32
+
+/* context priority values */
+#define GUC_CLIENT_PRIORITY_KMD_HIGH 0
+#define GUC_CLIENT_PRIORITY_HIGH 1
+#define GUC_CLIENT_PRIORITY_KMD_NORMAL 2
+#define GUC_CLIENT_PRIORITY_NORMAL 3
+#define GUC_CLIENT_PRIORITY_NUM 4
+
+/* Context registration */
+#define GUC_ID_MAX 65535
+#define GUC_ID_UNKNOWN 0xffffffff
+
+#define CONTEXT_REGISTRATION_FLAG_KMD BIT(0)
+#define CONTEXT_REGISTRATION_FLAG_TYPE GENMASK(2, 1)
+#define GUC_CONTEXT_NORMAL 0
+#define GUC_CONTEXT_COMPRESSION_SAVE 1
+#define GUC_CONTEXT_COMPRESSION_RESTORE 2
+#define GUC_CONTEXT_COUNT (GUC_CONTEXT_COMPRESSION_RESTORE + 1)
+
+/* context enable/disable */
+#define GUC_CONTEXT_DISABLE 0
+#define GUC_CONTEXT_ENABLE 1
+
+#endif
diff --git a/drivers/gpu/drm/xe/xe_guc_capture.h b/drivers/gpu/drm/xe/xe_guc_capture.h
index 20a078dc4b85..34d6fdc64f56 100644
--- a/drivers/gpu/drm/xe/xe_guc_capture.h
+++ b/drivers/gpu/drm/xe/xe_guc_capture.h
@@ -8,8 +8,8 @@
#include <linux/types.h>
#include "abi/guc_capture_abi.h"
+#include "abi/guc_scheduler_abi.h"
#include "xe_guc.h"
-#include "xe_guc_fwif.h"
struct xe_exec_queue;
struct xe_guc;
diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h
index a04faec477ae..a33ea288b907 100644
--- a/drivers/gpu/drm/xe/xe_guc_fwif.h
+++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
@@ -10,6 +10,7 @@
#include "abi/guc_capture_abi.h"
#include "abi/guc_klvs_abi.h"
+#include "abi/guc_scheduler_abi.h"
#include "xe_hw_engine_types.h"
#define G2H_LEN_DW_SCHED_CONTEXT_MODE_SET 4
@@ -19,59 +20,6 @@
#define G2H_LEN_DW_MULTI_QUEUE_CONTEXT 3
#define G2H_LEN_DW_PAGE_RECLAMATION 3
-#define GUC_ID_MAX 65535
-#define GUC_ID_UNKNOWN 0xffffffff
-
-#define GUC_CONTEXT_DISABLE 0
-#define GUC_CONTEXT_ENABLE 1
-
-#define GUC_CLIENT_PRIORITY_KMD_HIGH 0
-#define GUC_CLIENT_PRIORITY_HIGH 1
-#define GUC_CLIENT_PRIORITY_KMD_NORMAL 2
-#define GUC_CLIENT_PRIORITY_NORMAL 3
-#define GUC_CLIENT_PRIORITY_NUM 4
-
-#define GUC_RENDER_ENGINE 0
-#define GUC_VIDEO_ENGINE 1
-#define GUC_BLITTER_ENGINE 2
-#define GUC_VIDEOENHANCE_ENGINE 3
-#define GUC_VIDEO_ENGINE2 4
-#define GUC_MAX_ENGINES_NUM (GUC_VIDEO_ENGINE2 + 1)
-
-#define GUC_RENDER_CLASS 0
-#define GUC_VIDEO_CLASS 1
-#define GUC_VIDEOENHANCE_CLASS 2
-#define GUC_BLITTER_CLASS 3
-#define GUC_COMPUTE_CLASS 4
-#define GUC_GSC_OTHER_CLASS 5
-#define GUC_LAST_ENGINE_CLASS GUC_GSC_OTHER_CLASS
-#define GUC_MAX_ENGINE_CLASSES 16
-#define GUC_MAX_INSTANCES_PER_CLASS 32
-
-#define GUC_CONTEXT_NORMAL 0
-#define GUC_CONTEXT_COMPRESSION_SAVE 1
-#define GUC_CONTEXT_COMPRESSION_RESTORE 2
-#define GUC_CONTEXT_COUNT (GUC_CONTEXT_COMPRESSION_RESTORE + 1)
-
-/* Helper for context registration H2G */
-struct guc_ctxt_registration_info {
- u32 flags;
- u32 context_idx;
- u32 engine_class;
- u32 engine_submit_mask;
- u32 wq_desc_lo;
- u32 wq_desc_hi;
- u32 wq_base_lo;
- u32 wq_base_hi;
- u32 wq_size;
- u32 cgp_lo;
- u32 cgp_hi;
- u32 hwlrca_lo;
- u32 hwlrca_hi;
-};
-#define CONTEXT_REGISTRATION_FLAG_KMD BIT(0)
-#define CONTEXT_REGISTRATION_FLAG_TYPE GENMASK(2, 1)
-
/* 32-bit KLV structure as used by policy updates and others */
struct guc_klv_generic_dw_t {
u32 kl;
diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
index b8d20c05d343..1646535b86a3 100644
--- a/drivers/gpu/drm/xe/xe_guc_submit.c
+++ b/drivers/gpu/drm/xe/xe_guc_submit.c
@@ -673,6 +673,23 @@ static void set_exec_queue_group_banned(struct xe_exec_queue *q)
mutex_unlock(&group->list_lock);
}
+/* Helper for context registration H2G */
+struct guc_ctxt_registration_info {
+ u32 flags;
+ u32 context_idx;
+ u32 engine_class;
+ u32 engine_submit_mask;
+ u32 wq_desc_lo;
+ u32 wq_desc_hi;
+ u32 wq_base_lo;
+ u32 wq_base_hi;
+ u32 wq_size;
+ u32 cgp_lo;
+ u32 cgp_hi;
+ u32 hwlrca_lo;
+ u32 hwlrca_hi;
+};
+
#define parallel_read(xe_, map_, field_) \
xe_map_rd_field(xe_, &map_, 0, struct guc_submit_parallel_scratch, \
field_)