diff options
| author | Samson Tam <Samson.Tam@amd.com> | 2022-03-21 10:22:19 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2022-06-03 16:45:01 -0400 |
| commit | b6a93844145395068574cbbfaf3aea91d1f24f1a (patch) | |
| tree | b177176ac57fd70971ae92c2cc097dd303eefe5a | |
| parent | 80fb7a409c64ef304e4040320e87dbb2f10968ca (diff) | |
drm/amd/display: Match dprefclk with clk registers
Update base.dprefclk_khz to match result from dcn32_dump_clk_registers()
Signed-off-by: Samson Tam <Samson.Tam@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c index 3d2807fc769f..6a1d7c86e6b7 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c @@ -622,7 +622,11 @@ void dcn32_clk_mgr_construct( clk_mgr->ss_on_dprefclk = false; clk_mgr->dfs_ref_freq_khz = 100000; - clk_mgr->base.dprefclk_khz = 717000; /* Changed as per DCN3.2_clock_frequency doc */ + /* Changed from DCN3.2_clock_frequency doc to match + * dcn32_dump_clk_registers from 4 * dentist_vco_freq_khz / + * dprefclk DID divider + */ + clk_mgr->base.dprefclk_khz = 716666; clk_mgr->dccg->ref_dtbclk_khz = 268750; /* integer part is now VCO frequency in kHz */ @@ -636,8 +640,7 @@ void dcn32_clk_mgr_construct( } if (clk_mgr->base.boot_snapshot.dprefclk != 0) { - //ASSERT(clk_mgr->base.dprefclk_khz == clk_mgr->base.boot_snapshot.dprefclk); - //clk_mgr->base.dprefclk_khz = clk_mgr->base.boot_snapshot.dprefclk; + clk_mgr->base.dprefclk_khz = clk_mgr->base.boot_snapshot.dprefclk; } dcn32_clock_read_ss_info(clk_mgr); |