summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorGeert Uytterhoeven <geert+renesas@glider.be>2025-11-13 21:17:37 +0100
committerGeert Uytterhoeven <geert+renesas@glider.be>2025-11-13 21:17:37 +0100
commitc23be4242bed1009ff57aaa4578abe638696e5de (patch)
treef53f0a977844d8c010c3a8990d4a88559dd457d4
parentc6b63d54c6f8d81e72c8b9b8e8d1cb5ada03c5dd (diff)
parenta95ce05cd0cc8b53f1559390c4e690bb8f79562f (diff)
Merge tag 'renesas-r9a09g057-dt-binding-defs-tag5' into renesas-clk-for-v6.19
Renesas RZ/V2N and RZ/V2H USB3.0 Core Clock DT Binding Definitions USB3.0 core clock DT binding definitions for the Renesas RZ/V2N (R9A09G056) and RZ/V2H (R9A09G057) SoCs, shared by driver and DT source files.
-rw-r--r--include/dt-bindings/clock/renesas,r9a09g056-cpg.h2
-rw-r--r--include/dt-bindings/clock/renesas,r9a09g057-cpg.h4
2 files changed, 6 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/renesas,r9a09g056-cpg.h b/include/dt-bindings/clock/renesas,r9a09g056-cpg.h
index a9af5af9e3a1..234dcf4f0f91 100644
--- a/include/dt-bindings/clock/renesas,r9a09g056-cpg.h
+++ b/include/dt-bindings/clock/renesas,r9a09g056-cpg.h
@@ -21,5 +21,7 @@
#define R9A09G056_GBETH_0_CLK_PTP_REF_I 10
#define R9A09G056_GBETH_1_CLK_PTP_REF_I 11
#define R9A09G056_SPI_CLK_SPI 12
+#define R9A09G056_USB3_0_REF_ALT_CLK_P 13
+#define R9A09G056_USB3_0_CLKCORE 14
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__ */
diff --git a/include/dt-bindings/clock/renesas,r9a09g057-cpg.h b/include/dt-bindings/clock/renesas,r9a09g057-cpg.h
index 5346a898ab60..f91d7f72922a 100644
--- a/include/dt-bindings/clock/renesas,r9a09g057-cpg.h
+++ b/include/dt-bindings/clock/renesas,r9a09g057-cpg.h
@@ -22,5 +22,9 @@
#define R9A09G057_GBETH_0_CLK_PTP_REF_I 11
#define R9A09G057_GBETH_1_CLK_PTP_REF_I 12
#define R9A09G057_SPI_CLK_SPI 13
+#define R9A09G057_USB3_0_REF_ALT_CLK_P 14
+#define R9A09G057_USB3_0_CLKCORE 15
+#define R9A09G057_USB3_1_REF_ALT_CLK_P 16
+#define R9A09G057_USB3_1_CLKCORE 17
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__ */