drm/i915/ddi: convert intel_wait_ddi_buf_idle() to struct intel_display

Convert the intel_ddi.[ch] interfaces to struct intel_display. Postpone
further conversion to avoid conflicts.

Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/2fe5c63f3a7f9861e3bd063b7355aafe32298f37.1740502116.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

3 files changed, 8 insertions, 11 deletions

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index e34bf175262b..780dad5c5de7 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -187,11 +187,8 @@ static i915_reg_t intel_ddi_buf_status_reg(struct intel_display *display, enum p
 		return DDI_BUF_CTL(port);
 }
 
-void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
-			     enum port port)
+void intel_wait_ddi_buf_idle(struct intel_display *display, enum port port)
 {
-	struct intel_display *display = &dev_priv->display;
-
 	/*
 	 * Bspec's platform specific timeouts:
 	 * MTL+   : 100 us
@@ -3092,7 +3089,7 @@ static void intel_ddi_buf_disable(struct intel_encoder *encoder,
 	intel_de_rmw(dev_priv, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0);
 
 	if (DISPLAY_VER(display) >= 14)
-		intel_wait_ddi_buf_idle(dev_priv, port);
+		intel_wait_ddi_buf_idle(display, port);
 
 	mtl_ddi_disable_d2d(encoder);
 
@@ -3104,7 +3101,7 @@ static void intel_ddi_buf_disable(struct intel_encoder *encoder,
 	intel_ddi_disable_fec(encoder, crtc_state);
 
 	if (DISPLAY_VER(display) < 14)
-		intel_wait_ddi_buf_idle(dev_priv, port);
+		intel_wait_ddi_buf_idle(display, port);
 
 	intel_ddi_wait_for_fec_status(encoder, crtc_state, false);
 }
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h
index 2faadd1441e2..353eb04079e9 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi.h
@@ -9,7 +9,6 @@
 #include "i915_reg_defs.h"
 
 struct drm_connector_state;
-struct drm_i915_private;
 struct intel_atomic_state;
 struct intel_bios_encoder_data;
 struct intel_connector;
@@ -54,8 +53,7 @@ void hsw_ddi_get_config(struct intel_encoder *encoder,
 struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder);
 void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
 				const struct intel_crtc_state *crtc_state);
-void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
-			     enum port port);
+void intel_wait_ddi_buf_idle(struct intel_display *display, enum port port);
 void intel_ddi_init(struct intel_display *display,
 		    const struct intel_bios_encoder_data *devdata);
 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index 024d0c7e0a88..7e67b3881fd0 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -886,6 +886,7 @@ train_done:
 void hsw_fdi_link_train(struct intel_encoder *encoder,
 			const struct intel_crtc_state *crtc_state)
 {
+	struct intel_display *display = to_intel_display(crtc_state);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	u32 temp, i, rx_ctl_val;
@@ -992,7 +993,7 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
 		intel_de_rmw(dev_priv, DP_TP_CTL(PORT_E), DP_TP_CTL_ENABLE, 0);
 		intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E));
 
-		intel_wait_ddi_buf_idle(dev_priv, PORT_E);
+		intel_wait_ddi_buf_idle(display, PORT_E);
 
 		/* Reset FDI_RX_MISC pwrdn lanes */
 		intel_de_rmw(dev_priv, FDI_RX_MISC(PIPE_A),
@@ -1011,6 +1012,7 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
 
 void hsw_fdi_disable(struct intel_encoder *encoder)
 {
+	struct intel_display *display = to_intel_display(encoder);
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
 	/*
@@ -1021,7 +1023,7 @@ void hsw_fdi_disable(struct intel_encoder *encoder)
 	 */
 	intel_de_rmw(dev_priv, FDI_RX_CTL(PIPE_A), FDI_RX_ENABLE, 0);
 	intel_de_rmw(dev_priv, DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE, 0);
-	intel_wait_ddi_buf_idle(dev_priv, PORT_E);
+	intel_wait_ddi_buf_idle(display, PORT_E);
 	intel_ddi_disable_clock(encoder);
 	intel_de_rmw(dev_priv, FDI_RX_MISC(PIPE_A),
 		     FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK,