diff options
| author | Rob Herring (Arm) <robh@kernel.org> | 2025-04-10 10:47:23 -0500 |
|---|---|---|
| committer | Florian Fainelli <florian.fainelli@broadcom.com> | 2025-04-11 16:35:45 -0700 |
| commit | c9e81198a750870fcd806b853177108e982a1db6 (patch) | |
| tree | 4ae42d03a821af19d96b0f8d1b4cf4358b689d90 | |
| parent | 7f55c25d978e90368a308569a2f6172be2790cba (diff) | |
arm64: dts: broadcom: bcm2712: Use "l2-cache" for L2 cache node names
There's no need include the CPU number in the L2 cache node names as
the names are local to the CPU nodes. The documented node name is
also just "l2-cache".
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Link: https://lore.kernel.org/all/20250410-dt-cpu-schema-v2-2-63d7dc9ddd0a@kernel.org/
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
| -rw-r--r-- | arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi index 1dc6fba4bf31..0a9212d3106f 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi @@ -64,7 +64,7 @@ i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set next-level-cache = <&l2_cache_l0>; - l2_cache_l0: l2-cache-l0 { + l2_cache_l0: l2-cache { compatible = "cache"; cache-size = <0x80000>; cache-line-size = <64>; @@ -88,7 +88,7 @@ i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set next-level-cache = <&l2_cache_l1>; - l2_cache_l1: l2-cache-l1 { + l2_cache_l1: l2-cache { compatible = "cache"; cache-size = <0x80000>; cache-line-size = <64>; @@ -112,7 +112,7 @@ i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set next-level-cache = <&l2_cache_l2>; - l2_cache_l2: l2-cache-l2 { + l2_cache_l2: l2-cache { compatible = "cache"; cache-size = <0x80000>; cache-line-size = <64>; @@ -136,7 +136,7 @@ i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set next-level-cache = <&l2_cache_l3>; - l2_cache_l3: l2-cache-l3 { + l2_cache_l3: l2-cache { compatible = "cache"; cache-size = <0x80000>; cache-line-size = <64>; |