diff options
| author | Horatiu Vultur <horatiu.vultur@microchip.com> | 2025-11-19 14:47:50 +0100 |
|---|---|---|
| committer | Claudiu Beznea <claudiu.beznea@tuxon.dev> | 2025-12-30 17:11:17 +0200 |
| commit | d1a6f1259b0bb415107e83f6403a2ecb945d042f (patch) | |
| tree | 6dae08af1dbbc65139f62e2ea8630b8650669c9d | |
| parent | 8f0b4cce4481fb22653697cced8d0d04027cb1e8 (diff) | |
ARM: dts: microchip: lan966x: Fix the access to the PHYs for pcb8290
The problem is that the MDIO controller can't detect any of the PHYs.
The reason is that the lan966x is not pulling high the GPIO 53 that is
connected to the PHYs reset GPIO. Without doing this the PHYs are kept
in reset. The mdio controller framework has the possibility to control a
GPIO to release the reset of the PHYs. So take advantage of this and set
line to be high before accessing the PHYs.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lore.kernel.org/r/20251119134750.394655-1-horatiu.vultur@microchip.com
[claudiu.beznea: add microchip in patch title, s/possiblity/possibility
in patch description]
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
| -rw-r--r-- | arch/arm/boot/dts/microchip/lan966x-pcb8290.dts | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/microchip/lan966x-pcb8290.dts b/arch/arm/boot/dts/microchip/lan966x-pcb8290.dts index 3b7577e48b46..50bd29572f3e 100644 --- a/arch/arm/boot/dts/microchip/lan966x-pcb8290.dts +++ b/arch/arm/boot/dts/microchip/lan966x-pcb8290.dts @@ -54,6 +54,7 @@ &mdio0 { pinctrl-0 = <&miim_a_pins>; pinctrl-names = "default"; + reset-gpios = <&gpio 53 GPIO_ACTIVE_LOW>; status = "okay"; ext_phy0: ethernet-phy@7 { |