diff options
| author | Buday Csaba <buday.csaba@prolan.hu> | 2025-11-03 09:13:42 +0100 |
|---|---|---|
| committer | Jakub Kicinski <kuba@kernel.org> | 2025-11-04 17:30:46 -0800 |
| commit | e0c78fcad2bb04651af2ad40ed20714501931d7a (patch) | |
| tree | f2f0ef6e478bfebc750d408ff0f2f11ef13ba5bd | |
| parent | f2143e283c6b993f4ad8b85a45aa16ac899f1abc (diff) | |
dt-bindings: net: ethernet-phy: clarify when compatible must specify PHY ID
Change PHY ID description in ethernet-phy.yaml to clarify that a
PHY ID is required (may -> must) when the PHY requires special
initialization sequence.
Link: https://lore.kernel.org/netdev/20251026212026.GA2959311-robh@kernel.org/
Link: https://lore.kernel.org/netdev/aQIZvDt5gooZSTcp@debianbuilder/
Signed-off-by: Buday Csaba <buday.csaba@prolan.hu>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Link: https://patch.msgid.link/64c52d1a726944a68a308355433e8ef0f82c4240.1762157515.git.buday.csaba@prolan.hu
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
| -rw-r--r-- | Documentation/devicetree/bindings/net/ethernet-phy.yaml | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/net/ethernet-phy.yaml b/Documentation/devicetree/bindings/net/ethernet-phy.yaml index 2ec2d9fda7e3..bb4c49fc5fd8 100644 --- a/Documentation/devicetree/bindings/net/ethernet-phy.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-phy.yaml @@ -35,9 +35,13 @@ properties: description: PHYs that implement IEEE802.3 clause 45 - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$" description: - If the PHY reports an incorrect ID (or none at all) then the - compatible list may contain an entry with the correct PHY ID - in the above form. + PHYs contain identification registers. These will be read to + identify the PHY. If the PHY reports an incorrect ID, or the + PHY requires a specific initialization sequence (like a + particular order of clocks, resets, power supplies), in + order to be able to read the ID registers, then the + compatible list must contain an entry with the correct PHY + ID in the above form. The first group of digits is the 16 bit Phy Identifier 1 register, this is the chip vendor OUI bits 3:18. The second group of digits is the Phy Identifier 2 register, |