diff options
| author | Imre Deak <imre.deak@intel.com> | 2025-12-15 21:23:50 +0200 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2025-12-19 16:46:40 +0200 |
| commit | e25b6f1334463c1dea3972222352f0cca035cb51 (patch) | |
| tree | 958a92acef90cc4ae200981ea34225ef0a2b2136 | |
| parent | 2fb850a6aeb20b6a28c23dbddf1eaa704abb9ce9 (diff) | |
drm/i915/dp: Account with MST, SSC BW overhead for uncompressed DP-MST stream BW
On MST links the symbol alignment and SSC have a BW overhead, which
should be accounted for when calculating the required stream BW, do so
during mode validation for an uncompressed stream.
Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patch.msgid.link/20251215192357.172201-11-imre.deak@intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index e4dd6b4ca051..0db6ed2d9664 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -1458,6 +1458,8 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector, const int min_bpp = 18; int max_dotclk = display->cdclk.max_dotclk_freq; int max_rate, mode_rate, max_lanes, max_link_clock; + unsigned long bw_overhead_flags = + DRM_DP_BW_OVERHEAD_MST | DRM_DP_BW_OVERHEAD_SSC_REF_CLK; int ret; bool dsc = false; u16 dsc_max_compressed_bpp = 0; @@ -1491,7 +1493,8 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector, max_link_clock, max_lanes); mode_rate = intel_dp_link_required(max_link_clock, max_lanes, mode->clock, mode->hdisplay, - fxp_q4_from_int(min_bpp), 0); + fxp_q4_from_int(min_bpp), + bw_overhead_flags); /* * TODO: |