diff options
| author | Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | 2025-12-10 17:02:49 -0800 |
|---|---|---|
| committer | Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | 2025-12-11 19:20:30 -0800 |
| commit | ee26c3b2765a34d1055660cbfd4f00766dd25412 (patch) | |
| tree | d54a7af6ae9d660b937725e015d68a2b3a25e1bd | |
| parent | 7319c2ceb2d74d54f24b7f5409b97aed406f0189 (diff) | |
drm/xe/multi_queue: Add multi_queue_enable_mask to gt information
Add multi_queue_enable_mask field to the gt information structure
which is bitmask of all engine classes with multi queue support
enabled.
v2: Rename multi_queue_enable_mask to multi_queue_engine_class_mask
(Matt Brost)
Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
Link: https://patch.msgid.link/20251211010249.1647839-20-niranjana.vishwanathapura@intel.com
| -rw-r--r-- | drivers/gpu/drm/xe/xe_debugfs.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/xe/xe_gt_types.h | 5 | ||||
| -rw-r--r-- | drivers/gpu/drm/xe/xe_pci.c | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/xe/xe_pci_types.h | 1 |
4 files changed, 9 insertions, 0 deletions
diff --git a/drivers/gpu/drm/xe/xe_debugfs.c b/drivers/gpu/drm/xe/xe_debugfs.c index 0f8a96a05a8e..4fa423a82bea 100644 --- a/drivers/gpu/drm/xe/xe_debugfs.c +++ b/drivers/gpu/drm/xe/xe_debugfs.c @@ -93,6 +93,8 @@ static int info(struct seq_file *m, void *data) xe_force_wake_ref(gt_to_fw(gt), XE_FW_GT)); drm_printf(&p, "gt%d engine_mask 0x%llx\n", id, gt->info.engine_mask); + drm_printf(&p, "gt%d multi_queue_engine_class_mask 0x%x\n", id, + gt->info.multi_queue_engine_class_mask); } return 0; diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h index 0a728180b6fe..5318d92fd473 100644 --- a/drivers/gpu/drm/xe/xe_gt_types.h +++ b/drivers/gpu/drm/xe/xe_gt_types.h @@ -140,6 +140,11 @@ struct xe_gt { u64 engine_mask; /** @info.gmdid: raw GMD_ID value from hardware */ u32 gmdid; + /** + * @multi_queue_engine_class_mask: Bitmask of engine classes with + * multi queue support enabled. + */ + u16 multi_queue_engine_class_mask; /** @info.id: Unique ID of this GT within the PCI Device */ u8 id; /** @info.has_indirect_ring_state: GT has indirect ring state support */ diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c index c8188a5b0f76..16b3eb247439 100644 --- a/drivers/gpu/drm/xe/xe_pci.c +++ b/drivers/gpu/drm/xe/xe_pci.c @@ -764,6 +764,7 @@ static struct xe_gt *alloc_primary_gt(struct xe_tile *tile, gt->info.type = XE_GT_TYPE_MAIN; gt->info.id = tile->id * xe->info.max_gt_per_tile; gt->info.has_indirect_ring_state = graphics_desc->has_indirect_ring_state; + gt->info.multi_queue_engine_class_mask = graphics_desc->multi_queue_engine_class_mask; gt->info.engine_mask = graphics_desc->hw_engine_mask; /* diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h index f19f35359696..b06c108e25e6 100644 --- a/drivers/gpu/drm/xe/xe_pci_types.h +++ b/drivers/gpu/drm/xe/xe_pci_types.h @@ -60,6 +60,7 @@ struct xe_device_desc { struct xe_graphics_desc { u64 hw_engine_mask; /* hardware engines provided by graphics IP */ + u16 multi_queue_engine_class_mask; /* bitmask of engine classes which support multi queue */ u8 has_asid:1; u8 has_atomic_enable_pte_bit:1; |