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authorFangzhi Zuo <jerry.zuo@amd.com>2026-10-24 12:55:24 -0400
committerAlex Deucher <alexander.deucher@amd.com>2026-11-04 12:27:16 -0500
commitfa19199dc93ccf09ff5aaee7014f4596280911f8 (patch)
treea69c82a542de676b4cbd94f35013c61f1c78e5d4
parent4c5ec969b9b011e824f1850d7ffe4fa5c41ba890 (diff)
drm/edid: Parse HDMI 2.2 FRL rates from the SCDS
[Why] drm_get_max_frl_rate() only decodes Max_FRL_Rate values 1-6, so a sink advertising an HDMI 2.2 rate (7, 8 or 9) falls into the default case and is reported as having no FRL support at all. [How] Decode the HDMI 2.2 Max_FRL_Rate values 7, 8 and 9 as 16, 20 and 24 Gbps per lane over 4 lanes. Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit 12d5a58d5bd747da992a04da44cfcaf711c8fef9)
-rw-r--r--drivers/gpu/drm/drm_edid.c12
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 3148038747b6..b8f882a17c8f 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -6194,6 +6194,18 @@ void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane
*max_lanes = 4;
*max_rate_per_lane = 12;
break;
+ case 7:
+ *max_lanes = 4;
+ *max_rate_per_lane = 16;
+ break;
+ case 8:
+ *max_lanes = 4;
+ *max_rate_per_lane = 20;
+ break;
+ case 9:
+ *max_lanes = 4;
+ *max_rate_per_lane = 24;
+ break;
case 0:
default:
*max_lanes = 0;