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authorMukul Joshi <mukul.joshi@amd.com>2025-09-05 22:22:32 -0400
committerAlex Deucher <alexander.deucher@amd.com>2026-01-05 16:59:56 -0500
commitfab4099549a050703b87da012e5ebd75463bd654 (patch)
tree698d62ece0f14eb6b16cb3f2b53d2f467165ac17
parente418a8fdb9644712364eb582984eca0905664080 (diff)
drm/amdgpu: Disable TCP Early Write Ack for GFX 12.1
Disable the TCP Early Write Ack feature on GFX 12.1. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Alex Sierra <alex.sierra@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c12
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
index 1f567bd6cc46..7d4b241fc3a4 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
@@ -2657,6 +2657,17 @@ static void gfx_v12_1_xcc_disable_burst(struct amdgpu_device *adev,
WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGLARB_DRAM_BURST_CTRL, 0xf);
}
+static void gfx_v12_1_xcc_disable_early_write_ack(struct amdgpu_device *adev,
+ int xcc_id)
+{
+ uint32_t data;
+
+ data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_CNTL3);
+ data = REG_SET_FIELD(data, TCP_CNTL3, DISABLE_EARLY_WRITE_ACK, 0x1);
+
+ WREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_CNTL3, data);
+}
+
static void gfx_v12_1_init_golden_registers(struct amdgpu_device *adev)
{
int i;
@@ -2665,6 +2676,7 @@ static void gfx_v12_1_init_golden_registers(struct amdgpu_device *adev)
gfx_v12_1_xcc_disable_burst(adev, i);
gfx_v12_1_xcc_enable_atomics(adev, i);
gfx_v12_1_xcc_setup_tcp_thrashing_ctrl(adev, i);
+ gfx_v12_1_xcc_disable_early_write_ack(adev, i);
}
}