Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

Pull arm64 updates from Will Deacon:
 "There's a reasonable amount of stuff here, including a bunch of
  updates to the perf PMU drivers and some MPAM updates to expose the
  memory bandwidth counters via resctrl.

  On the architecture side, some highlights include support for BBML3
  and steps towards support for an architectural NMI solution, all
  wrapped up in a web of fixes for latent issues identified by Sashiko.

  ACPI:

   - Combine reads of AMU counters into a single FFH feedback counter op

  Confidential computing:

   - Fix smp_processor_id() in preemptible context when retrieving an
     attestation token inside a realm

   - Convert pKVM over to a "CC platform"

   - Clean-up our SWIOTLB configuration in preparation for reworking the
     handling of encrypted/decryped DMA buffers in the dma-mapping tree

  CPU errata handling:

   - Work around broken device memory ordering on NVIDIA Olympus cores

   - Fix broken 'nospectre_bhb' command-line option

   - Select the idle loop backend instruction on the command-line

  CPU features:

   - Replace our BBML2-noabort feature with the new architectural BBML3
     feature

   - Disable in-kernel BTI for recent versions of Clang due to issues
     with livepatch that are still being investigated

   - Clean-up documentation describing which ID register fields are
     exposed to userspace

  Interrupts:

   - Preliminary work towards supporting FEAT_NMI, which cleans up our
     IRQ entry code and fixes some latent issues with pseudo-NMI

   - Support for an SDEI backend to trigger an NMI backtrace

  Memory management:

   - Treat all devices as coherent when CLIDR_EL1.LoC == 0

   - Fix no-map handling of sub-page-sized regions

   - Second attempt at unmapping the linear aliases of the kernel data
     and bss sections

   - Fix EFI runtime calls when software-PAN is enabled

  Miscellaneous:

   - Add Mark Rutland as a reviewer!

   - Tidy-up our futex cmpxchg logic when using the new LSUI
     instructions

   - Drop the requirement on DYNAMIC_FTRACE_WITH_CALL_OPS when
     selecting HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS

   - Fix a false-positive KCSCAN splat in the delay loop

   - Use a portable typedef for 128-bit scalar types in our UAPI headers

   - Non-critical fixes for Sashiko reports all over

  MPAM:

   - Hook MPAM memory bandwidth counters into resctrl's counter
     assignment interface

   - Fix a quirk in the MPAM bandwidth counting on Nvidia T241 so that
     it also applies to 63 bit counters

  Perf:

   - Workarounds for hardware issues in the CMN-S3 PMU (Graviton 5) and
     CPU PMU (NVIDIA Olympus again!)

   - Add support for the DDR PMU on Marvell CN20K SoCs

   - Add support for Picoheart implementations of the DCW PCIe PMU

   - Add support for Channel/Rank/Bank filtering in the CXL PMU driver

   - Add support for 64-bit counters in the CSPMU device

   - Add support for revision 2 of the CMN S3 PMU

  Ptrace:

   - Fix a decade-old bug in our handling of seccomp and tracing on
     syscall entry

   - Fix regset handling for inactive SVE and SSVE registers

  Selftests

   - Add some tests for the decade-old bug that we just tried to fix in
     our syscall entry path

   - Fix SVE test crash on SME-only CPUs"

* tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (95 commits)
  arm64/efi: Avoid voluntary preemption with efi_mm installed
  arm64: bti: Disable in-kernel BTI with recent versions of Clang
  arm64: entry: Avoid unnecessary local_irq_disable() on kernel exit
  irqchip/gic-v3: make the unmasking of pseudo-NMIs explicit when handling IRQs
  arm64: Disable KCSAN instrumentation in delay.o
  arm_mpam: Disable driver unbind to avoid UAF
  arm_mpam: Fix a NULL pointer dereference on unbinding after an error interrupt
  perf: arm_pmuv3: Zero initialize hw_id branch stack field
  arm64: mm: Unmap kernel data/bss entirely from the linear map
  iommu/arm-smmu-v3-sva: Use system_supports_bbml3() to detect CPU feature
  perf/arm-cmn: Support CMN S3 r2
  perf/arm-cmn: Plumb in new filter types
  perf/arm-cmn: Refactor event filter data
  perf/arm-cmn: Refactor event filter programming
  perf/arm-cmn: Rename filter variables for clarity
  arm64: mm: fix accidental linear mapping of no-map reserved memory
  tools: Ensure tools copy of linux/filter.h exports the UAPI
  kselftest/arm64: Fix abi test compilation errors
  arch: arm64: add early_param idle=<wfi|yield|nop>
  arm64: entry: mask DAIF before returning from C EL1 handlers
  ...

3 files changed, 392 insertions, 229 deletions

diff --git a/Documentation/arch/arm64/cpu-feature-registers.rst b/Documentation/arch/arm64/cpu-feature-registers.rst
index add66afc7b03..f603afe323d6 100644
--- a/Documentation/arch/arm64/cpu-feature-registers.rst
+++ b/Documentation/arch/arm64/cpu-feature-registers.rst
@@ -113,240 +113,375 @@ infrastructure:
 4. List of registers with visible features
 -------------------------------------------
 
-  1) ID_AA64ISAR0_EL1 - Instruction Set Attribute Register 0
-
-     +------------------------------+---------+---------+
-     | Name                         |  bits   | visible |
-     +------------------------------+---------+---------+
-     | RNDR                         | [63-60] |    y    |
-     +------------------------------+---------+---------+
-     | TS                           | [55-52] |    y    |
-     +------------------------------+---------+---------+
-     | FHM                          | [51-48] |    y    |
-     +------------------------------+---------+---------+
-     | DP                           | [47-44] |    y    |
-     +------------------------------+---------+---------+
-     | SM4                          | [43-40] |    y    |
-     +------------------------------+---------+---------+
-     | SM3                          | [39-36] |    y    |
-     +------------------------------+---------+---------+
-     | SHA3                         | [35-32] |    y    |
-     +------------------------------+---------+---------+
-     | RDM                          | [31-28] |    y    |
-     +------------------------------+---------+---------+
-     | ATOMICS                      | [23-20] |    y    |
-     +------------------------------+---------+---------+
-     | CRC32                        | [19-16] |    y    |
-     +------------------------------+---------+---------+
-     | SHA2                         | [15-12] |    y    |
-     +------------------------------+---------+---------+
-     | SHA1                         | [11-8]  |    y    |
-     +------------------------------+---------+---------+
-     | AES                          | [7-4]   |    y    |
-     +------------------------------+---------+---------+
-
-
-  2) ID_AA64PFR0_EL1 - Processor Feature Register 0
-
-     +------------------------------+---------+---------+
-     | Name                         |  bits   | visible |
-     +------------------------------+---------+---------+
-     | DIT                          | [51-48] |    y    |
-     +------------------------------+---------+---------+
-     | MPAM                         | [43-40] |    n    |
-     +------------------------------+---------+---------+
-     | SVE                          | [35-32] |    y    |
-     +------------------------------+---------+---------+
-     | GIC                          | [27-24] |    n    |
-     +------------------------------+---------+---------+
-     | AdvSIMD                      | [23-20] |    y    |
-     +------------------------------+---------+---------+
-     | FP                           | [19-16] |    y    |
-     +------------------------------+---------+---------+
-     | EL3                          | [15-12] |    n    |
-     +------------------------------+---------+---------+
-     | EL2                          | [11-8]  |    n    |
-     +------------------------------+---------+---------+
-     | EL1                          | [7-4]   |    n    |
-     +------------------------------+---------+---------+
-     | EL0                          | [3-0]   |    n    |
-     +------------------------------+---------+---------+
-
-
-  3) ID_AA64PFR1_EL1 - Processor Feature Register 1
-
-     +------------------------------+---------+---------+
-     | Name                         |  bits   | visible |
-     +------------------------------+---------+---------+
-     | SME                          | [27-24] |    y    |
-     +------------------------------+---------+---------+
-     | MTE                          | [11-8]  |    y    |
-     +------------------------------+---------+---------+
-     | SSBS                         | [7-4]   |    y    |
-     +------------------------------+---------+---------+
-     | BT                           | [3-0]   |    y    |
-     +------------------------------+---------+---------+
-
-
-  4) MIDR_EL1 - Main ID Register
-
-     +------------------------------+---------+---------+
-     | Name                         |  bits   | visible |
-     +------------------------------+---------+---------+
-     | Implementer                  | [31-24] |    y    |
-     +------------------------------+---------+---------+
-     | Variant                      | [23-20] |    y    |
-     +------------------------------+---------+---------+
-     | Architecture                 | [19-16] |    y    |
-     +------------------------------+---------+---------+
-     | PartNum                      | [15-4]  |    y    |
-     +------------------------------+---------+---------+
-     | Revision                     | [3-0]   |    y    |
-     +------------------------------+---------+---------+
+  ID_AA64FPFR0_EL1 - Floating Point feature ID register 0
+
+     +------------------------------+---------+
+     | Name                         |  bits   |
+     +------------------------------+---------+
+     | F8CVT                        | [31]    |
+     +------------------------------+---------+
+     | F8FMA                        | [30]    |
+     +------------------------------+---------+
+     | F8DP4                        | [29]    |
+     +------------------------------+---------+
+     | F8DP2                        | [28]    |
+     +------------------------------+---------+
+     | F8MM8                        | [27]    |
+     +------------------------------+---------+
+     | F8MM4                        | [26]    |
+     +------------------------------+---------+
+     | F16MM2                       | [15]    |
+     +------------------------------+---------+
+     | F8E4M3                       | [1]     |
+     +------------------------------+---------+
+     | F8E5M2                       | [0]     |
+     +------------------------------+---------+
+
+  ID_AA64ISAR0_EL1 - Instruction Set Attribute Register 0
+
+     +------------------------------+---------+
+     | Name                         |  bits   |
+     +------------------------------+---------+
+     | RNDR                         | [63-60] |
+     +------------------------------+---------+
+     | TS                           | [55-52] |
+     +------------------------------+---------+
+     | FHM                          | [51-48] |
+     +------------------------------+---------+
+     | DP                           | [47-44] |
+     +------------------------------+---------+
+     | SM4                          | [43-40] |
+     +------------------------------+---------+
+     | SM3                          | [39-36] |
+     +------------------------------+---------+
+     | SHA3                         | [35-32] |
+     +------------------------------+---------+
+     | RDM                          | [31-28] |
+     +------------------------------+---------+
+     | ATOMICS                      | [23-20] |
+     +------------------------------+---------+
+     | CRC32                        | [19-16] |
+     +------------------------------+---------+
+     | SHA2                         | [15-12] |
+     +------------------------------+---------+
+     | SHA1                         | [11-8]  |
+     +------------------------------+---------+
+     | AES                          | [7-4]   |
+     +------------------------------+---------+
+
+
+  ID_AA64ISAR1_EL1 - Instruction set attribute register 1
+
+     +------------------------------+---------+
+     | Name                         |  bits   |
+     +------------------------------+---------+
+     | LS64                         | [63-60] |
+     +------------------------------+---------+
+     | I8MM                         | [55-52] |
+     +------------------------------+---------+
+     | DGH                          | [51-48] |
+     +------------------------------+---------+
+     | BF16                         | [47-44] |
+     +------------------------------+---------+
+     | SB                           | [39-36] |
+     +------------------------------+---------+
+     | FRINTTS                      | [35-32] |
+     +------------------------------+---------+
+     | GPI                          | [31-28] |
+     +------------------------------+---------+
+     | GPA                          | [27-24] |
+     +------------------------------+---------+
+     | LRCPC                        | [23-20] |
+     +------------------------------+---------+
+     | FCMA                         | [19-16] |
+     +------------------------------+---------+
+     | JSCVT                        | [15-12] |
+     +------------------------------+---------+
+     | API                          | [11-8]  |
+     +------------------------------+---------+
+     | APA                          | [7-4]   |
+     +------------------------------+---------+
+     | DPB                          | [3-0]   |
+     +------------------------------+---------+
+
+  ID_AA64ISAR2_EL1 - Instruction set attribute register 2
+
+     +------------------------------+---------+
+     | Name                         |  bits   |
+     +------------------------------+---------+
+     | LUT                          | [59-56] |
+     +------------------------------+---------+
+     | CSSC                         | [55-52] |
+     +------------------------------+---------+
+     | RPRFM                        | [51-48] |
+     +------------------------------+---------+
+     | BC                           | [23-20] |
+     +------------------------------+---------+
+     | MOPS                         | [19-16] |
+     +------------------------------+---------+
+     | APA3                         | [15-12] |
+     +------------------------------+---------+
+     | GPA3                         | [11-8]  |
+     +------------------------------+---------+
+     | RPRES                        | [7-4]   |
+     +------------------------------+---------+
+     | WFXT                         | [3-0]   |
+     +------------------------------+---------+
+
+  ID_AA64ISAR3_EL1 - Instruction set attribute register 3
+
+     +------------------------------+---------+
+     | Name                         |  bits   |
+     +------------------------------+---------+
+     | FPRCVT                       | [31-28] |
+     +------------------------------+---------+
+     | LSFE                         | [19-16] |
+     +------------------------------+---------+
+     | FAMINMAX                     | [7-4]   |
+     +------------------------------+---------+
+
+  ID_AA64MMFR0_EL1 - Memory model feature register 0
+
+     +------------------------------+---------+
+     | Name                         |  bits   |
+     +------------------------------+---------+
+     | ECV                          | [63-60] |
+     +------------------------------+---------+
+
+  ID_AA64MMFR1_EL1 - Memory model feature register 1
+
+     +------------------------------+---------+
+     | Name                         |  bits   |
+     +------------------------------+---------+
+     | AFP                          | [47-44] |
+     +------------------------------+---------+
+
+  ID_AA64MMFR2_EL1 - Memory model feature register 2
+
+     +------------------------------+---------+
+     | Name                         |  bits   |
+     +------------------------------+---------+
+     | AT                           | [35-32] |
+     +------------------------------+---------+
+
+  ID_AA64MMFR3_EL1 - Memory model feature register 3
+
+     +------------------------------+---------+
+     | Name                         |  bits   |
+     +------------------------------+---------+
+     | S1POE                        | [19-16] |
+     +------------------------------+---------+
+
+  ID_AA64PFR0_EL1 - Processor Feature Register 0
+
+     +------------------------------+---------+
+     | Name                         |  bits   |
+     +------------------------------+---------+
+     | DIT                          | [51-48] |
+     +------------------------------+---------+
+     | SVE                          | [35-32] |
+     +------------------------------+---------+
+     | AdvSIMD                      | [23-20] |
+     +------------------------------+---------+
+     | FP                           | [19-16] |
+     +------------------------------+---------+
+
+
+  ID_AA64PFR1_EL1 - Processor Feature Register 1
+
+     +------------------------------+---------+
+     | Name                         |  bits   |
+     +------------------------------+---------+
+     | GCS                          | [47-44] |
+     +------------------------------+---------+
+     | SME                          | [27-24] |
+     +------------------------------+---------+
+     | MTE                          | [11-8]  |
+     +------------------------------+---------+
+     | SSBS                         | [7-4]   |
+     +------------------------------+---------+
+     | BT                           | [3-0]   |
+     +------------------------------+---------+
+
+  ID_AA64PFR2_EL1 - Processor Feature Register 2
+
+     +------------------------------+---------+
+     | Name                         |  bits   |
+     +------------------------------+---------+
+     | FPMR                         | [35-32] |
+     +------------------------------+---------+
+     | MTEFAR                       | [11-8]  |
+     +------------------------------+---------+
+     | MTESTOREONLY                 | [7-4]   |
+     +------------------------------+---------+
+
+  ID_AA64SMFR0_EL1 - SME feature ID register 0
+
+     +------------------------------+---------+
+     | Name                         |  bits   |
+     +------------------------------+---------+
+     | FA64                         | [63]    |
+     +------------------------------+---------+
+     | LUT6                         | [61]    |
+     +------------------------------+---------+
+     | LUTv2                        | [60]    |
+     +------------------------------+---------+
+     | SMEver                       | [59-56] |
+     +------------------------------+---------+
+     | I16I64                       | [55-52] |
+     +------------------------------+---------+
+     | F64F64                       | [48]    |
+     +------------------------------+---------+
+     | I16I32                       | [47-44] |
+     +------------------------------+---------+
+     | B16B16                       | [43]    |
+     +------------------------------+---------+
+     | F16F16                       | [42]    |
+     +------------------------------+---------+
+     | F8F16                        | [41]    |
+     +------------------------------+---------+
+     | F8F32                        | [40]    |
+     +------------------------------+---------+
+     | I8I32                        | [39-36] |
+     +------------------------------+---------+
+     | F16F32                       | [35]    |
+     +------------------------------+---------+
+     | B16F32                       | [34]    |
+     +------------------------------+---------+
+     | BI32I32                      | [33]    |
+     +------------------------------+---------+
+     | F32F32                       | [32]    |
+     +------------------------------+---------+
+     | SF8FMA                       | [30]    |
+     +------------------------------+---------+
+     | SF8DP4                       | [29]    |
+     +------------------------------+---------+
+     | SF8DP2                       | [28]    |
+     +------------------------------+---------+
+     | SBitPerm                     | [25]    |
+     +------------------------------+---------+
+     | AES                          | [24]    |
+     +------------------------------+---------+
+     | SFEXPA                       | [23]    |
+     +------------------------------+---------+
+     | STMOP                        | [16]    |
+     +------------------------------+---------+
+     | SMOP4                        | [0]     |
+     +------------------------------+---------+
+
+  ID_AA64ZFR0_EL1 - SVE feature ID register 0
+
+     +------------------------------+---------+
+     | Name                         |  bits   |
+     +------------------------------+---------+
+     | F64MM                        | [59-56] |
+     +------------------------------+---------+
+     | F32MM                        | [55-52] |
+     +------------------------------+---------+
+     | F16MM                        | [51-48] |
+     +------------------------------+---------+
+     | I8MM                         | [47-44] |
+     +------------------------------+---------+
+     | SM4                          | [43-40] |
+     +------------------------------+---------+
+     | SHA3                         | [35-32] |
+     +------------------------------+---------+
+     | B16B16                       | [27-24] |
+     +------------------------------+---------+
+     | BF16                         | [23-20] |
+     +------------------------------+---------+
+     | BitPerm                      | [19-16] |
+     +------------------------------+---------+
+     | EltPerm                      | [15-12] |
+     +------------------------------+---------+
+     | AES                          | [7-4]   |
+     +------------------------------+---------+
+     | SVEVer                       | [3-0]   |
+     +------------------------------+---------+
+
+  ID_ISAR5_EL1 - AArch32 Instruction Set Attribute Register 5
+
+     +------------------------------+---------+
+     | Name                         |  bits   |
+     +------------------------------+---------+
+     | CRC32                        | [19-16] |
+     +------------------------------+---------+
+     | SHA2                         | [15-12] |
+     +------------------------------+---------+
+     | SHA1                         | [11-8]  |
+     +------------------------------+---------+
+     | AES                          | [7-4]   |
+     +------------------------------+---------+
+
+  ID_ISAR6_EL1 - AArch32 Instruction Set Attribute Register 6
+
+     +------------------------------+---------+
+     | Name                         |  bits   |
+     +------------------------------+---------+
+     | I8MM                         | [27-24] |
+     +------------------------------+---------+
+     | BF16                         | [23-20] |
+     +------------------------------+---------+
+     | SB                           | [15-12] |
+     +------------------------------+---------+
+     | FHM                          | [11-8]  |
+     +------------------------------+---------+
+     | DP                           | [7-4]   |
+     +------------------------------+---------+
+
+  ID_PFR2_EL1 - AArch32 Processor Feature Register 2
+
+     +------------------------------+---------+
+     | Name                         |  bits   |
+     +------------------------------+---------+
+     | SSBS                         | [7-4]   |
+     +------------------------------+---------+
+
+  MIDR_EL1 - Main ID Register
+
+     +------------------------------+---------+
+     | Name                         |  bits   |
+     +------------------------------+---------+
+     | Implementer                  | [31-24] |
+     +------------------------------+---------+
+     | Variant                      | [23-20] |
+     +------------------------------+---------+
+     | Architecture                 | [19-16] |
+     +------------------------------+---------+
+     | PartNum                      | [15-4]  |
+     +------------------------------+---------+
+     | Revision                     | [3-0]   |
+     +------------------------------+---------+
 
    NOTE: The 'visible' fields of MIDR_EL1 will contain the value
    as available on the CPU where it is fetched and is not a system
    wide safe value.
 
-  5) ID_AA64ISAR1_EL1 - Instruction set attribute register 1
-
-     +------------------------------+---------+---------+
-     | Name                         |  bits   | visible |
-     +------------------------------+---------+---------+
-     | I8MM                         | [55-52] |    y    |
-     +------------------------------+---------+---------+
-     | DGH                          | [51-48] |    y    |
-     +------------------------------+---------+---------+
-     | BF16                         | [47-44] |    y    |
-     +------------------------------+---------+---------+
-     | SB                           | [39-36] |    y    |
-     +------------------------------+---------+---------+
-     | FRINTTS                      | [35-32] |    y    |
-     +------------------------------+---------+---------+
-     | GPI                          | [31-28] |    y    |
-     +------------------------------+---------+---------+
-     | GPA                          | [27-24] |    y    |
-     +------------------------------+---------+---------+
-     | LRCPC                        | [23-20] |    y    |
-     +------------------------------+---------+---------+
-     | FCMA                         | [19-16] |    y    |
-     +------------------------------+---------+---------+
-     | JSCVT                        | [15-12] |    y    |
-     +------------------------------+---------+---------+
-     | API                          | [11-8]  |    y    |
-     +------------------------------+---------+---------+
-     | APA                          | [7-4]   |    y    |
-     +------------------------------+---------+---------+
-     | DPB                          | [3-0]   |    y    |
-     +------------------------------+---------+---------+
-
-  6) ID_AA64MMFR0_EL1 - Memory model feature register 0
-
-     +------------------------------+---------+---------+
-     | Name                         |  bits   | visible |
-     +------------------------------+---------+---------+
-     | ECV                          | [63-60] |    y    |
-     +------------------------------+---------+---------+
-
-  7) ID_AA64MMFR2_EL1 - Memory model feature register 2
-
-     +------------------------------+---------+---------+
-     | Name                         |  bits   | visible |
-     +------------------------------+---------+---------+
-     | AT                           | [35-32] |    y    |
-     +------------------------------+---------+---------+
-
-  8) ID_AA64ZFR0_EL1 - SVE feature ID register 0
-
-     +------------------------------+---------+---------+
-     | Name                         |  bits   | visible |
-     +------------------------------+---------+---------+
-     | F64MM                        | [59-56] |    y    |
-     +------------------------------+---------+---------+
-     | F32MM                        | [55-52] |    y    |
-     +------------------------------+---------+---------+
-     | I8MM                         | [47-44] |    y    |
-     +------------------------------+---------+---------+
-     | SM4                          | [43-40] |    y    |
-     +------------------------------+---------+---------+
-     | SHA3                         | [35-32] |    y    |
-     +------------------------------+---------+---------+
-     | B16B16                       | [27-24] |    y    |
-     +------------------------------+---------+---------+
-     | BF16                         | [23-20] |    y    |
-     +------------------------------+---------+---------+
-     | BitPerm                      | [19-16] |    y    |
-     +------------------------------+---------+---------+
-     | AES                          | [7-4]   |    y    |
-     +------------------------------+---------+---------+
-     | SVEVer                       | [3-0]   |    y    |
-     +------------------------------+---------+---------+
-
-  8) ID_AA64MMFR1_EL1 - Memory model feature register 1
-
-     +------------------------------+---------+---------+
-     | Name                         |  bits   | visible |
-     +------------------------------+---------+---------+
-     | AFP                          | [47-44] |    y    |
-     +------------------------------+---------+---------+
-
-  9) ID_AA64ISAR2_EL1 - Instruction set attribute register 2
-
-     +------------------------------+---------+---------+
-     | Name                         |  bits   | visible |
-     +------------------------------+---------+---------+
-     | CSSC                         | [55-52] |    y    |
-     +------------------------------+---------+---------+
-     | RPRFM                        | [51-48] |    y    |
-     +------------------------------+---------+---------+
-     | BC                           | [23-20] |    y    |
-     +------------------------------+---------+---------+
-     | MOPS                         | [19-16] |    y    |
-     +------------------------------+---------+---------+
-     | APA3                         | [15-12] |    y    |
-     +------------------------------+---------+---------+
-     | GPA3                         | [11-8]  |    y    |
-     +------------------------------+---------+---------+
-     | RPRES                        | [7-4]   |    y    |
-     +------------------------------+---------+---------+
-     | WFXT                         | [3-0]   |    y    |
-     +------------------------------+---------+---------+
-
-  10) MVFR0_EL1 - AArch32 Media and VFP Feature Register 0
-
-     +------------------------------+---------+---------+
-     | Name                         |  bits   | visible |
-     +------------------------------+---------+---------+
-     | FPDP                         | [11-8]  |    y    |
-     +------------------------------+---------+---------+
-
-  11) MVFR1_EL1 - AArch32 Media and VFP Feature Register 1
-
-     +------------------------------+---------+---------+
-     | Name                         |  bits   | visible |
-     +------------------------------+---------+---------+
-     | SIMDFMAC                     | [31-28] |    y    |
-     +------------------------------+---------+---------+
-     | SIMDSP                       | [19-16] |    y    |
-     +------------------------------+---------+---------+
-     | SIMDInt                      | [15-12] |    y    |
-     +------------------------------+---------+---------+
-     | SIMDLS                       | [11-8]  |    y    |
-     +------------------------------+---------+---------+
-
-  12) ID_ISAR5_EL1 - AArch32 Instruction Set Attribute Register 5
-
-     +------------------------------+---------+---------+
-     | Name                         |  bits   | visible |
-     +------------------------------+---------+---------+
-     | CRC32                        | [19-16] |    y    |
-     +------------------------------+---------+---------+
-     | SHA2                         | [15-12] |    y    |
-     +------------------------------+---------+---------+
-     | SHA1                         | [11-8]  |    y    |
-     +------------------------------+---------+---------+
-     | AES                          | [7-4]   |    y    |
-     +------------------------------+---------+---------+
+  MVFR0_EL1 - AArch32 Media and VFP Feature Register 0
+
+     +------------------------------+---------+
+     | Name                         |  bits   |
+     +------------------------------+---------+
+     | FPDP                         | [11-8]  |
+     +------------------------------+---------+
+
+  MVFR1_EL1 - AArch32 Media and VFP Feature Register 1
+
+     +------------------------------+---------+
+     | Name                         |  bits   |
+     +------------------------------+---------+
+     | SIMDFMAC                     | [31-28] |
+     +------------------------------+---------+
+     | FPHP                         | [27-24] |
+     +------------------------------+---------+
+     | SIMDHP                       | [23-20] |
+     +------------------------------+---------+
+     | SIMDSP                       | [19-16] |
+     +------------------------------+---------+
+     | SIMDInt                      | [15-12] |
+     +------------------------------+---------+
+     | SIMDLS                       | [11-8]  |
+     +------------------------------+---------+
 
 
 Appendix I: Example
diff --git a/Documentation/arch/arm64/mpam.rst b/Documentation/arch/arm64/mpam.rst
index 570f51a8d4eb..67fe515ed501 100644
--- a/Documentation/arch/arm64/mpam.rst
+++ b/Documentation/arch/arm64/mpam.rst
@@ -65,6 +65,28 @@ The supported features are:
   there is at least one CSU monitor on each MSC that makes up the L3 group.
   Exposing CSU counters from other caches or devices is not supported.
 
+* Memory Bandwidth Usage (MBWU) on or after the L3 cache.  resctrl uses the
+  L3 cache-id to identify where the memory bandwidth is measured. For this
+  reason the platform must have an L3 cache with cache-id's supplied by
+  firmware. (The platform doesn't need to support MPAM.)
+
+  Memory bandwidth monitoring makes use of MBWU monitors in each MSC that
+  makes up the L3 group. If the memory bandwidth monitoring is on the memory
+  rather than the L3 then there must be a single global L3 as otherwise it
+  is unknown which L3 the traffic came from.
+
+  To expose 'mbm_total_bytes', the topology of the group of MSC chosen must
+  match the topology of the L3 cache so that the cache-id's can be
+  repainted. For example: Platforms with Memory bandwidth monitors on
+  CPU-less NUMA nodes cannot expose 'mbm_total_bytes' as these nodes do not
+  have a corresponding L3 cache. 'mbm_local_bytes' is not exposed as MPAM
+  cannot distinguish local traffic from global traffic.
+
+  All these restrictions based on L3 cache are due to resctrl, currently, only
+  supporting monitoring at the L3 scope. It is expected that going forward more
+  MBWU monitors can be exposed to the user after support for more monitoring
+  scopes is added to resctrl.
+
 Reporting Bugs
 ==============
 If you are not seeing the counters or controls you expect please share the
diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst
index 88b4aa45a206..68acd6555661 100644
--- a/Documentation/arch/arm64/silicon-errata.rst
+++ b/Documentation/arch/arm64/silicon-errata.rst
@@ -246,10 +246,14 @@ stable kernels.
 +----------------+-----------------+-----------------+-----------------------------+
 | ARM            | Neoverse-V3AE   | #4193784        | ARM64_ERRATUM_4118414       |
 +----------------+-----------------+-----------------+-----------------------------+
+| ARM            | C1-Premium      | #3683289        | N/A                         |
++----------------+-----------------+-----------------+-----------------------------+
 | ARM            | C1-Premium      | #4193780        | ARM64_ERRATUM_4118414       |
 +----------------+-----------------+-----------------+-----------------------------+
 | ARM            | C1-Pro          | #4193714        | ARM64_ERRATUM_4193714       |
 +----------------+-----------------+-----------------+-----------------------------+
+| ARM            | C1-Ultra        | #3683289        | N/A                         |
++----------------+-----------------+-----------------+-----------------------------+
 | ARM            | C1-Ultra        | #4193780        | ARM64_ERRATUM_4118414       |
 +----------------+-----------------+-----------------+-----------------------------+
 | ARM            | MMU-500         | #562869,        | ARM_SMMU_MMU_500_CPRE_ERRATA|
@@ -308,6 +312,8 @@ stable kernels.
 +----------------+-----------------+-----------------+-----------------------------+
 | NVIDIA         | Carmel Core     | N/A             | NVIDIA_CARMEL_CNP_ERRATUM   |
 +----------------+-----------------+-----------------+-----------------------------+
+| NVIDIA         | Olympus core    | T410-OLY-1027   | NVIDIA_OLYMPUS_1027_ERRATUM |
++----------------+-----------------+-----------------+-----------------------------+
 | NVIDIA         | Olympus core    | T410-OLY-1029   | ARM64_ERRATUM_4118414       |
 +----------------+-----------------+-----------------+-----------------------------+
 | NVIDIA         | T241 GICv3/4.x  | T241-FABRIC-4   | N/A                         |