diff options
| author | James Clark <james.clark@linaro.org> | 2025-09-01 13:40:35 +0100 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2025-09-18 14:17:02 +0100 |
| commit | 00d7a1af5ab58d89c2f0af27485b2d710c862dfc (patch) | |
| tree | 4e16db1e1f19b9a0bcc49a5553c9962d38abe4ed /Documentation/arch | |
| parent | 510a8fa49dc1d18b120e2d3992fa2aff7fc5c46b (diff) | |
arm64/boot: Enable EL2 requirements for SPE_FEAT_FDS
SPE data source filtering (optional from Armv8.8) requires that traps to
the filter register PMSDSFR be disabled. Document the requirements and
disable the traps if the feature is present.
Tested-by: Leo Yan <leo.yan@arm.com>
Reviewed-by: Leo Yan <leo.yan@arm.com>
Signed-off-by: James Clark <james.clark@linaro.org>
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'Documentation/arch')
| -rw-r--r-- | Documentation/arch/arm64/booting.rst | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/Documentation/arch/arm64/booting.rst b/Documentation/arch/arm64/booting.rst index 2f666a7c303c..e4f953839f71 100644 --- a/Documentation/arch/arm64/booting.rst +++ b/Documentation/arch/arm64/booting.rst @@ -466,6 +466,17 @@ Before jumping into the kernel, the following conditions must be met: - HDFGWTR2_EL2.nPMICFILTR_EL0 (bit 3) must be initialised to 0b1. - HDFGWTR2_EL2.nPMUACR_EL1 (bit 4) must be initialised to 0b1. + For CPUs with SPE data source filtering (FEAT_SPE_FDS): + + - If EL3 is present: + + - MDCR_EL3.EnPMS3 (bit 42) must be initialised to 0b1. + + - If the kernel is entered at EL1 and EL2 is present: + + - HDFGRTR2_EL2.nPMSDSFR_EL1 (bit 19) must be initialised to 0b1. + - HDFGWTR2_EL2.nPMSDSFR_EL1 (bit 19) must be initialised to 0b1. + For CPUs with Memory Copy and Memory Set instructions (FEAT_MOPS): - If the kernel is entered at EL1 and EL2 is present: |