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authorJian Hu <jian.hu@amlogic.com>2025-12-12 10:26:14 +0800
committerJerome Brunet <jbrunet@baylibre.com>2025-12-15 10:42:28 +0100
commit5437753728ac40a0410f3a4c6c471d0ab9919ceb (patch)
treeb8b4fff119682ee297fdb1500f50c6ed359b84b0 /Documentation/devicetree/bindings/clock
parent8f0b4cce4481fb22653697cced8d0d04027cb1e8 (diff)
dt-bindings: clock: add Amlogic T7 PLL clock controller
Add DT bindings for the PLL clock controller of the Amlogic T7 SoC family. Signed-off-by: Jian Hu <jian.hu@amlogic.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20251212022619.3072132-2-jian.hu@amlogic.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'Documentation/devicetree/bindings/clock')
-rw-r--r--Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml114
1 files changed, 114 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml
new file mode 100644
index 000000000000..49c61f65deff
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml
@@ -0,0 +1,114 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/amlogic,t7-pll-clkc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amlogic T7 PLL Clock Control Controller
+
+maintainers:
+ - Neil Armstrong <neil.armstrong@linaro.org>
+ - Jerome Brunet <jbrunet@baylibre.com>
+ - Jian Hu <jian.hu@amlogic.com>
+ - Xianwei Zhao <xianwei.zhao@amlogic.com>
+
+properties:
+ compatible:
+ enum:
+ - amlogic,t7-gp0-pll
+ - amlogic,t7-gp1-pll
+ - amlogic,t7-hifi-pll
+ - amlogic,t7-pcie-pll
+ - amlogic,t7-mpll
+ - amlogic,t7-hdmi-pll
+ - amlogic,t7-mclk-pll
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+ clocks:
+ items:
+ - description: mclk pll input oscillator gate
+ - description: oscillator input clock source for mclk_sel_0
+ - description: fixed input clock source for mclk_sel_0
+ minItems: 1
+
+ clock-names:
+ items:
+ - const: in0
+ - const: in1
+ - const: in2
+ minItems: 1
+
+required:
+ - compatible
+ - '#clock-cells'
+ - reg
+ - clocks
+ - clock-names
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: amlogic,t7-mclk-pll
+
+ then:
+ properties:
+ clocks:
+ minItems: 3
+
+ clock-names:
+ minItems: 3
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - amlogic,t7-gp0-pll
+ - amlogic,t7-gp1--pll
+ - amlogic,t7-hifi-pll
+ - amlogic,t7-pcie-pll
+ - amlogic,t7-mpll
+ - amlogic,t7-hdmi-pll
+
+ then:
+ properties:
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ maxItems: 1
+
+additionalProperties: false
+
+examples:
+ - |
+ apb {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clock-controller@8080 {
+ compatible = "amlogic,t7-gp0-pll";
+ reg = <0 0x8080 0 0x20>;
+ clocks = <&scmi_clk 2>;
+ clock-names = "in0";
+ #clock-cells = <1>;
+ };
+
+ clock-controller@8300 {
+ compatible = "amlogic,t7-mclk-pll";
+ reg = <0 0x8300 0 0x18>;
+ clocks = <&scmi_clk 2>,
+ <&xtal>,
+ <&scmi_clk 31>;
+ clock-names = "in0", "in1", "in2";
+ #clock-cells = <1>;
+ };
+ };