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authorPierre-Henry Moussay <pierre-henry.moussay@microchip.com>2026-01-13 22:11:46 +0000
committerClaudiu Beznea <claudiu.beznea@tuxon.dev>2026-01-16 08:48:38 +0200
commite6584bda8d4584a58f020b559617ae7cfde51644 (patch)
tree93b648fa9a3560b6162c78319487e554f2ba4883 /Documentation/devicetree/bindings/clock
parentdfb208b9aebb32dece9ceddfecf84b35a876fbd3 (diff)
dt-bindings: clock: mpfs-ccc: Add pic64gx compatibility
pic64gx SoC Clock Conditioning Circuitry is compatibles with the Polarfire SoC Signed-off-by: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20260113-guise-conceded-88030697b831@spud Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Diffstat (limited to 'Documentation/devicetree/bindings/clock')
-rw-r--r--Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml6
1 files changed, 5 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml b/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml
index f1770360798f..9a6b50527c42 100644
--- a/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml
+++ b/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml
@@ -17,7 +17,11 @@ description: |
properties:
compatible:
- const: microchip,mpfs-ccc
+ oneOf:
+ - items:
+ - const: microchip,pic64gx-ccc
+ - const: microchip,mpfs-ccc
+ - const: microchip,mpfs-ccc
reg:
items: