diff options
| author | Fancy Fang <chen.fang@nxp.com> | 2019-03-15 12:09:58 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 15:59:55 +0800 |
| commit | a087a95aa2ce963e64b8f36c267b011ebe8cd842 (patch) | |
| tree | dcf5bf23a100a03443d4d4c593afeb0088d8daa1 /Documentation/devicetree/bindings/display | |
| parent | 688f619a41cb0bf2e25a35610f6777911eb29d73 (diff) | |
MLK-21150-3 drm/bridge: sec-dsim: add a new property 'pref-rate'
Add a new property 'pref-rate' support which can be used to
assign a different clock frequency for the DPHY PLL reference
clock in the dtb file. And if this property does not exist,
the default clock frequency for the reference clock will be
used. And according to the spec, the DPHY PLL reference clk
frequency should be in [6MHz, 300MHz] range.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Diffstat (limited to 'Documentation/devicetree/bindings/display')
| -rw-r--r-- | Documentation/devicetree/bindings/display/bridge/sec_dsim.txt | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/display/bridge/sec_dsim.txt b/Documentation/devicetree/bindings/display/bridge/sec_dsim.txt index 9bc5e9dd2539..fd4246136d37 100644 --- a/Documentation/devicetree/bindings/display/bridge/sec_dsim.txt +++ b/Documentation/devicetree/bindings/display/bridge/sec_dsim.txt @@ -16,6 +16,9 @@ Required properties: "pll-ref" - DSIM PHY PLL reference clock - assigned-clocks: phandles to clocks that requires initial configuration - assigned-clock-rates: rates of the clocks that requires initial configuration +- pref-clk: Assign DPHY PLL reference clock frequency. If not exists, + DSIM bridge driver will use the default lock frequency + which is 27MHz. - port: input and output port nodes with endpoint definitions as defined in Documentation/devicetree/bindings/graph.txt; the input port should be connected to an encoder or a |