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| author | Miquel Raynal <miquel.raynal@bootlin.com> | 2021-06-10 10:20:23 +0200 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> | 2021-06-10 17:14:35 +0200 |
| commit | a70eb9165e2a0f2867f0eb78f12665893d135ee1 (patch) | |
| tree | 7198ff9c2d83ea1560b5371ffa470bede2958e7f /Documentation/devicetree/bindings/memory-controllers | |
| parent | 6efb943b8616ec53a5e444193dccf1af9ad627b5 (diff) | |
dt-binding: memory: pl353-smc: Rephrase the binding
Reword this document before converting it to yaml.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210610082040.2075611-2-miquel.raynal@bootlin.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Diffstat (limited to 'Documentation/devicetree/bindings/memory-controllers')
| -rw-r--r-- | Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt b/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt index d56615fd343a..f0b7fe173668 100644 --- a/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt @@ -1,8 +1,7 @@ Device tree bindings for ARM PL353 static memory controller -PL353 static memory controller supports two kinds of memory -interfaces.i.e NAND and SRAM/NOR interfaces. -The actual devices are instantiated from the child nodes of pl353 smc node. +PL353 Static Memory Controller is a bus where you can connect two kinds +of memory interfaces: NAND and memory mapped interfaces (such as SRAM or NOR). Required properties: - compatible : Should be "arm,pl353-smc-r2p1", "arm,primecell". @@ -13,9 +12,9 @@ Required properties: - address-cells : Must be 2. - size-cells : Must be 1. -Child nodes: - For NAND the "arm,pl353-nand-r2p1" and for NOR the "cfi-flash" drivers are -supported as child nodes. +The child device node represents the controller connected to the SMC +bus. Only one between: NAND controller, NOR controller and SRAM controller +is allowed in a single system. for NAND partition information please refer the below file Documentation/devicetree/bindings/mtd/partition.txt |