diff options
| author | Hou Zhiqiang <Zhiqiang.Hou@nxp.com> | 2020-08-28 11:12:54 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2021-11-02 17:05:21 +0800 |
| commit | 241a373797283531a55c1f514514cacb3a0205b3 (patch) | |
| tree | 1f112ed7ff65f0ea5c98f712c61fc16c823ad73b /Documentation/devicetree/bindings/pci | |
| parent | 6d0d10f1bee40c4288c914c669e6fb96c31bd97f (diff) | |
dt-bindings: pci: layerscape-pci: Update the description of SCFG property
Update the description of the second entry of 'fsl,pcie-scfg' property,
as the LS1043A PCIe controller also has some control registers in SCFG
block, while it has 3 controllers.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Diffstat (limited to 'Documentation/devicetree/bindings/pci')
| -rw-r--r-- | Documentation/devicetree/bindings/pci/layerscape-pci.txt | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index 4614ce591ae5..56e22df79bf3 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -35,7 +35,7 @@ Required properties: "intr": The interrupt that is asserted for controller interrupts - fsl,pcie-scfg: Must include two entries. The first entry must be a link to the SCFG device node - The second entry must be '0' or '1' based on physical PCIe controller index. + The second entry is the physical PCIe controller index starting from '0'. This is used to get SCFG PEXN registers - dma-coherent: Indicates that the hardware IP block can ensure the coherency of the data transferred from/to the IP block. This can avoid the software |