diff options
| author | Dong Aisheng <aisheng.dong@nxp.com> | 2021-11-30 14:59:53 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2021-11-30 14:59:53 +0800 |
| commit | 841bf366158fe120f871c8e919251deabf8c4f05 (patch) | |
| tree | 01edab7ca14780bbd9fc383697e3a61fb7384360 /Documentation/devicetree/bindings/pci | |
| parent | 5865329eb17c89b85d689179ec233e0215a92548 (diff) | |
| parent | 7440a2ee26be4df0e6754445031386f389103e2f (diff) | |
Merge remote-tracking branch 'origin/pcie/dwc' into pcie/next
* origin/pcie/dwc: (49 commits)
PCI: layerscape: Add controller setup in resume routine
LF-4747 PCI: imx6: fix the spell mistake when enable ep mode
LF-4336-2 PCI: imx: to solve the compatible issue do perst properly
LF-4336-1 Revert "LF-4081 PCI: imx: wait specified minimum period following the end of a reset"
LF-4081 PCI: imx: wait specified minimum period following the end of a reset
...
Diffstat (limited to 'Documentation/devicetree/bindings/pci')
| -rw-r--r-- | Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 19 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/pci/layerscape-pci.txt | 7 |
2 files changed, 25 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index acea1cd444fd..8d944d02198f 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml @@ -25,6 +25,8 @@ properties: - fsl,imx6qp-pcie - fsl,imx7d-pcie - fsl,imx8mq-pcie + - fsl,imx8qm-pcie + - fsl,imx8qxp-pcie reg: items: @@ -148,6 +150,23 @@ properties: the three PCIe PHY powers. This regulator can be supplied by both 1.8v and 3.3v voltage supplies (optional required). + hsio-cfg: + description: hsio configuration mode when the pcie node is supported. + mode 1: pciea 2 lanes and one sata ahci port. + mode 2: pciea 1 lane, pcieb 1 lane and one sata ahci port. + mode 3: pciea 2 lanes, pcieb 1 lane. + + local-addr: + description: the local address used in hsio module. + + reset-names: + description: Must contain the following entries: "clkreq" + + l1ss-disabled: + description: Force to disable L1SS or not. If present then the L1 + substate would be force disabled although it might be supported by the + chip. + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index a0ce177c9eb8..5b38c2ec1fcd 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -25,6 +25,7 @@ Required properties: EP mode: "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep" "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep" + "fsl,ls1028a-pcie-ep", "fsl,ls-pcie-ep" "fsl,ls2088a-pcie-ep", "fsl,ls-pcie-ep" "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep" - reg: base addresses and lengths of the PCIe controller register blocks. @@ -38,12 +39,16 @@ Required properties: ...... - fsl,pcie-scfg: Must include two entries. The first entry must be a link to the SCFG device node - The second entry must be '0' or '1' based on physical PCIe controller index. + The second entry is the physical PCIe controller index starting from '0'. This is used to get SCFG PEXN registers - dma-coherent: Indicates that the hardware IP block can ensure the coherency of the data transferred from/to the IP block. This can avoid the software cache flush/invalid actions, and improve the performance significantly. +Optional properties: +- big-endian: If the PEX_LUT and PF register block is in big-endian, specify + this property. + Example: pcie@3400000 { |