diff options
author | Richard Zhu <hongxing.zhu@nxp.com> | 2020-02-12 20:37:59 +0800 |
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committer | Richard Zhu <hongxing.zhu@nxp.com> | 2020-02-13 10:40:17 +0800 |
commit | 05bcf727b39bb5a80eacfb0c1db297cf5c2d92ed (patch) | |
tree | 08c9df4a42897beef766db501d900638b8b05a5d /Documentation/devicetree/bindings/phy | |
parent | d3f9a020a694af76eb143636f7faf772adeeeec5 (diff) |
MLK-23303-4 dt-bindings: phy: add imx pcie phy driver support
Add one standalone PCIe PHY for iMX8MP PCIe.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Fugang Duan <Fugang.duan@nxp.com>
Diffstat (limited to 'Documentation/devicetree/bindings/phy')
-rw-r--r-- | Documentation/devicetree/bindings/phy/fsl,imx-pcie-phy.txt | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/phy/fsl,imx-pcie-phy.txt b/Documentation/devicetree/bindings/phy/fsl,imx-pcie-phy.txt new file mode 100644 index 000000000000..627b508ecadc --- /dev/null +++ b/Documentation/devicetree/bindings/phy/fsl,imx-pcie-phy.txt @@ -0,0 +1,22 @@ +* Freescale i.MX PCIE PHY binding + +Required properties: +- compatible: Should be "fsl,imx-pcie-phy" +- #phys-cells: must be 0 (see phy-bindings.txt in this directory) +- reg: The base address and length of the registers +- clocks: Phandles to the clocks for each clock listed in clock-names +- clock-names: Must contain "phy" +- power-domains: Phandle to the power domain that the device is part of + +Example: + pcie_phy: pcie-phy@32f00000 { + compatible = "fsl,imx8mp-pcie-phy"; + reg = <0x0 0x32f00000 0x0 0x10000>; + clocks = <&clk IMX8MP_CLK_PCIE_PHY>; + clock-names = "phy"; + assigned-clocks = <&clk IMX8MP_CLK_PCIE_PHY>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + #phy-cells = <0>; + power-domains = <&pcie_pd>; + status = "disabled"; + }; |