diff options
author | Liu Ying <victor.liu@nxp.com> | 2020-03-18 11:01:09 +0800 |
---|---|---|
committer | Liu Ying <victor.liu@nxp.com> | 2020-03-18 18:43:57 +0800 |
commit | 3c97abb58120e5308ece03ca04fda02804b9d20e (patch) | |
tree | f2f63160fea7b854a71f0c6795414116aaec82c9 /Documentation/devicetree/bindings/phy | |
parent | f967f755ed4bd7675fce9efd9a829e8759058ae3 (diff) |
MLK-23616-1 dt-bindings: imx8mp-lvds-phy: Add APB clock relevant properties
The phy registers are accessible after APB clock is enabled.
So, add the relevant clock properties in device tree doc.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Diffstat (limited to 'Documentation/devicetree/bindings/phy')
-rw-r--r-- | Documentation/devicetree/bindings/phy/fsl,imx8mp-lvds-phy.yaml | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8mp-lvds-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8mp-lvds-phy.yaml index 17d84c5533f4..2dc5e0038365 100644 --- a/Documentation/devicetree/bindings/phy/fsl,imx8mp-lvds-phy.yaml +++ b/Documentation/devicetree/bindings/phy/fsl,imx8mp-lvds-phy.yaml @@ -29,6 +29,13 @@ properties: $ref: /schemas/types.yaml#/definitions/phandle description: phandle to block control syscon + clocks: + maxItems: 1 + + clock-names: + items: + - const: apb + port@0: type: object description: A port node pointing to the PHY instance0's port node @@ -74,6 +81,8 @@ examples: #address-cells = <1>; #size-cells = <0>; gpr = <&mediamix_blk_ctl>; + clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "apb"; ldb_phy1: port@0 { reg = <0>; |