diff options
| author | Ran Wang <ran.wang_1@nxp.com> | 2019-11-22 14:11:22 +0800 |
|---|---|---|
| committer | Ran Wang <ran.wang_1@nxp.com> | 2019-11-28 14:40:53 +0800 |
| commit | b1b26e7ed411daade797a9397119aa1ce472f54e (patch) | |
| tree | 3744c703d845c4f66981251a236e51f255ffc4b1 /Documentation/devicetree/bindings/usb | |
| parent | 9ae7fab35e4bc63ec0ea61660a5acc2de50472ba (diff) | |
usb: dwc3: Add chip-specific compatible string
Some Layerscape paltforms (such as LS1088A, LS2088A, etc) require update HW
default cache type configuration to fix DWC3 init failure when applying
property dma-coherent.
Note that the cache type configuration is actually native feature of DWC3,
not additional desgin coming from SoC, so add this support here.
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Jun Li <jun.li@nxp.com>
Diffstat (limited to 'Documentation/devicetree/bindings/usb')
| -rw-r--r-- | Documentation/devicetree/bindings/usb/dwc3.txt | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt index d2d5a8e99db5..45043c4c54ae 100644 --- a/Documentation/devicetree/bindings/usb/dwc3.txt +++ b/Documentation/devicetree/bindings/usb/dwc3.txt @@ -4,7 +4,15 @@ DWC3- USB3 CONTROLLER. Complies to the generic USB binding properties as described in 'usb/generic.txt' Required properties: - - compatible: must be "snps,dwc3" + - compatible: must be "snps,dwc3" and (if applicable) may contain a + chip-specific compatible string in front of it to allow dwc3 driver be + able to update cache type configuration accordingly, otherwise + Layerscape SoC will encounter USB init failure when adding property + dma-coherent on device tree. + Example: + * "fsl,layerscape-dwc3", "snps,dwc3" + * "snps,dwc3" + - reg : Address and length of the register set for the device - interrupts: Interrupts used by the dwc3 controller. - clock-names: should contain "ref", "bus_early", "suspend" |