diff options
| author | Markus Stockhausen <markus.stockhausen@gmx.de> | 2026-06-05 23:16:40 +0200 |
|---|---|---|
| committer | Thomas Gleixner <tglx@kernel.org> | 2026-06-29 17:19:05 +0200 |
| commit | 9d9faab6f562b8a447b4f7aae2862d071ba1ae0d (patch) | |
| tree | 1ccdade3c26b800fce26e60028b1f65a2906040d /Documentation/devicetree | |
| parent | dc59e4fea9d83f03bad6bddf3fa2e52491777482 (diff) | |
dt-bindings: interrupt-controller: realtek,rtl-intc: Allow 2 interrupt cells
The Realtek Otto SoC interrupt controller supports hardware interrupt
routing to multiple parent CPU interrupt lines. To utilize this
multi-domain support, peripheral devices need a way to explicitly
specify their desired parent interrupt line in the device tree.
Update the "#interrupt-cells" property to accept either 1 or 2 cells.
1 cell: Specifies the hardware interrupt index, implicitly routing it
to the first available parent (maintaining backward compatibility).
2 cells: The first cell specifies the hardware interrupt index and
the second cell specifies the targeted parent interrupt index.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20260605211646.2101652-2-markus.stockhausen@gmx.de
Diffstat (limited to 'Documentation/devicetree')
| -rw-r--r-- | Documentation/devicetree/bindings/interrupt-controller/realtek,rtl-intc.yaml | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/interrupt-controller/realtek,rtl-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/realtek,rtl-intc.yaml index 833a01cdd1b1..5c52e57c6647 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/realtek,rtl-intc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/realtek,rtl-intc.yaml @@ -32,8 +32,9 @@ properties: "#interrupt-cells": description: - SoC interrupt line index. - const: 1 + First cell is the SoC interrupt line index. Optional second cell + specifies the parent interrupt index to route to. + enum: [1, 2] reg: minItems: 1 |