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authorDave Airlie <airlied@redhat.com>2026-05-07 09:50:50 +1000
committerDave Airlie <airlied@redhat.com>2026-05-07 09:50:50 +1000
commitbc0400e6f41cbc43a5eaa5ed1c7749da7af7eb1d (patch)
tree4af6abdda20f8e5c958ca54e65a87c56867c5ad0 /Documentation/gpu
parent7a777dccc2d7957f81fec38183abd15254679ac4 (diff)
parent0d831487b5be0ae59cac865a0aa87b0acc3dc717 (diff)
Merge tag 'amd-drm-next-7.2-2026-05-06' of https://gitlab.freedesktop.org/agd5f/linux into drm-next
amd-drm-next-7.2-2026-05-06: amdgpu: - GFX9 fixes - Hawaii SMU fixes - SDMA4 fix - GART fixes - Userq fixes - Finish support for using multiple SDMA queues for TTM operations - SWSMU updates - Misc cleanups and fixes - GC 12.1 updates - RAS updates - SMU 15.0.8 updates - DCN 4.2 updates - DC type conversion fixes - Enable DC power module - Replay/PSR updates - SMU 13.x updates - Compute queue quantum MQD updates - ASPM fix - GPUVM fixes - DCE 6 fixes - Align VKMS with common implementation - RDNA 4 fix - DC analog support fixes - UVD 3 fixes - TCC harvesting fixes for SI - GC 11 APU module reload fix - NBIO 6.3.2 support - IH 7.1 updates - DC cursor fixes - VCN user fence fixes - JPEG user fence fixes - DC support for connectors without DDC - Prefer ROM BAR for default VGA device - DC bandwidth fixes amdkfd: - GPUVM TLB flush fix - Hotplug fix - Boundary check fixes - Misc cleanups and fixes - SVM fixes - CRIU fixes radeon: - Hawaii SMU fixes - Misc cleanups and fixes From: Alex Deucher <alexander.deucher@amd.com> Link: https://patch.msgid.link/20260506164726.1733646-1-alexander.deucher@amd.com Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'Documentation/gpu')
-rw-r--r--Documentation/gpu/amdgpu/amdgpu-glossary.rst9
1 files changed, 8 insertions, 1 deletions
diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
index 033167025fcc..d553dd599c96 100644
--- a/Documentation/gpu/amdgpu/amdgpu-glossary.rst
+++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
@@ -233,8 +233,15 @@ we have a dedicated glossary for Display Core at
TC
Texture Cache
+ TCC
+ Texture Cache per Channel - L2 cache attached to the memory channels.
+ May be used when shader cores are accessing memory.
+ Despite "Texture" in the name, this is used by any kind of memory access.
+ TCCs may be mapped to TCPs, depending on the architecture.
+
TCP (AMDGPU)
- Texture Cache per Pipe. Even though the name "Texture" is part of this
+ Texture Cache per Pipe - L1 cache attached to each CU.
+ Even though the name "Texture" is part of this
acronym, the TCP represents the path to memory shaders; i.e., it is not
related to texture. The name is a leftover from older designs where shader
stages had different cache designs; it refers to the L1 cache in older