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authorRodrigo Siqueira <siqueira@igalia.com>2025-11-18 17:45:51 -0700
committerAlex Deucher <alexander.deucher@amd.com>2025-12-08 13:56:32 -0500
commite0f90f184d18c70c1b04e8b03a5243e275ce86f4 (patch)
tree96304a190c4529dbfd6aace698fbf6aa1192e128 /Documentation/gpu
parentb9befc9a21bdeafb0f81b757c60df66e6e9feb17 (diff)
Documentation/gpu: Add new glossary entries from UMR
When using UMR, a dashboard is available that displays the CPC, CPF, CPG, TCP, and UTCL utilization. This commit introduces the meanings of those acronyms (and others) to the glossary to improve the comprehension of the UMR dashboard. Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: Timur Kristóf <timur.kristof@gmail.com> Cc: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'Documentation/gpu')
-rw-r--r--Documentation/gpu/amdgpu/amdgpu-glossary.rst30
1 files changed, 30 insertions, 0 deletions
diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
index 43a36362dc73..ac13213d84fa 100644
--- a/Documentation/gpu/amdgpu/amdgpu-glossary.rst
+++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
@@ -30,6 +30,15 @@ we have a dedicated glossary for Display Core at
CP
Command Processor
+ CPC
+ Command Processor Compute
+
+ CPF
+ Command Processor Fetch
+
+ CPG
+ Command Processor Graphics
+
CPLIB
Content Protection Library
@@ -78,6 +87,9 @@ we have a dedicated glossary for Display Core at
GMC
Graphic Memory Controller
+ GPR
+ General Purpose Register
+
GPUVM
GPU Virtual Memory. This is the GPU's MMU. The GPU supports multiple
virtual address spaces that can be in flight at any given time. These
@@ -92,9 +104,15 @@ we have a dedicated glossary for Display Core at
table for use by the kernel driver or into per process GPUVM page tables
for application usage.
+ GWS
+ Global Wave Sync
+
IH
Interrupt Handler
+ IV
+ Interrupt Vector
+
HQD
Hardware Queue Descriptor
@@ -215,12 +233,24 @@ we have a dedicated glossary for Display Core at
TC
Texture Cache
+ TCP (AMDGPU)
+ Texture Cache per Pipe. Even though the name "Texture" is part of this
+ acronym, the TCP represents the path to memory shaders; i.e., it is not
+ related to texture. The name is a leftover from older designs where shader
+ stages had different cache designs; it refers to the L1 cache in older
+ architectures.
+
TOC
Table of Contents
UMSCH
User Mode Scheduler
+ UTC (AMDGPU)
+ Unified Translation Cache. UTC is equivalent to TLB. You might see a
+ variation of this acronym with L at the end, i.e., UTCL followed by a
+ number; L means the cache level (e.g., UTCL1 and UTCL2).
+
UVD
Unified Video Decoder